[llvm] [RISCV][P-ext] Add packed saturating rounding shift codegen (PR #208630)

[Craig Topper via llvm-commits]

topperc wrote:

> However, the selected .hs instruction processes all four lanes, so an undefined upper lane could set the sticky VXSAT flag. Please let me know if the lowering should zero the upper lanes instead.

I think we'll need specific intrinsics if we want to support users who care about VXSAT. The compiler can generate other instructions that can set the vxsat flag so it is already unreliable.

https://github.com/llvm/llvm-project/pull/208630