[llvm] [SDAG] Freeze condition in select of load fold (PR #208683)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 10 03:19:29 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-mips
@llvm/pr-subscribers-backend-nvptx
Author: Nikita Popov (nikic)
<details>
<summary>Changes</summary>
When converting `select cond, (load p1), (load p2)` to `load (select cond, p1, p2)`, if `cond` is poison, originally this would result in a `poison` result, while after the transform it would result in a load of poison, which is immediate UB. Fix this by freezing the condition.
Fixes https://github.com/llvm/llvm-project/issues/208611.
---
Patch is 154.53 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/208683.diff
14 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+9-7)
- (modified) llvm/test/CodeGen/AArch64/icmp.ll (+11-15)
- (modified) llvm/test/CodeGen/ARM/fp16-promote.ll (+1-1)
- (modified) llvm/test/CodeGen/Mips/cconv/vector.ll (+5-5)
- (modified) llvm/test/CodeGen/Mips/cmov.ll (+1-1)
- (modified) llvm/test/CodeGen/NVPTX/i1-select.ll (+7-7)
- (modified) llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll (+82-26)
- (modified) llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll (+696-240)
- (modified) llvm/test/CodeGen/X86/fp128-libcalls-strict.ll (+2)
- (modified) llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll (+102-42)
- (modified) llvm/test/CodeGen/X86/isel-select-cmov.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/select-constant-xor.ll (+8-4)
- (modified) llvm/test/CodeGen/X86/select-mmx.ll (+2-2)
- (added) llvm/test/CodeGen/X86/select-of-load-poison.ll (+21)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c81c43c94b0f0..f5fde1e599458 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -30506,10 +30506,12 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
SDNode::hasPredecessorHelper(RLD, Visited, Worklist)))
return false;
- Addr = DAG.getSelect(SDLoc(TheSelect),
- LLD->getBasePtr().getValueType(),
- TheSelect->getOperand(0), LLD->getBasePtr(),
- RLD->getBasePtr());
+ // If the condition is poison, originally this would result in a poison
+ // result. After the transform, this would result in a load of poison,
+ // which is UB. Freeze the condition to prevent this.
+ Addr = DAG.getSelect(SDLoc(TheSelect), LLD->getBasePtr().getValueType(),
+ DAG.getFreeze(TheSelect->getOperand(0)),
+ LLD->getBasePtr(), RLD->getBasePtr());
} else { // Otherwise SELECT_CC
// We cannot do this optimization if any pair of {RLD, LLD} is a
// predecessor to {RLD, LLD, CondLHS, CondRHS}. As we've already compared
@@ -30528,10 +30530,10 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
SDNode::hasPredecessorHelper(RLD, Visited, Worklist)))
return false;
+ SDValue FrozenOp0 = TheSelect->getOperand(0);
+ SDValue FrozenOp1 = TheSelect->getOperand(1);
Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
- LLD->getBasePtr().getValueType(),
- TheSelect->getOperand(0),
- TheSelect->getOperand(1),
+ LLD->getBasePtr().getValueType(), FrozenOp0, FrozenOp1,
LLD->getBasePtr(), RLD->getBasePtr(),
TheSelect->getOperand(4));
}
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index b0fdf1820d7eb..6830ce834ab11 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -1376,26 +1376,22 @@ entry:
define <2 x i128> @v2i128_i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %d, <2 x i128> %e) {
; CHECK-SD-LABEL: v2i128_i128:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: cmp x2, x6
; CHECK-SD-NEXT: add x10, sp, #32
; CHECK-SD-NEXT: mov x11, sp
+; CHECK-SD-NEXT: sbcs xzr, x3, x7
+; CHECK-SD-NEXT: cset w8, lt
; CHECK-SD-NEXT: cmp x0, x4
-; CHECK-SD-NEXT: orr x12, x10, #0x8
-; CHECK-SD-NEXT: orr x13, x11, #0x8
; CHECK-SD-NEXT: sbcs xzr, x1, x5
+; CHECK-SD-NEXT: cset w9, lt
+; CHECK-SD-NEXT: cmp w9, #0
+; CHECK-SD-NEXT: csel x9, x11, x10, ne
+; CHECK-SD-NEXT: cmp w8, #0
; CHECK-SD-NEXT: add x8, sp, #48
-; CHECK-SD-NEXT: add x9, sp, #16
-; CHECK-SD-NEXT: csel x12, x13, x12, lt
-; CHECK-SD-NEXT: csel x10, x11, x10, lt
-; CHECK-SD-NEXT: cmp x2, x6
-; CHECK-SD-NEXT: orr x11, x8, #0x8
-; CHECK-SD-NEXT: orr x13, x9, #0x8
-; CHECK-SD-NEXT: sbcs xzr, x3, x7
-; CHECK-SD-NEXT: ldr x0, [x10]
-; CHECK-SD-NEXT: csel x8, x9, x8, lt
-; CHECK-SD-NEXT: csel x9, x13, x11, lt
-; CHECK-SD-NEXT: ldr x1, [x12]
-; CHECK-SD-NEXT: ldr x2, [x8]
-; CHECK-SD-NEXT: ldr x3, [x9]
+; CHECK-SD-NEXT: add x10, sp, #16
+; CHECK-SD-NEXT: ldp x0, x1, [x9]
+; CHECK-SD-NEXT: csel x8, x10, x8, ne
+; CHECK-SD-NEXT: ldp x2, x3, [x8]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i128_i128:
diff --git a/llvm/test/CodeGen/ARM/fp16-promote.ll b/llvm/test/CodeGen/ARM/fp16-promote.ll
index 27a0bf2eb9037..5b3539def98a0 100644
--- a/llvm/test/CodeGen/ARM/fp16-promote.ll
+++ b/llvm/test/CodeGen/ARM/fp16-promote.ll
@@ -348,7 +348,7 @@ define half @test_tailcall_flipped(half %a, half %b) #0 {
; No conversion is needed
define void @test_select(ptr %p, ptr %q, i1 zeroext %c) #0 {
; CHECK-ALL-LABEL: test_select:
-; CHECK-ALL: cmp r2, #0
+; CHECK-ALL: tst r2, #1
; CHECK-ALL-NEXT: movne r1, r0
; CHECK-ALL-NEXT: ldrh r1, [r1]
; CHECK-ALL-NEXT: strh r1, [r0]
diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll
index c64c60ddef73d..5cd2b77615fcd 100644
--- a/llvm/test/CodeGen/Mips/cconv/vector.ll
+++ b/llvm/test/CodeGen/Mips/cconv/vector.ll
@@ -6038,15 +6038,15 @@ entry:
define <4 x float> @select(<4 x i32> %cond, <4 x float> %arg1, <4 x float> %arg2) {
; MIPS32-LABEL: select:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: andi $1, $7, 1
-; MIPS32-NEXT: lw $2, 16($sp)
-; MIPS32-NEXT: andi $2, $2, 1
+; MIPS32-NEXT: lw $1, 16($sp)
+; MIPS32-NEXT: andi $2, $7, 1
+; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: addiu $3, $sp, 44
; MIPS32-NEXT: addiu $5, $sp, 28
; MIPS32-NEXT: addiu $7, $sp, 48
; MIPS32-NEXT: addiu $8, $sp, 32
-; MIPS32-NEXT: movn $7, $8, $2
-; MIPS32-NEXT: movn $3, $5, $1
+; MIPS32-NEXT: movn $7, $8, $1
+; MIPS32-NEXT: movn $3, $5, $2
; MIPS32-NEXT: andi $1, $6, 1
; MIPS32-NEXT: addiu $2, $sp, 40
; MIPS32-NEXT: addiu $5, $sp, 24
diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll
index bb3c7c27a122d..ee60b353b86b6 100644
--- a/llvm/test/CodeGen/Mips/cmov.ll
+++ b/llvm/test/CodeGen/Mips/cmov.ll
@@ -65,7 +65,7 @@ entry:
; 64-CMOV: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
; 64-CMOV: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
-; 64-CMOV: movn $[[R1]], $[[R0]], $4
+; 64-CMOV: movn $[[R1]], $[[R0]], $2
; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
; 64-CMP-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
diff --git a/llvm/test/CodeGen/NVPTX/i1-select.ll b/llvm/test/CodeGen/NVPTX/i1-select.ll
index c91a3df204d80..c13e494c3077a 100644
--- a/llvm/test/CodeGen/NVPTX/i1-select.ll
+++ b/llvm/test/CodeGen/NVPTX/i1-select.ll
@@ -70,9 +70,9 @@ define i32 @test_select_i1_trunc_2(i64 %a, i16 %b, i32 %c, i32 %true, i32 %false
define i32 @test_select_i1_basic(i32 %v1, i32 %v2, i32 %v3, i32 %true, i32 %false) {
; CHECK-LABEL: test_select_i1_basic(
; CHECK: {
-; CHECK-NEXT: .reg .pred %p<4>;
+; CHECK-NEXT: .reg .pred %p<6>;
; CHECK-NEXT: .reg .b32 %r<6>;
-; CHECK-NEXT: .reg .b64 %rd<6>;
+; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [test_select_i1_basic_param_0];
@@ -81,13 +81,13 @@ define i32 @test_select_i1_basic(i32 %v1, i32 %v2, i32 %v3, i32 %true, i32 %fals
; CHECK-NEXT: setp.ne.b32 %p1, %r1, 0;
; CHECK-NEXT: ld.param.b32 %r4, [test_select_i1_basic_param_2];
; CHECK-NEXT: setp.eq.b32 %p2, %r4, 0;
-; CHECK-NEXT: setp.eq.b32 %p3, %r3, 0;
+; CHECK-NEXT: and.pred %p3, %p1, %p2;
+; CHECK-NEXT: setp.eq.b32 %p4, %r3, 0;
+; CHECK-NEXT: or.pred %p5, %p4, %p3;
; CHECK-NEXT: mov.b64 %rd1, test_select_i1_basic_param_4;
; CHECK-NEXT: mov.b64 %rd2, test_select_i1_basic_param_3;
-; CHECK-NEXT: selp.b64 %rd3, %rd2, %rd1, %p2;
-; CHECK-NEXT: selp.b64 %rd4, %rd3, %rd1, %p1;
-; CHECK-NEXT: selp.b64 %rd5, %rd2, %rd4, %p3;
-; CHECK-NEXT: ld.param.b32 %r5, [%rd5];
+; CHECK-NEXT: selp.b64 %rd3, %rd2, %rd1, %p5;
+; CHECK-NEXT: ld.param.b32 %r5, [%rd3];
; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NEXT: ret;
%b1 = icmp eq i32 %v1, 0
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll
index 6a6b86e8efa7c..8e660e9193fcf 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll
@@ -49,10 +49,12 @@ define i32 @test_f16_oeq_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setnp %al
+; X86-FP16-NEXT: sete %cl
+; X86-FP16-NEXT: testb %al, %cl
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-FP16-NEXT: cmovnel %eax, %ecx
-; X86-FP16-NEXT: cmovpl %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -112,9 +114,11 @@ define i32 @test_f16_ogt_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: seta %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmoval %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -173,9 +177,11 @@ define i32 @test_f16_oge_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setae %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovael %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -236,9 +242,11 @@ define i32 @test_f16_olt_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: seta %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmoval %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -299,9 +307,11 @@ define i32 @test_f16_ole_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setae %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovael %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -360,6 +370,8 @@ define i32 @test_f16_one_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setne %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-FP16-NEXT: cmovnel %eax, %ecx
@@ -421,9 +433,11 @@ define i32 @test_f16_ord_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setnp %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovnpl %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -482,9 +496,11 @@ define i32 @test_f16_ueq_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: sete %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovel %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -545,9 +561,11 @@ define i32 @test_f16_ugt_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setb %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovbl %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -608,9 +626,11 @@ define i32 @test_f16_uge_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setbe %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovbel %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -669,9 +689,11 @@ define i32 @test_f16_ult_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setb %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovbl %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -730,9 +752,11 @@ define i32 @test_f16_ule_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setbe %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovbel %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -793,10 +817,12 @@ define i32 @test_f16_une_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setp %al
+; X86-FP16-NEXT: setne %cl
+; X86-FP16-NEXT: orb %al, %cl
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-FP16-NEXT: cmovnel %eax, %ecx
-; X86-FP16-NEXT: cmovpl %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -856,9 +882,11 @@ define i32 @test_f16_uno_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setp %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovpl %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -919,10 +947,12 @@ define i32 @test_f16_oeq_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setnp %al
+; X86-FP16-NEXT: sete %cl
+; X86-FP16-NEXT: testb %al, %cl
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-FP16-NEXT: cmovnel %eax, %ecx
-; X86-FP16-NEXT: cmovpl %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -982,9 +1012,11 @@ define i32 @test_f16_ogt_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: seta %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmoval %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -1043,9 +1075,11 @@ define i32 @test_f16_oge_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setae %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovael %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -1106,9 +1140,11 @@ define i32 @test_f16_olt_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: seta %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmoval %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -1169,9 +1205,11 @@ define i32 @test_f16_ole_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setae %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovael %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -1230,6 +1268,8 @@ define i32 @test_f16_one_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setne %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-FP16-NEXT: cmovnel %eax, %ecx
@@ -1291,9 +1331,11 @@ define i32 @test_f16_ord_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setnp %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovnpl %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -1352,9 +1394,11 @@ define i32 @test_f16_ueq_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: sete %al
+; X86-FP16-NEXT: testb %al, %al
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-FP16-NEXT: leal {{[0-9]+}}(%esp), %ecx
-; X86-FP16-NEXT: cmovel %eax, %ecx
+; X86-FP16-NEXT: cmovnel %eax, %ecx
; X86-FP16-NEXT: movl (%ecx), %eax
; X86-FP16-NEXT: retl
;
@@ -1415,9 +1459,11 @@ define i32 @test_f16_ugt_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
; X86-FP16: # %bb.0:
; X86-FP16-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-FP16-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
+; X86-FP16-NEXT: setb %al
+; X86-FP16-NEXT: testb %al, %al
; X8...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/208683
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