[llvm] 1d73e32 - [AArch64][GlobalISel] Update scalar types in postlegalizer tests. NFC (#208620)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 9 22:01:49 PDT 2026
Author: David Green
Date: 2026-07-10T06:01:43+01:00
New Revision: 1d73e32bf36b98cce9dda0d5fba482aa81a88d1d
URL: https://github.com/llvm/llvm-project/commit/1d73e32bf36b98cce9dda0d5fba482aa81a88d1d
DIFF: https://github.com/llvm/llvm-project/commit/1d73e32bf36b98cce9dda0d5fba482aa81a88d1d.diff
LOG: [AArch64][GlobalISel] Update scalar types in postlegalizer tests. NFC (#208620)
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-anyext-to-zext.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-copy-prop.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-undef.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-trn.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-uzp.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-mulpow2.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
index ec64c9e02791d..bea2d7a08fd44 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
@@ -16,13 +16,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
- %1:_(s64) = G_CONSTANT i64 4
- %2:_(s64) = G_CONSTANT i64 12
+ %1:_(i64) = G_CONSTANT i64 4
+ %2:_(i64) = G_CONSTANT i64 12
%3:_(p0) = G_PTR_ADD %0(p0), %1
%4:_(p0) = G_PTR_ADD %3(p0), %2
$x0 = COPY %4(p0)
@@ -40,13 +40,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
- %1:_(s64) = G_CONSTANT i64 4
- %2:_(s64) = G_CONSTANT i64 12
+ %1:_(i64) = G_CONSTANT i64 4
+ %2:_(i64) = G_CONSTANT i64 12
%3:_(p0) = nuw G_PTR_ADD %0(p0), %1
%4:_(p0) = nuw G_PTR_ADD %3(p0), %2
$x0 = COPY %4(p0)
@@ -64,13 +64,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
- %1:_(s64) = G_CONSTANT i64 4
- %2:_(s64) = G_CONSTANT i64 12
+ %1:_(i64) = G_CONSTANT i64 4
+ %2:_(i64) = G_CONSTANT i64 12
%3:_(p0) = nuw nusw inbounds G_PTR_ADD %0(p0), %1
%4:_(p0) = nuw nusw inbounds G_PTR_ADD %3(p0), %2
$x0 = COPY %4(p0)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
index 1f7d5e7ed434e..5dc61236279dc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir
@@ -19,17 +19,17 @@ body: |
; CHECK-LABEL: name: remove_and_with_one_bit
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %cmp:_(s32) = G_ICMP intpred(eq), %x(s32), %y
- ; CHECK-NEXT: $w0 = COPY %cmp(s32)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %cmp:_(i32) = G_ICMP intpred(eq), %x(i32), %y
+ ; CHECK-NEXT: $w0 = COPY %cmp(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %cmp:_(s32) = G_ICMP intpred(eq), %x(s32), %y
- %mask:_(s32) = G_CONSTANT i32 1
- %and:_(s32) = G_AND %cmp(s32), %mask
- $w0 = COPY %and(s32)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %cmp:_(i32) = G_ICMP intpred(eq), %x(i32), %y
+ %mask:_(i32) = G_CONSTANT i32 1
+ %and:_(i32) = G_AND %cmp(i32), %mask
+ $w0 = COPY %and(i32)
RET_ReallyLR implicit $w0
...
@@ -44,17 +44,17 @@ body: |
; CHECK-LABEL: name: remove_and_all_ones_mask
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %z:_(s32) = COPY $w2
- ; CHECK-NEXT: $w0 = COPY %z(s32)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %z:_(i32) = COPY $w2
+ ; CHECK-NEXT: $w0 = COPY %z(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %z:_(s32) = COPY $w2
- %mask:_(s32) = G_CONSTANT i32 -1
- %and:_(s32) = G_AND %z(s32), %mask
- $w0 = COPY %and(s32)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %z:_(i32) = COPY $w2
+ %mask:_(i32) = G_CONSTANT i32 -1
+ %and:_(i32) = G_AND %z(i32), %mask
+ $w0 = COPY %and(i32)
RET_ReallyLR implicit $w0
...
@@ -72,19 +72,19 @@ body: |
; CHECK-LABEL: name: remove_and_all_ones_zext
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %z:_(s32) = COPY $w2
- ; CHECK-NEXT: %ext:_(s64) = G_ZEXT %z(s32)
- ; CHECK-NEXT: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %z:_(i32) = COPY $w2
+ ; CHECK-NEXT: %ext:_(i64) = G_ZEXT %z(i32)
+ ; CHECK-NEXT: $x0 = COPY %ext(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %z:_(s32) = COPY $w2
- %ext:_(s64) = G_ZEXT %z
- %mask:_(s64) = G_CONSTANT i64 4294967295
- %and:_(s64) = G_AND %ext(s64), %mask
- $x0 = COPY %and(s64)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %z:_(i32) = COPY $w2
+ %ext:_(i64) = G_ZEXT %z
+ %mask:_(i64) = G_CONSTANT i64 4294967295
+ %and:_(i64) = G_AND %ext(i64), %mask
+ $x0 = COPY %and(i64)
RET_ReallyLR implicit $x0
...
@@ -99,19 +99,19 @@ body: |
; CHECK-LABEL: name: remove_and_all_ones_anyext
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %z:_(s32) = COPY $w2
- ; CHECK-NEXT: %ext:_(s64) = G_ZEXT %z(s32)
- ; CHECK-NEXT: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %z:_(i32) = COPY $w2
+ ; CHECK-NEXT: %ext:_(i64) = G_ZEXT %z(i32)
+ ; CHECK-NEXT: $x0 = COPY %ext(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %z:_(s32) = COPY $w2
- %ext:_(s64) = G_ZEXT %z
- %mask:_(s64) = G_CONSTANT i64 4294967295
- %and:_(s64) = G_AND %ext(s64), %mask
- $x0 = COPY %and(s64)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %z:_(i32) = COPY $w2
+ %ext:_(i64) = G_ZEXT %z
+ %mask:_(i64) = G_CONSTANT i64 4294967295
+ %and:_(i64) = G_AND %ext(i64), %mask
+ $x0 = COPY %and(i64)
RET_ReallyLR implicit $x0
...
@@ -127,21 +127,21 @@ body: |
; CHECK-LABEL: name: dont_remove_all_ones_sext
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %z:_(s32) = COPY $w2
- ; CHECK-NEXT: %ext:_(s64) = G_SEXT %z(s32)
- ; CHECK-NEXT: %mask:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK-NEXT: %and:_(s64) = G_AND %ext, %mask
- ; CHECK-NEXT: $x0 = COPY %and(s64)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %z:_(i32) = COPY $w2
+ ; CHECK-NEXT: %ext:_(i64) = G_SEXT %z(i32)
+ ; CHECK-NEXT: %mask:_(i64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: %and:_(i64) = G_AND %ext, %mask
+ ; CHECK-NEXT: $x0 = COPY %and(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %z:_(s32) = COPY $w2
- %ext:_(s64) = G_SEXT %z
- %mask:_(s64) = G_CONSTANT i64 4294967295
- %and:_(s64) = G_AND %ext(s64), %mask
- $x0 = COPY %and(s64)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %z:_(i32) = COPY $w2
+ %ext:_(i64) = G_SEXT %z
+ %mask:_(i64) = G_CONSTANT i64 4294967295
+ %and:_(i64) = G_AND %ext(i64), %mask
+ $x0 = COPY %and(i64)
RET_ReallyLR implicit $x0
...
@@ -159,19 +159,19 @@ body: |
; CHECK-LABEL: name: remove_and_positive_constant_sext
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %z:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: %ext:_(s64) = G_SEXT %z(s32)
- ; CHECK-NEXT: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %z:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: %ext:_(i64) = G_SEXT %z(i32)
+ ; CHECK-NEXT: $x0 = COPY %ext(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %z:_(s32) = G_CONSTANT i32 42
- %ext:_(s64) = G_SEXT %z
- %mask:_(s64) = G_CONSTANT i64 63
- %and:_(s64) = G_AND %ext(s64), %mask
- $x0 = COPY %and(s64)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %z:_(i32) = G_CONSTANT i32 42
+ %ext:_(i64) = G_SEXT %z
+ %mask:_(i64) = G_CONSTANT i64 63
+ %and:_(i64) = G_AND %ext(i64), %mask
+ $x0 = COPY %and(i64)
RET_ReallyLR implicit $x0
...
@@ -186,19 +186,19 @@ body: |
; CHECK-LABEL: name: not_a_mask
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %cmp:_(s32) = G_ICMP intpred(eq), %x(s32), %y
- ; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: %and:_(s32) = G_AND %cmp, %mask
- ; CHECK-NEXT: $w0 = COPY %and(s32)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %cmp:_(i32) = G_ICMP intpred(eq), %x(i32), %y
+ ; CHECK-NEXT: %mask:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: %and:_(i32) = G_AND %cmp, %mask
+ ; CHECK-NEXT: $w0 = COPY %and(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %cmp:_(s32) = G_ICMP intpred(eq), %x(s32), %y
- %mask:_(s32) = G_CONSTANT i32 6
- %and:_(s32) = G_AND %cmp(s32), %mask
- $w0 = COPY %and(s32)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %cmp:_(i32) = G_ICMP intpred(eq), %x(i32), %y
+ %mask:_(i32) = G_CONSTANT i32 6
+ %and:_(i32) = G_AND %cmp(i32), %mask
+ $w0 = COPY %and(i32)
RET_ReallyLR implicit $w0
...
@@ -214,19 +214,19 @@ body: |
; CHECK-LABEL: name: unknown_val
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %z:_(s32) = COPY $w2
- ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: %and:_(s32) = G_AND %z, %one
- ; CHECK-NEXT: $w0 = COPY %and(s32)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %z:_(i32) = COPY $w2
+ ; CHECK-NEXT: %one:_(i32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: %and:_(i32) = G_AND %z, %one
+ ; CHECK-NEXT: $w0 = COPY %and(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %z:_(s32) = COPY $w2
- %one:_(s32) = G_CONSTANT i32 32
- %and:_(s32) = G_AND %z(s32), %one
- $w0 = COPY %and(s32)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %z:_(i32) = COPY $w2
+ %one:_(i32) = G_CONSTANT i32 32
+ %and:_(i32) = G_AND %z(i32), %one
+ $w0 = COPY %and(i32)
RET_ReallyLR implicit $w0
...
---
@@ -242,15 +242,15 @@ body: |
; CHECK-LABEL: name: remove_and_assert_zext
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %assert_zext:_(s32) = G_ASSERT_ZEXT %x, 8
- ; CHECK-NEXT: $w0 = COPY %assert_zext(s32)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %assert_zext:_(i32) = G_ASSERT_ZEXT %x, 8
+ ; CHECK-NEXT: $w0 = COPY %assert_zext(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %x:_(s32) = COPY $w0
- %assert_zext:_(s32) = G_ASSERT_ZEXT %x(s32), 8
- %mask:_(s32) = G_CONSTANT i32 255
- %and:_(s32) = G_AND %assert_zext(s32), %mask
- $w0 = COPY %and(s32)
+ %x:_(i32) = COPY $w0
+ %assert_zext:_(i32) = G_ASSERT_ZEXT %x(i32), 8
+ %mask:_(i32) = G_CONSTANT i32 255
+ %and:_(i32) = G_AND %assert_zext(i32), %mask
+ $w0 = COPY %and(i32)
RET_ReallyLR implicit $w0
...
---
@@ -265,15 +265,15 @@ body: |
; CHECK-LABEL: name: dont_remove_and_assert_zext_wrong_mask
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %assert_zext:_(s32) = G_ASSERT_ZEXT %x, 16
- ; CHECK-NEXT: %mask:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: %and:_(s32) = G_AND %assert_zext, %mask
- ; CHECK-NEXT: $w0 = COPY %and(s32)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %assert_zext:_(i32) = G_ASSERT_ZEXT %x, 16
+ ; CHECK-NEXT: %mask:_(i32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: %and:_(i32) = G_AND %assert_zext, %mask
+ ; CHECK-NEXT: $w0 = COPY %and(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %x:_(s32) = COPY $w0
- %assert_zext:_(s32) = G_ASSERT_ZEXT %x(s32), 16
- %mask:_(s32) = G_CONSTANT i32 255
- %and:_(s32) = G_AND %assert_zext(s32), %mask
- $w0 = COPY %and(s32)
+ %x:_(i32) = COPY $w0
+ %assert_zext:_(i32) = G_ASSERT_ZEXT %x(i32), 16
+ %mask:_(i32) = G_CONSTANT i32 255
+ %and:_(i32) = G_AND %assert_zext(i32), %mask
+ $w0 = COPY %and(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-anyext-to-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-anyext-to-zext.mir
index 24baa2fc13317..69d2f9f0cd3bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-anyext-to-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-anyext-to-zext.mir
@@ -15,17 +15,17 @@ body: |
; CHECK-LABEL: name: scalar_icmp
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:_(s64) = COPY $x0
- ; CHECK-NEXT: %cst_1:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %icmp:_(s32) = G_ICMP intpred(eq), %copy(s64), %cst_1
- ; CHECK-NEXT: %ext:_(s64) = G_ZEXT %icmp(s32)
- ; CHECK-NEXT: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: %copy:_(i64) = COPY $x0
+ ; CHECK-NEXT: %cst_1:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %icmp:_(i32) = G_ICMP intpred(eq), %copy(i64), %cst_1
+ ; CHECK-NEXT: %ext:_(i64) = G_ZEXT %icmp(i32)
+ ; CHECK-NEXT: $x0 = COPY %ext(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:_(s64) = COPY $x0
- %cst_1:_(s64) = G_CONSTANT i64 1
- %icmp:_(s32) = G_ICMP intpred(eq), %copy(s64), %cst_1
- %ext:_(s64) = G_ANYEXT %icmp(s32)
- $x0 = COPY %ext(s64)
+ %copy:_(i64) = COPY $x0
+ %cst_1:_(i64) = G_CONSTANT i64 1
+ %icmp:_(i32) = G_ICMP intpred(eq), %copy(i64), %cst_1
+ %ext:_(i64) = G_ANYEXT %icmp(i32)
+ $x0 = COPY %ext(i64)
RET_ReallyLR implicit $x0
@@ -42,19 +42,19 @@ body: |
; CHECK-LABEL: name: vector_icmp
; CHECK: liveins: $x0, $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %cst_1:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: %vec_cst_1:_(<2 x s32>) = G_BUILD_VECTOR %cst_1(s32), %cst_1(s32)
- ; CHECK-NEXT: %icmp:_(<2 x s32>) = G_ICMP intpred(eq), %copy(<2 x s32>), %vec_cst_1
- ; CHECK-NEXT: %ext:_(<2 x s64>) = G_ANYEXT %icmp(<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY %ext(<2 x s64>)
+ ; CHECK-NEXT: %copy:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %cst_1:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %vec_cst_1:_(<2 x i32>) = G_BUILD_VECTOR %cst_1(i32), %cst_1(i32)
+ ; CHECK-NEXT: %icmp:_(<2 x i32>) = G_ICMP intpred(eq), %copy(<2 x i32>), %vec_cst_1
+ ; CHECK-NEXT: %ext:_(<2 x i64>) = G_ANYEXT %icmp(<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY %ext(<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:_(<2 x s32>) = COPY $d0
- %cst_1:_(s32) = G_CONSTANT i32 1
- %vec_cst_1:_(<2 x s32>) = G_BUILD_VECTOR %cst_1, %cst_1
- %icmp:_(<2 x s32>) = G_ICMP intpred(eq), %copy(<2 x s32>), %vec_cst_1
- %ext:_(<2 x s64>) = G_ANYEXT %icmp(<2 x s32>)
- $q0 = COPY %ext(<2 x s64>)
+ %copy:_(<2 x i32>) = COPY $d0
+ %cst_1:_(i32) = G_CONSTANT i32 1
+ %vec_cst_1:_(<2 x i32>) = G_BUILD_VECTOR %cst_1, %cst_1
+ %icmp:_(<2 x i32>) = G_ICMP intpred(eq), %copy(<2 x i32>), %vec_cst_1
+ %ext:_(<2 x i64>) = G_ANYEXT %icmp(<2 x i32>)
+ $q0 = COPY %ext(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -70,15 +70,15 @@ body: |
; CHECK-LABEL: name: scalar_fcmp
; CHECK: liveins: $x0, $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:_(s64) = COPY $d0
- ; CHECK-NEXT: %cst_1:_(s64) = G_FCONSTANT double 1.000000e+00
- ; CHECK-NEXT: %fcmp:_(s32) = G_FCMP intpred(eq), %copy(s64), %cst_1
- ; CHECK-NEXT: %ext:_(s64) = G_ZEXT %fcmp(s32)
- ; CHECK-NEXT: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: %copy:_(f64) = COPY $d0
+ ; CHECK-NEXT: %cst_1:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; CHECK-NEXT: %fcmp:_(i32) = G_FCMP intpred(eq), %copy(f64), %cst_1
+ ; CHECK-NEXT: %ext:_(i64) = G_ZEXT %fcmp(i32)
+ ; CHECK-NEXT: $x0 = COPY %ext(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:_(s64) = COPY $d0
- %cst_1:_(s64) = G_FCONSTANT double 1.0
- %fcmp:_(s32) = G_FCMP intpred(eq), %copy(s64), %cst_1
- %ext:_(s64) = G_ANYEXT %fcmp(s32)
- $x0 = COPY %ext(s64)
+ %copy:_(f64) = COPY $d0
+ %cst_1:_(f64) = G_FCONSTANT double 1.0
+ %fcmp:_(i32) = G_FCMP intpred(eq), %copy(f64), %cst_1
+ %ext:_(i64) = G_ANYEXT %fcmp(i32)
+ $x0 = COPY %ext(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
index 0435baaf30f01..45b503d28cabe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
@@ -14,13 +14,13 @@ body: |
; CHECK-LABEL: name: add
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: $x0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: $x0 = COPY %res(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %a:_(s64) = G_CONSTANT i64 40
- %b:_(s64) = G_CONSTANT i64 2
- %res:_(s64) = G_ADD %a, %b
- $x0 = COPY %res(s64)
+ %a:_(i64) = G_CONSTANT i64 40
+ %b:_(i64) = G_CONSTANT i64 2
+ %res:_(i64) = G_ADD %a, %b
+ $x0 = COPY %res(i64)
RET_ReallyLR implicit $x0
...
@@ -37,13 +37,13 @@ body: |
; CHECK-LABEL: name: sub
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 38
- ; CHECK-NEXT: $x0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(i64) = G_CONSTANT i64 38
+ ; CHECK-NEXT: $x0 = COPY %res(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %a:_(s64) = G_CONSTANT i64 40
- %b:_(s64) = G_CONSTANT i64 2
- %res:_(s64) = G_SUB %a, %b
- $x0 = COPY %res(s64)
+ %a:_(i64) = G_CONSTANT i64 40
+ %b:_(i64) = G_CONSTANT i64 2
+ %res:_(i64) = G_SUB %a, %b
+ $x0 = COPY %res(i64)
RET_ReallyLR implicit $x0
...
@@ -60,13 +60,13 @@ body: |
; CHECK-LABEL: name: mul
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 80
- ; CHECK-NEXT: $x0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(i64) = G_CONSTANT i64 80
+ ; CHECK-NEXT: $x0 = COPY %res(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %a:_(s64) = G_CONSTANT i64 40
- %b:_(s64) = G_CONSTANT i64 2
- %res:_(s64) = G_MUL %a, %b
- $x0 = COPY %res(s64)
+ %a:_(i64) = G_CONSTANT i64 40
+ %b:_(i64) = G_CONSTANT i64 2
+ %res:_(i64) = G_MUL %a, %b
+ $x0 = COPY %res(i64)
RET_ReallyLR implicit $x0
...
@@ -83,13 +83,13 @@ body: |
; CHECK-LABEL: name: and
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY %res(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %a:_(s64) = G_CONSTANT i64 40
- %b:_(s64) = G_CONSTANT i64 2
- %res:_(s64) = G_AND %a, %b
- $x0 = COPY %res(s64)
+ %a:_(i64) = G_CONSTANT i64 40
+ %b:_(i64) = G_CONSTANT i64 2
+ %res:_(i64) = G_AND %a, %b
+ $x0 = COPY %res(i64)
RET_ReallyLR implicit $x0
...
@@ -106,13 +106,13 @@ body: |
; CHECK-LABEL: name: or
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 62
- ; CHECK-NEXT: $x0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(i64) = G_CONSTANT i64 62
+ ; CHECK-NEXT: $x0 = COPY %res(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %a:_(s64) = G_CONSTANT i64 42
- %b:_(s64) = G_CONSTANT i64 22
- %res:_(s64) = G_OR %a, %b
- $x0 = COPY %res(s64)
+ %a:_(i64) = G_CONSTANT i64 42
+ %b:_(i64) = G_CONSTANT i64 22
+ %res:_(i64) = G_OR %a, %b
+ $x0 = COPY %res(i64)
RET_ReallyLR implicit $x0
...
@@ -129,13 +129,13 @@ body: |
; CHECK-LABEL: name: xor
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: $x0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: $x0 = COPY %res(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %a:_(s64) = G_CONSTANT i64 8
- %b:_(s64) = G_CONSTANT i64 4
- %res:_(s64) = G_XOR %a, %b
- $x0 = COPY %res(s64)
+ %a:_(i64) = G_CONSTANT i64 8
+ %b:_(i64) = G_CONSTANT i64 4
+ %res:_(i64) = G_XOR %a, %b
+ $x0 = COPY %res(i64)
RET_ReallyLR implicit $x0
...
@@ -151,13 +151,13 @@ body: |
; CHECK-LABEL: name: fadd
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 4.200000e+01
- ; CHECK-NEXT: $d0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(f64) = G_FCONSTANT double 4.200000e+01
+ ; CHECK-NEXT: $d0 = COPY %res(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 40.0
- %b:_(s64) = G_FCONSTANT double 2.0
- %res:_(s64) = G_FADD %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 40.0
+ %b:_(f64) = G_FCONSTANT double 2.0
+ %res:_(f64) = G_FADD %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -173,13 +173,13 @@ body: |
; CHECK-LABEL: name: fsub
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 3.800000e+01
- ; CHECK-NEXT: $d0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(f64) = G_FCONSTANT double 3.800000e+01
+ ; CHECK-NEXT: $d0 = COPY %res(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 40.0
- %b:_(s64) = G_FCONSTANT double 2.0
- %res:_(s64) = G_FSUB %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 40.0
+ %b:_(f64) = G_FCONSTANT double 2.0
+ %res:_(f64) = G_FSUB %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -195,13 +195,13 @@ body: |
; CHECK-LABEL: name: fmul
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 8.000000e+01
- ; CHECK-NEXT: $d0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(f64) = G_FCONSTANT double 8.000000e+01
+ ; CHECK-NEXT: $d0 = COPY %res(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 40.0
- %b:_(s64) = G_FCONSTANT double 2.0
- %res:_(s64) = G_FMUL %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 40.0
+ %b:_(f64) = G_FCONSTANT double 2.0
+ %res:_(f64) = G_FMUL %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -217,13 +217,13 @@ body: |
; CHECK-LABEL: name: fdiv
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 2.000000e+01
- ; CHECK-NEXT: $d0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(f64) = G_FCONSTANT double 2.000000e+01
+ ; CHECK-NEXT: $d0 = COPY %res(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 40.0
- %b:_(s64) = G_FCONSTANT double 2.0
- %res:_(s64) = G_FDIV %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 40.0
+ %b:_(f64) = G_FCONSTANT double 2.0
+ %res:_(f64) = G_FDIV %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -239,13 +239,13 @@ body: |
; CHECK-LABEL: name: fminimumnum
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %a:_(s64) = G_FCONSTANT double 2.000000e+00
- ; CHECK-NEXT: $d0 = COPY %a(s64)
+ ; CHECK-NEXT: %a:_(f64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: $d0 = COPY %a(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 2.0
- %b:_(s64) = G_FCONSTANT double 5.0
- %res:_(s64) = G_FMINIMUMNUM %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 2.0
+ %b:_(f64) = G_FCONSTANT double 5.0
+ %res:_(f64) = G_FMINIMUMNUM %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -261,13 +261,13 @@ body: |
; CHECK-LABEL: name: fmaximumnum
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %b:_(s64) = G_FCONSTANT double 5.000000e+00
- ; CHECK-NEXT: $d0 = COPY %b(s64)
+ ; CHECK-NEXT: %b:_(f64) = G_FCONSTANT double 5.000000e+00
+ ; CHECK-NEXT: $d0 = COPY %b(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 2.0
- %b:_(s64) = G_FCONSTANT double 5.0
- %res:_(s64) = G_FMAXIMUMNUM %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 2.0
+ %b:_(f64) = G_FCONSTANT double 5.0
+ %res:_(f64) = G_FMAXIMUMNUM %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -284,13 +284,13 @@ body: |
; CHECK-LABEL: name: fcopysign
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double -3.000000e+00
- ; CHECK-NEXT: $d0 = COPY %res(s64)
+ ; CHECK-NEXT: %res:_(f64) = G_FCONSTANT double -3.000000e+00
+ ; CHECK-NEXT: $d0 = COPY %res(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 3.0
- %b:_(s64) = G_FCONSTANT double -1.0
- %res:_(s64) = G_FCOPYSIGN %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 3.0
+ %b:_(f64) = G_FCONSTANT double -1.0
+ %res:_(f64) = G_FCOPYSIGN %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -307,13 +307,13 @@ body: |
; CHECK-LABEL: name: fminnum
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %a:_(s64) = G_FCONSTANT double 2.000000e+00
- ; CHECK-NEXT: $d0 = COPY %a(s64)
+ ; CHECK-NEXT: %a:_(f64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: $d0 = COPY %a(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 2.0
- %b:_(s64) = G_FCONSTANT double 5.0
- %res:_(s64) = G_FMINNUM %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 2.0
+ %b:_(f64) = G_FCONSTANT double 5.0
+ %res:_(f64) = G_FMINNUM %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -330,13 +330,13 @@ body: |
; CHECK-LABEL: name: fmaxnum
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %b:_(s64) = G_FCONSTANT double 5.000000e+00
- ; CHECK-NEXT: $d0 = COPY %b(s64)
+ ; CHECK-NEXT: %b:_(f64) = G_FCONSTANT double 5.000000e+00
+ ; CHECK-NEXT: $d0 = COPY %b(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 2.0
- %b:_(s64) = G_FCONSTANT double 5.0
- %res:_(s64) = G_FMAXNUM %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 2.0
+ %b:_(f64) = G_FCONSTANT double 5.0
+ %res:_(f64) = G_FMAXNUM %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -353,13 +353,13 @@ body: |
; CHECK-LABEL: name: fminimum
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %a:_(s64) = G_FCONSTANT double 2.000000e+00
- ; CHECK-NEXT: $d0 = COPY %a(s64)
+ ; CHECK-NEXT: %a:_(f64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: $d0 = COPY %a(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 2.0
- %b:_(s64) = G_FCONSTANT double 5.0
- %res:_(s64) = G_FMINIMUM %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 2.0
+ %b:_(f64) = G_FCONSTANT double 5.0
+ %res:_(f64) = G_FMINIMUM %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -376,13 +376,13 @@ body: |
; CHECK-LABEL: name: fmaximum
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %b:_(s64) = G_FCONSTANT double 5.000000e+00
- ; CHECK-NEXT: $d0 = COPY %b(s64)
+ ; CHECK-NEXT: %b:_(f64) = G_FCONSTANT double 5.000000e+00
+ ; CHECK-NEXT: $d0 = COPY %b(f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:_(s64) = G_FCONSTANT double 2.0
- %b:_(s64) = G_FCONSTANT double 5.0
- %res:_(s64) = G_FMAXIMUM %a, %b
- $d0 = COPY %res(s64)
+ %a:_(f64) = G_FCONSTANT double 2.0
+ %b:_(f64) = G_FCONSTANT double 5.0
+ %res:_(f64) = G_FMAXIMUM %a, %b
+ $d0 = COPY %res(f64)
RET_ReallyLR implicit $d0
...
@@ -398,13 +398,13 @@ body: |
; CHECK-LABEL: name: fadd32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %res:_(s32) = G_FCONSTANT float 4.200000e+01
- ; CHECK-NEXT: $s0 = COPY %res(s32)
+ ; CHECK-NEXT: %res:_(i32) = G_FCONSTANT float 4.200000e+01
+ ; CHECK-NEXT: $s0 = COPY %res(i32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %a:_(s32) = G_FCONSTANT float 40.0
- %b:_(s32) = G_FCONSTANT float 2.0
- %res:_(s32) = G_FADD %a, %b
- $s0 = COPY %res(s32)
+ %a:_(i32) = G_FCONSTANT float 40.0
+ %b:_(i32) = G_FCONSTANT float 2.0
+ %res:_(i32) = G_FADD %a, %b
+ $s0 = COPY %res(i32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-copy-prop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-copy-prop.mir
index d867fc4341b4e..ff141a383c563 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-copy-prop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-copy-prop.mir
@@ -13,17 +13,17 @@ body: |
; CHECK-LABEL: name: postlegalize_copy_prop
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[ADD]]
- ; CHECK-NEXT: $x0 = COPY [[ADD1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i64) = G_ADD [[ADD]], [[ADD]]
+ ; CHECK-NEXT: $x0 = COPY [[ADD1]](i64)
; CHECK-NEXT: RET_ReallyLR
- %0:_(s64) = COPY $x0
- %1:_(s64) = COPY $x1
- %2:_(s64) = G_ADD %0, %1
- %3:_(s64) = COPY %2
- %4:_(s64) = G_ADD %3, %3
+ %0:_(i64) = COPY $x0
+ %1:_(i64) = COPY $x1
+ %2:_(i64) = G_ADD %0, %1
+ %3:_(i64) = COPY %2
+ %4:_(i64) = G_ADD %3, %3
$x0 = COPY %4
RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
index 0d36f5c8d8c03..540012453f79b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
@@ -14,13 +14,13 @@ body: |
; CHECK-LABEL: name: shift_of_zero
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %a:_(s64) = COPY $x0
- ; CHECK-NEXT: $x0 = COPY %a(s64)
+ ; CHECK-NEXT: %a:_(i64) = COPY $x0
+ ; CHECK-NEXT: $x0 = COPY %a(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %a:_(s64) = COPY $x0
- %b:_(s64) = G_CONSTANT i64 0
- %res:_(s64) = G_LSHR %a, %b
- $x0 = COPY %res(s64)
+ %a:_(i64) = COPY $x0
+ %b:_(i64) = G_CONSTANT i64 0
+ %res:_(i64) = G_LSHR %a, %b
+ $x0 = COPY %res(i64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
index 9e7c573cd8a5f..041ef55fed637 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
@@ -14,13 +14,13 @@ body: |
; CHECK-LABEL: name: merge_unmerge
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:_(s64) = COPY $x0
- %a:_(s32), %b:_(s32) = G_UNMERGE_VALUES %0
- %merge:_(s64) = G_MERGE_VALUES %a, %b
- $x0 = COPY %merge(s64)
+ %0:_(i64) = COPY $x0
+ %a:_(i32), %b:_(i32) = G_UNMERGE_VALUES %0
+ %merge:_(i64) = G_MERGE_VALUES %a, %b
+ $x0 = COPY %merge(i64)
RET_ReallyLR implicit $x0
...
@@ -37,15 +37,15 @@ body: |
; CHECK-LABEL: name: merge_unmerge_mismatched_order
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: %b:_(s32), %a:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK-NEXT: %merge:_(s64) = G_MERGE_VALUES %a(s32), %b(s32)
- ; CHECK-NEXT: $x0 = COPY %merge(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: %b:_(i32), %a:_(i32) = G_UNMERGE_VALUES [[COPY]](i64)
+ ; CHECK-NEXT: %merge:_(i64) = G_MERGE_VALUES %a(i32), %b(i32)
+ ; CHECK-NEXT: $x0 = COPY %merge(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:_(s64) = COPY $x0
- %b:_(s32), %a:_(s32) = G_UNMERGE_VALUES %0
- %merge:_(s64) = G_MERGE_VALUES %a, %b
- $x0 = COPY %merge(s64)
+ %0:_(i64) = COPY $x0
+ %b:_(i32), %a:_(i32) = G_UNMERGE_VALUES %0
+ %merge:_(i64) = G_MERGE_VALUES %a, %b
+ $x0 = COPY %merge(i64)
RET_ReallyLR implicit $x0
...
@@ -62,15 +62,15 @@ body: |
; CHECK-LABEL: name: merge_unmerge_mismatched_num_defs
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
- ; CHECK-NEXT: %a:_(s32), %b:_(s32), %c:_(s32), %d:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK-NEXT: %merge:_(s64) = G_MERGE_VALUES %a(s32), %b(s32)
- ; CHECK-NEXT: $x0 = COPY %merge(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i128) = COPY $q0
+ ; CHECK-NEXT: %a:_(i32), %b:_(i32), %c:_(i32), %d:_(i32) = G_UNMERGE_VALUES [[COPY]](i128)
+ ; CHECK-NEXT: %merge:_(i64) = G_MERGE_VALUES %a(i32), %b(i32)
+ ; CHECK-NEXT: $x0 = COPY %merge(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:_(s128) = COPY $q0
- %a:_(s32), %b:_(s32), %c:_(s32), %d:_(s32) = G_UNMERGE_VALUES %0
- %merge:_(s64) = G_MERGE_VALUES %a, %b
- $x0 = COPY %merge(s64)
+ %0:_(i128) = COPY $q0
+ %a:_(i32), %b:_(i32), %c:_(i32), %d:_(i32) = G_UNMERGE_VALUES %0
+ %merge:_(i64) = G_MERGE_VALUES %a, %b
+ $x0 = COPY %merge(i64)
RET_ReallyLR implicit $x0
...
@@ -87,14 +87,14 @@ body: |
; CHECK-LABEL: name: merge_to_zext
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v:_(s32) = COPY $w0
- ; CHECK-NEXT: %merge:_(s64) = G_ZEXT %v(s32)
- ; CHECK-NEXT: $x0 = COPY %merge(s64)
+ ; CHECK-NEXT: %v:_(i32) = COPY $w0
+ ; CHECK-NEXT: %merge:_(i64) = G_ZEXT %v(i32)
+ ; CHECK-NEXT: $x0 = COPY %merge(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %v:_(s32) = COPY $w0
- %zero:_(s32) = G_CONSTANT i32 0
- %merge:_(s64) = G_MERGE_VALUES %v, %zero
- $x0 = COPY %merge(s64)
+ %v:_(i32) = COPY $w0
+ %zero:_(i32) = G_CONSTANT i32 0
+ %merge:_(i64) = G_MERGE_VALUES %v, %zero
+ $x0 = COPY %merge(i64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
index 5da796c637c97..90af83c768848 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
@@ -14,12 +14,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x0:_(p0) = COPY $x0
- ; CHECK-NEXT: %sextload:_(s32) = G_SEXTLOAD %x0(p0) :: (load (s16))
- ; CHECK-NEXT: $w0 = COPY %sextload(s32)
+ ; CHECK-NEXT: %sextload:_(i32) = G_SEXTLOAD %x0(p0) :: (load (i16))
+ ; CHECK-NEXT: $w0 = COPY %sextload(i32)
%x0:_(p0) = COPY $x0
- %sextload:_(s32) = G_SEXTLOAD %x0:_(p0) :: (load (s16))
- %sext_inreg:_(s32) = G_SEXT_INREG %sextload:_(s32), 24
- $w0 = COPY %sext_inreg(s32)
+ %sextload:_(i32) = G_SEXTLOAD %x0:_(p0) :: (load (i16))
+ %sext_inreg:_(i32) = G_SEXT_INREG %sextload:_(i32), 24
+ $w0 = COPY %sext_inreg(i32)
...
---
name: assert_sext
@@ -34,13 +34,13 @@ body: |
; CHECK-LABEL: name: assert_sext
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %w0:_(s32) = COPY $w0
- ; CHECK-NEXT: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
- ; CHECK-NEXT: $w0 = COPY %assert_sext(s32)
- %w0:_(s32) = COPY $w0
- %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
- %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 24
- $w0 = COPY %sext_inreg(s32)
+ ; CHECK-NEXT: %w0:_(i32) = COPY $w0
+ ; CHECK-NEXT: %assert_sext:_(i32) = G_ASSERT_SEXT %w0, 24
+ ; CHECK-NEXT: $w0 = COPY %assert_sext(i32)
+ %w0:_(i32) = COPY $w0
+ %assert_sext:_(i32) = G_ASSERT_SEXT %w0, 24
+ %sext_inreg:_(i32) = G_SEXT_INREG %assert_sext:_(i32), 24
+ $w0 = COPY %sext_inreg(i32)
...
---
name: assert_sext_greater_width
@@ -55,14 +55,14 @@ body: |
; CHECK-LABEL: name: assert_sext_greater_width
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %w0:_(s32) = COPY $w0
- ; CHECK-NEXT: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
- ; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext, 12
- ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
- %w0:_(s32) = COPY $w0
- %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
- %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 12
- $w0 = COPY %sext_inreg(s32)
+ ; CHECK-NEXT: %w0:_(i32) = COPY $w0
+ ; CHECK-NEXT: %assert_sext:_(i32) = G_ASSERT_SEXT %w0, 24
+ ; CHECK-NEXT: %sext_inreg:_(i32) = G_SEXT_INREG %assert_sext, 12
+ ; CHECK-NEXT: $w0 = COPY %sext_inreg(i32)
+ %w0:_(i32) = COPY $w0
+ %assert_sext:_(i32) = G_ASSERT_SEXT %w0, 24
+ %sext_inreg:_(i32) = G_SEXT_INREG %assert_sext:_(i32), 12
+ $w0 = COPY %sext_inreg(i32)
...
---
name: assert_sext_smaller_width
@@ -77,11 +77,11 @@ body: |
; CHECK-LABEL: name: assert_sext_smaller_width
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %w0:_(s32) = COPY $w0
- ; CHECK-NEXT: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 8
- ; CHECK-NEXT: $w0 = COPY %assert_sext(s32)
- %w0:_(s32) = COPY $w0
- %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 8
- %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 12
- $w0 = COPY %sext_inreg(s32)
+ ; CHECK-NEXT: %w0:_(i32) = COPY $w0
+ ; CHECK-NEXT: %assert_sext:_(i32) = G_ASSERT_SEXT %w0, 8
+ ; CHECK-NEXT: $w0 = COPY %assert_sext(i32)
+ %w0:_(i32) = COPY $w0
+ %assert_sext:_(i32) = G_ASSERT_SEXT %w0, 8
+ %sext_inreg:_(i32) = G_SEXT_INREG %assert_sext:_(i32), 12
+ $w0 = COPY %sext_inreg(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir
index 2d286ede38d5d..c9af72dab2293 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir
@@ -9,22 +9,22 @@ body: |
bb.1:
; CHECK-LABEL: name: crash_fn
; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16), align 8)
- ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16))
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ZEXTLOAD1]], [[ZEXTLOAD]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[C]](p0) :: (load (i16), align 8)
+ ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[C]](p0) :: (load (i16))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ZEXTLOAD1]], [[ZEXTLOAD]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:_(p0) = G_CONSTANT i64 0
- %6:_(s32) = G_CONSTANT i32 0
- %9:_(s1) = G_CONSTANT i1 false
- %0:_(s16) = G_LOAD %1(p0) :: (load (s16), align 8)
- %2:_(s32) = G_ZEXT %0(s16)
- %3:_(s16) = G_LOAD %1(p0) :: (load (s16))
- %4:_(s32) = G_ZEXT %3(s16)
- %5:_(s32) = G_AND %4, %2
- $w0 = COPY %5(s32)
+ %6:_(i32) = G_CONSTANT i32 0
+ %9:_(i1) = G_CONSTANT i1 false
+ %0:_(i16) = G_LOAD %1(p0) :: (load (i16), align 8)
+ %2:_(i32) = G_ZEXT %0(i16)
+ %3:_(i16) = G_LOAD %1(p0) :: (load (i16))
+ %4:_(i32) = G_ZEXT %3(i16)
+ %5:_(i32) = G_AND %4, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir
index 5c6f057a39317..05efb5fa4388f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir
@@ -16,16 +16,16 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %zero:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](i64)
- ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64), align 16)
- ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE %zero(i64), [[COPY]](p0) :: (store (i64), align 16)
+ ; CHECK-NEXT: G_STORE %zero(i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s64) = G_CONSTANT i64 0
- %zerovec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
- G_STORE %zerovec(<2 x s64>), %0(p0) :: (store (<2 x s64>))
+ %zero:_(i64) = G_CONSTANT i64 0
+ %zerovec:_(<2 x i64>) = G_BUILD_VECTOR %zero, %zero
+ G_STORE %zerovec(<2 x i64>), %0(p0) :: (store (<2 x i64>))
RET_ReallyLR
...
@@ -48,9 +48,9 @@ body: |
; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s32) = G_CONSTANT i32 0
- %zerovec:_(<4 x s32>) = G_BUILD_VECTOR %zero, %zero, %zero, %zero
- G_STORE %zerovec(<4 x s32>), %0(p0) :: (store (<4 x s32>))
+ %zero:_(i32) = G_CONSTANT i32 0
+ %zerovec:_(<4 x i32>) = G_BUILD_VECTOR %zero, %zero, %zero, %zero
+ G_STORE %zerovec(<4 x i32>), %0(p0) :: (store (<4 x i32>))
RET_ReallyLR
...
@@ -73,9 +73,9 @@ body: |
; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s16) = G_CONSTANT i16 0
- %zerovec:_(<8 x s16>) = G_BUILD_VECTOR %zero, %zero, %zero, %zero, %zero, %zero, %zero, %zero
- G_STORE %zerovec(<8 x s16>), %0(p0) :: (store (<8 x s16>))
+ %zero:_(i16) = G_CONSTANT i16 0
+ %zerovec:_(<8 x i16>) = G_BUILD_VECTOR %zero, %zero, %zero, %zero, %zero, %zero, %zero, %zero
+ G_STORE %zerovec(<8 x i16>), %0(p0) :: (store (<8 x i16>))
RET_ReallyLR
...
@@ -93,14 +93,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: %zerovec:_(<2 x s32>) = G_BUILD_VECTOR %zero(s32), %zero(s32)
- ; CHECK-NEXT: G_STORE %zerovec(<2 x s32>), [[COPY]](p0) :: (store (<2 x s32>))
+ ; CHECK-NEXT: %zero:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %zerovec:_(<2 x i32>) = G_BUILD_VECTOR %zero(i32), %zero(i32)
+ ; CHECK-NEXT: G_STORE %zerovec(<2 x i32>), [[COPY]](p0) :: (store (<2 x i32>))
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s32) = G_CONSTANT i32 0
- %zerovec:_(<2 x s32>) = G_BUILD_VECTOR %zero, %zero
- G_STORE %zerovec(<2 x s32>), %0(p0) :: (store (<2 x s32>))
+ %zero:_(i32) = G_CONSTANT i32 0
+ %zerovec:_(<2 x i32>) = G_BUILD_VECTOR %zero, %zero
+ G_STORE %zerovec(<2 x i32>), %0(p0) :: (store (<2 x i32>))
RET_ReallyLR
...
@@ -116,15 +116,15 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %zerovec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: G_STORE %zerovec(<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
- ; CHECK-NEXT: $q0 = COPY %zerovec(<2 x s64>)
+ ; CHECK-NEXT: %zero:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %zerovec:_(<2 x i64>) = G_BUILD_VECTOR %zero(i64), %zero(i64)
+ ; CHECK-NEXT: G_STORE %zerovec(<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>))
+ ; CHECK-NEXT: $q0 = COPY %zerovec(<2 x i64>)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s64) = G_CONSTANT i64 0
- %zerovec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
- G_STORE %zerovec(<2 x s64>), %0(p0) :: (store (<2 x s64>))
+ %zero:_(i64) = G_CONSTANT i64 0
+ %zerovec:_(<2 x i64>) = G_BUILD_VECTOR %zero, %zero
+ G_STORE %zerovec(<2 x i64>), %0(p0) :: (store (<2 x i64>))
$q0 = COPY %zerovec
RET_ReallyLR
@@ -141,14 +141,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %zerovec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: G_STORE %zerovec(<2 x s64>), [[COPY]](p0) :: (store (<2 x s32>))
+ ; CHECK-NEXT: %zero:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %zerovec:_(<2 x i64>) = G_BUILD_VECTOR %zero(i64), %zero(i64)
+ ; CHECK-NEXT: G_STORE %zerovec(<2 x i64>), [[COPY]](p0) :: (store (<2 x i32>))
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s64) = G_CONSTANT i64 0
- %zerovec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
- G_STORE %zerovec(<2 x s64>), %0(p0) :: (store (<2 x s32>))
+ %zero:_(i64) = G_CONSTANT i64 0
+ %zerovec:_(<2 x i64>) = G_BUILD_VECTOR %zero, %zero
+ G_STORE %zerovec(<2 x i64>), %0(p0) :: (store (<2 x i32>))
RET_ReallyLR
...
@@ -164,14 +164,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %zerovec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: G_STORE %zerovec(<2 x s64>), [[COPY]](p0) :: (volatile store (<2 x s64>))
+ ; CHECK-NEXT: %zero:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %zerovec:_(<2 x i64>) = G_BUILD_VECTOR %zero(i64), %zero(i64)
+ ; CHECK-NEXT: G_STORE %zerovec(<2 x i64>), [[COPY]](p0) :: (volatile store (<2 x i64>))
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s64) = G_CONSTANT i64 0
- %zerovec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
- G_STORE %zerovec(<2 x s64>), %0(p0) :: (volatile store (<2 x s64>))
+ %zero:_(i64) = G_CONSTANT i64 0
+ %zerovec:_(<2 x i64>) = G_BUILD_VECTOR %zero, %zero
+ G_STORE %zerovec(<2 x i64>), %0(p0) :: (volatile store (<2 x i64>))
RET_ReallyLR
...
@@ -189,12 +189,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: %zero:_(s128) = G_CONSTANT i128 0
- ; CHECK-NEXT: G_STORE %zero(s128), [[COPY]](p0) :: (store (s128))
+ ; CHECK-NEXT: %zero:_(i128) = G_CONSTANT i128 0
+ ; CHECK-NEXT: G_STORE %zero(i128), [[COPY]](p0) :: (store (i128))
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %zero:_(s128) = G_CONSTANT i128 0
- G_STORE %zero(s128), %0(p0) :: (store (s128))
+ %zero:_(i128) = G_CONSTANT i128 0
+ G_STORE %zero(i128), %0(p0) :: (store (i128))
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-undef.mir
index 085a6694995ff..bc65891cec7ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-undef.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-undef.mir
@@ -18,8 +18,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
- %1:_(s32) = G_IMPLICIT_DEF
- G_STORE %1(s32), %0(p0) :: (store (s32))
+ %1:_(i32) = G_IMPLICIT_DEF
+ G_STORE %1(i32), %0(p0) :: (store (i32))
RET_ReallyLR
...
@@ -34,12 +34,12 @@ body: |
; CHECK-LABEL: name: delete_add_undef
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: $x0 = COPY [[DEF]](i64)
; CHECK-NEXT: RET_ReallyLR
- %0:_(s64) = COPY $x0
- %1:_(s64) = G_IMPLICIT_DEF
- %add:_(s64) = G_ADD %0(s64), %1(s64)
+ %0:_(i64) = COPY $x0
+ %1:_(i64) = G_IMPLICIT_DEF
+ %add:_(i64) = G_ADD %0(i64), %1(i64)
$x0 = COPY %add
RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
index 1a9f8ed88ef4b..57d0e93ef4334 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
@@ -7,17 +7,17 @@ legalized: true
body: |
bb.1.entry:
; CHECK-LABEL: name: unmerge_dup8
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<8 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[DUPLANE8_1:%[0-9]+]]:_(<8 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: $d0 = COPY [[DUPLANE8_]](<8 x s8>)
- ; CHECK-NEXT: $d1 = COPY [[DUPLANE8_1]](<8 x s8>)
+ ; CHECK: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<8 x i8>) = G_DUPLANE8 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[DUPLANE8_1:%[0-9]+]]:_(<8 x i8>) = G_DUPLANE8 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[DUPLANE8_]](<8 x i8>)
+ ; CHECK-NEXT: $d1 = COPY [[DUPLANE8_1]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:_(<16 x s8>) = COPY $q0
- %1:_(s64) = G_CONSTANT i64 1
- %2:_(<16 x s8>) = G_DUPLANE8 %0, %1
- %3:_(<8 x s8>), %4:_(<8 x s8>) = G_UNMERGE_VALUES %2
+ %0:_(<16 x i8>) = COPY $q0
+ %1:_(i64) = G_CONSTANT i64 1
+ %2:_(<16 x i8>) = G_DUPLANE8 %0, %1
+ %3:_(<8 x i8>), %4:_(<8 x i8>) = G_UNMERGE_VALUES %2
$d0 = COPY %3
$d1 = COPY %4
RET_ReallyLR implicit $x0
@@ -29,17 +29,17 @@ legalized: true
body: |
bb.1.entry:
; CHECK-LABEL: name: unmerge_dup16
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<4 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[DUPLANE16_1:%[0-9]+]]:_(<4 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: $d0 = COPY [[DUPLANE16_]](<4 x s16>)
- ; CHECK-NEXT: $d1 = COPY [[DUPLANE16_1]](<4 x s16>)
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<4 x i16>) = G_DUPLANE16 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[DUPLANE16_1:%[0-9]+]]:_(<4 x i16>) = G_DUPLANE16 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[DUPLANE16_]](<4 x i16>)
+ ; CHECK-NEXT: $d1 = COPY [[DUPLANE16_1]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:_(<8 x s16>) = COPY $q0
- %1:_(s64) = G_CONSTANT i64 1
- %2:_(<8 x s16>) = G_DUPLANE16 %0, %1
- %3:_(<4 x s16>), %4:_(<4 x s16>) = G_UNMERGE_VALUES %2
+ %0:_(<8 x i16>) = COPY $q0
+ %1:_(i64) = G_CONSTANT i64 1
+ %2:_(<8 x i16>) = G_DUPLANE16 %0, %1
+ %3:_(<4 x i16>), %4:_(<4 x i16>) = G_UNMERGE_VALUES %2
$d0 = COPY %3
$d1 = COPY %4
RET_ReallyLR implicit $x0
@@ -51,17 +51,17 @@ legalized: true
body: |
bb.1.entry:
; CHECK-LABEL: name: unmerge_dup32
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[DUPLANE32_1:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
- ; CHECK-NEXT: $d1 = COPY [[DUPLANE32_1]](<2 x s32>)
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x i32>) = G_DUPLANE32 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[DUPLANE32_1:%[0-9]+]]:_(<2 x i32>) = G_DUPLANE32 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x i32>)
+ ; CHECK-NEXT: $d1 = COPY [[DUPLANE32_1]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(s64) = G_CONSTANT i64 1
- %2:_(<4 x s32>) = G_DUPLANE32 %0, %1
- %3:_(<2 x s32>), %4:_(<2 x s32>) = G_UNMERGE_VALUES %2
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(i64) = G_CONSTANT i64 1
+ %2:_(<4 x i32>) = G_DUPLANE32 %0, %1
+ %3:_(<2 x i32>), %4:_(<2 x i32>) = G_UNMERGE_VALUES %2
$d0 = COPY %3
$d1 = COPY %4
RET_ReallyLR implicit $x0
@@ -73,20 +73,20 @@ legalized: true
body: |
bb.1.entry:
; CHECK-LABEL: name: unmerge_dup64
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](s64)
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x i64>) = G_DUPLANE64 [[COPY]], [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C1]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x i64>), [[C1]](i64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C2]](i64)
- ; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
- ; CHECK-NEXT: $d1 = COPY [[EVEC1]](s64)
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x i64>), [[C2]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[EVEC]](i64)
+ ; CHECK-NEXT: $d1 = COPY [[EVEC1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:_(<2 x s64>) = COPY $q0
- %1:_(s64) = G_CONSTANT i64 1
- %2:_(<2 x s64>) = G_DUPLANE64 %0, %1
- %3:_(s64), %4:_(s64) = G_UNMERGE_VALUES %2
+ %0:_(<2 x i64>) = COPY $q0
+ %1:_(i64) = G_CONSTANT i64 1
+ %2:_(<2 x i64>) = G_DUPLANE64 %0, %1
+ %3:_(i64), %4:_(i64) = G_UNMERGE_VALUES %2
$d0 = COPY %3
$d1 = COPY %4
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
index a86691b30f44d..56c1088c3a580 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
@@ -20,10 +20,10 @@ body: |
; LOWER-LABEL: name: slt_to_sle_s32
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %reg(i32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: slt_to_sle_s32
@@ -34,10 +34,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 4097
- %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 4097
+ %cmp:_(i32) = G_ICMP intpred(slt), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -56,10 +56,10 @@ body: |
; LOWER-LABEL: name: slt_to_sle_s64
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %reg(i64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: slt_to_sle_s64
@@ -70,10 +70,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 4097
- %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 4097
+ %cmp:_(i32) = G_ICMP intpred(slt), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -92,10 +92,10 @@ body: |
; LOWER-LABEL: name: sge_to_sgt_s32
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s32), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sgt), %reg(i32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: sge_to_sgt_s32
@@ -106,10 +106,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 4097
- %cmp:_(s32) = G_ICMP intpred(sge), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 4097
+ %cmp:_(i32) = G_ICMP intpred(sge), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -128,10 +128,10 @@ body: |
; LOWER-LABEL: name: sge_to_sgt_s64
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s64), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sgt), %reg(i64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: sge_to_sgt_s64
@@ -142,10 +142,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 4097
- %cmp:_(s32) = G_ICMP intpred(sge), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 4097
+ %cmp:_(i32) = G_ICMP intpred(sge), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -164,10 +164,10 @@ body: |
; LOWER-LABEL: name: ult_to_ule_s32
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ule), %reg(s32), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(ule), %reg(i32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: ult_to_ule_s32
@@ -178,10 +178,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 4097
- %cmp:_(s32) = G_ICMP intpred(ult), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 4097
+ %cmp:_(i32) = G_ICMP intpred(ult), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -200,10 +200,10 @@ body: |
; LOWER-LABEL: name: ult_to_ule_s64
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ule), %reg(s64), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(ule), %reg(i64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: ult_to_ule_s64
@@ -214,10 +214,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 4097
- %cmp:_(s32) = G_ICMP intpred(ult), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 4097
+ %cmp:_(i32) = G_ICMP intpred(ult), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -236,10 +236,10 @@ body: |
; LOWER-LABEL: name: uge_to_ugt_s32
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ugt), %reg(s32), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(ugt), %reg(i32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: uge_to_ugt_s32
@@ -250,10 +250,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 4097
- %cmp:_(s32) = G_ICMP intpred(uge), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 4097
+ %cmp:_(i32) = G_ICMP intpred(uge), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -272,10 +272,10 @@ body: |
; LOWER-LABEL: name: uge_to_ugt_s64
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ugt), %reg(s64), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(ugt), %reg(i64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: uge_to_ugt_s64
@@ -286,10 +286,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 4097
- %cmp:_(s32) = G_ICMP intpred(uge), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 4097
+ %cmp:_(i32) = G_ICMP intpred(uge), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -309,10 +309,10 @@ body: |
; LOWER-LABEL: name: sle_to_slt_s32
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8192
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8192
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %reg(i32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: sle_to_slt_s32
@@ -323,10 +323,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 8191
- %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 8191
+ %cmp:_(i32) = G_ICMP intpred(sle), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -345,10 +345,10 @@ body: |
; LOWER-LABEL: name: sle_to_slt_s64
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8192
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8192
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %reg(i64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: sle_to_slt_s64
@@ -359,10 +359,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 8191
- %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 8191
+ %cmp:_(i32) = G_ICMP intpred(sle), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -381,10 +381,10 @@ body: |
; LOWER-LABEL: name: sgt_to_sge_s32
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8192
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %reg(s32), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8192
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sge), %reg(i32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: sgt_to_sge_s32
@@ -395,10 +395,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 8191
- %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 8191
+ %cmp:_(i32) = G_ICMP intpred(sgt), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -417,10 +417,10 @@ body: |
; LOWER-LABEL: name: sgt_to_sge_s64
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8192
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %reg(s64), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8192
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sge), %reg(i64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: sgt_to_sge_s64
@@ -431,10 +431,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 8191
- %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 8191
+ %cmp:_(i32) = G_ICMP intpred(sgt), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -455,10 +455,10 @@ body: |
; LOWER-LABEL: name: no_opt_int32_min
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 -2147483648
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), %cst
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 -2147483648
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %reg(i32), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: no_opt_int32_min
@@ -470,10 +470,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 -2147483648
- %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 -2147483648
+ %cmp:_(i32) = G_ICMP intpred(slt), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -494,10 +494,10 @@ body: |
; LOWER-LABEL: name: no_opt_int64_min
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 -9223372036854775808
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), %cst
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %reg(i64), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: no_opt_int64_min
@@ -509,10 +509,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 -9223372036854775808
- %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 -9223372036854775808
+ %cmp:_(i32) = G_ICMP intpred(slt), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -533,10 +533,10 @@ body: |
; LOWER-LABEL: name: no_opt_int32_max
; LOWER: liveins: $w0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s32) = COPY $w0
- ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 2147483647
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), %cst
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i32) = COPY $w0
+ ; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 2147483647
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %reg(i32), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: no_opt_int32_max
@@ -548,10 +548,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 2147483647
- %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 2147483647
+ %cmp:_(i32) = G_ICMP intpred(sle), %reg(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -573,10 +573,10 @@ body: |
; LOWER-LABEL: name: no_opt_int64_max
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 9223372036854775807
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), %cst
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %reg(i64), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: no_opt_int64_max
@@ -588,10 +588,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 9223372036854775807
- %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 9223372036854775807
+ %cmp:_(i32) = G_ICMP intpred(sle), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -612,10 +612,10 @@ body: |
; LOWER-LABEL: name: no_opt_zero
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 0
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ult), %reg(s64), %cst
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(ult), %reg(i64), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: no_opt_zero
@@ -626,10 +626,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 0
- %cmp:_(s32) = G_ICMP intpred(ult), %reg(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 0
+ %cmp:_(i32) = G_ICMP intpred(ult), %reg(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -647,12 +647,12 @@ body: |
; LOWER-LABEL: name: cmp_and_select
; LOWER: liveins: $w0, $w1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg0:_(s32) = COPY $w0
- ; LOWER-NEXT: %reg1:_(s32) = COPY $w1
- ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 -1
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg0(s32), %cst
- ; LOWER-NEXT: %select:_(s32) = G_SELECT %cmp(s32), %reg0, %reg1
- ; LOWER-NEXT: $w0 = COPY %select(s32)
+ ; LOWER-NEXT: %reg0:_(i32) = COPY $w0
+ ; LOWER-NEXT: %reg1:_(i32) = COPY $w1
+ ; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 -1
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %reg0(i32), %cst
+ ; LOWER-NEXT: %select:_(i32) = G_SELECT %cmp(i32), %reg0, %reg1
+ ; LOWER-NEXT: $w0 = COPY %select(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: cmp_and_select
@@ -664,12 +664,12 @@ body: |
; SELECT-NEXT: %select:gpr32 = CSELWr %reg0, %reg1, 13, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %select
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg0:_(s32) = COPY $w0
- %reg1:_(s32) = COPY $w1
- %cst:_(s32) = G_CONSTANT i32 -1
- %cmp:_(s32) = G_ICMP intpred(sle), %reg0(s32), %cst
- %select:_(s32) = G_SELECT %cmp, %reg0, %reg1
- $w0 = COPY %select(s32)
+ %reg0:_(i32) = COPY $w0
+ %reg1:_(i32) = COPY $w1
+ %cst:_(i32) = G_CONSTANT i32 -1
+ %cmp:_(i32) = G_ICMP intpred(sle), %reg0(i32), %cst
+ %select:_(i32) = G_SELECT %cmp, %reg0, %reg1
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -686,12 +686,12 @@ body: |
; LOWER-LABEL: name: andsxri
; LOWER: liveins: $x0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg0:gpr(s64) = COPY $x0
- ; LOWER-NEXT: %bit:gpr(s64) = G_CONSTANT i64 8
- ; LOWER-NEXT: %and:gpr(s64) = G_AND %reg0, %bit
- ; LOWER-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
- ; LOWER-NEXT: %cmp:gpr(s32) = G_ICMP intpred(sge), %and(s64), [[C]]
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg0:gpr(i64) = COPY $x0
+ ; LOWER-NEXT: %bit:gpr(i64) = G_CONSTANT i64 8
+ ; LOWER-NEXT: %and:gpr(i64) = G_AND %reg0, %bit
+ ; LOWER-NEXT: [[C:%[0-9]+]]:gpr(i64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cmp:gpr(i32) = G_ICMP intpred(sge), %and(i64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: andsxri
@@ -702,10 +702,10 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %and:gpr(s64) = G_AND %reg0, %bit
- %cst:gpr(s64) = G_CONSTANT i64 -1
- %cmp:gpr(s32) = G_ICMP intpred(sgt), %and(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %and:gpr(i64) = G_AND %reg0, %bit
+ %cst:gpr(i64) = G_CONSTANT i64 -1
+ %cmp:gpr(i32) = G_ICMP intpred(sgt), %and(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
index 35cc62293200b..45e7bde34661c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
@@ -15,16 +15,16 @@ body: |
; CHECK-LABEL: name: v8s8_cst3
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: %v1:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: %v2:_(<8 x i8>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v1, %v2, [[C]](i32)
- ; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
+ ; CHECK-NEXT: %shuf:_(<8 x i8>) = G_EXT %v1, %v2, [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %v1:_(<8 x s8>) = COPY $d0
- %v2:_(<8 x s8>) = COPY $d1
- %shuf:_(<8 x s8>) = G_SHUFFLE_VECTOR %v1(<8 x s8>), %v2, shufflemask(3, 4, 5, 6, 7, 8, 9, 10)
- $d0 = COPY %shuf(<8 x s8>)
+ %v1:_(<8 x i8>) = COPY $d0
+ %v2:_(<8 x i8>) = COPY $d1
+ %shuf:_(<8 x i8>) = G_SHUFFLE_VECTOR %v1(<8 x i8>), %v2, shufflemask(3, 4, 5, 6, 7, 8, 9, 10)
+ $d0 = COPY %shuf(<8 x i8>)
RET_ReallyLR implicit $d0
...
---
@@ -38,16 +38,16 @@ body: |
; CHECK-LABEL: name: v8s8_cst5
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: %v1:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: %v2:_(<8 x i8>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v2, %v1, [[C]](i32)
- ; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
+ ; CHECK-NEXT: %shuf:_(<8 x i8>) = G_EXT %v2, %v1, [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %v1:_(<8 x s8>) = COPY $d0
- %v2:_(<8 x s8>) = COPY $d1
- %shuf:_(<8 x s8>) = G_SHUFFLE_VECTOR %v1(<8 x s8>), %v2, shufflemask(13, 14, 15, 0, 1, 2, 3, 4)
- $d0 = COPY %shuf(<8 x s8>)
+ %v1:_(<8 x i8>) = COPY $d0
+ %v2:_(<8 x i8>) = COPY $d1
+ %shuf:_(<8 x i8>) = G_SHUFFLE_VECTOR %v1(<8 x i8>), %v2, shufflemask(13, 14, 15, 0, 1, 2, 3, 4)
+ $d0 = COPY %shuf(<8 x i8>)
RET_ReallyLR implicit $d0
...
---
@@ -61,16 +61,16 @@ body: |
; CHECK-LABEL: name: v16s8_cst3
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: %v2:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: %v1:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: %v2:_(<16 x i8>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v1, %v2, [[C]](i32)
- ; CHECK-NEXT: $q0 = COPY %shuf(<16 x s8>)
+ ; CHECK-NEXT: %shuf:_(<16 x i8>) = G_EXT %v1, %v2, [[C]](i32)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<16 x s8>) = COPY $q0
- %v2:_(<16 x s8>) = COPY $q1
- %shuf:_(<16 x s8>) = G_SHUFFLE_VECTOR %v1(<16 x s8>), %v2, shufflemask(3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
- $q0 = COPY %shuf(<16 x s8>)
+ %v1:_(<16 x i8>) = COPY $q0
+ %v2:_(<16 x i8>) = COPY $q1
+ %shuf:_(<16 x i8>) = G_SHUFFLE_VECTOR %v1(<16 x i8>), %v2, shufflemask(3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
+ $q0 = COPY %shuf(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -84,16 +84,16 @@ body: |
; CHECK-LABEL: name: v16s8_cst7
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: %v2:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: %v1:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: %v2:_(<16 x i8>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
- ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v2, %v1, [[C]](i32)
- ; CHECK-NEXT: $q0 = COPY %shuf(<16 x s8>)
+ ; CHECK-NEXT: %shuf:_(<16 x i8>) = G_EXT %v2, %v1, [[C]](i32)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<16 x s8>) = COPY $q0
- %v2:_(<16 x s8>) = COPY $q1
- %shuf:_(<16 x s8>) = G_SHUFFLE_VECTOR %v1(<16 x s8>), %v2, shufflemask(23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 1, 2, 3, 4, 5, 6)
- $q0 = COPY %shuf(<16 x s8>)
+ %v1:_(<16 x i8>) = COPY $q0
+ %v2:_(<16 x i8>) = COPY $q1
+ %shuf:_(<16 x i8>) = G_SHUFFLE_VECTOR %v1(<16 x i8>), %v2, shufflemask(23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 1, 2, 3, 4, 5, 6)
+ $q0 = COPY %shuf(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -107,16 +107,16 @@ body: |
; CHECK-LABEL: name: v4s16_cst6
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: %v2:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: %v1:_(<4 x i16>) = COPY $d0
+ ; CHECK-NEXT: %v2:_(<4 x i16>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
- ; CHECK-NEXT: %shuf:_(<4 x s16>) = G_EXT %v1, %v2, [[C]](i32)
- ; CHECK-NEXT: $d0 = COPY %shuf(<4 x s16>)
+ ; CHECK-NEXT: %shuf:_(<4 x i16>) = G_EXT %v1, %v2, [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %v1:_(<4 x s16>) = COPY $d0
- %v2:_(<4 x s16>) = COPY $d1
- %shuf:_(<4 x s16>) = G_SHUFFLE_VECTOR %v1(<4 x s16>), %v2, shufflemask(3, 4, 5, 6)
- $d0 = COPY %shuf(<4 x s16>)
+ %v1:_(<4 x i16>) = COPY $d0
+ %v2:_(<4 x i16>) = COPY $d1
+ %shuf:_(<4 x i16>) = G_SHUFFLE_VECTOR %v1(<4 x i16>), %v2, shufflemask(3, 4, 5, 6)
+ $d0 = COPY %shuf(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -130,16 +130,16 @@ body: |
; CHECK-LABEL: name: v4s32_cst12
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: %v2:_(<4 x s32>) = COPY $q1
+ ; CHECK-NEXT: %v1:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: %v2:_(<4 x i32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_EXT %v1, %v2, [[C]](i32)
- ; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
+ ; CHECK-NEXT: %shuf:_(<4 x i32>) = G_EXT %v1, %v2, [[C]](i32)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<4 x s32>) = COPY $q0
- %v2:_(<4 x s32>) = COPY $q1
- %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %v1(<4 x s32>), %v2, shufflemask(3, 4, 5, 6)
- $q0 = COPY %shuf(<4 x s32>)
+ %v1:_(<4 x i32>) = COPY $q0
+ %v2:_(<4 x i32>) = COPY $q1
+ %shuf:_(<4 x i32>) = G_SHUFFLE_VECTOR %v1(<4 x i32>), %v2, shufflemask(3, 4, 5, 6)
+ $q0 = COPY %shuf(<4 x i32>)
RET_ReallyLR implicit $q0
...
---
@@ -155,16 +155,16 @@ body: |
; CHECK-LABEL: name: undef_elts_should_match_1
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: %v1:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: %v2:_(<8 x i8>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v1, %v2, [[C]](i32)
- ; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
+ ; CHECK-NEXT: %shuf:_(<8 x i8>) = G_EXT %v1, %v2, [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %v1:_(<8 x s8>) = COPY $d0
- %v2:_(<8 x s8>) = COPY $d1
- %shuf:_(<8 x s8>) = G_SHUFFLE_VECTOR %v1(<8 x s8>), %v2, shufflemask(3, -1, -1, 6, 7, 8, 9, 10)
- $d0 = COPY %shuf(<8 x s8>)
+ %v1:_(<8 x i8>) = COPY $d0
+ %v2:_(<8 x i8>) = COPY $d1
+ %shuf:_(<8 x i8>) = G_SHUFFLE_VECTOR %v1(<8 x i8>), %v2, shufflemask(3, -1, -1, 6, 7, 8, 9, 10)
+ $d0 = COPY %shuf(<8 x i8>)
RET_ReallyLR implicit $d0
...
---
@@ -180,16 +180,16 @@ body: |
; CHECK-LABEL: name: undef_elts_should_match_2
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: %v1:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: %v2:_(<8 x i8>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v2, %v1, [[C]](i32)
- ; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
+ ; CHECK-NEXT: %shuf:_(<8 x i8>) = G_EXT %v2, %v1, [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %v1:_(<8 x s8>) = COPY $d0
- %v2:_(<8 x s8>) = COPY $d1
- %shuf:_(<8 x s8>) = G_SHUFFLE_VECTOR %v1(<8 x s8>), %v2, shufflemask(-1, -1, -1, -1, 2, 3, 4, 5)
- $d0 = COPY %shuf(<8 x s8>)
+ %v1:_(<8 x i8>) = COPY $d0
+ %v2:_(<8 x i8>) = COPY $d1
+ %shuf:_(<8 x i8>) = G_SHUFFLE_VECTOR %v1(<8 x i8>), %v2, shufflemask(-1, -1, -1, -1, 2, 3, 4, 5)
+ $d0 = COPY %shuf(<8 x i8>)
RET_ReallyLR implicit $d0
...
---
@@ -205,16 +205,16 @@ body: |
; CHECK-LABEL: name: undef_elts_should_match_3
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: %v2:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: %v1:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: %v2:_(<16 x i8>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
- ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v2, %v1, [[C]](i32)
- ; CHECK-NEXT: $q0 = COPY %shuf(<16 x s8>)
+ ; CHECK-NEXT: %shuf:_(<16 x i8>) = G_EXT %v2, %v1, [[C]](i32)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<16 x s8>) = COPY $q0
- %v2:_(<16 x s8>) = COPY $q1
- %shuf:_(<16 x s8>) = G_SHUFFLE_VECTOR %v1(<16 x s8>), %v2, shufflemask(23, 24, 25, 26, -1, -1, 29, 30, 31, 0, 1, 2, 3, 4, -1, 6)
- $q0 = COPY %shuf(<16 x s8>)
+ %v1:_(<16 x i8>) = COPY $q0
+ %v2:_(<16 x i8>) = COPY $q1
+ %shuf:_(<16 x i8>) = G_SHUFFLE_VECTOR %v1(<16 x i8>), %v2, shufflemask(23, 24, 25, 26, -1, -1, 29, 30, 31, 0, 1, 2, 3, 4, -1, 6)
+ $q0 = COPY %shuf(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -230,16 +230,16 @@ body: |
; CHECK-LABEL: name: undef_elts_should_match_4
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: %v2:_(<8 x s16>) = COPY $q1
+ ; CHECK-NEXT: %v1:_(<8 x i16>) = COPY $q0
+ ; CHECK-NEXT: %v2:_(<8 x i16>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
- ; CHECK-NEXT: %shuf:_(<8 x s16>) = G_EXT %v2, %v1, [[C]](i32)
- ; CHECK-NEXT: $q0 = COPY %shuf(<8 x s16>)
+ ; CHECK-NEXT: %shuf:_(<8 x i16>) = G_EXT %v2, %v1, [[C]](i32)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<8 x s16>) = COPY $q0
- %v2:_(<8 x s16>) = COPY $q1
- %shuf:_(<8 x s16>) = G_SHUFFLE_VECTOR %v1(<8 x s16>), %v2, shufflemask(-1, -1, -1, -1, 1, 2, 3, 4)
- $q0 = COPY %shuf(<8 x s16>)
+ %v1:_(<8 x i16>) = COPY $q0
+ %v2:_(<8 x i16>) = COPY $q1
+ %shuf:_(<8 x i16>) = G_SHUFFLE_VECTOR %v1(<8 x i16>), %v2, shufflemask(-1, -1, -1, -1, 1, 2, 3, 4)
+ $q0 = COPY %shuf(<8 x i16>)
RET_ReallyLR implicit $q0
...
---
@@ -254,15 +254,15 @@ body: |
; CHECK-LABEL: name: all_undef
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<8 x s16>) = COPY $q0
+ ; CHECK-NEXT: %v1:_(<8 x i16>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<8 x s16>) = G_DUPLANE16 %v1, [[C]](i64)
- ; CHECK-NEXT: $q0 = COPY %shuf(<8 x s16>)
+ ; CHECK-NEXT: %shuf:_(<8 x i16>) = G_DUPLANE16 %v1, [[C]](i64)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<8 x s16>) = COPY $q0
- %v2:_(<8 x s16>) = COPY $q1
- %shuf:_(<8 x s16>) = G_SHUFFLE_VECTOR %v1(<8 x s16>), %v2, shufflemask(-1, -1, -1, -1, -1, -1, -1, -1)
- $q0 = COPY %shuf(<8 x s16>)
+ %v1:_(<8 x i16>) = COPY $q0
+ %v2:_(<8 x i16>) = COPY $q1
+ %shuf:_(<8 x i16>) = G_SHUFFLE_VECTOR %v1(<8 x i16>), %v2, shufflemask(-1, -1, -1, -1, -1, -1, -1, -1)
+ $q0 = COPY %shuf(<8 x i16>)
RET_ReallyLR implicit $q0
...
---
@@ -276,15 +276,15 @@ body: |
; CHECK-LABEL: name: v2s64_singleton_ext
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: %v1:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
- ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_EXT %v1, %v1, [[C]](i32)
- ; CHECK-NEXT: $q0 = COPY %shuf(<2 x s64>)
+ ; CHECK-NEXT: %shuf:_(<2 x i64>) = G_EXT %v1, %v1, [[C]](i32)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<2 x s64>) = COPY $q0
- %v2:_(<2 x s64>) = G_IMPLICIT_DEF
- %shuf:_(<2 x s64>) = G_SHUFFLE_VECTOR %v1(<2 x s64>), %v2, shufflemask(1, 0)
- $q0 = COPY %shuf(<2 x s64>)
+ %v1:_(<2 x i64>) = COPY $q0
+ %v2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %shuf:_(<2 x i64>) = G_SHUFFLE_VECTOR %v1(<2 x i64>), %v2, shufflemask(1, 0)
+ $q0 = COPY %shuf(<2 x i64>)
RET_ReallyLR implicit $q0
...
---
@@ -298,15 +298,15 @@ body: |
; CHECK-LABEL: name: v2s64_singleton_ext_all_undef
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: %v1:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_DUPLANE64 %v1, [[C]](i64)
- ; CHECK-NEXT: $q0 = COPY %shuf(<2 x s64>)
+ ; CHECK-NEXT: %shuf:_(<2 x i64>) = G_DUPLANE64 %v1, [[C]](i64)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<2 x s64>) = COPY $q0
- %v2:_(<2 x s64>) = G_IMPLICIT_DEF
- %shuf:_(<2 x s64>) = G_SHUFFLE_VECTOR %v1(<2 x s64>), %v2, shufflemask(undef, undef)
- $q0 = COPY %shuf(<2 x s64>)
+ %v1:_(<2 x i64>) = COPY $q0
+ %v2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %shuf:_(<2 x i64>) = G_SHUFFLE_VECTOR %v1(<2 x i64>), %v2, shufflemask(undef, undef)
+ $q0 = COPY %shuf(<2 x i64>)
RET_ReallyLR implicit $q0
...
---
@@ -320,14 +320,14 @@ body: |
; CHECK-LABEL: name: v2s64_singleton_ext_same
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: %v1:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_DUPLANE64 %v1, [[C]](i64)
- ; CHECK-NEXT: $q0 = COPY %shuf(<2 x s64>)
+ ; CHECK-NEXT: %shuf:_(<2 x i64>) = G_DUPLANE64 %v1, [[C]](i64)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<2 x s64>) = COPY $q0
- %v2:_(<2 x s64>) = G_IMPLICIT_DEF
- %shuf:_(<2 x s64>) = G_SHUFFLE_VECTOR %v1(<2 x s64>), %v2, shufflemask(1, 1)
- $q0 = COPY %shuf(<2 x s64>)
+ %v1:_(<2 x i64>) = COPY $q0
+ %v2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %shuf:_(<2 x i64>) = G_SHUFFLE_VECTOR %v1(<2 x i64>), %v2, shufflemask(1, 1)
+ $q0 = COPY %shuf(<2 x i64>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
index bdd633076d49c..74e940266776c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
@@ -16,14 +16,14 @@ body: |
; CHECK-LABEL: name: rev64_mask_1_0
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[REV64_:%[0-9]+]]:_(<2 x s32>) = G_REV64 [[COPY]]
- ; CHECK-NEXT: $d0 = COPY [[REV64_]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[REV64_:%[0-9]+]]:_(<2 x i32>) = G_REV64 [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY [[REV64_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0)
- $d0 = COPY %2(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(1, 0)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -38,17 +38,17 @@ body: |
; CHECK-LABEL: name: rev64_mask_1_undef
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY]](<2 x s32>), [[DEF]](<2 x s32>)
- ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](i64)
- ; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x i32>) = G_CONCAT_VECTORS [[COPY]](<2 x i32>), [[DEF]](<2 x i32>)
+ ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x i32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, undef)
- $d0 = COPY %2(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(1, undef)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -74,13 +74,13 @@ body: |
; CHECK-LABEL: name: no_rev64_mask_1
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x s32>) = G_ZIP2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[ZIP2_]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x i32>) = G_ZIP2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[ZIP2_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 3)
- $d0 = COPY %2(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(1, 3)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir
index 76d4d29102cc1..65d8d96dd2e1b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir
@@ -10,15 +10,15 @@ body: |
; CHECK-LABEL: name: v4s32
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x s32>) = G_DUP [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL %v1, [[DUP]](<4 x s32>)
- ; CHECK-NEXT: %sext:_(<4 x s32>) = G_VASHR [[SHL]], 16
- ; CHECK-NEXT: $q0 = COPY %sext(<4 x s32>)
+ ; CHECK-NEXT: %v1:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x i32>) = G_DUP [[C]](i32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x i32>) = G_SHL %v1, [[DUP]](<4 x i32>)
+ ; CHECK-NEXT: %sext:_(<4 x i32>) = G_VASHR [[SHL]], 16
+ ; CHECK-NEXT: $q0 = COPY %sext(<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<4 x s32>) = COPY $q0
- %sext:_(<4 x s32>) = G_SEXT_INREG %v1, 16
+ %v1:_(<4 x i32>) = COPY $q0
+ %sext:_(<4 x i32>) = G_SEXT_INREG %v1, 16
$q0 = COPY %sext
RET_ReallyLR implicit $q0
...
@@ -31,12 +31,12 @@ body: |
; CHECK-LABEL: name: scalar_no_lower
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(s64) = COPY $x0
- ; CHECK-NEXT: %sext:_(s64) = G_SEXT_INREG %v1, 16
- ; CHECK-NEXT: $x0 = COPY %sext(s64)
+ ; CHECK-NEXT: %v1:_(i64) = COPY $x0
+ ; CHECK-NEXT: %sext:_(i64) = G_SEXT_INREG %v1, 16
+ ; CHECK-NEXT: $x0 = COPY %sext(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %v1:_(s64) = COPY $x0
- %sext:_(s64) = G_SEXT_INREG %v1, 16
+ %v1:_(i64) = COPY $x0
+ %sext:_(i64) = G_SEXT_INREG %v1, 16
$x0 = COPY %sext
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
index 31d7a3f23a127..643ad10a2ec6b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
@@ -22,17 +22,17 @@ body: |
; CHECK-LABEL: name: v2s32_match_left_0
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %left(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(0, 0)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(0, 0)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -52,17 +52,17 @@ body: |
; CHECK-LABEL: name: v2s32_match_left_1
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %left(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(1, 1)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(1, 1)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -82,18 +82,18 @@ body: |
; CHECK-LABEL: name: v2s32_match_left_3
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %right:_(<2 x i32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %right(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(0, 3)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(0, 3)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
@@ -114,18 +114,18 @@ body: |
; CHECK-LABEL: name: v2s32_match_right_3
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %right:_(<2 x i32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %left(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(1, 3)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(1, 3)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -145,18 +145,18 @@ body: |
; CHECK-LABEL: name: v2s32_match_right_2
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %right:_(<2 x i32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %left(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 0)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(2, 0)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -174,15 +174,15 @@ body: |
; CHECK-LABEL: name: dont_combine_too_many_matches_right
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 3)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %right:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(2, 3)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 3)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(2, 3)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -203,18 +203,18 @@ body: |
; CHECK-LABEL: name: tiebreaker
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %right:_(<2 x i32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %right(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 1)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(2, 1)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -234,18 +234,18 @@ body: |
; CHECK-LABEL: name: tiebreaker_undef
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %right:_(<2 x i32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %right(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, -1)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(2, -1)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -265,18 +265,18 @@ body: |
; CHECK-LABEL: name: match_left_undef
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: %left:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: %right:_(<2 x i32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %right(<2 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
+ ; CHECK-NEXT: %shuf:_(<2 x i32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $d0 = COPY %shuf(<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %left:_(<2 x s32>) = COPY $d0
- %right:_(<2 x s32>) = COPY $d1
- %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(3, -1)
- $d0 = COPY %shuf(<2 x s32>)
+ %left:_(<2 x i32>) = COPY $d0
+ %right:_(<2 x i32>) = COPY $d1
+ %shuf:_(<2 x i32>) = G_SHUFFLE_VECTOR %left(<2 x i32>), %right, shufflemask(3, -1)
+ $d0 = COPY %shuf(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -295,16 +295,16 @@ body: |
; CHECK-LABEL: name: match_right_undef
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %left:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: %right:_(<4 x s32>) = COPY $q1
+ ; CHECK-NEXT: %left:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: %right:_(<4 x i32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT %left(<4 x i32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
- ; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
+ ; CHECK-NEXT: %shuf:_(<4 x i32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](i32), [[C1]](i64)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %left:_(<4 x s32>) = COPY $q0
- %right:_(<4 x s32>) = COPY $q1
- %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %left(<4 x s32>), %right, shufflemask(4, -1, -1, 2)
- $q0 = COPY %shuf(<4 x s32>)
+ %left:_(<4 x i32>) = COPY $q0
+ %right:_(<4 x i32>) = COPY $q1
+ %shuf:_(<4 x i32>) = G_SHUFFLE_VECTOR %left(<4 x i32>), %right, shufflemask(4, -1, -1, 2)
+ $q0 = COPY %shuf(<4 x i32>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
index 5297ecd7019bb..a94f2ac13f3de 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
@@ -14,10 +14,10 @@ body: |
; CHECK-LABEL: name: duplane64
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](i64)
- ; CHECK-NEXT: $q0 = COPY [[DUPLANE64_]](<2 x s64>)
+ ; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x i64>) = G_DUPLANE64 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUPLANE64_]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
; SELECTED-LABEL: name: duplane64
@@ -27,10 +27,10 @@ body: |
; SELECTED-NEXT: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY]], 0
; SELECTED-NEXT: $q0 = COPY [[DUPv2i64lane]]
; SELECTED-NEXT: RET_ReallyLR implicit $q0
- %1:_(<2 x s64>) = COPY $q0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0)
- $q0 = COPY %4(<2 x s64>)
+ %1:_(<2 x i64>) = COPY $q0
+ %2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %4:_(<2 x i64>) = G_SHUFFLE_VECTOR %1(<2 x i64>), %2, shufflemask(0, 0)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -46,10 +46,10 @@ body: |
; CHECK-LABEL: name: duplane32
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<4 x s32>) = G_DUPLANE32 [[COPY]], [[C]](i64)
- ; CHECK-NEXT: $q0 = COPY [[DUPLANE32_]](<4 x s32>)
+ ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<4 x i32>) = G_DUPLANE32 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUPLANE32_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
; SELECTED-LABEL: name: duplane32
@@ -59,10 +59,10 @@ body: |
; SELECTED-NEXT: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY]], 0
; SELECTED-NEXT: $q0 = COPY [[DUPv4i32lane]]
; SELECTED-NEXT: RET_ReallyLR implicit $q0
- %1:_(<4 x s32>) = COPY $q0
- %2:_(<4 x s32>) = G_IMPLICIT_DEF
- %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0)
- $q0 = COPY %4(<4 x s32>)
+ %1:_(<4 x i32>) = COPY $q0
+ %2:_(<4 x i32>) = G_IMPLICIT_DEF
+ %4:_(<4 x i32>) = G_SHUFFLE_VECTOR %1(<4 x i32>), %2, shufflemask(0, 0, 0, 0)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -78,10 +78,10 @@ body: |
; CHECK-LABEL: name: duplane16
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<8 x s16>) = G_DUPLANE16 [[COPY]], [[C]](i64)
- ; CHECK-NEXT: $q0 = COPY [[DUPLANE16_]](<8 x s16>)
+ ; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<8 x i16>) = G_DUPLANE16 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUPLANE16_]](<8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
; SELECTED-LABEL: name: duplane16
@@ -91,10 +91,10 @@ body: |
; SELECTED-NEXT: [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY]], 0
; SELECTED-NEXT: $q0 = COPY [[DUPv8i16lane]]
; SELECTED-NEXT: RET_ReallyLR implicit $q0
- %1:_(<8 x s16>) = COPY $q0
- %2:_(<8 x s16>) = G_IMPLICIT_DEF
- %4:_(<8 x s16>) = G_SHUFFLE_VECTOR %1(<8 x s16>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
- $q0 = COPY %4(<8 x s16>)
+ %1:_(<8 x i16>) = COPY $q0
+ %2:_(<8 x i16>) = G_IMPLICIT_DEF
+ %4:_(<8 x i16>) = G_SHUFFLE_VECTOR %1(<8 x i16>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ $q0 = COPY %4(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -110,10 +110,10 @@ body: |
; CHECK-LABEL: name: duplane8
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<16 x s8>) = G_DUPLANE8 [[COPY]], [[C]](i64)
- ; CHECK-NEXT: $q0 = COPY [[DUPLANE8_]](<16 x s8>)
+ ; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<16 x i8>) = G_DUPLANE8 [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUPLANE8_]](<16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
; SELECTED-LABEL: name: duplane8
@@ -123,10 +123,10 @@ body: |
; SELECTED-NEXT: [[DUPv16i8lane:%[0-9]+]]:fpr128 = DUPv16i8lane [[COPY]], 0
; SELECTED-NEXT: $q0 = COPY [[DUPv16i8lane]]
; SELECTED-NEXT: RET_ReallyLR implicit $q0
- %1:_(<16 x s8>) = COPY $q0
- %2:_(<16 x s8>) = G_IMPLICIT_DEF
- %4:_(<16 x s8>) = G_SHUFFLE_VECTOR %1(<16 x s8>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
- $q0 = COPY %4(<16 x s8>)
+ %1:_(<16 x i8>) = COPY $q0
+ %2:_(<16 x i8>) = G_IMPLICIT_DEF
+ %4:_(<16 x i8>) = G_SHUFFLE_VECTOR %1(<16 x i8>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ $q0 = COPY %4(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -148,13 +148,13 @@ body: |
; CHECK-LABEL: name: v2s32_duplane32
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY1]](<2 x s32>), [[DEF]](<2 x s32>)
- ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](i64)
- ; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x i32>) = G_CONCAT_VECTORS [[COPY1]](<2 x i32>), [[DEF]](<2 x i32>)
+ ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x i32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
;
; SELECTED-LABEL: name: v2s32_duplane32
@@ -166,11 +166,11 @@ body: |
; SELECTED-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; SELECTED-NEXT: $d0 = COPY [[DUPv2i32lane]]
; SELECTED-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_IMPLICIT_DEF
- %3:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0)
- $d0 = COPY %3(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_IMPLICIT_DEF
+ %3:_(<2 x i32>) = G_SHUFFLE_VECTOR %1(<2 x i32>), %2, shufflemask(0, 0)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
index 650a4fb8a8232..8e20fff540d4e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
@@ -13,16 +13,16 @@ body: |
; CHECK-LABEL: name: splat_4xi32
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x s32>) = G_DUP [[COPY]](s32)
- ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x i32>) = G_DUP [[COPY]](i32)
+ ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s32) = COPY $w0
- %2:_(<4 x s32>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64)
- %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0)
- $q0 = COPY %4(<4 x s32>)
+ %0:_(i32) = COPY $w0
+ %2:_(<4 x i32>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<4 x i32>) = G_INSERT_VECTOR_ELT %2, %0(i32), %3(i64)
+ %4:_(<4 x i32>) = G_SHUFFLE_VECTOR %1(<4 x i32>), %2, shufflemask(0, 0, 0, 0)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -38,16 +38,16 @@ body: |
; CHECK-LABEL: name: splat_2xi64
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x s64>) = G_DUP [[COPY]](s64)
- ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x i64>) = G_DUP [[COPY]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s64) = COPY $x0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64)
- %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0)
- $q0 = COPY %4(<2 x s64>)
+ %0:_(i64) = COPY $x0
+ %2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x i64>) = G_INSERT_VECTOR_ELT %2, %0(i64), %3(i64)
+ %4:_(<2 x i64>) = G_SHUFFLE_VECTOR %1(<2 x i64>), %2, shufflemask(0, 0)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -63,16 +63,16 @@ body: |
; CHECK-LABEL: name: splat_2xi32
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x s32>) = G_DUP [[COPY]](s32)
- ; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x i32>) = G_DUP [[COPY]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(s32) = COPY $w0
- %2:_(<2 x s32>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64)
- %4:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0)
- $d0 = COPY %4(<2 x s32>)
+ %0:_(i32) = COPY $w0
+ %2:_(<2 x i32>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x i32>) = G_INSERT_VECTOR_ELT %2, %0(i32), %3(i64)
+ %4:_(<2 x i32>) = G_SHUFFLE_VECTOR %1(<2 x i32>), %2, shufflemask(0, 0)
+ $d0 = COPY %4(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -88,16 +88,16 @@ body: |
; CHECK-LABEL: name: splat_4xf32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x s32>) = G_DUP [[COPY]](s32)
- ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $s0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x i32>) = G_DUP [[COPY]](i32)
+ ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s32) = COPY $s0
- %2:_(<4 x s32>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64)
- %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0)
- $q0 = COPY %4(<4 x s32>)
+ %0:_(i32) = COPY $s0
+ %2:_(<4 x i32>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<4 x i32>) = G_INSERT_VECTOR_ELT %2, %0(i32), %3(i64)
+ %4:_(<4 x i32>) = G_SHUFFLE_VECTOR %1(<4 x i32>), %2, shufflemask(0, 0, 0, 0)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -113,16 +113,16 @@ body: |
; CHECK-LABEL: name: splat_2xf64
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x s64>) = G_DUP [[COPY]](s64)
- ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $d0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x i64>) = G_DUP [[COPY]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s64) = COPY $d0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64)
- %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0)
- $q0 = COPY %4(<2 x s64>)
+ %0:_(i64) = COPY $d0
+ %2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x i64>) = G_INSERT_VECTOR_ELT %2, %0(i64), %3(i64)
+ %4:_(<2 x i64>) = G_SHUFFLE_VECTOR %1(<2 x i64>), %2, shufflemask(0, 0)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -138,16 +138,16 @@ body: |
; CHECK-LABEL: name: splat_2xf32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x s32>) = G_DUP [[COPY]](s32)
- ; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $s0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x i32>) = G_DUP [[COPY]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(s32) = COPY $s0
- %2:_(<2 x s32>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64)
- %4:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0)
- $d0 = COPY %4(<2 x s32>)
+ %0:_(i32) = COPY $s0
+ %2:_(<2 x i32>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x i32>) = G_INSERT_VECTOR_ELT %2, %0(i32), %3(i64)
+ %4:_(<2 x i32>) = G_SHUFFLE_VECTOR %1(<2 x i32>), %2, shufflemask(0, 0)
+ $d0 = COPY %4(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -165,18 +165,18 @@ body: |
; CHECK-LABEL: name: splat_2xf64_copies
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x s64>) = G_DUP [[COPY]](s64)
- ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $d0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x i64>) = G_DUP [[COPY]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s64) = COPY $d0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %6:_(<2 x s64>) = COPY %2
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s64)
- %7:_(<2 x s64>) = COPY %1
- %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %7(<2 x s64>), %2, shufflemask(0, 0)
- $q0 = COPY %4(<2 x s64>)
+ %0:_(i64) = COPY $d0
+ %2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %6:_(<2 x i64>) = COPY %2
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x i64>) = G_INSERT_VECTOR_ELT %6, %0(i64), %3(i64)
+ %7:_(<2 x i64>) = COPY %1
+ %4:_(<2 x i64>) = G_SHUFFLE_VECTOR %7(<2 x i64>), %2, shufflemask(0, 0)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -192,19 +192,19 @@ body: |
; CHECK-LABEL: name: not_all_zeros
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[IVEC]](<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i64>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY [[IVEC]](<2 x i64>)
+ ; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s64) = COPY $x0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64)
- %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 1)
- $q0 = COPY %4(<2 x s64>)
+ %0:_(i64) = COPY $x0
+ %2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x i64>) = G_INSERT_VECTOR_ELT %2, %0(i64), %3(i64)
+ %4:_(<2 x i64>) = G_SHUFFLE_VECTOR %1(<2 x i64>), %2, shufflemask(0, 1)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -222,16 +222,16 @@ body: |
; CHECK-LABEL: name: all_undef
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x s64>) = G_DUP [[COPY]](s64)
- ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<2 x i64>) = G_DUP [[COPY]](i64)
+ ; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s64) = COPY $x0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64)
- %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(-1, -1)
- $q0 = COPY %4(<2 x s64>)
+ %0:_(i64) = COPY $x0
+ %2:_(<2 x i64>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x i64>) = G_INSERT_VECTOR_ELT %2, %0(i64), %3(i64)
+ %4:_(<2 x i64>) = G_SHUFFLE_VECTOR %1(<2 x i64>), %2, shufflemask(-1, -1)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -248,16 +248,16 @@ body: |
; CHECK-LABEL: name: one_undef
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x s32>) = G_DUP [[COPY]](s32)
- ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $s0
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x i32>) = G_DUP [[COPY]](i32)
+ ; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s32) = COPY $s0
- %2:_(<4 x s32>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64)
- %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, -1, 0, 0)
- $q0 = COPY %4(<4 x s32>)
+ %0:_(i32) = COPY $s0
+ %2:_(<4 x i32>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<4 x i32>) = G_INSERT_VECTOR_ELT %2, %0(i32), %3(i64)
+ %4:_(<4 x i32>) = G_SHUFFLE_VECTOR %1(<4 x i32>), %2, shufflemask(0, -1, 0, 0)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -272,19 +272,19 @@ body: |
; CHECK-LABEL: name: not_all_zeros_with_undefs
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s64)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(undef, 0, 0, 3)
- ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $s0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](i32), [[C]](i64)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x i32>), [[DEF]], shufflemask(undef, 0, 0, 3)
+ ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(s32) = COPY $s0
- %2:_(<4 x s32>) = G_IMPLICIT_DEF
- %3:_(s64) = G_CONSTANT i64 0
- %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64)
- %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(-1, 0, 0, 3)
- $q0 = COPY %4(<4 x s32>)
+ %0:_(i32) = COPY $s0
+ %2:_(<4 x i32>) = G_IMPLICIT_DEF
+ %3:_(i64) = G_CONSTANT i64 0
+ %1:_(<4 x i32>) = G_INSERT_VECTOR_ELT %2, %0(i32), %3(i64)
+ %4:_(<4 x i32>) = G_SHUFFLE_VECTOR %1(<4 x i32>), %2, shufflemask(-1, 0, 0, 3)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -299,16 +299,16 @@ body: |
; CHECK-LABEL: name: splat_4xi16
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:_(s16) = COPY $h0
- ; CHECK-NEXT: %splat:_(<4 x s16>) = G_DUP %copy(s16)
- ; CHECK-NEXT: $d0 = COPY %splat(<4 x s16>)
+ ; CHECK-NEXT: %copy:_(i16) = COPY $h0
+ ; CHECK-NEXT: %splat:_(<4 x i16>) = G_DUP %copy(i16)
+ ; CHECK-NEXT: $d0 = COPY %splat(<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:_(s16) = COPY $h0
- %undef:_(<4 x s16>) = G_IMPLICIT_DEF
- %cst:_(s64) = G_CONSTANT i64 0
- %ins:_(<4 x s16>) = G_INSERT_VECTOR_ELT %undef, %copy(s16), %cst(s64)
- %splat:_(<4 x s16>) = G_SHUFFLE_VECTOR %ins(<4 x s16>), %undef, shufflemask(0, 0, 0, 0)
- $d0 = COPY %splat(<4 x s16>)
+ %copy:_(i16) = COPY $h0
+ %undef:_(<4 x i16>) = G_IMPLICIT_DEF
+ %cst:_(i64) = G_CONSTANT i64 0
+ %ins:_(<4 x i16>) = G_INSERT_VECTOR_ELT %undef, %copy(i16), %cst(i64)
+ %splat:_(<4 x i16>) = G_SHUFFLE_VECTOR %ins(<4 x i16>), %undef, shufflemask(0, 0, 0, 0)
+ $d0 = COPY %splat(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -323,16 +323,16 @@ body: |
; CHECK-LABEL: name: splat_8xi8
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: %splat:_(<8 x s8>) = G_DUP %copy(s32)
- ; CHECK-NEXT: $d0 = COPY %splat(<8 x s8>)
+ ; CHECK-NEXT: %copy:_(i32) = COPY $w0
+ ; CHECK-NEXT: %splat:_(<8 x i8>) = G_DUP %copy(i32)
+ ; CHECK-NEXT: $d0 = COPY %splat(<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:_(s32) = COPY $w0
- %undef:_(<8 x s8>) = G_IMPLICIT_DEF
- %cst:_(s64) = G_CONSTANT i64 0
- %ins:_(<8 x s8>) = G_INSERT_VECTOR_ELT %undef, %copy(s32), %cst(s64)
- %splat:_(<8 x s8>) = G_SHUFFLE_VECTOR %ins(<8 x s8>), %undef, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
- $d0 = COPY %splat(<8 x s8>)
+ %copy:_(i32) = COPY $w0
+ %undef:_(<8 x i8>) = G_IMPLICIT_DEF
+ %cst:_(i64) = G_CONSTANT i64 0
+ %ins:_(<8 x i8>) = G_INSERT_VECTOR_ELT %undef, %copy(i32), %cst(i64)
+ %splat:_(<8 x i8>) = G_SHUFFLE_VECTOR %ins(<8 x i8>), %undef, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ $d0 = COPY %splat(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -349,32 +349,32 @@ body: |
; CHECK-LABEL: name: build_vector
; CHECK: liveins: $w0, $w1, $w2, $w3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %lane:_(s32) = COPY $w0
- ; CHECK-NEXT: %b:_(s32) = COPY $w1
- ; CHECK-NEXT: %c:_(s32) = COPY $w2
- ; CHECK-NEXT: %d:_(s32) = COPY $w3
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %lane:_(i32) = COPY $w0
+ ; CHECK-NEXT: %b:_(i32) = COPY $w1
+ ; CHECK-NEXT: %c:_(i32) = COPY $w2
+ ; CHECK-NEXT: %d:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane(s32), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane(i32), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(i32), [[C1]](i64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(i32), [[C2]](i64)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](i64)
- ; CHECK-NEXT: %buildvec:_(<4 x s32>) = COPY [[IVEC3]](<4 x s32>)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(i32), [[C3]](i64)
+ ; CHECK-NEXT: %buildvec:_(<4 x i32>) = COPY [[IVEC3]](<4 x i32>)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_DUPLANE32 %buildvec, [[C4]](i64)
- ; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
+ ; CHECK-NEXT: %shuf:_(<4 x i32>) = G_DUPLANE32 %buildvec, [[C4]](i64)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lane:_(s32) = COPY $w0
- %b:_(s32) = COPY $w1
- %c:_(s32) = COPY $w2
- %d:_(s32) = COPY $w3
- %undef:_(<4 x s32>) = G_IMPLICIT_DEF
- %buildvec:_(<4 x s32>) = G_BUILD_VECTOR %lane, %b, %c, %d
- %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %buildvec(<4 x s32>), %undef, shufflemask(0, 0, 0, 0)
- $q0 = COPY %shuf(<4 x s32>)
+ %lane:_(i32) = COPY $w0
+ %b:_(i32) = COPY $w1
+ %c:_(i32) = COPY $w2
+ %d:_(i32) = COPY $w3
+ %undef:_(<4 x i32>) = G_IMPLICIT_DEF
+ %buildvec:_(<4 x i32>) = G_BUILD_VECTOR %lane, %b, %c, %d
+ %shuf:_(<4 x i32>) = G_SHUFFLE_VECTOR %buildvec(<4 x i32>), %undef, shufflemask(0, 0, 0, 0)
+ $q0 = COPY %shuf(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -391,41 +391,41 @@ body: |
; CHECK-LABEL: name: build_vector_rhs
; CHECK: liveins: $w0, $w1, $w2, $w3, $w4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %lane_0:_(s32) = COPY $w0
- ; CHECK-NEXT: %lane_1:_(s32) = COPY $w1
- ; CHECK-NEXT: %b:_(s32) = COPY $w2
- ; CHECK-NEXT: %c:_(s32) = COPY $w3
- ; CHECK-NEXT: %d:_(s32) = COPY $w4
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %lane_0:_(i32) = COPY $w0
+ ; CHECK-NEXT: %lane_1:_(i32) = COPY $w1
+ ; CHECK-NEXT: %b:_(i32) = COPY $w2
+ ; CHECK-NEXT: %c:_(i32) = COPY $w3
+ ; CHECK-NEXT: %d:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane_0(s32), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane_0(i32), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(i32), [[C1]](i64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(i32), [[C2]](i64)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](i64)
- ; CHECK-NEXT: %buildvec0:_(<4 x s32>) = COPY [[IVEC3]](<4 x s32>)
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(i32), [[C3]](i64)
+ ; CHECK-NEXT: %buildvec0:_(<4 x i32>) = COPY [[IVEC3]](<4 x i32>)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], %lane_1(s32), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[DEF1]], %lane_1(i32), [[C4]](i64)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC4]], %b(s32), [[C5]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC4]], %b(i32), [[C5]](i64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC5]], %c(s32), [[C6]](i64)
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC5]], %c(i32), [[C6]](i64)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC6]], %d(s32), [[C7]](i64)
- ; CHECK-NEXT: %buildvec1:_(<4 x s32>) = COPY [[IVEC7]](<4 x s32>)
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %buildvec0(<4 x s32>), %buildvec1, shufflemask(4, 4, 4, 4)
- ; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
+ ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC6]], %d(i32), [[C7]](i64)
+ ; CHECK-NEXT: %buildvec1:_(<4 x i32>) = COPY [[IVEC7]](<4 x i32>)
+ ; CHECK-NEXT: %shuf:_(<4 x i32>) = G_SHUFFLE_VECTOR %buildvec0(<4 x i32>), %buildvec1, shufflemask(4, 4, 4, 4)
+ ; CHECK-NEXT: $q0 = COPY %shuf(<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lane_0:_(s32) = COPY $w0
- %lane_1:_(s32) = COPY $w1
- %b:_(s32) = COPY $w2
- %c:_(s32) = COPY $w3
- %d:_(s32) = COPY $w4
- %buildvec0:_(<4 x s32>) = G_BUILD_VECTOR %lane_0(s32), %b(s32), %c(s32), %d(s32)
- %buildvec1:_(<4 x s32>) = G_BUILD_VECTOR %lane_1(s32), %b(s32), %c(s32), %d(s32)
- %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %buildvec0(<4 x s32>), %buildvec1, shufflemask(4, 4, 4, 4)
- $q0 = COPY %shuf(<4 x s32>)
+ %lane_0:_(i32) = COPY $w0
+ %lane_1:_(i32) = COPY $w1
+ %b:_(i32) = COPY $w2
+ %c:_(i32) = COPY $w3
+ %d:_(i32) = COPY $w4
+ %buildvec0:_(<4 x i32>) = G_BUILD_VECTOR %lane_0(i32), %b(i32), %c(i32), %d(i32)
+ %buildvec1:_(<4 x i32>) = G_BUILD_VECTOR %lane_1(i32), %b(i32), %c(i32), %d(i32)
+ %shuf:_(<4 x i32>) = G_SHUFFLE_VECTOR %buildvec0(<4 x i32>), %buildvec1, shufflemask(4, 4, 4, 4)
+ $q0 = COPY %shuf(<4 x i32>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-trn.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-trn.mir
index cfafc68cc0073..dc73efe3f8204 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-trn.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-trn.mir
@@ -17,15 +17,15 @@ body: |
; CHECK-LABEL: name: trn1_v8s8
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<8 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[TRN1_]](<8 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i8>) = COPY $d1
+ ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<8 x i8>) = G_TRN1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[TRN1_]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<8 x s8>) = COPY $d0
- %1:_(<8 x s8>) = COPY $d1
- %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 8, 2, 10, 4, 12, 6, 14)
- $d0 = COPY %2(<8 x s8>)
+ %0:_(<8 x i8>) = COPY $d0
+ %1:_(<8 x i8>) = COPY $d1
+ %2:_(<8 x i8>) = G_SHUFFLE_VECTOR %0(<8 x i8>), %1, shufflemask(0, 8, 2, 10, 4, 12, 6, 14)
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $q0
...
@@ -40,15 +40,15 @@ body: |
; CHECK-LABEL: name: trn2_v8s8
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<8 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[TRN2_]](<8 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i8>) = COPY $d1
+ ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<8 x i8>) = G_TRN2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[TRN2_]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<8 x s8>) = COPY $d0
- %1:_(<8 x s8>) = COPY $d1
- %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(1, 9, 3, 11, 5, 13, 7, 15)
- $d0 = COPY %2(<8 x s8>)
+ %0:_(<8 x i8>) = COPY $d0
+ %1:_(<8 x i8>) = COPY $d1
+ %2:_(<8 x i8>) = G_SHUFFLE_VECTOR %0(<8 x i8>), %1, shufflemask(1, 9, 3, 11, 5, 13, 7, 15)
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $q0
...
@@ -63,15 +63,15 @@ body: |
; CHECK-LABEL: name: trn1_v16s8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
- ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<16 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[TRN1_]](<16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x i8>) = COPY $q1
+ ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<16 x i8>) = G_TRN1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[TRN1_]](<16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<16 x s8>) = COPY $q0
- %1:_(<16 x s8>) = COPY $q1
- %2:_(<16 x s8>) = G_SHUFFLE_VECTOR %0(<16 x s8>), %1, shufflemask(0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30)
- $q0 = COPY %2(<16 x s8>)
+ %0:_(<16 x i8>) = COPY $q0
+ %1:_(<16 x i8>) = COPY $q1
+ %2:_(<16 x i8>) = G_SHUFFLE_VECTOR %0(<16 x i8>), %1, shufflemask(0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30)
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -86,15 +86,15 @@ body: |
; CHECK-LABEL: name: trn2_v16s8
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
- ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<16 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[TRN2_]](<16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x i8>) = COPY $q1
+ ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<16 x i8>) = G_TRN2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[TRN2_]](<16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<16 x s8>) = COPY $q0
- %1:_(<16 x s8>) = COPY $q1
- %2:_(<16 x s8>) = G_SHUFFLE_VECTOR %0(<16 x s8>), %1, shufflemask(1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31)
- $q0 = COPY %2(<16 x s8>)
+ %0:_(<16 x i8>) = COPY $q0
+ %1:_(<16 x i8>) = COPY $q1
+ %2:_(<16 x i8>) = G_SHUFFLE_VECTOR %0(<16 x i8>), %1, shufflemask(1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31)
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -109,15 +109,15 @@ body: |
; CHECK-LABEL: name: trn1_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<4 x s32>) = G_TRN1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[TRN1_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<4 x i32>) = G_TRN1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[TRN1_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 4, 2, 6)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(0, 4, 2, 6)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -132,15 +132,15 @@ body: |
; CHECK-LABEL: name: trn2_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<4 x s32>) = G_TRN2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[TRN2_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<4 x i32>) = G_TRN2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[TRN2_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(1, 5, 3, 7)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(1, 5, 3, 7)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -156,15 +156,15 @@ body: |
; CHECK-LABEL: name: redundant_with_zip1
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<2 x s32>) = G_ZIP1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[ZIP1_]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<2 x i32>) = G_ZIP1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[ZIP1_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0, 2)
- $d0 = COPY %2(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(0, 2)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -180,15 +180,15 @@ body: |
; CHECK-LABEL: name: redundant_with_zip2
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x s32>) = G_ZIP2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[ZIP2_]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x i32>) = G_ZIP2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[ZIP2_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 3)
- $d0 = COPY %2(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(1, 3)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -204,15 +204,15 @@ body: |
; CHECK-LABEL: name: trn1_undef
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<8 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[TRN1_]](<8 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i8>) = COPY $d1
+ ; CHECK-NEXT: [[TRN1_:%[0-9]+]]:_(<8 x i8>) = G_TRN1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[TRN1_]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<8 x s8>) = COPY $d0
- %1:_(<8 x s8>) = COPY $d1
- %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 8, -1, -1, 4, 12, 6, 14)
- $d0 = COPY %2(<8 x s8>)
+ %0:_(<8 x i8>) = COPY $d0
+ %1:_(<8 x i8>) = COPY $d1
+ %2:_(<8 x i8>) = G_SHUFFLE_VECTOR %0(<8 x i8>), %1, shufflemask(0, 8, -1, -1, 4, 12, 6, 14)
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -228,13 +228,13 @@ body: |
; CHECK-LABEL: name: trn2_undef
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<8 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[TRN2_]](<8 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i8>) = COPY $d1
+ ; CHECK-NEXT: [[TRN2_:%[0-9]+]]:_(<8 x i8>) = G_TRN2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[TRN2_]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<8 x s8>) = COPY $d0
- %1:_(<8 x s8>) = COPY $d1
- %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(1, -1, 3, 11, 5, 13, -1, -1)
- $d0 = COPY %2(<8 x s8>)
+ %0:_(<8 x i8>) = COPY $d0
+ %1:_(<8 x i8>) = COPY $d1
+ %2:_(<8 x i8>) = G_SHUFFLE_VECTOR %0(<8 x i8>), %1, shufflemask(1, -1, 3, 11, 5, 13, -1, -1)
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
index 28b55a69d3c9b..5fd4fb2fa10b7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
@@ -11,12 +11,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
- ; CHECK-NEXT: %val:_(s32) = COPY $w1
- ; CHECK-NEXT: G_STORE %val(s32), %ptr(p0) :: (store (s8))
+ ; CHECK-NEXT: %val:_(i32) = COPY $w1
+ ; CHECK-NEXT: G_STORE %val(i32), %ptr(p0) :: (store (i8))
%ptr:_(p0) = COPY $x0
- %val:_(s32) = COPY $w1
- %trunc:_(s8) = G_TRUNC %val
- G_STORE %trunc(s8), %ptr(p0) :: (store (s8))
+ %val:_(i32) = COPY $w1
+ %trunc:_(i8) = G_TRUNC %val
+ G_STORE %trunc(i8), %ptr(p0) :: (store (i8))
...
---
name: truncstore_vector
@@ -28,13 +28,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
- ; CHECK-NEXT: %val:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: %trunc:_(<4 x s8>) = G_TRUNC %val(<4 x s32>)
- ; CHECK-NEXT: G_STORE %trunc(<4 x s8>), %ptr(p0) :: (store (<4 x s8>))
+ ; CHECK-NEXT: %val:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: %trunc:_(<4 x i8>) = G_TRUNC %val(<4 x i32>)
+ ; CHECK-NEXT: G_STORE %trunc(<4 x i8>), %ptr(p0) :: (store (<4 x i8>))
%ptr:_(p0) = COPY $x0
- %val:_(<4 x s32>) = COPY $q0
- %trunc:_(<4 x s8>) = G_TRUNC %val
- G_STORE %trunc(<4 x s8>), %ptr(p0) :: (store (<4 x s8>))
+ %val:_(<4 x i32>) = COPY $q0
+ %trunc:_(<4 x i8>) = G_TRUNC %val
+ G_STORE %trunc(<4 x i8>), %ptr(p0) :: (store (<4 x i8>))
...
---
name: truncstore_too_large
@@ -46,11 +46,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
- ; CHECK-NEXT: %val:_(s128) = COPY $q0
- ; CHECK-NEXT: %trunc:_(s32) = G_TRUNC %val(s128)
- ; CHECK-NEXT: G_STORE %trunc(s32), %ptr(p0) :: (store (s32))
+ ; CHECK-NEXT: %val:_(i128) = COPY $q0
+ ; CHECK-NEXT: %trunc:_(i32) = G_TRUNC %val(i128)
+ ; CHECK-NEXT: G_STORE %trunc(i32), %ptr(p0) :: (store (i32))
%ptr:_(p0) = COPY $x0
- %val:_(s128) = COPY $q0
- %trunc:_(s32) = G_TRUNC %val
- G_STORE %trunc(s32), %ptr(p0) :: (store (s32))
+ %val:_(i128) = COPY $q0
+ %trunc:_(i32) = G_TRUNC %val
+ G_STORE %trunc(i32), %ptr(p0) :: (store (i32))
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
index 52ef2d3578b33..24cdd6e82096b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
@@ -10,17 +10,17 @@ body: |
; CHECK-LABEL: name: v4s32
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: %unmerge:_(<2 x s32>) = G_EXTRACT_SUBVECTOR %v1(<4 x s32>), 2
- ; CHECK-NEXT: %fpext:_(<2 x s64>) = G_FPEXT %unmerge(<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY %fpext(<2 x s64>)
+ ; CHECK-NEXT: %v1:_(<4 x f32>) = COPY $q0
+ ; CHECK-NEXT: %unmerge:_(<2 x f32>) = G_EXTRACT_SUBVECTOR %v1(<4 x f32>), 2
+ ; CHECK-NEXT: %fpext:_(<2 x f64>) = G_FPEXT %unmerge(<2 x f32>)
+ ; CHECK-NEXT: $q0 = COPY %fpext(<2 x f64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<4 x s32>) = COPY $q0
- %implicit:_(<4 x s32>) = G_IMPLICIT_DEF
- %C:_(s32) = G_CONSTANT i32 8
- %ext:_(<4 x s32>) = G_EXT %v1:_, %implicit:_, %C:_(s32)
- %unmerge:_(<2 x s32>), %unused:_(<2 x s32>) = G_UNMERGE_VALUES %ext:_(<4 x s32>)
- %fpext:_(<2 x s64>) = G_FPEXT %unmerge:_(<2 x s32>)
+ %v1:_(<4 x f32>) = COPY $q0
+ %implicit:_(<4 x f32>) = G_IMPLICIT_DEF
+ %C:_(i32) = G_CONSTANT i32 8
+ %ext:_(<4 x f32>) = G_EXT %v1:_, %implicit:_, %C:_(i32)
+ %unmerge:_(<2 x f32>), %unused:_(<2 x f32>) = G_UNMERGE_VALUES %ext:_(<4 x f32>)
+ %fpext:_(<2 x f64>) = G_FPEXT %unmerge:_(<2 x f32>)
$q0 = COPY %fpext
RET_ReallyLR implicit $q0
...
@@ -33,40 +33,17 @@ body: |
; CHECK-LABEL: name: v8s16
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: %unmerge:_(<4 x s16>) = G_EXTRACT_SUBVECTOR %v1(<8 x s16>), 4
- ; CHECK-NEXT: %fpext:_(<4 x s32>) = G_FPEXT %unmerge(<4 x s16>)
- ; CHECK-NEXT: $q0 = COPY %fpext(<4 x s32>)
+ ; CHECK-NEXT: %v1:_(<8 x f16>) = COPY $q0
+ ; CHECK-NEXT: %unmerge:_(<4 x f16>) = G_EXTRACT_SUBVECTOR %v1(<8 x f16>), 4
+ ; CHECK-NEXT: %fpext:_(<4 x f32>) = G_FPEXT %unmerge(<4 x f16>)
+ ; CHECK-NEXT: $q0 = COPY %fpext(<4 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<8 x s16>) = COPY $q0
- %implicit:_(<8 x s16>) = G_IMPLICIT_DEF
- %C:_(s32) = G_CONSTANT i32 8
- %ext:_(<8 x s16>) = G_EXT %v1:_, %implicit:_, %C:_(s32)
- %unmerge:_(<4 x s16>), %unused:_(<4 x s16>) = G_UNMERGE_VALUES %ext:_(<8 x s16>)
- %fpext:_(<4 x s32>) = G_FPEXT %unmerge:_(<4 x s16>)
- $q0 = COPY %fpext
- RET_ReallyLR implicit $q0
-...
----
-name: v16s8
-legalized: true
-body: |
- bb.0.entry:
- liveins: $q0
- ; CHECK-LABEL: name: v16s8
- ; CHECK: liveins: $q0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: %unmerge:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %v1(<16 x s8>), 8
- ; CHECK-NEXT: %fpext:_(<8 x s16>) = G_FPEXT %unmerge(<8 x s8>)
- ; CHECK-NEXT: $q0 = COPY %fpext(<8 x s16>)
- ; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<16 x s8>) = COPY $q0
- %implicit:_(<16 x s8>) = G_IMPLICIT_DEF
- %C:_(s32) = G_CONSTANT i32 8
- %ext:_(<16 x s8>) = G_EXT %v1:_, %implicit:_, %C:_(s32)
- %unmerge:_(<8 x s8>), %unused:_(<8 x s8>) = G_UNMERGE_VALUES %ext:_(<16 x s8>)
- %fpext:_(<8 x s16>) = G_FPEXT %unmerge:_(<8 x s8>)
+ %v1:_(<8 x f16>) = COPY $q0
+ %implicit:_(<8 x f16>) = G_IMPLICIT_DEF
+ %C:_(i32) = G_CONSTANT i32 8
+ %ext:_(<8 x f16>) = G_EXT %v1:_, %implicit:_, %C:_(i32)
+ %unmerge:_(<4 x f16>), %unused:_(<4 x f16>) = G_UNMERGE_VALUES %ext:_(<8 x f16>)
+ %fpext:_(<4 x f32>) = G_FPEXT %unmerge:_(<4 x f16>)
$q0 = COPY %fpext
RET_ReallyLR implicit $q0
...
@@ -79,20 +56,20 @@ body: |
; CHECK-LABEL: name: skip_not_const
; CHECK: liveins: $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: %implicit:_(<16 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: %C:_(s32) = COPY $w0
- ; CHECK-NEXT: %ext:_(<16 x s8>) = G_EXT %v1, %implicit, %C(s32)
- ; CHECK-NEXT: %unmerge:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %ext(<16 x s8>), 0
- ; CHECK-NEXT: %fpext:_(<8 x s16>) = G_FPEXT %unmerge(<8 x s8>)
- ; CHECK-NEXT: $q0 = COPY %fpext(<8 x s16>)
+ ; CHECK-NEXT: %v1:_(<8 x f16>) = COPY $q0
+ ; CHECK-NEXT: %implicit:_(<8 x f16>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %C:_(i32) = COPY $w0
+ ; CHECK-NEXT: %ext:_(<8 x f16>) = G_EXT %v1, %implicit, %C(i32)
+ ; CHECK-NEXT: %unmerge:_(<4 x f16>) = G_EXTRACT_SUBVECTOR %ext(<8 x f16>), 0
+ ; CHECK-NEXT: %fpext:_(<4 x f32>) = G_FPEXT %unmerge(<4 x f16>)
+ ; CHECK-NEXT: $q0 = COPY %fpext(<4 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<16 x s8>) = COPY $q0
- %implicit:_(<16 x s8>) = G_IMPLICIT_DEF
- %C:_(s32) = COPY $w0
- %ext:_(<16 x s8>) = G_EXT %v1:_, %implicit:_, %C:_(s32)
- %unmerge:_(<8 x s8>), %unused:_(<8 x s8>) = G_UNMERGE_VALUES %ext:_(<16 x s8>)
- %fpext:_(<8 x s16>) = G_FPEXT %unmerge:_(<8 x s8>)
+ %v1:_(<8 x f16>) = COPY $q0
+ %implicit:_(<8 x f16>) = G_IMPLICIT_DEF
+ %C:_(i32) = COPY $w0
+ %ext:_(<8 x f16>) = G_EXT %v1:_, %implicit:_, %C:_(i32)
+ %unmerge:_(<4 x f16>), %unused:_(<4 x f16>) = G_UNMERGE_VALUES %ext:_(<8 x f16>)
+ %fpext:_(<4 x f32>) = G_FPEXT %unmerge:_(<4 x f16>)
$q0 = COPY %fpext
RET_ReallyLR implicit $q0
...
@@ -105,24 +82,24 @@ body: |
; CHECK-LABEL: name: skip_not_unused
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: %implicit:_(<16 x s8>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: %C:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: %ext:_(<16 x s8>) = G_EXT %v1, %implicit, %C(s32)
- ; CHECK-NEXT: %unmerge:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %ext(<16 x s8>), 0
- ; CHECK-NEXT: %unused:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %ext(<16 x s8>), 8
- ; CHECK-NEXT: %fpext:_(<8 x s16>) = G_FPEXT %unmerge(<8 x s8>)
- ; CHECK-NEXT: %fpext2:_(<8 x s16>) = G_FPEXT %unused(<8 x s8>)
- ; CHECK-NEXT: $q0 = COPY %fpext(<8 x s16>)
- ; CHECK-NEXT: $q1 = COPY %fpext2(<8 x s16>)
+ ; CHECK-NEXT: %v1:_(<8 x f16>) = COPY $q0
+ ; CHECK-NEXT: %implicit:_(<8 x f16>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %C:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: %ext:_(<8 x f16>) = G_EXT %v1, %implicit, %C(i32)
+ ; CHECK-NEXT: %unmerge:_(<4 x f16>) = G_EXTRACT_SUBVECTOR %ext(<8 x f16>), 0
+ ; CHECK-NEXT: %unused:_(<4 x f16>) = G_EXTRACT_SUBVECTOR %ext(<8 x f16>), 4
+ ; CHECK-NEXT: %fpext:_(<4 x f32>) = G_FPEXT %unmerge(<4 x f16>)
+ ; CHECK-NEXT: %fpext2:_(<4 x f32>) = G_FPEXT %unused(<4 x f16>)
+ ; CHECK-NEXT: $q0 = COPY %fpext(<4 x f32>)
+ ; CHECK-NEXT: $q1 = COPY %fpext2(<4 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
- %v1:_(<16 x s8>) = COPY $q0
- %implicit:_(<16 x s8>) = G_IMPLICIT_DEF
- %C:_(s32) = G_CONSTANT i32 8
- %ext:_(<16 x s8>) = G_EXT %v1:_, %implicit:_, %C:_(s32)
- %unmerge:_(<8 x s8>), %unused:_(<8 x s8>) = G_UNMERGE_VALUES %ext:_(<16 x s8>)
- %fpext:_(<8 x s16>) = G_FPEXT %unmerge:_(<8 x s8>)
- %fpext2:_(<8 x s16>) = G_FPEXT %unused:_(<8 x s8>)
+ %v1:_(<8 x f16>) = COPY $q0
+ %implicit:_(<8 x f16>) = G_IMPLICIT_DEF
+ %C:_(i32) = G_CONSTANT i32 8
+ %ext:_(<8 x f16>) = G_EXT %v1:_, %implicit:_, %C:_(i32)
+ %unmerge:_(<4 x f16>), %unused:_(<4 x f16>) = G_UNMERGE_VALUES %ext:_(<8 x f16>)
+ %fpext:_(<4 x f32>) = G_FPEXT %unmerge:_(<4 x f16>)
+ %fpext2:_(<4 x f32>) = G_FPEXT %unused:_(<4 x f16>)
$q0 = COPY %fpext
$q1 = COPY %fpext2
RET_ReallyLR implicit $q0, implicit $q1
@@ -136,20 +113,20 @@ body: |
; CHECK-LABEL: name: skip_borders
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %v1:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: %implicit:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: %C:_(s32) = G_CONSTANT i32 9
- ; CHECK-NEXT: %ext:_(<4 x s32>) = G_EXT %v1, %implicit, %C(s32)
- ; CHECK-NEXT: %unmerge:_(<2 x s32>) = G_EXTRACT_SUBVECTOR %ext(<4 x s32>), 0
- ; CHECK-NEXT: %fpext:_(<2 x s64>) = G_FPEXT %unmerge(<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY %fpext(<2 x s64>)
+ ; CHECK-NEXT: %v1:_(<4 x f32>) = COPY $q0
+ ; CHECK-NEXT: %implicit:_(<4 x f32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %C:_(i32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: %ext:_(<4 x f32>) = G_EXT %v1, %implicit, %C(i32)
+ ; CHECK-NEXT: %unmerge:_(<2 x f32>) = G_EXTRACT_SUBVECTOR %ext(<4 x f32>), 0
+ ; CHECK-NEXT: %fpext:_(<2 x f64>) = G_FPEXT %unmerge(<2 x f32>)
+ ; CHECK-NEXT: $q0 = COPY %fpext(<2 x f64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %v1:_(<4 x s32>) = COPY $q0
- %implicit:_(<4 x s32>) = G_IMPLICIT_DEF
- %C:_(s32) = G_CONSTANT i32 9
- %ext:_(<4 x s32>) = G_EXT %v1:_, %implicit:_, %C:_(s32)
- %unmerge:_(<2 x s32>), %unused:_(<2 x s32>) = G_UNMERGE_VALUES %ext:_(<4 x s32>)
- %fpext:_(<2 x s64>) = G_FPEXT %unmerge:_(<2 x s32>)
+ %v1:_(<4 x f32>) = COPY $q0
+ %implicit:_(<4 x f32>) = G_IMPLICIT_DEF
+ %C:_(i32) = G_CONSTANT i32 9
+ %ext:_(<4 x f32>) = G_EXT %v1:_, %implicit:_, %C:_(i32)
+ %unmerge:_(<2 x f32>), %unused:_(<2 x f32>) = G_UNMERGE_VALUES %ext:_(<4 x f32>)
+ %fpext:_(<2 x f64>) = G_FPEXT %unmerge:_(<2 x f32>)
$q0 = COPY %fpext
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-uzp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-uzp.mir
index 00d5231cd0899..65b51bdab72ba 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-uzp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-uzp.mir
@@ -18,15 +18,15 @@ body: |
; CHECK-LABEL: name: uzp1_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[UZP1_:%[0-9]+]]:_(<4 x s32>) = G_UZP1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[UZP1_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[UZP1_:%[0-9]+]]:_(<4 x i32>) = G_UZP1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[UZP1_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 2, 4, 6)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(0, 2, 4, 6)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -41,15 +41,15 @@ body: |
; CHECK-LABEL: name: uzp2_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[UZP2_:%[0-9]+]]:_(<4 x s32>) = G_UZP2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[UZP2_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[UZP2_:%[0-9]+]]:_(<4 x i32>) = G_UZP2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[UZP2_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(1, 3, 5, 7)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(1, 3, 5, 7)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -66,15 +66,15 @@ body: |
; CHECK-LABEL: name: no_uzp1
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflemask(0, 1, 4, 6)
- ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x i32>), [[COPY1]], shufflemask(0, 1, 4, 6)
+ ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 4, 6)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(0, 1, 4, 6)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -91,15 +91,15 @@ body: |
; CHECK-LABEL: name: no_uzp2
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflemask(1, 4, 5, 7)
- ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x i32>), [[COPY1]], shufflemask(1, 4, 5, 7)
+ ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(1, 4, 5, 7)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(1, 4, 5, 7)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -116,15 +116,15 @@ body: |
; CHECK-LABEL: name: uzp1_undef
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[UZP1_:%[0-9]+]]:_(<4 x s32>) = G_UZP1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[UZP1_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[UZP1_:%[0-9]+]]:_(<4 x i32>) = G_UZP1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[UZP1_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, -1, 4, 6)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(0, -1, 4, 6)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -141,13 +141,13 @@ body: |
; CHECK-LABEL: name: uzp2_undef
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[UZP2_:%[0-9]+]]:_(<4 x s32>) = G_UZP2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[UZP2_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[UZP2_:%[0-9]+]]:_(<4 x i32>) = G_UZP2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[UZP2_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(1, 3, -1, 7)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(1, 3, -1, 7)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir
index dfaddba5c7772..f6e2f1d9ea758 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir
@@ -14,15 +14,15 @@ body: |
; CHECK-LABEL: name: ashr_v4s32
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VASHR:%[0-9]+]]:_(<4 x s32>) = G_VASHR [[COPY]], 5
- ; CHECK-NEXT: $q0 = COPY [[VASHR]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VASHR:%[0-9]+]]:_(<4 x i32>) = G_VASHR [[COPY]], 5
+ ; CHECK-NEXT: $q0 = COPY [[VASHR]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(s32) = G_CONSTANT i32 5
- %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
- %3:_(<4 x s32>) = G_ASHR %0, %2(<4 x s32>)
- $q0 = COPY %3(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(i32) = G_CONSTANT i32 5
+ %2:_(<4 x i32>) = G_BUILD_VECTOR %1(i32), %1(i32), %1(i32), %1(i32)
+ %3:_(<4 x i32>) = G_ASHR %0, %2(<4 x i32>)
+ $q0 = COPY %3(<4 x i32>)
RET_ReallyLR implicit $q0
...
---
@@ -37,15 +37,15 @@ body: |
; CHECK-LABEL: name: lshr_v4s32
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VLSHR:%[0-9]+]]:_(<4 x s32>) = G_VLSHR [[COPY]], 5
- ; CHECK-NEXT: $q0 = COPY [[VLSHR]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VLSHR:%[0-9]+]]:_(<4 x i32>) = G_VLSHR [[COPY]], 5
+ ; CHECK-NEXT: $q0 = COPY [[VLSHR]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(s32) = G_CONSTANT i32 5
- %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
- %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
- $q0 = COPY %3(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(i32) = G_CONSTANT i32 5
+ %2:_(<4 x i32>) = G_BUILD_VECTOR %1(i32), %1(i32), %1(i32), %1(i32)
+ %3:_(<4 x i32>) = G_LSHR %0, %2(<4 x i32>)
+ $q0 = COPY %3(<4 x i32>)
RET_ReallyLR implicit $q0
...
---
@@ -60,15 +60,15 @@ body: |
; CHECK-LABEL: name: lshr_v8s16
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[VLSHR:%[0-9]+]]:_(<8 x s16>) = G_VLSHR [[COPY]], 5
- ; CHECK-NEXT: $q0 = COPY [[VLSHR]](<8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $q0
+ ; CHECK-NEXT: [[VLSHR:%[0-9]+]]:_(<8 x i16>) = G_VLSHR [[COPY]], 5
+ ; CHECK-NEXT: $q0 = COPY [[VLSHR]](<8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<8 x s16>) = COPY $q0
- %1:_(s16) = G_CONSTANT i16 5
- %2:_(<8 x s16>) = G_BUILD_VECTOR %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16)
- %3:_(<8 x s16>) = G_LSHR %0, %2(<8 x s16>)
- $q0 = COPY %3(<8 x s16>)
+ %0:_(<8 x i16>) = COPY $q0
+ %1:_(i16) = G_CONSTANT i16 5
+ %2:_(<8 x i16>) = G_BUILD_VECTOR %1(i16), %1(i16), %1(i16), %1(i16), %1(i16), %1(i16), %1(i16), %1(i16)
+ %3:_(<8 x i16>) = G_LSHR %0, %2(<8 x i16>)
+ $q0 = COPY %3(<8 x i16>)
RET_ReallyLR implicit $q0
...
---
@@ -83,17 +83,17 @@ body: |
; CHECK-LABEL: name: imm_too_large
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x s32>) = G_DUP [[C]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[DUP]](<4 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 40
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x i32>) = G_DUP [[C]](i32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x i32>) = G_LSHR [[COPY]], [[DUP]](<4 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(s32) = G_CONSTANT i32 40
- %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
- %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
- $q0 = COPY %3(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(i32) = G_CONSTANT i32 40
+ %2:_(<4 x i32>) = G_BUILD_VECTOR %1(i32), %1(i32), %1(i32), %1(i32)
+ %3:_(<4 x i32>) = G_LSHR %0, %2(<4 x i32>)
+ $q0 = COPY %3(<4 x i32>)
RET_ReallyLR implicit $q0
...
---
@@ -108,17 +108,17 @@ body: |
; CHECK-LABEL: name: imm_zero
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x i32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(s32) = G_CONSTANT i32 0
- %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
- %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
- $q0 = COPY %3(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(i32) = G_CONSTANT i32 0
+ %2:_(<4 x i32>) = G_BUILD_VECTOR %1(i32), %1(i32), %1(i32), %1(i32)
+ %3:_(<4 x i32>) = G_LSHR %0, %2(<4 x i32>)
+ $q0 = COPY %3(<4 x i32>)
RET_ReallyLR implicit $q0
...
---
@@ -133,18 +133,18 @@ body: |
; CHECK-LABEL: name: imm_not_splat
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C1]](i32), [[C]](i32), [[C]](i32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x i32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(s32) = G_CONSTANT i32 4
- %4:_(s32) = G_CONSTANT i32 6
- %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %4(s32), %1(s32), %1(s32)
- %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)
- $q0 = COPY %3(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(i32) = G_CONSTANT i32 4
+ %4:_(i32) = G_CONSTANT i32 6
+ %2:_(<4 x i32>) = G_BUILD_VECTOR %1(i32), %4(i32), %1(i32), %1(i32)
+ %3:_(<4 x i32>) = G_LSHR %0, %2(<4 x i32>)
+ $q0 = COPY %3(<4 x i32>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
index 5c00bfb634ef4..e0f057aa3fd94 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
@@ -19,15 +19,15 @@ body: |
; CHECK-LABEL: name: zip1_v2s32
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<2 x s32>) = G_ZIP1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[ZIP1_]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<2 x i32>) = G_ZIP1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[ZIP1_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0, 2)
- $d0 = COPY %2(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(0, 2)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -43,15 +43,15 @@ body: |
; CHECK-LABEL: name: zip1_v2s64
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<2 x s64>) = G_ZIP1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[ZIP1_]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<2 x i64>) = G_ZIP1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[ZIP1_]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<2 x s64>) = COPY $q0
- %1:_(<2 x s64>) = COPY $q1
- %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(0, 2)
- $q0 = COPY %2(<2 x s64>)
+ %0:_(<2 x i64>) = COPY $q0
+ %1:_(<2 x i64>) = COPY $q1
+ %2:_(<2 x i64>) = G_SHUFFLE_VECTOR %0(<2 x i64>), %1, shufflemask(0, 2)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -67,15 +67,15 @@ body: |
; CHECK-LABEL: name: zip1_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<4 x s32>) = G_ZIP1 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[ZIP1_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[ZIP1_:%[0-9]+]]:_(<4 x i32>) = G_ZIP1 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[ZIP1_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 4, 1, 5)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(0, 4, 1, 5)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -91,15 +91,15 @@ body: |
; CHECK-LABEL: name: zip2_v2s32
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x s32>) = G_ZIP2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[ZIP2_]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x i32>) = G_ZIP2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[ZIP2_]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 3)
- $d0 = COPY %2(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(1, 3)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -115,15 +115,15 @@ body: |
; CHECK-LABEL: name: zip2_v2s64
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x s64>) = G_ZIP2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[ZIP2_]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<2 x i64>) = G_ZIP2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[ZIP2_]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<2 x s64>) = COPY $q0
- %1:_(<2 x s64>) = COPY $q1
- %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 3)
- $q0 = COPY %2(<2 x s64>)
+ %0:_(<2 x i64>) = COPY $q0
+ %1:_(<2 x i64>) = COPY $q1
+ %2:_(<2 x i64>) = G_SHUFFLE_VECTOR %0(<2 x i64>), %1, shufflemask(1, 3)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -139,15 +139,15 @@ body: |
; CHECK-LABEL: name: zip2_v4s32
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<4 x s32>) = G_ZIP2 [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[ZIP2_]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[ZIP2_:%[0-9]+]]:_(<4 x i32>) = G_ZIP2 [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[ZIP2_]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(2, 6, 3, 7)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(2, 6, 3, 7)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -165,16 +165,16 @@ body: |
; CHECK-LABEL: name: zip2_no_combine_idx_mismatch
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[EXT:%[0-9]+]]:_(<2 x s64>) = G_EXT [[COPY]], [[COPY1]], [[C]](i32)
- ; CHECK-NEXT: $q0 = COPY [[EXT]](<2 x s64>)
+ ; CHECK-NEXT: [[EXT:%[0-9]+]]:_(<2 x i64>) = G_EXT [[COPY]], [[COPY1]], [[C]](i32)
+ ; CHECK-NEXT: $q0 = COPY [[EXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<2 x s64>) = COPY $q0
- %1:_(<2 x s64>) = COPY $q1
- %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 2)
- $q0 = COPY %2(<2 x s64>)
+ %0:_(<2 x i64>) = COPY $q0
+ %1:_(<2 x i64>) = COPY $q1
+ %2:_(<2 x i64>) = G_SHUFFLE_VECTOR %0(<2 x i64>), %1, shufflemask(1, 2)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -192,14 +192,14 @@ body: |
; CHECK-LABEL: name: zip1_no_combine_idx_mismatch
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[COPY]](<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<2 x s64>) = COPY $q0
- %1:_(<2 x s64>) = COPY $q1
- %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(0, 1)
- $q0 = COPY %2(<2 x s64>)
+ %0:_(<2 x i64>) = COPY $q0
+ %1:_(<2 x i64>) = COPY $q1
+ %2:_(<2 x i64>) = G_SHUFFLE_VECTOR %0(<2 x i64>), %1, shufflemask(0, 1)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -216,13 +216,13 @@ body: |
; CHECK-LABEL: name: no_combine_first_elt_of_mask_must_be_zero_or_one
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflemask(3, 4, 1, 5)
- ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x i32>), [[COPY1]], shufflemask(3, 4, 1, 5)
+ ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<4 x s32>) = COPY $q0
- %1:_(<4 x s32>) = COPY $q1
- %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(3, 4, 1, 5)
- $q0 = COPY %2(<4 x s32>)
+ %0:_(<4 x i32>) = COPY $q0
+ %1:_(<4 x i32>) = COPY $q1
+ %2:_(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(3, 4, 1, 5)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
index f4dc5ecd4e03f..565bdde81fe0d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
@@ -24,11 +24,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.addr)
- ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[COPY]](p0) :: (load (i8) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](i32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
- %2:_(s32) = G_ZEXT %1
+ %1:_(i8) = G_LOAD %0 :: (load (i8) from %ir.addr)
+ %2:_(i32) = G_ZEXT %1
$w0 = COPY %2
...
@@ -42,10 +42,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.addr)
- ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[COPY]](p0) :: (load (i32) from %ir.addr)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD]](i64)
%0:_(p0) = COPY $x0
- %1:_(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
- %2:_(s64) = G_ANYEXT %1
+ %1:_(i32) = G_LOAD %0 :: (load (i32) from %ir.addr)
+ %2:_(i64) = G_ANYEXT %1
$x0 = COPY %2
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
index 819a81a472788..8d659c00ce8dc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
@@ -14,21 +14,21 @@ body: |
; CHECK-LABEL: name: f64_faddp
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f64>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C1]](i64)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[EVEC]], [[EVEC1]]
- ; CHECK-NEXT: $d0 = COPY [[FADD]](s64)
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f64>), [[C1]](i64)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[EVEC]], [[EVEC1]]
+ ; CHECK-NEXT: $d0 = COPY [[FADD]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s64>) = COPY $q0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %5:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %2, shufflemask(1, undef)
- %3:_(<2 x s64>) = G_FADD %1, %0
- %4:_(s64) = G_EXTRACT_VECTOR_ELT %3(<2 x s64>), %5(s64)
- $d0 = COPY %4(s64)
+ %0:_(<2 x f64>) = COPY $q0
+ %2:_(<2 x f64>) = G_IMPLICIT_DEF
+ %5:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x f64>) = G_SHUFFLE_VECTOR %0(<2 x f64>), %2, shufflemask(1, undef)
+ %3:_(<2 x f64>) = G_FADD %1, %0
+ %4:_(f64) = G_EXTRACT_VECTOR_ELT %3(<2 x f64>), %5(i64)
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -46,21 +46,21 @@ body: |
; CHECK-LABEL: name: f64_faddp_commuted
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f64>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C1]](i64)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[EVEC]], [[EVEC1]]
- ; CHECK-NEXT: $d0 = COPY [[FADD]](s64)
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f64>), [[C1]](i64)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[EVEC]], [[EVEC1]]
+ ; CHECK-NEXT: $d0 = COPY [[FADD]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s64>) = COPY $q0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %5:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %2, shufflemask(1, undef)
- %3:_(<2 x s64>) = G_FADD %0, %1
- %4:_(s64) = G_EXTRACT_VECTOR_ELT %3(<2 x s64>), %5(s64)
- $d0 = COPY %4(s64)
+ %0:_(<2 x f64>) = COPY $q0
+ %2:_(<2 x f64>) = G_IMPLICIT_DEF
+ %5:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x f64>) = G_SHUFFLE_VECTOR %0(<2 x f64>), %2, shufflemask(1, undef)
+ %3:_(<2 x f64>) = G_FADD %0, %1
+ %4:_(f64) = G_EXTRACT_VECTOR_ELT %3(<2 x f64>), %5(i64)
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -78,21 +78,21 @@ body: |
; CHECK-LABEL: name: f32_faddp
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C1]](i64)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[EVEC]], [[EVEC1]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f32>), [[C1]](i64)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[EVEC]], [[EVEC1]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:_(<2 x s32>) = COPY $d0
- %2:_(<2 x s32>) = G_IMPLICIT_DEF
- %5:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, undef)
- %3:_(<2 x s32>) = G_FADD %1, %0
- %4:_(s32) = G_EXTRACT_VECTOR_ELT %3(<2 x s32>), %5(s64)
- $s0 = COPY %4(s32)
+ %0:_(<2 x f32>) = COPY $d0
+ %2:_(<2 x f32>) = G_IMPLICIT_DEF
+ %5:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x f32>) = G_SHUFFLE_VECTOR %0(<2 x f32>), %2, shufflemask(1, undef)
+ %3:_(<2 x f32>) = G_FADD %1, %0
+ %4:_(f32) = G_EXTRACT_VECTOR_ELT %3(<2 x f32>), %5(i64)
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -110,21 +110,21 @@ body: |
; CHECK-LABEL: name: f32_faddp_commuted
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f32>), [[C]](i64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C1]](i64)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[EVEC]], [[EVEC1]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f32>), [[C1]](i64)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[EVEC]], [[EVEC1]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:_(<2 x s32>) = COPY $d0
- %2:_(<2 x s32>) = G_IMPLICIT_DEF
- %5:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, undef)
- %3:_(<2 x s32>) = G_FADD %0, %1
- %4:_(s32) = G_EXTRACT_VECTOR_ELT %3(<2 x s32>), %5(s64)
- $s0 = COPY %4(s32)
+ %0:_(<2 x f32>) = COPY $d0
+ %2:_(<2 x f32>) = G_IMPLICIT_DEF
+ %5:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x f32>) = G_SHUFFLE_VECTOR %0(<2 x f32>), %2, shufflemask(1, undef)
+ %3:_(<2 x f32>) = G_FADD %0, %1
+ %4:_(f32) = G_EXTRACT_VECTOR_ELT %3(<2 x f32>), %5(i64)
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -142,21 +142,21 @@ body: |
; CHECK-LABEL: name: wrong_extract_idx
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[DEF]], shufflemask(1, undef)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[SHUF]], [[COPY]]
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[FADD]](<2 x s64>), [[C]](s64)
- ; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x f64>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x f64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x f64>), [[DEF]], shufflemask(1, undef)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<2 x f64>) = G_FADD [[SHUF]], [[COPY]]
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[FADD]](<2 x f64>), [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[EVEC]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s64>) = COPY $q0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %5:_(s64) = G_CONSTANT i64 1
- %1:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %2, shufflemask(1, undef)
- %3:_(<2 x s64>) = G_FADD %1, %0
- %4:_(s64) = G_EXTRACT_VECTOR_ELT %3(<2 x s64>), %5(s64)
- $d0 = COPY %4(s64)
+ %0:_(<2 x f64>) = COPY $q0
+ %2:_(<2 x f64>) = G_IMPLICIT_DEF
+ %5:_(i64) = G_CONSTANT i64 1
+ %1:_(<2 x f64>) = G_SHUFFLE_VECTOR %0(<2 x f64>), %2, shufflemask(1, undef)
+ %3:_(<2 x f64>) = G_FADD %1, %0
+ %4:_(f64) = G_EXTRACT_VECTOR_ELT %3(<2 x f64>), %5(i64)
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -174,21 +174,21 @@ body: |
; CHECK-LABEL: name: wrong_shuffle_mask
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[DEF]], shufflemask(0, undef)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[SHUF]], [[COPY]]
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[FADD]](<2 x s64>), [[C]](s64)
- ; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $q0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x f64>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x f64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x f64>), [[DEF]], shufflemask(0, undef)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<2 x f64>) = G_FADD [[SHUF]], [[COPY]]
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[FADD]](<2 x f64>), [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[EVEC]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s64>) = COPY $q0
- %2:_(<2 x s64>) = G_IMPLICIT_DEF
- %5:_(s64) = G_CONSTANT i64 0
- %1:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %2, shufflemask(0, undef)
- %3:_(<2 x s64>) = G_FADD %1, %0
- %4:_(s64) = G_EXTRACT_VECTOR_ELT %3(<2 x s64>), %5(s64)
- $d0 = COPY %4(s64)
+ %0:_(<2 x f64>) = COPY $q0
+ %2:_(<2 x f64>) = G_IMPLICIT_DEF
+ %5:_(i64) = G_CONSTANT i64 0
+ %1:_(<2 x f64>) = G_SHUFFLE_VECTOR %0(<2 x f64>), %2, shufflemask(0, undef)
+ %3:_(<2 x f64>) = G_FADD %1, %0
+ %4:_(f64) = G_EXTRACT_VECTOR_ELT %3(<2 x f64>), %5(i64)
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
index 8e0121f922849..4ab3721440934 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
@@ -13,18 +13,18 @@ body: |
; CHECK-LABEL: name: or_combine_sext
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y
- ; CHECK-NEXT: %logic_op:_(s64) = G_SEXT [[OR]](s32)
- ; CHECK-NEXT: $x0 = COPY %logic_op(s64)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR %x, %y
+ ; CHECK-NEXT: %logic_op:_(i64) = G_SEXT [[OR]](i32)
+ ; CHECK-NEXT: $x0 = COPY %logic_op(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %hand1:_(s64) = G_SEXT %x(s32)
- %hand2:_(s64) = G_SEXT %y(s32)
- %logic_op:_(s64) = G_OR %hand1, %hand2
- $x0 = COPY %logic_op(s64)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %hand1:_(i64) = G_SEXT %x(i32)
+ %hand2:_(i64) = G_SEXT %y(i32)
+ %logic_op:_(i64) = G_OR %hand1, %hand2
+ $x0 = COPY %logic_op(i64)
RET_ReallyLR implicit $x0
...
@@ -40,23 +40,23 @@ body: |
; CHECK-LABEL: name: illegal_ty
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x_wide:_(s32) = COPY $w0
- ; CHECK-NEXT: %y_wide:_(s32) = COPY $w1
- ; CHECK-NEXT: %x:_(s1) = G_TRUNC %x_wide(s32)
- ; CHECK-NEXT: %y:_(s1) = G_TRUNC %y_wide(s32)
- ; CHECK-NEXT: %hand1:_(s64) = G_SEXT %x(s1)
- ; CHECK-NEXT: %hand2:_(s64) = G_SEXT %y(s1)
- ; CHECK-NEXT: %logic_op:_(s64) = G_OR %hand1, %hand2
- ; CHECK-NEXT: $x0 = COPY %logic_op(s64)
+ ; CHECK-NEXT: %x_wide:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y_wide:_(i32) = COPY $w1
+ ; CHECK-NEXT: %x:_(i1) = G_TRUNC %x_wide(i32)
+ ; CHECK-NEXT: %y:_(i1) = G_TRUNC %y_wide(i32)
+ ; CHECK-NEXT: %hand1:_(i64) = G_SEXT %x(i1)
+ ; CHECK-NEXT: %hand2:_(i64) = G_SEXT %y(i1)
+ ; CHECK-NEXT: %logic_op:_(i64) = G_OR %hand1, %hand2
+ ; CHECK-NEXT: $x0 = COPY %logic_op(i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %x_wide:_(s32) = COPY $w0
- %y_wide:_(s32) = COPY $w1
- %x:_(s1) = G_TRUNC %x_wide
- %y:_(s1) = G_TRUNC %y_wide
- %hand1:_(s64) = G_SEXT %x(s1)
- %hand2:_(s64) = G_SEXT %y(s1)
- %logic_op:_(s64) = G_OR %hand1, %hand2
- $x0 = COPY %logic_op(s64)
+ %x_wide:_(i32) = COPY $w0
+ %y_wide:_(i32) = COPY $w1
+ %x:_(i1) = G_TRUNC %x_wide
+ %y:_(i1) = G_TRUNC %y_wide
+ %hand1:_(i64) = G_SEXT %x(i1)
+ %hand2:_(i64) = G_SEXT %y(i1)
+ %logic_op:_(i64) = G_OR %hand1, %hand2
+ $x0 = COPY %logic_op(i64)
RET_ReallyLR implicit $x0
...
@@ -71,13 +71,13 @@ body: |
; CHECK-LABEL: name: dont_combine_physreg
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:_(s32) = COPY $w0
- ; CHECK-NEXT: %y:_(s32) = COPY $w1
- ; CHECK-NEXT: %logic_op:_(s32) = G_OR %x, %y
- ; CHECK-NEXT: $w0 = COPY %logic_op(s32)
+ ; CHECK-NEXT: %x:_(i32) = COPY $w0
+ ; CHECK-NEXT: %y:_(i32) = COPY $w1
+ ; CHECK-NEXT: %logic_op:_(i32) = G_OR %x, %y
+ ; CHECK-NEXT: $w0 = COPY %logic_op(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %x:_(s32) = COPY $w0
- %y:_(s32) = COPY $w1
- %logic_op:_(s32) = G_OR %x, %y
- $w0 = COPY %logic_op(s32)
+ %x:_(i32) = COPY $w0
+ %y:_(i32) = COPY $w1
+ %logic_op:_(i32) = G_OR %x, %y
+ $w0 = COPY %logic_op(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-mulpow2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-mulpow2.mir
index 7cba6b78c5b4e..f9bc49db4a1f5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-mulpow2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-mulpow2.mir
@@ -15,19 +15,19 @@ body: |
; CHECK-LABEL: name: dont_combine_ptr_add
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %reg0:_(s64) = COPY $x0
- ; CHECK-NEXT: %reg1:_(s64) = COPY $x1
+ ; CHECK-NEXT: %reg0:_(i64) = COPY $x0
+ ; CHECK-NEXT: %reg1:_(i64) = COPY $x1
; CHECK-NEXT: %ptr:_(p0) = COPY $x2
- ; CHECK-NEXT: %cst:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: %mul:_(s64) = nsw G_MUL %reg0, %cst
- ; CHECK-NEXT: %ptr_add:_(p0) = G_PTR_ADD %ptr, %mul(s64)
+ ; CHECK-NEXT: %cst:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: %mul:_(i64) = nsw G_MUL %reg0, %cst
+ ; CHECK-NEXT: %ptr_add:_(p0) = G_PTR_ADD %ptr, %mul(i64)
; CHECK-NEXT: $x0 = COPY %ptr_add(p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:_(s64) = COPY $x0
- %reg1:_(s64) = COPY $x1
+ %reg0:_(i64) = COPY $x0
+ %reg1:_(i64) = COPY $x1
%ptr:_(p0) = COPY $x2
- %cst:_(s64) = G_CONSTANT i64 6
- %mul:_(s64) = nsw G_MUL %reg0, %cst
+ %cst:_(i64) = G_CONSTANT i64 6
+ %mul:_(i64) = nsw G_MUL %reg0, %cst
%ptr_add:_(p0) = G_PTR_ADD %ptr, %mul
$x0 = COPY %ptr_add(p0)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
index 2bb4f00bcde72..4229c53649322 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
@@ -17,15 +17,15 @@ body: |
; CHECK-LABEL: name: rotl
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
- ; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(i32) = G_ROTL [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[ROTL]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:_(s32) = COPY $w0
- %5:_(s64) = G_CONSTANT i64 -16
- %2:_(s32) = G_ROTL %0, %5(s64)
- $w0 = COPY %2(s32)
+ %0:_(i32) = COPY $w0
+ %5:_(i64) = G_CONSTANT i64 -16
+ %2:_(i32) = G_ROTL %0, %5(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -43,15 +43,15 @@ body: |
; CHECK-LABEL: name: rotr
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[C]](s64)
- ; CHECK-NEXT: $w0 = COPY [[ROTR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(i32) = G_ROTR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[ROTR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:_(s32) = COPY $w0
- %5:_(s64) = G_CONSTANT i64 -16
- %2:_(s32) = G_ROTR %0, %5(s64)
- $w0 = COPY %2(s32)
+ %0:_(i32) = COPY $w0
+ %5:_(i64) = G_CONSTANT i64 -16
+ %2:_(i32) = G_ROTR %0, %5(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -69,15 +69,15 @@ body: |
; CHECK-LABEL: name: rotl_bitwidth_cst
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
- ; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(i32) = G_ROTL [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[ROTL]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:_(s32) = COPY $w0
- %5:_(s64) = G_CONSTANT i64 32
- %2:_(s32) = G_ROTL %0, %5(s64)
- $w0 = COPY %2(s32)
+ %0:_(i32) = COPY $w0
+ %5:_(i64) = G_CONSTANT i64 32
+ %2:_(i32) = G_ROTL %0, %5(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -95,15 +95,15 @@ body: |
; CHECK-LABEL: name: rotl_bitwidth_minus_one_cst
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)
- ; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 31
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(i32) = G_ROTL [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[ROTL]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:_(s32) = COPY $w0
- %5:_(s64) = G_CONSTANT i64 31
- %2:_(s32) = G_ROTL %0, %5(s64)
- $w0 = COPY %2(s32)
+ %0:_(i32) = COPY $w0
+ %5:_(i64) = G_CONSTANT i64 31
+ %2:_(i32) = G_ROTL %0, %5(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir
index ac0d561c99a1b..c2c457884c786 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir
@@ -10,12 +10,12 @@ body: |
; CHECK-LABEL: name: test_combine_select_same_res
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
- %0:_(s64) = COPY $x0
- %1:_(s1) = G_TRUNC %0
- %2:_(s64) = G_SELECT %1, %0, %0
- $x0 = COPY %2(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
+ %0:_(i64) = COPY $x0
+ %1:_(i1) = G_TRUNC %0
+ %2:_(i64) = G_SELECT %1, %0, %0
+ $x0 = COPY %2(i64)
...
---
# select (undef, x, y) -> y
@@ -27,13 +27,13 @@ body: |
; CHECK-LABEL: name: test_combine_select_undef_res0_res1
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
- %0:_(s64) = COPY $x0
- %1:_(s64) = COPY $x1
- %2:_(s1) = G_IMPLICIT_DEF
- %3:_(s64) = G_SELECT %2, %0, %1
- $x0 = COPY %3(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
+ %0:_(i64) = COPY $x0
+ %1:_(i64) = COPY $x1
+ %2:_(i1) = G_IMPLICIT_DEF
+ %3:_(i64) = G_SELECT %2, %0, %1
+ $x0 = COPY %3(i64)
...
---
# select (false, x, y) -> y
@@ -45,13 +45,13 @@ body: |
; CHECK-LABEL: name: test_combine_select_false_res0_res1
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
- %0:_(s64) = COPY $x0
- %1:_(s64) = COPY $x1
- %2:_(s1) = G_CONSTANT i1 false
- %3:_(s64) = G_SELECT %2, %0, %1
- $x0 = COPY %3(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
+ %0:_(i64) = COPY $x0
+ %1:_(i64) = COPY $x1
+ %2:_(i1) = G_CONSTANT i1 false
+ %3:_(i64) = G_SELECT %2, %0, %1
+ $x0 = COPY %3(i64)
...
---
# select (true, x, y) -> x
@@ -63,11 +63,11 @@ body: |
; CHECK-LABEL: name: test_combine_select_true_res0_res1
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
- %0:_(s64) = COPY $x0
- %1:_(s64) = COPY $x1
- %2:_(s1) = G_CONSTANT i1 true
- %3:_(s64) = G_SELECT %2, %0, %1
- $x0 = COPY %3(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
+ %0:_(i64) = COPY $x0
+ %1:_(i64) = COPY $x1
+ %2:_(i1) = G_CONSTANT i1 true
+ %3:_(i64) = G_SELECT %2, %0, %1
+ $x0 = COPY %3(i64)
...
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