[llvm] [SelectionDAG] Add computeKnownBits support for ISD::VECREDUCE_ADD (PR #207631)

[Sabona Abdi via llvm-commits]

================
@@ -38,31 +40,82 @@ entry:
 }
 
 define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-LABEL: sad_4x8_as_i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vmv.s.x v10, zero
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT:    vminu.vv v11, v8, v9
-; CHECK-NEXT:    vmaxu.vv v8, v8, v9
-; CHECK-NEXT:    vsub.vv v8, v8, v11
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT:    vzext.vf4 v9, v8
-; CHECK-NEXT:    vredsum.vs v8, v9, v10
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    ret
+; RV32-LABEL: sad_4x8_as_i32:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    vmv.s.x v10, zero
+; RV32-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT:    vminu.vv v11, v8, v9
+; RV32-NEXT:    vmaxu.vv v8, v8, v9
+; RV32-NEXT:    vsub.vv v8, v8, v11
+; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT:    vzext.vf4 v9, v8
+; RV32-NEXT:    vredsum.vs v8, v9, v10
+; RV32-NEXT:    vmv.x.s a0, v8
+; RV32-NEXT:    ret
 ;
-; ZVABD-LABEL: sad_4x8_as_i32:
-; ZVABD:       # %bb.0: # %entry
-; ZVABD-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; ZVABD-NEXT:    vmv.s.x v10, zero
-; ZVABD-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; ZVABD-NEXT:    vabdu.vv v8, v8, v9
-; ZVABD-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
-; ZVABD-NEXT:    vzext.vf4 v9, v8
-; ZVABD-NEXT:    vredsum.vs v8, v9, v10
-; ZVABD-NEXT:    vmv.x.s a0, v8
-; ZVABD-NEXT:    ret
+; RV64-LABEL: sad_4x8_as_i32:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT:    vmv.s.x v10, zero
+; RV64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT:    vminu.vv v11, v8, v9
+; RV64-NEXT:    vmaxu.vv v8, v8, v9
+; RV64-NEXT:    vsub.vv v8, v8, v11
+; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT:    vzext.vf4 v9, v8
+; RV64-NEXT:    vredsum.vs v8, v9, v10
+; RV64-NEXT:    vmv.x.s a0, v8
+; RV64-NEXT:    andi a0, a0, 1023
+; RV64-NEXT:    ret
+;
+; RV32ZVABD-LABEL: sad_4x8_as_i32:
+; RV32ZVABD:       # %bb.0: # %entry
+; RV32ZVABD-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32ZVABD-NEXT:    vmv.s.x v10, zero
+; RV32ZVABD-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
+; RV32ZVABD-NEXT:    vabdu.vv v8, v8, v9
+; RV32ZVABD-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVABD-NEXT:    vzext.vf4 v9, v8
+; RV32ZVABD-NEXT:    vredsum.vs v8, v9, v10
+; RV32ZVABD-NEXT:    vmv.x.s a0, v8
+; RV32ZVABD-NEXT:    ret
+;
+; RV64ZVABD-LABEL: sad_4x8_as_i32:
+; RV64ZVABD:       # %bb.0: # %entry
+; RV64ZVABD-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64ZVABD-NEXT:    vmv.s.x v10, zero
+; RV64ZVABD-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
+; RV64ZVABD-NEXT:    vabdu.vv v8, v8, v9
+; RV64ZVABD-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVABD-NEXT:    vzext.vf4 v9, v8
+; RV64ZVABD-NEXT:    vredsum.vs v8, v9, v10
+; RV64ZVABD-NEXT:    vmv.x.s a0, v8
+; RV64ZVABD-NEXT:    andi a0, a0, 1023
+; RV64ZVABD-NEXT:    ret
+; ZVABD32-LABEL: sad_4x8_as_i32:
----------------
sabonaoabdi wrote:

removed the ZVABD32 and ZVABD64 lines, thanks

https://github.com/llvm/llvm-project/pull/207631