[llvm] [AArch64] Fold vector shifts guarded against oversized amounts into USHL (PR #207628)
Adam Scott via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 9 18:09:02 PDT 2026
================
@@ -0,0 +1,324 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64-none-elf < %s | FileCheck %s
+
+define <4 x i32> @masked_shl_v4i32(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: masked_shl_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #63
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %m = and <4 x i32> %amt, splat (i32 63)
+ %shl = shl <4 x i32> %x, %m
+ %ok = icmp ult <4 x i32> %m, splat (i32 32)
+ %res = select <4 x i1> %ok, <4 x i32> %shl, <4 x i32> zeroinitializer
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @masked_shl_v4i32_swapped(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: masked_shl_v4i32_swapped:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #63
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %m = and <4 x i32> %amt, splat (i32 63)
+ %shl = shl <4 x i32> %x, %m
+ %oob = icmp uge <4 x i32> %m, splat (i32 32)
+ %res = select <4 x i1> %oob, <4 x i32> zeroinitializer, <4 x i32> %shl
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @masked_srl_v4i32(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: masked_srl_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #63
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %m = and <4 x i32> %amt, splat (i32 63)
+ %srl = lshr <4 x i32> %x, %m
+ %ok = icmp ult <4 x i32> %m, splat (i32 32)
+ %res = select <4 x i1> %ok, <4 x i32> %srl, <4 x i32> zeroinitializer
+ ret <4 x i32> %res
+}
+
+define <16 x i8> @masked_shl_v16i8(<16 x i8> %x, <16 x i8> %amt) {
+; CHECK-LABEL: masked_shl_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.16b, #15
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ushl v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+entry:
+ %m = and <16 x i8> %amt, splat (i8 15)
+ %shl = shl <16 x i8> %x, %m
+ %ok = icmp ult <16 x i8> %m, splat (i8 8)
+ %res = select <16 x i1> %ok, <16 x i8> %shl, <16 x i8> zeroinitializer
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @masked_shl_v8i16(<8 x i16> %x, <8 x i16> %amt) {
+; CHECK-LABEL: masked_shl_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.8h, #31
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+entry:
+ %m = and <8 x i16> %amt, splat (i16 31)
+ %shl = shl <8 x i16> %x, %m
+ %ok = icmp ult <8 x i16> %m, splat (i16 16)
+ %res = select <8 x i1> %ok, <8 x i16> %shl, <8 x i16> zeroinitializer
+ ret <8 x i16> %res
+}
+
+define <2 x i64> @masked_shl_v2i64(<2 x i64> %x, <2 x i64> %amt) {
+; CHECK-LABEL: masked_shl_v2i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #127 // =0x7f
+; CHECK-NEXT: dup v2.2d, x8
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ushl v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+entry:
+ %m = and <2 x i64> %amt, splat (i64 127)
+ %shl = shl <2 x i64> %x, %m
+ %ok = icmp ult <2 x i64> %m, splat (i64 64)
+ %res = select <2 x i1> %ok, <2 x i64> %shl, <2 x i64> zeroinitializer
+ ret <2 x i64> %res
+}
+
+define <2 x i32> @masked_shl_v2i32(<2 x i32> %x, <2 x i32> %amt) {
+; CHECK-LABEL: masked_shl_v2i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.2s, #63
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+entry:
+ %m = and <2 x i32> %amt, splat (i32 63)
+ %shl = shl <2 x i32> %x, %m
+ %ok = icmp ult <2 x i32> %m, splat (i32 32)
+ %res = select <2 x i1> %ok, <2 x i32> %shl, <2 x i32> zeroinitializer
+ ret <2 x i32> %res
+}
+
+define <4 x i32> @unbounded_shl_v4i32(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: unbounded_shl_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #32
+; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %shl = shl <4 x i32> %x, %amt
+ %ok = icmp ult <4 x i32> %amt, splat (i32 32)
+ %res = select <4 x i1> %ok, <4 x i32> %shl, <4 x i32> zeroinitializer
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @unbounded_srl_v4i32(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: unbounded_srl_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #32
+; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %srl = lshr <4 x i32> %x, %amt
+ %ok = icmp ult <4 x i32> %amt, splat (i32 32)
+ %res = select <4 x i1> %ok, <4 x i32> %srl, <4 x i32> zeroinitializer
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @masked_shl_v4i32_mask255(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: masked_shl_v4i32_mask255:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-NEXT: movi v3.4s, #32
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: umin v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %m = and <4 x i32> %amt, splat (i32 255)
+ %shl = shl <4 x i32> %x, %m
+ %ok = icmp ult <4 x i32> %m, splat (i32 32)
+ %res = select <4 x i1> %ok, <4 x i32> %shl, <4 x i32> zeroinitializer
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @masked_input_shl_v4i32(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: masked_input_shl_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #63
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %m = and <4 x i32> %amt, splat (i32 63)
+ %ok = icmp ult <4 x i32> %m, splat (i32 32)
+ %zx = select <4 x i1> %ok, <4 x i32> %x, <4 x i32> zeroinitializer
+ %res = shl <4 x i32> %zx, %m
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @masked_input_shl_v4i32_swapped(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: masked_input_shl_v4i32_swapped:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #63
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %m = and <4 x i32> %amt, splat (i32 63)
+ %oob = icmp uge <4 x i32> %m, splat (i32 32)
+ %zx = select <4 x i1> %oob, <4 x i32> zeroinitializer, <4 x i32> %x
+ %res = shl <4 x i32> %zx, %m
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @masked_input_srl_v4i32(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: masked_input_srl_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #63
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: neg v1.4s, v1.4s
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+entry:
+ %m = and <4 x i32> %amt, splat (i32 63)
+ %ok = icmp ult <4 x i32> %m, splat (i32 32)
+ %zx = select <4 x i1> %ok, <4 x i32> %x, <4 x i32> zeroinitializer
+ %res = lshr <4 x i32> %zx, %m
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @unbounded_input_shl_v4i32(<4 x i32> %x, <4 x i32> %amt) {
+; CHECK-LABEL: unbounded_input_shl_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
----------------
as4230 wrote:
Yes, exactly. For amt >= 32 the shift input is 0 and shl(0, amt) is poison so the lane can be anything and ushl's result is fine
https://github.com/llvm/llvm-project/pull/207628
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