[llvm] Optimize register bank and info emission. (PR #208297)

[via llvm-commits]

https://github.com/roman1741941 updated https://github.com/llvm/llvm-project/pull/208297

>From 376f543d2b2dc977a91f568d68dea269528f46fa Mon Sep 17 00:00:00 2001
From: Roman Divacky <rdivacky at vlakno.cz>
Date: Wed, 8 Jul 2026 21:16:11 +0200
Subject: [PATCH] Optimize register bank and info emission.

Dont go via a BitVector just to a read a single value out of it.
---
 .../TableGen/Common/CodeGenRegisters.cpp      | 36 ++++++++++++-------
 llvm/utils/TableGen/Common/CodeGenRegisters.h |  9 +++++
 llvm/utils/TableGen/RegisterBankEmitter.cpp   |  4 +--
 3 files changed, 34 insertions(+), 15 deletions(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index eb6f07d761029..1530fa05883aa 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1024,18 +1024,12 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
          "Biggest class wasn't first");
 
   // Find all the subreg classes and order them by size too.
-  std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
+  std::vector<CodeGenRegisterClass *> SuperRegClasses;
   for (auto &RC : RegClasses) {
-    BitVector SuperRegClassesBV(RegClasses.size());
-    RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
-    if (SuperRegClassesBV.any())
-      SuperRegClasses.emplace_back(&RC, SuperRegClassesBV);
+    if (!RC.emptySuperRegClass(SubIdx))
+      SuperRegClasses.emplace_back(&RC);
   }
-  llvm::stable_sort(SuperRegClasses,
-                    [&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
-                        const std::pair<CodeGenRegisterClass *, BitVector> &B) {
-                      return WeakSizeOrder(A.first, B.first);
-                    });
+  llvm::stable_sort(SuperRegClasses, WeakSizeOrder);
 
   // Find the biggest subclass and subreg class such that R:subidx is in the
   // subreg class for all R in subclass.
@@ -1049,8 +1043,8 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
   CodeGenRegisterClass *ChosenSuperRegClass = nullptr;
   CodeGenRegisterClass *SubRegRC = nullptr;
   for (CodeGenRegisterClass *SuperRegRC : SuperRegRCs) {
-    for (const auto &[SuperRegClass, SuperRegClassBV] : SuperRegClasses) {
-      if (SuperRegClassBV[SuperRegRC->EnumValue]) {
+    for (auto *SuperRegClass : SuperRegClasses) {
+      if (SuperRegClass->hasSuperRegClass(SubIdx, SuperRegRC)) {
         SubRegRC = SuperRegClass;
         ChosenSuperRegClass = SuperRegRC;
 
@@ -1077,6 +1071,24 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
   return std::nullopt;
 }
 
+bool CodeGenRegisterClass::hasNoSuperRegClasses(
+    const CodeGenSubRegIndex *SubIdx) const {
+  auto FindI = SuperRegClasses.find(SubIdx);
+  if (FindI == SuperRegClasses.end())
+    return true;
+
+  return FindI->second.empty();
+}
+
+bool CodeGenRegisterClass::hasSuperRegClass(
+    const CodeGenSubRegIndex *SubIdx, const CodeGenRegisterClass *RC) const {
+  auto FindI = SuperRegClasses.find(SubIdx);
+  if (FindI == SuperRegClasses.end())
+    return false;
+
+  return FindI->second.contains(RC);
+}
+
 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
                                               BitVector &Out) const {
   auto FindI = SuperRegClasses.find(SubIdx);
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 077294783f8ae..f76d019e9caf5 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -447,6 +447,15 @@ class CodeGenRegisterClass {
     SubClassWithSubReg[SubIdx] = SubRC;
   }
 
+  /// Checks if there are no super-register classes for this SubIdx of this
+  /// class.
+  bool hasNoSuperRegClasses(const CodeGenSubRegIndex *SubIdx) const;
+
+  /// Checks if there is any super-register class for this SubIdx of this
+  /// class.
+  bool hasSuperRegClass(const CodeGenSubRegIndex *SubIdx,
+                        const CodeGenRegisterClass *RC) const;
+
   // getSuperRegClasses - Returns a bit vector of all register classes
   // containing only SubIdx super-registers of this class.
   void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index c2cb06fe456c7..c53aca4444057 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -206,9 +206,7 @@ static void visitRegisterBankClasses(
     // PossibleSubclass for all registers Reg from RC using any
     // subregister-index SubReg
     for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
-      BitVector BV(RegisterClassHierarchy.getRegClasses().size());
-      PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
-      if (BV.test(RC->EnumValue)) {
+      if (PossibleSubclass.hasSuperRegClass(&SubIdx, RC)) {
         std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +
                                 " class-with-subregs: " + RC->getName())
                                    .str();