[llvm] 64a9e0c - [AArch64][GlobalISel] Update scalar types in selection tests. NFC (#208534)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 9 12:03:00 PDT 2026
Author: David Green
Date: 2026-07-09T20:02:54+01:00
New Revision: 64a9e0c2a5301797ca4cc89b9a332f01e34404fe
URL: https://github.com/llvm/llvm-project/commit/64a9e0c2a5301797ca4cc89b9a332f01e34404fe
DIFF: https://github.com/llvm/llvm-project/commit/64a9e0c2a5301797ca4cc89b9a332f01e34404fe.diff
LOG: [AArch64][GlobalISel] Update scalar types in selection tests. NFC (#208534)
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-bit.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-extract.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ld2.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ld4.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-modf.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-st2.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ubfx.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-zip.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
index 9389fff12fb93..49ed1f35b03af 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
@@ -203,8 +203,8 @@ body: |
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
%wide_1:gpr(i32) = COPY $w1
- %1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(i32) = G_SEXT %1(s8)
+ %1:gpr(i8) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_SEXT %1(i8)
%add_lhs:gpr(i32) = COPY $w2
%res:gpr(i32) = G_ADD %add_lhs, %ext
$w3 = COPY %res(i32)
@@ -229,8 +229,8 @@ body: |
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
%wide_1:gpr(i32) = COPY $w1
- %1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(i32) = G_ZEXT %1(s8)
+ %1:gpr(i8) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ZEXT %1(i8)
%add_lhs:gpr(i32) = COPY $w2
%res:gpr(i32) = G_ADD %add_lhs, %ext
$w3 = COPY %res(i32)
@@ -255,8 +255,8 @@ body: |
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
%wide_1:gpr(i32) = COPY $w1
- %1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(i32) = G_ANYEXT %1(s8)
+ %1:gpr(i8) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ANYEXT %1(i8)
%add_lhs:gpr(i32) = COPY $w2
%res:gpr(i32) = G_ADD %add_lhs, %ext
$w3 = COPY %res(i32)
@@ -541,8 +541,8 @@ body: |
bb.0:
liveins: $w1, $w2, $x2
%wide_1:gpr(i32) = COPY $w1
- %1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(i32) = G_SEXT %1(s8)
+ %1:gpr(i8) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_SEXT %1(i8)
%sub_lhs:gpr(i32) = COPY $w2
%res:gpr(i32) = G_SUB %sub_lhs, %ext
$w3 = COPY %res(i32)
@@ -567,8 +567,8 @@ body: |
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
%wide_1:gpr(i32) = COPY $w1
- %1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(i32) = G_ZEXT %1(s8)
+ %1:gpr(i8) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ZEXT %1(i8)
%sub_lhs:gpr(i32) = COPY $w2
%res:gpr(i32) = G_SUB %sub_lhs, %ext
$w3 = COPY %res(i32)
@@ -593,8 +593,8 @@ body: |
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
%wide_1:gpr(i32) = COPY $w1
- %1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(i32) = G_ANYEXT %1(s8)
+ %1:gpr(i8) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ANYEXT %1(i8)
%sub_lhs:gpr(i32) = COPY $w2
%res:gpr(i32) = G_SUB %sub_lhs, %ext
$w3 = COPY %res(i32)
@@ -721,8 +721,8 @@ body: |
%0:gpr(p0) = COPY $x0
%1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %small:gpr(s8) = G_TRUNC %1
- %zext:gpr(i64) = G_ZEXT %small(s8)
+ %small:gpr(i8) = G_TRUNC %1
+ %zext:gpr(i64) = G_ZEXT %small(i8)
%cst:gpr(i64) = G_CONSTANT i64 3
%shl:gpr(i64) = G_SHL %zext, %cst(i64)
%gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
@@ -793,8 +793,8 @@ body: |
%0:gpr(p0) = COPY $x0
%1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %small:gpr(s8) = G_TRUNC %1
- %zext:gpr(i64) = G_SEXT %small(s8)
+ %small:gpr(i8) = G_TRUNC %1
+ %zext:gpr(i64) = G_SEXT %small(i8)
%cst:gpr(i64) = G_CONSTANT i64 3
%shl:gpr(i64) = G_SHL %zext, %cst(i64)
%gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
index da3c962f2468e..5d9b7e0d42a01 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
@@ -32,12 +32,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (s8) from %ir.ptr, align 8)
+ ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (i8) from %ir.ptr, align 8)
; CHECK-NEXT: $w0 = COPY [[LDARB]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_LOAD %0(p0) :: (load acquire (s8) from %ir.ptr, align 8)
- $w0 = COPY %2(s32)
+ %2:gpr(i32) = G_LOAD %0(p0) :: (load acquire (i8) from %ir.ptr, align 8)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -50,13 +50,13 @@ body: |
bb.1:
; CHECK-LABEL: name: anyext_load_monotonic_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $xzr
- ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load monotonic (s32) from `ptr null`)
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load monotonic (i32) from `ptr null`)
; CHECK-NEXT: %ld:gpr64all = SUBREG_TO_REG [[LDRWui]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY %ld
; CHECK-NEXT: RET_ReallyLR implicit $x0
%1:gpr(p0) = G_CONSTANT i64 0
- %ld:gpr(s64) = G_LOAD %1(p0) :: (load monotonic (s32) from `ptr null`)
- $x0 = COPY %ld(s64)
+ %ld:gpr(i64) = G_LOAD %1(p0) :: (load monotonic (i32) from `ptr null`)
+ $x0 = COPY %ld(i64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
index 457c5d6411b64..7d8c1e0f1b28e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
@@ -33,12 +33,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
- ; CHECK-NEXT: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)
+ ; CHECK-NEXT: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (i64) on %ir.addr)
; CHECK-NEXT: $x0 = COPY [[SWPX]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 1
- %2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic (s64) on %ir.addr)
- $x0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 1
+ %2:gpr(i64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic (i64) on %ir.addr)
+ $x0 = COPY %2(i64)
...
---
name: atomicrmw_add_i64
@@ -55,12 +55,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
- ; CHECK-NEXT: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)
+ ; CHECK-NEXT: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (i64) on %ir.addr)
; CHECK-NEXT: $x0 = COPY [[LDADDX]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 1
- %2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s64) on %ir.addr)
- $x0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 1
+ %2:gpr(i64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (i64) on %ir.addr)
+ $x0 = COPY %2(i64)
...
---
name: atomicrmw_add_i32
@@ -76,12 +76,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDADDALW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -98,12 +98,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDADDALW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -121,12 +121,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]]
- ; CHECK-NEXT: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDCLRAW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -143,12 +143,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDSETLW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_OR %0, %1 :: (load store release (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -165,12 +165,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDEORALW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -187,12 +187,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDSMINALW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -209,12 +209,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDSMAXALW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -231,12 +231,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDUMINALW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
---
@@ -253,10 +253,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)
+ ; CHECK-NEXT: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDUMAXALW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel (s32) on %ir.addr)
- $w0 = COPY %2(s32)
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel (i32) on %ir.addr)
+ $w0 = COPY %2(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bit.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bit.mir
index e3edb62809774..e64da1ec822ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bit.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bit.mir
@@ -20,11 +20,11 @@ body: |
; CHECK-NEXT: %bit:fpr64 = BSPv8i8 %lhs, %mhs, %rhs
; CHECK-NEXT: $d0 = COPY %bit
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %lhs:fpr(<2 x s32>) = COPY $d0
- %mhs:fpr(<2 x s32>) = COPY $d1
- %rhs:fpr(<2 x s32>) = COPY $d2
- %bit:fpr(<2 x s32>) = G_BSP %lhs, %mhs, %rhs
- $d0 = COPY %bit(<2 x s32>)
+ %lhs:fpr(<2 x i32>) = COPY $d0
+ %mhs:fpr(<2 x i32>) = COPY $d1
+ %rhs:fpr(<2 x i32>) = COPY $d2
+ %bit:fpr(<2 x i32>) = G_BSP %lhs, %mhs, %rhs
+ $d0 = COPY %bit(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -45,11 +45,11 @@ body: |
; CHECK-NEXT: %bit:fpr64 = BSPv8i8 %lhs, %mhs, %rhs
; CHECK-NEXT: $d0 = COPY %bit
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %lhs:fpr(<4 x s16>) = COPY $d0
- %mhs:fpr(<4 x s16>) = COPY $d1
- %rhs:fpr(<4 x s16>) = COPY $d2
- %bit:fpr(<4 x s16>) = G_BSP %lhs, %mhs, %rhs
- $d0 = COPY %bit(<4 x s16>)
+ %lhs:fpr(<4 x i16>) = COPY $d0
+ %mhs:fpr(<4 x i16>) = COPY $d1
+ %rhs:fpr(<4 x i16>) = COPY $d2
+ %bit:fpr(<4 x i16>) = G_BSP %lhs, %mhs, %rhs
+ $d0 = COPY %bit(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -71,11 +71,11 @@ body: |
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
; CHECK-NEXT: $q0 = COPY %bit
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %mhs:fpr(<2 x s64>) = COPY $q1
- %rhs:fpr(<2 x s64>) = COPY $q2
- %bit:fpr(<2 x s64>) = G_BSP %lhs, %mhs, %rhs
- $q0 = COPY %bit(<2 x s64>)
+ %lhs:fpr(<2 x i64>) = COPY $q0
+ %mhs:fpr(<2 x i64>) = COPY $q1
+ %rhs:fpr(<2 x i64>) = COPY $q2
+ %bit:fpr(<2 x i64>) = G_BSP %lhs, %mhs, %rhs
+ $q0 = COPY %bit(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -97,11 +97,11 @@ body: |
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
; CHECK-NEXT: $q0 = COPY %bit
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<4 x s32>) = COPY $q0
- %mhs:fpr(<4 x s32>) = COPY $q1
- %rhs:fpr(<4 x s32>) = COPY $q2
- %bit:fpr(<4 x s32>) = G_BSP %lhs, %mhs, %rhs
- $q0 = COPY %bit(<4 x s32>)
+ %lhs:fpr(<4 x i32>) = COPY $q0
+ %mhs:fpr(<4 x i32>) = COPY $q1
+ %rhs:fpr(<4 x i32>) = COPY $q2
+ %bit:fpr(<4 x i32>) = G_BSP %lhs, %mhs, %rhs
+ $q0 = COPY %bit(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -123,11 +123,11 @@ body: |
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
; CHECK-NEXT: $q0 = COPY %bit
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<8 x s16>) = COPY $q0
- %mhs:fpr(<8 x s16>) = COPY $q1
- %rhs:fpr(<8 x s16>) = COPY $q2
- %bit:fpr(<8 x s16>) = G_BSP %lhs, %mhs, %rhs
- $q0 = COPY %bit(<8 x s16>)
+ %lhs:fpr(<8 x i16>) = COPY $q0
+ %mhs:fpr(<8 x i16>) = COPY $q1
+ %rhs:fpr(<8 x i16>) = COPY $q2
+ %bit:fpr(<8 x i16>) = G_BSP %lhs, %mhs, %rhs
+ $q0 = COPY %bit(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -149,9 +149,9 @@ body: |
; CHECK-NEXT: %bit:fpr128 = BSPv16i8 %lhs, %mhs, %rhs
; CHECK-NEXT: $q0 = COPY %bit
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<16 x s8>) = COPY $q0
- %mhs:fpr(<16 x s8>) = COPY $q1
- %rhs:fpr(<16 x s8>) = COPY $q2
- %bit:fpr(<16 x s8>) = G_BSP %lhs, %mhs, %rhs
- $q0 = COPY %bit(<16 x s8>)
+ %lhs:fpr(<16 x i8>) = COPY $q0
+ %mhs:fpr(<16 x i8>) = COPY $q1
+ %rhs:fpr(<16 x i8>) = COPY $q2
+ %bit:fpr(<16 x i8>) = G_BSP %lhs, %mhs, %rhs
+ $q0 = COPY %bit(<16 x i8>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
index 74436c21d79d8..fb38abd071c0f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
@@ -17,7 +17,7 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
; CHECK-NEXT: [[REV64v2i32_:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY2]]
; CHECK-NEXT: $x0 = COPY [[REV64v2i32_]]
- %0:fpr(<2 x s32>) = COPY $x0
- %1:fpr(s64) = G_BITCAST %0
- $x0 = COPY %1(s64)
+ %0:fpr(<2 x i32>) = COPY $x0
+ %1:fpr(i64) = G_BITCAST %0
+ $x0 = COPY %1(i64)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
index e615b4d8efbb4..8ffea5447afde 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
@@ -35,9 +35,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[COPY2]]
- %0(s32) = COPY $w0
- %1(<2 x s16>) = G_BITCAST %0
- %2(s32) = G_BITCAST %1
+ %0(i32) = COPY $w0
+ %1(<2 x i16>) = G_BITCAST %0
+ %2(i32) = G_BITCAST %1
$w0 = COPY %2
...
@@ -61,9 +61,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[COPY1]]
; CHECK-NEXT: $s0 = COPY [[COPY2]]
- %0(s32) = COPY $s0
- %1(<2 x s16>) = G_BITCAST %0
- %2(s32) = G_BITCAST %1
+ %0(i32) = COPY $s0
+ %1(<2 x i16>) = G_BITCAST %0
+ %2(i32) = G_BITCAST %1
$s0 = COPY %2
...
@@ -86,8 +86,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
; CHECK-NEXT: $s0 = COPY [[COPY1]]
- %0(s32) = COPY $w0
- %1(<2 x s16>) = G_BITCAST %0
+ %0(i32) = COPY $w0
+ %1(<2 x i16>) = G_BITCAST %0
$s0 = COPY %1
...
@@ -110,9 +110,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %0(<2 x s16>) = COPY $s0
- %1(s32) = G_BITCAST %0
- $w0 = COPY %1(s32)
+ %0(<2 x i16>) = COPY $s0
+ %1(i32) = G_BITCAST %0
+ $w0 = COPY %1(i32)
...
---
@@ -136,10 +136,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[COPY2]]
- %0(s64) = COPY $x0
- %1(<2 x s32>) = G_BITCAST %0
- %2(s64) = G_BITCAST %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(<2 x i32>) = G_BITCAST %0
+ %2(i64) = G_BITCAST %1
+ $x0 = COPY %2(i64)
...
---
@@ -160,8 +160,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: $d0 = COPY [[COPY]]
- %0(s64) = COPY $d0
- %1(<2 x s32>) = G_BITCAST %0
+ %0(i64) = COPY $d0
+ %1(<2 x i32>) = G_BITCAST %0
$d0 = COPY %1
...
@@ -183,8 +183,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
; CHECK-NEXT: $d0 = COPY [[COPY1]]
- %0(s64) = COPY $x0
- %1(<2 x s32>) = G_BITCAST %0
+ %0(i64) = COPY $x0
+ %1(<2 x i32>) = G_BITCAST %0
$d0 = COPY %1
...
@@ -207,8 +207,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
; CHECK-NEXT: $x0 = COPY [[COPY1]]
- %0(s64) = COPY $d0
- %1(<2 x s32>) = G_BITCAST %0
+ %0(i64) = COPY $d0
+ %1(<2 x i32>) = G_BITCAST %0
$x0 = COPY %1
...
@@ -230,9 +230,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: $x0 = COPY [[COPY]]
- %0(s64) = COPY $d0
- %1(<2 x s32>) = G_BITCAST %0
- $x0 = COPY %1(<2 x s32>)
+ %0(i64) = COPY $d0
+ %1(<2 x i32>) = G_BITCAST %0
+ $x0 = COPY %1(<2 x i32>)
...
---
@@ -253,7 +253,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: $x0 = COPY [[COPY]]
- %0(s64) = COPY $d0
- %1(<8 x s8>) = G_BITCAST %0
- $x0 = COPY %1(<8 x s8>)
+ %0(i64) = COPY $d0
+ %1(<8 x i8>) = G_BITCAST %0
+ $x0 = COPY %1(<8 x i8>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
index e47411b7b178a..fae3870534ad9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
@@ -42,7 +42,7 @@ registers:
body: |
bb.0:
successors: %bb.0, %bb.1
- %1(s32) = COPY $w0
+ %1(i32) = COPY $w0
G_BRCOND %1, %bb.1
G_BR %bb.0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
index d0f2c9ceed7ef..5df0ea7811e83 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
@@ -13,7 +13,7 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: TBZW [[LDRBBui]], 0, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -26,7 +26,7 @@ body: |
liveins: $x0
%0:gpr(p0) = COPY $x0
- %8:gpr(i8) = G_LOAD %0(p0) :: (load (s8))
+ %8:gpr(i8) = G_LOAD %0(p0) :: (load (i8))
%4:gpr(i32) = G_ANYEXT %8(i8)
%5:gpr(i32) = G_CONSTANT i32 1
%6:gpr(i32) = G_XOR %4, %5
@@ -52,7 +52,7 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: TBZW [[LDRBBui]], 0, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -67,7 +67,7 @@ body: |
liveins: $x0
%0:gpr(p0) = COPY $x0
- %8:gpr(i8) = G_LOAD %0(p0) :: (load (s8))
+ %8:gpr(i8) = G_LOAD %0(p0) :: (load (i8))
%4:gpr(i64) = G_ANYEXT %8(i8)
%5:gpr(i64) = G_CONSTANT i64 1
%6:gpr(i64) = G_XOR %4, %5
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
index 5e0121682e327..46773eab46eaf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
@@ -21,8 +21,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
; CHECK-NEXT: $w0 = COPY [[REVWr]]
- %0(s32) = COPY $w0
- %1(s32) = G_BSWAP %0
+ %0(i32) = COPY $w0
+ %1(i32) = G_BSWAP %0
$w0 = COPY %1
...
@@ -45,8 +45,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
; CHECK-NEXT: $x0 = COPY [[REVXr]]
- %0(s64) = COPY $x0
- %1(s64) = G_BSWAP %0
+ %0(i64) = COPY $x0
+ %1(i64) = G_BSWAP %0
$x0 = COPY %1
...
@@ -68,9 +68,9 @@ body: |
; CHECK-NEXT: [[REV16v8i8_:%[0-9]+]]:fpr64 = REV16v8i8 [[COPY]]
; CHECK-NEXT: $d0 = COPY [[REV16v8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_BSWAP %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = G_BSWAP %0
+ $d0 = COPY %1(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -91,9 +91,9 @@ body: |
; CHECK-NEXT: [[REV16v16i8_:%[0-9]+]]:fpr128 = REV16v16i8 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[REV16v16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_BSWAP %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = G_BSWAP %0
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -115,9 +115,9 @@ body: |
; CHECK-NEXT: [[REV32v16i8_:%[0-9]+]]:fpr128 = REV32v16i8 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[REV32v16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_BSWAP %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = G_BSWAP %0
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -139,9 +139,9 @@ body: |
; CHECK-NEXT: [[REV32v8i8_:%[0-9]+]]:fpr64 = REV32v8i8 [[COPY]]
; CHECK-NEXT: $d0 = COPY [[REV32v8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_BSWAP %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = G_BSWAP %0
+ $d0 = COPY %1(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -163,9 +163,9 @@ body: |
; CHECK-NEXT: [[REV64v16i8_:%[0-9]+]]:fpr128 = REV64v16i8 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[REV64v16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_BSWAP %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = G_BSWAP %0
+ $q0 = COPY %1(<2 x i64>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
index 0b2121db4e7c4..4e88d5edd6df2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
@@ -33,12 +33,12 @@ body: |
; CHECK-NEXT: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi32lane2]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s3
- %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)
- $q0 = COPY %4(<4 x s32>)
+ %0:fpr(i32) = COPY $s0
+ %1:fpr(i32) = COPY $s1
+ %2:fpr(i32) = COPY $s2
+ %3:fpr(i32) = COPY $s3
+ %4:fpr(<4 x i32>) = G_BUILD_VECTOR %0(i32), %1(i32), %2(i32), %3(i32)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -67,10 +67,10 @@ body: |
; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64)
- $q0 = COPY %4(<2 x s64>)
+ %0:fpr(i64) = COPY $d0
+ %1:fpr(i64) = COPY $d1
+ %4:fpr(<2 x i64>) = G_BUILD_VECTOR %0(i64), %1(i64)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -101,12 +101,12 @@ body: |
; CHECK-NEXT: [[INSvi32gpr2:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, [[COPY3]]
; CHECK-NEXT: $q0 = COPY [[INSvi32gpr2]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = COPY $w2
- %3:gpr(s32) = COPY $w3
- %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)
- $q0 = COPY %4(<4 x s32>)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = COPY $w2
+ %3:gpr(i32) = COPY $w3
+ %4:fpr(<4 x i32>) = G_BUILD_VECTOR %0(i32), %1(i32), %2(i32), %3(i32)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -133,10 +133,10 @@ body: |
; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64)
- $q0 = COPY %4(<2 x s64>)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %4:fpr(<2 x i64>) = G_BUILD_VECTOR %0(i64), %1(i64)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -191,13 +191,13 @@ body: |
; CHECK-NEXT: $q0 = COPY [[MOVIv2d_ns]]
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_CONSTANT i32 0
- %3:fpr(s32) = COPY %2(s32)
- %4:fpr(s32) = COPY %2(s32)
- %5:fpr(s32) = COPY %2(s32)
- %6:fpr(s32) = COPY %2(s32)
- %1:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32), %5(s32), %6(s32)
- $q0 = COPY %1(<4 x s32>)
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %3:fpr(i32) = COPY %2(i32)
+ %4:fpr(i32) = COPY %2(i32)
+ %5:fpr(i32) = COPY %2(i32)
+ %6:fpr(i32) = COPY %2(i32)
+ %1:fpr(<4 x i32>) = G_BUILD_VECTOR %3(i32), %4(i32), %5(i32), %6(i32)
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR
...
---
@@ -222,17 +222,17 @@ body: |
; CHECK-NEXT: $d0 = COPY [[COPY]]
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %2:gpr(s8) = G_CONSTANT i8 0
- %3:fpr(s8) = COPY %2(s8)
- %4:fpr(s8) = COPY %2(s8)
- %5:fpr(s8) = COPY %2(s8)
- %6:fpr(s8) = COPY %2(s8)
- %7:fpr(s8) = COPY %2(s8)
- %8:fpr(s8) = COPY %2(s8)
- %9:fpr(s8) = COPY %2(s8)
- %10:fpr(s8) = COPY %2(s8)
- %1:fpr(<8 x s8>) = G_BUILD_VECTOR %3(s8), %4(s8), %5(s8), %6(s8), %7(s8), %8(s8), %9(s8), %10(s8)
- $d0 = COPY %1(<8 x s8>)
+ %2:gpr(i8) = G_CONSTANT i8 0
+ %3:fpr(i8) = COPY %2(i8)
+ %4:fpr(i8) = COPY %2(i8)
+ %5:fpr(i8) = COPY %2(i8)
+ %6:fpr(i8) = COPY %2(i8)
+ %7:fpr(i8) = COPY %2(i8)
+ %8:fpr(i8) = COPY %2(i8)
+ %9:fpr(i8) = COPY %2(i8)
+ %10:fpr(i8) = COPY %2(i8)
+ %1:fpr(<8 x i8>) = G_BUILD_VECTOR %3(i8), %4(i8), %5(i8), %6(i8), %7(i8), %8(i8), %9(i8), %10(i8)
+ $d0 = COPY %1(<8 x i8>)
RET_ReallyLR
...
---
@@ -253,10 +253,10 @@ body: |
; CHECK-NEXT: %bv:fpr128 = SUBREG_TO_REG %val, %subreg.ssub
; CHECK-NEXT: $q0 = COPY %bv
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %val:fpr(s32) = COPY $s0
- %undef:fpr(s32) = G_IMPLICIT_DEF
- %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32)
- $q0 = COPY %bv(<4 x s32>)
+ %val:fpr(i32) = COPY $s0
+ %undef:fpr(i32) = G_IMPLICIT_DEF
+ %bv:fpr(<4 x i32>) = G_BUILD_VECTOR %val(i32), %undef(i32), %undef(i32), %undef(i32)
+ $q0 = COPY %bv(<4 x i32>)
RET_ReallyLR implicit $q0
...
...
@@ -279,9 +279,9 @@ body: |
; CHECK-NEXT: %bv:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub
; CHECK-NEXT: $q0 = COPY %bv
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %val:gpr(s32) = COPY $w0
- %undef:gpr(s32) = G_IMPLICIT_DEF
- %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32)
- $q0 = COPY %bv(<4 x s32>)
+ %val:gpr(i32) = COPY $w0
+ %undef:gpr(i32) = G_IMPLICIT_DEF
+ %bv:fpr(<4 x i32>) = G_BUILD_VECTOR %val(i32), %undef(i32), %undef(i32), %undef(i32)
+ $q0 = COPY %bv(<4 x i32>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
index 0da29c9d0c110..7fd1c8b419ab9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
@@ -21,9 +21,9 @@ body: |
liveins: $w0
successors: %bb.0, %bb.1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_ICMP intpred(eq), %0, %1
G_BRCOND %2, %bb.1
G_BR %bb.0
@@ -50,9 +50,9 @@ body: |
liveins: $x0
successors: %bb.0, %bb.1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 0
- %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 0
+ %2:gpr(i32) = G_ICMP intpred(eq), %0, %1
G_BRCOND %2, %bb.1
G_BR %bb.0
@@ -79,9 +79,9 @@ body: |
liveins: $w0
successors: %bb.0, %bb.1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_ICMP intpred(ne), %0, %1
G_BRCOND %2, %bb.1
G_BR %bb.0
@@ -108,9 +108,9 @@ body: |
liveins: $x0
successors: %bb.0, %bb.1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 0
- %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 0
+ %2:gpr(i32) = G_ICMP intpred(ne), %0, %1
G_BRCOND %2, %bb.1
G_BR %bb.0
@@ -134,7 +134,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64))
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (i64))
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: RET_ReallyLR
@@ -143,14 +143,14 @@ body: |
liveins: $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(s64) = G_CONSTANT i64 0
- %1:gpr(p0) = G_INTTOPTR %2(s64)
- %4:gpr(s32) = G_ICMP intpred(eq), %0(p0), %1
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %1:gpr(p0) = G_INTTOPTR %2(i64)
+ %4:gpr(i32) = G_ICMP intpred(eq), %0(p0), %1
G_BRCOND %4, %bb.3
bb.2:
- %5:gpr(s64) = G_CONSTANT i64 0
- G_STORE %5(s64), %0(p0) :: (store (s64))
+ %5:gpr(i64) = G_CONSTANT i64 0
+ G_STORE %5(i64), %0(p0) :: (store (i64))
bb.3:
RET_ReallyLR
@@ -169,14 +169,14 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load (s64))
+ ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load (i64))
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64))
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (i64))
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: RET_ReallyLR
@@ -185,15 +185,15 @@ body: |
liveins: $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(s64) = G_CONSTANT i64 42
- %4:gpr(s64) = G_CONSTANT i64 0
- %1:gpr(s64) = G_LOAD %0(p0) :: (load (s64))
- %5:gpr(s32) = G_ICMP intpred(eq), %1(s64), %2
+ %2:gpr(i64) = G_CONSTANT i64 42
+ %4:gpr(i64) = G_CONSTANT i64 0
+ %1:gpr(i64) = G_LOAD %0(p0) :: (load (i64))
+ %5:gpr(i32) = G_ICMP intpred(eq), %1(i64), %2
G_BRCOND %5, %bb.3
bb.2:
- %6:gpr(s64) = G_CONSTANT i64 0
- G_STORE %6(s64), %0(p0) :: (store (s64))
+ %6:gpr(i64) = G_CONSTANT i64 0
+ G_STORE %6(i64), %0(p0) :: (store (i64))
bb.3:
RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
index 33cb75f7b8f46..c8e343ac67972 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
@@ -23,13 +23,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK-NEXT: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY1]], [[MOVi32imm]], [[COPY]] :: (load store monotonic (s32) on %ir.addr)
+ ; CHECK-NEXT: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY1]], [[MOVi32imm]], [[COPY]] :: (load store monotonic (i32) on %ir.addr)
; CHECK-NEXT: $w0 = COPY [[CASW]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32) on %ir.addr)
- $w0 = COPY %3(s32)
+ %1:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (i32) on %ir.addr)
+ $w0 = COPY %3(i32)
...
---
@@ -48,11 +48,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
- ; CHECK-NEXT: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY1]], [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)
+ ; CHECK-NEXT: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY1]], [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (i64) on %ir.addr)
; CHECK-NEXT: $x0 = COPY [[CASX]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 0
- %2:gpr(s64) = G_CONSTANT i64 1
- %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s64) on %ir.addr)
- $x0 = COPY %3(s64)
+ %1:gpr(i64) = G_CONSTANT i64 0
+ %2:gpr(i64) = G_CONSTANT i64 1
+ %3:gpr(i64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (i64) on %ir.addr)
+ $x0 = COPY %3(i64)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
index 53d8b82509481..23dc446156173 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
@@ -28,10 +28,10 @@ body: |
; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>)
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<4 x i32>) = G_CONCAT_VECTORS %0(<2 x i32>), %1(<2 x i32>)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -62,10 +62,10 @@ body: |
; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>)
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<8 x i16>) = G_CONCAT_VECTORS %0(<4 x i16>), %1(<4 x i16>)
+ $q0 = COPY %2(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -86,10 +86,10 @@ body: |
; CHECK-NEXT: %concat:fpr128 = INSERT_SUBREG [[DEF]], %a, %subreg.dsub
; CHECK-NEXT: $q0 = COPY %concat
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %a:fpr(<8 x s8>) = G_IMPLICIT_DEF
- %b:fpr(<8 x s8>) = G_IMPLICIT_DEF
- %concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
- $q0 = COPY %concat(<16 x s8>)
+ %a:fpr(<8 x i8>) = G_IMPLICIT_DEF
+ %b:fpr(<8 x i8>) = G_IMPLICIT_DEF
+ %concat:fpr(<16 x i8>) = G_CONCAT_VECTORS %a(<8 x i8>), %b(<8 x i8>)
+ $q0 = COPY %concat(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -113,10 +113,10 @@ body: |
; CHECK-NEXT: %concat:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY %concat
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %a:fpr(<8 x s8>) = COPY $d0
- %b:fpr(<8 x s8>) = COPY $d1
- %concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
- $q0 = COPY %concat(<16 x s8>)
+ %a:fpr(<8 x i8>) = COPY $d0
+ %b:fpr(<8 x i8>) = COPY $d1
+ %concat:fpr(<16 x i8>) = G_CONCAT_VECTORS %a(<8 x i8>), %b(<8 x i8>)
+ $q0 = COPY %concat(<16 x i8>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
index 041b76c54a5f8..25183359f4416 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
@@ -22,10 +22,10 @@ body: |
; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
; CHECK: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %3:fpr(s64) = G_FCONSTANT double 5.000000e-01
- %2:fpr(s64) = G_FCONSTANT double 1.600000e+01
- %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
- G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))
+ %3:fpr(f64) = G_FCONSTANT double 5.000000e-01
+ %2:fpr(f64) = G_FCONSTANT double 1.600000e+01
+ %1:fpr(<2 x f64>) = G_BUILD_VECTOR %2(f64), %3(f64)
+ G_STORE %1(<2 x f64>), %0(p0) :: (store (<2 x s64>))
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
index 34ac115640814..68b9aabe5431c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
@@ -24,10 +24,10 @@ body: |
; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %3:fpr(s64) = G_FCONSTANT double 5.000000e-01
- %2:fpr(s64) = G_FCONSTANT double 1.600000e+01
- %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
- G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))
+ %3:fpr(f64) = G_FCONSTANT double 5.000000e-01
+ %2:fpr(f64) = G_FCONSTANT double 1.600000e+01
+ %1:fpr(<2 x f64>) = G_BUILD_VECTOR %2(f64), %3(f64)
+ G_STORE %1(<2 x f64>), %0(p0) :: (store (<2 x s64>))
RET_ReallyLR
...
@@ -54,10 +54,10 @@ body: |
; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %3:fpr(s32) = G_FCONSTANT float 5.000000e-01
- %2:fpr(s32) = G_FCONSTANT float 1.600000e+01
- %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %3(s32), %3(s32)
- G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
+ %3:fpr(f32) = G_FCONSTANT float 5.000000e-01
+ %2:fpr(f32) = G_FCONSTANT float 1.600000e+01
+ %1:fpr(<4 x f32>) = G_BUILD_VECTOR %2(f32), %3(f32), %3(f32), %3(f32)
+ G_STORE %1(<4 x f32>), %0(p0) :: (store (<4 x s32>))
RET_ReallyLR
...
@@ -81,13 +81,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
- ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
+ ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x i64>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %3:gpr(s64) = G_CONSTANT i64 67839
- %2:gpr(s64) = G_CONSTANT i64 12375
- %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
- G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))
+ %3:gpr(i64) = G_CONSTANT i64 67839
+ %2:gpr(i64) = G_CONSTANT i64 12375
+ %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(i64), %3(i64)
+ G_STORE %1(<2 x i64>), %0(p0) :: (store (<2 x i64>))
RET_ReallyLR
...
@@ -111,13 +111,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
- ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
+ ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x i32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %3:gpr(s32) = G_CONSTANT i32 67839
- %2:gpr(s32) = G_CONSTANT i32 12375
- %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %2(s32), %3(s32)
- G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
+ %3:gpr(i32) = G_CONSTANT i32 67839
+ %2:gpr(i32) = G_CONSTANT i32 12375
+ %1:fpr(<4 x i32>) = G_BUILD_VECTOR %2(i32), %3(i32), %2(i32), %3(i32)
+ G_STORE %1(<4 x i32>), %0(p0) :: (store (<4 x i32>))
RET_ReallyLR
...
@@ -142,13 +142,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s64) from constant-pool)
- ; CHECK-NEXT: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x s32>))
+ ; CHECK-NEXT: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x i32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %3:gpr(s32) = G_CONSTANT i32 67839
- %2:gpr(s32) = G_CONSTANT i32 12375
- %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32)
- G_STORE %1(<2 x s32>), %0(p0) :: (store (<2 x s32>))
+ %3:gpr(i32) = G_CONSTANT i32 67839
+ %2:gpr(i32) = G_CONSTANT i32 12375
+ %1:fpr(<2 x i32>) = G_BUILD_VECTOR %2(i32), %3(i32)
+ G_STORE %1(<2 x i32>), %0(p0) :: (store (<2 x i32>))
RET_ReallyLR
...
@@ -174,9 +174,9 @@ body: |
; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
- G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %1:fpr(<4 x f32>) = G_BUILD_VECTOR %2(f32), %2(f32), %2(f32), %2(f32)
+ G_STORE %1(<4 x f32>), %0(p0) :: (store (<4 x s32>))
RET_ReallyLR
...
@@ -202,9 +202,9 @@ body: |
; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %2:fpr(s32) = G_FCONSTANT float 0xFFFFFFFFE0000000
- %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
- G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
+ %2:fpr(f32) = G_FCONSTANT float 0xFFFFFFFFE0000000
+ %1:fpr(<4 x f32>) = G_BUILD_VECTOR %2(f32), %2(f32), %2(f32), %2(f32)
+ G_STORE %1(<4 x f32>), %0(p0) :: (store (<4 x s32>))
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index de1775ef8369a..95f860bafb2b9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -31,9 +31,9 @@ body: |
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
; CHECK-NEXT: $w0 = COPY [[COPY]]
- %0:gpr(s8) = G_CONSTANT i8 42
- %1:gpr(s32) = G_ANYEXT %0(s8)
- $w0 = COPY %1(s32)
+ %0:gpr(i8) = G_CONSTANT i8 42
+ %1:gpr(i32) = G_ANYEXT %0(i8)
+ $w0 = COPY %1(i32)
...
---
@@ -46,9 +46,9 @@ body: |
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
; CHECK-NEXT: $w0 = COPY [[COPY]]
- %0:gpr(s16) = G_CONSTANT i16 42
- %1:gpr(s32) = G_ANYEXT %0(s16)
- $w0 = COPY %1(s32)
+ %0:gpr(i16) = G_CONSTANT i16 42
+ %1:gpr(i32) = G_ANYEXT %0(i16)
+ $w0 = COPY %1(i32)
...
---
@@ -63,8 +63,8 @@ body: |
; CHECK-LABEL: name: const_s32
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]
- %0(s32) = G_CONSTANT i32 42
- $w0 = COPY %0(s32)
+ %0(i32) = G_CONSTANT i32 42
+ $w0 = COPY %0(i32)
...
---
@@ -79,8 +79,8 @@ body: |
; CHECK-LABEL: name: const_s64
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234567890123
; CHECK-NEXT: $x0 = COPY [[MOVi64imm]]
- %0(s64) = G_CONSTANT i64 1234567890123
- $x0 = COPY %0(s64)
+ %0(i64) = G_CONSTANT i64 1234567890123
+ $x0 = COPY %0(i64)
...
---
@@ -95,8 +95,8 @@ body: |
; CHECK-LABEL: name: const_s32_zero
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: $w0 = COPY [[COPY]]
- %0(s32) = G_CONSTANT i32 0
- $w0 = COPY %0(s32)
+ %0(i32) = G_CONSTANT i32 0
+ $w0 = COPY %0(i32)
...
---
@@ -111,8 +111,8 @@ body: |
; CHECK-LABEL: name: const_s64_zero
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK-NEXT: $x0 = COPY [[COPY]]
- %0(s64) = G_CONSTANT i64 0
- $x0 = COPY %0(s64)
+ %0(i64) = G_CONSTANT i64 0
+ $x0 = COPY %0(i64)
...
---
@@ -201,8 +201,8 @@ body: |
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 42
; CHECK-NEXT: $x0 = COPY [[MOVi64imm]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = G_CONSTANT i64 42
- $x0 = COPY %0(s64)
+ %0:gpr(i64) = G_CONSTANT i64 42
+ $x0 = COPY %0(i64)
RET_ReallyLR implicit $x0
...
---
@@ -216,7 +216,7 @@ body: |
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = G_CONSTANT i64 42
- $x0 = COPY %0(s64)
+ %0:gpr(i64) = G_CONSTANT i64 42
+ $x0 = COPY %0(i64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
index 4d76bdf405b3d..f041634351e24 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
@@ -21,10 +21,10 @@ body: |
; CHECK-NEXT: %v2:fpr64 = COPY $d1
; CHECK-NEXT: %shuf:fpr64 = EXTv8i8 %v1, %v2, 3
; CHECK-NEXT: $d0 = COPY %shuf
- %v1:fpr(<8 x s8>) = COPY $d0
- %v2:fpr(<8 x s8>) = COPY $d1
- %3:gpr(s32) = G_CONSTANT i32 3
- %shuf:fpr(<8 x s8>) = G_EXT %v1, %v2, %3(s32)
+ %v1:fpr(<8 x i8>) = COPY $d0
+ %v2:fpr(<8 x i8>) = COPY $d1
+ %3:gpr(i32) = G_CONSTANT i32 3
+ %shuf:fpr(<8 x i8>) = G_EXT %v1, %v2, %3(i32)
$d0 = COPY %shuf
...
@@ -45,10 +45,10 @@ body: |
; CHECK-NEXT: %v2:fpr128 = COPY $q1
; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v1, %v2, 3
; CHECK-NEXT: $q0 = COPY %shuf
- %v1:fpr(<16 x s8>) = COPY $q0
- %v2:fpr(<16 x s8>) = COPY $q1
- %3:gpr(s32) = G_CONSTANT i32 3
- %shuf:fpr(<16 x s8>) = G_EXT %v1, %v2, %3(s32)
+ %v1:fpr(<16 x i8>) = COPY $q0
+ %v2:fpr(<16 x i8>) = COPY $q1
+ %3:gpr(i32) = G_CONSTANT i32 3
+ %shuf:fpr(<16 x i8>) = G_EXT %v1, %v2, %3(i32)
$q0 = COPY %shuf
...
@@ -69,10 +69,10 @@ body: |
; CHECK-NEXT: %v2:fpr64 = COPY $d1
; CHECK-NEXT: %shuf:fpr64 = EXTv8i8 %v1, %v2, 6
; CHECK-NEXT: $d0 = COPY %shuf
- %v1:fpr(<4 x s16>) = COPY $d0
- %v2:fpr(<4 x s16>) = COPY $d1
- %3:gpr(s32) = G_CONSTANT i32 6
- %shuf:fpr(<4 x s16>) = G_EXT %v1, %v2, %3(s32)
+ %v1:fpr(<4 x i16>) = COPY $d0
+ %v2:fpr(<4 x i16>) = COPY $d1
+ %3:gpr(i32) = G_CONSTANT i32 6
+ %shuf:fpr(<4 x i16>) = G_EXT %v1, %v2, %3(i32)
$d0 = COPY %shuf
...
@@ -93,10 +93,10 @@ body: |
; CHECK-NEXT: %v2:fpr128 = COPY $q1
; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v2, %v1, 10
; CHECK-NEXT: $q0 = COPY %shuf
- %v1:fpr(<8 x s16>) = COPY $q0
- %v2:fpr(<8 x s16>) = COPY $q1
- %3:gpr(s32) = G_CONSTANT i32 10
- %shuf:fpr(<8 x s16>) = G_EXT %v2, %v1, %3(s32)
+ %v1:fpr(<8 x i16>) = COPY $q0
+ %v2:fpr(<8 x i16>) = COPY $q1
+ %3:gpr(i32) = G_CONSTANT i32 10
+ %shuf:fpr(<8 x i16>) = G_EXT %v2, %v1, %3(i32)
$q0 = COPY %shuf
...
@@ -118,10 +118,10 @@ body: |
; CHECK-NEXT: %v2:fpr128 = COPY $q1
; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v1, %v2, 12
; CHECK-NEXT: $q0 = COPY %shuf
- %v1:fpr(<4 x s32>) = COPY $q0
- %v2:fpr(<4 x s32>) = COPY $q1
- %3:gpr(s32) = G_CONSTANT i32 12
- %shuf:fpr(<4 x s32>) = G_EXT %v1, %v2, %3(s32)
+ %v1:fpr(<4 x i32>) = COPY $q0
+ %v2:fpr(<4 x i32>) = COPY $q1
+ %3:gpr(i32) = G_CONSTANT i32 12
+ %shuf:fpr(<4 x i32>) = G_EXT %v1, %v2, %3(i32)
$q0 = COPY %shuf
...
@@ -142,10 +142,10 @@ body: |
; CHECK-NEXT: %v2:fpr64 = COPY $d1
; CHECK-NEXT: %shuf:fpr64 = EXTv8i8 %v1, %v2, 2
; CHECK-NEXT: $d0 = COPY %shuf
- %v1:fpr(<2 x s32>) = COPY $d0
- %v2:fpr(<2 x s32>) = COPY $d1
- %3:gpr(s32) = G_CONSTANT i32 2
- %shuf:fpr(<2 x s32>) = G_EXT %v1, %v2, %3(s32)
+ %v1:fpr(<2 x i32>) = COPY $d0
+ %v2:fpr(<2 x i32>) = COPY $d1
+ %3:gpr(i32) = G_CONSTANT i32 2
+ %shuf:fpr(<2 x i32>) = G_EXT %v1, %v2, %3(i32)
$d0 = COPY %shuf
...
@@ -166,9 +166,9 @@ body: |
; CHECK-NEXT: %v2:fpr128 = COPY $q1
; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v1, %v2, 2
; CHECK-NEXT: $q0 = COPY %shuf
- %v1:fpr(<2 x s64>) = COPY $q0
- %v2:fpr(<2 x s64>) = COPY $q1
- %3:gpr(s32) = G_CONSTANT i32 2
- %shuf:fpr(<2 x s64>) = G_EXT %v1, %v2, %3(s32)
+ %v1:fpr(<2 x i64>) = COPY $q0
+ %v2:fpr(<2 x i64>) = COPY $q1
+ %3:gpr(i32) = G_CONSTANT i32 2
+ %shuf:fpr(<2 x i64>) = G_EXT %v1, %v2, %3(i32)
$q0 = COPY %shuf
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
index 5ba0353e23f76..9b14cedb66263 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
@@ -22,11 +22,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_LOAD %0 :: (load (s16) from %ir.addr)
- $w0 = COPY %1(s32)
+ %1:gpr(i32) = G_LOAD %0 :: (load (i16) from %ir.addr)
+ $w0 = COPY %1(i32)
...
---
@@ -42,11 +42,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16) from %ir.addr)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
- %2:gpr(s32) = G_ANYEXT %1
- $w0 = COPY %2(s32)
+ %1:gpr(i16) = G_LOAD %0 :: (load (i16) from %ir.addr)
+ %2:gpr(i32) = G_ANYEXT %1
+ $w0 = COPY %2(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
index 69f97f449b430..58b51556c26b9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
@@ -17,12 +17,12 @@ body: |
; CHECK-NEXT: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[COPY]], 1
; CHECK-NEXT: $x0 = COPY [[SMOVvi32to64_]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:fpr(<4 x s32>) = COPY $q0
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
- %5:gpr(s32) = COPY %2(s32)
- %4:gpr(s64) = G_SEXT %5(s32)
- $x0 = COPY %4(s64)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(i32) = G_EXTRACT_VECTOR_ELT %0(<4 x i32>), %3(i64)
+ %5:gpr(i32) = COPY %2(i32)
+ %4:gpr(i64) = G_SEXT %5(i32)
+ $x0 = COPY %4(i64)
RET_ReallyLR implicit $x0
...
@@ -44,12 +44,12 @@ body: |
; CHECK-NEXT: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $x0 = COPY [[SMOVvi32to64_]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:fpr(<2 x s32>) = COPY $d0
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
- %5:gpr(s32) = COPY %2(s32)
- %4:gpr(s64) = G_SEXT %5(s32)
- $x0 = COPY %4(s64)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(i32) = G_EXTRACT_VECTOR_ELT %0(<2 x i32>), %3(i64)
+ %5:gpr(i32) = COPY %2(i32)
+ %4:gpr(i64) = G_SEXT %5(i32)
+ $x0 = COPY %4(i64)
RET_ReallyLR implicit $x0
...
@@ -70,12 +70,12 @@ body: |
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:fpr(<4 x s32>) = COPY $q0
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
- %5:gpr(s32) = COPY %2(s32)
- %4:gpr(s64) = G_ZEXT %5(s32)
- $x0 = COPY %4(s64)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(i32) = G_EXTRACT_VECTOR_ELT %0(<4 x i32>), %3(i64)
+ %5:gpr(i32) = COPY %2(i32)
+ %4:gpr(i64) = G_ZEXT %5(i32)
+ $x0 = COPY %4(i64)
RET_ReallyLR implicit $x0
...
@@ -98,12 +98,12 @@ body: |
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:fpr(<2 x s32>) = COPY $d0
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
- %5:gpr(s32) = COPY %2(s32)
- %4:gpr(s64) = G_ZEXT %5(s32)
- $x0 = COPY %4(s64)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(i32) = G_EXTRACT_VECTOR_ELT %0(<2 x i32>), %3(i64)
+ %5:gpr(i32) = COPY %2(i32)
+ %4:gpr(i64) = G_ZEXT %5(i32)
+ $x0 = COPY %4(i64)
RET_ReallyLR implicit $x0
...
@@ -123,12 +123,12 @@ body: |
; CHECK-NEXT: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[COPY]], 1
; CHECK-NEXT: $w0 = COPY [[SMOVvi16to32_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<8 x s16>) = COPY $q0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
- %6:gpr(s16) = COPY %3(s16)
- %5:gpr(s32) = G_SEXT %6(s16)
- $w0 = COPY %5(s32)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<8 x i16>), %4(i64)
+ %6:gpr(i16) = COPY %3(i16)
+ %5:gpr(i32) = G_SEXT %6(i16)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -148,12 +148,12 @@ body: |
; CHECK-NEXT: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[COPY]], 1
; CHECK-NEXT: $w0 = COPY [[UMOVvi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<8 x s16>) = COPY $q0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
- %6:gpr(s16) = COPY %3(s16)
- %5:gpr(s32) = G_ZEXT %6(s16)
- $w0 = COPY %5(s32)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<8 x i16>), %4(i64)
+ %6:gpr(i16) = COPY %3(i16)
+ %5:gpr(i32) = G_ZEXT %6(i16)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -175,12 +175,12 @@ body: |
; CHECK-NEXT: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $w0 = COPY [[SMOVvi16to32_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<4 x s16>) = COPY $d0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
- %6:gpr(s16) = COPY %3(s16)
- %5:gpr(s32) = G_SEXT %6(s16)
- $w0 = COPY %5(s32)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<4 x i16>), %4(i64)
+ %6:gpr(i16) = COPY %3(i16)
+ %5:gpr(i32) = G_SEXT %6(i16)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -202,12 +202,12 @@ body: |
; CHECK-NEXT: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $w0 = COPY [[UMOVvi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<4 x s16>) = COPY $d0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
- %6:gpr(s16) = COPY %3(s16)
- %5:gpr(s32) = G_ZEXT %6(s16)
- $w0 = COPY %5(s32)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<4 x i16>), %4(i64)
+ %6:gpr(i16) = COPY %3(i16)
+ %5:gpr(i32) = G_ZEXT %6(i16)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -227,12 +227,12 @@ body: |
; CHECK-NEXT: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[COPY]], 1
; CHECK-NEXT: $w0 = COPY [[SMOVvi8to32_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<16 x s8>) = COPY $q0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
- %7:gpr(s8) = COPY %3(s8)
- %6:gpr(s32) = G_SEXT %7(s8)
- $w0 = COPY %6(s32)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i8) = G_EXTRACT_VECTOR_ELT %0(<16 x i8>), %4(i64)
+ %7:gpr(i8) = COPY %3(i8)
+ %6:gpr(i32) = G_SEXT %7(i8)
+ $w0 = COPY %6(i32)
RET_ReallyLR implicit $w0
...
---
@@ -251,12 +251,12 @@ body: |
; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 1
; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<16 x s8>) = COPY $q0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
- %7:gpr(s8) = COPY %3(s8)
- %6:gpr(s32) = G_ZEXT %7(s8)
- $w0 = COPY %6(s32)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i8) = G_EXTRACT_VECTOR_ELT %0(<16 x i8>), %4(i64)
+ %7:gpr(i8) = COPY %3(i8)
+ %6:gpr(i32) = G_ZEXT %7(i8)
+ $w0 = COPY %6(i32)
RET_ReallyLR implicit $w0
...
@@ -278,12 +278,12 @@ body: |
; CHECK-NEXT: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $w0 = COPY [[SMOVvi8to32_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<8 x s8>) = COPY $d0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
- %7:gpr(s8) = COPY %3(s8)
- %6:gpr(s32) = G_SEXT %7(s8)
- $w0 = COPY %6(s32)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i8) = G_EXTRACT_VECTOR_ELT %0(<8 x i8>), %4(i64)
+ %7:gpr(i8) = COPY %3(i8)
+ %6:gpr(i32) = G_SEXT %7(i8)
+ $w0 = COPY %6(i32)
RET_ReallyLR implicit $w0
...
---
@@ -304,12 +304,12 @@ body: |
; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<8 x s8>) = COPY $d0
- %4:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
- %7:gpr(s8) = COPY %3(s8)
- %6:gpr(s32) = G_ZEXT %7(s8)
- $w0 = COPY %6(s32)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %4:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i8) = G_EXTRACT_VECTOR_ELT %0(<8 x i8>), %4(i64)
+ %7:gpr(i8) = COPY %3(i8)
+ %6:gpr(i32) = G_ZEXT %7(i8)
+ $w0 = COPY %6(i32)
RET_ReallyLR implicit $w0
...
@@ -326,11 +326,11 @@ body: |
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY]], %subreg.bsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %5:fpr(<16 x s8>) = G_IMPLICIT_DEF
- %12:gpr(s64) = G_CONSTANT i64 0
- %4:fpr(s8) = G_EXTRACT_VECTOR_ELT %5(<16 x s8>), %12(s64)
- %11:gpr(s8) = COPY %4(s8)
- %8:gpr(s16) = G_ANYEXT %11(s8)
- %ext:gpr(s32) = G_ANYEXT %8(s16)
- $w0 = COPY %ext(s32)
+ %5:fpr(<16 x i8>) = G_IMPLICIT_DEF
+ %12:gpr(i64) = G_CONSTANT i64 0
+ %4:fpr(i8) = G_EXTRACT_VECTOR_ELT %5(<16 x i8>), %12(i64)
+ %11:gpr(i8) = COPY %4(i8)
+ %8:gpr(i16) = G_ANYEXT %11(i8)
+ %ext:gpr(i32) = G_ANYEXT %8(i16)
+ $w0 = COPY %ext(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
index 375506f300de0..0f716ae7ab6e8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
@@ -25,11 +25,11 @@ body: |
; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $s0 = COPY [[DUPi32_]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(<2 x s32>) = COPY $d0
- %2:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s64) = COPY %2(s64)
- %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
- $s0 = COPY %1(s32)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %2:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i64) = COPY %2(i64)
+ %1:fpr(i32) = G_EXTRACT_VECTOR_ELT %0(<2 x i32>), %3(i64)
+ $s0 = COPY %1(i32)
RET_ReallyLR implicit $s0
...
@@ -49,11 +49,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK-NEXT: $s0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(<2 x s32>) = COPY $d0
- %2:gpr(s64) = G_CONSTANT i64 0
- %3:fpr(s64) = COPY %2(s64)
- %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
- $s0 = COPY %1(s32)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %3:fpr(i64) = COPY %2(i64)
+ %1:fpr(i32) = G_EXTRACT_VECTOR_ELT %0(<2 x i32>), %3(i64)
+ $s0 = COPY %1(i32)
RET_ReallyLR implicit $s0
...
@@ -79,11 +79,11 @@ body: |
; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 2
; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %2:gpr(s64) = G_CONSTANT i64 2
- %3:fpr(s64) = COPY %2(s64)
- %1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
- $d0 = COPY %1(s64)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %2:gpr(i64) = G_CONSTANT i64 2
+ %3:fpr(i64) = COPY %2(i64)
+ %1:fpr(i64) = G_EXTRACT_VECTOR_ELT %0(<2 x i64>), %3(i64)
+ $d0 = COPY %1(i64)
RET_ReallyLR implicit $d0
...
@@ -111,11 +111,11 @@ body: |
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(<4 x s16>) = COPY $d0
- %2:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s64) = COPY %2(s64)
- %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
- $h0 = COPY %1(s16)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %2:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i64) = COPY %2(i64)
+ %1:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<4 x i16>), %3(i64)
+ $h0 = COPY %1(i16)
RET_ReallyLR implicit $h0
...
@@ -135,11 +135,11 @@ body: |
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(<8 x s16>) = COPY $q0
- %2:gpr(s64) = G_CONSTANT i64 1
- %3:fpr(s64) = COPY %2(s64)
- %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
- $h0 = COPY %1(s16)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %2:gpr(i64) = G_CONSTANT i64 1
+ %3:fpr(i64) = COPY %2(i64)
+ %1:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<8 x i16>), %3(i64)
+ $h0 = COPY %1(i16)
RET_ReallyLR implicit $h0
...
@@ -159,12 +159,12 @@ body: |
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s64) = G_ZEXT %1
- %3:fpr(s64) = COPY %2(s64)
- %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
- $h0 = COPY %4(s16)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i64) = G_ZEXT %1
+ %3:fpr(i64) = COPY %2(i64)
+ %4:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<8 x i16>), %3(i64)
+ $h0 = COPY %4(i16)
RET_ReallyLR implicit $h0
...
@@ -184,12 +184,12 @@ body: |
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s64) = G_SEXT %1
- %3:fpr(s64) = COPY %2(s64)
- %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
- $h0 = COPY %4(s16)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i64) = G_SEXT %1
+ %3:fpr(i64) = COPY %2(i64)
+ %4:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<8 x i16>), %3(i64)
+ $h0 = COPY %4(i16)
RET_ReallyLR implicit $h0
...
@@ -209,13 +209,13 @@ body: |
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:gpr(s64) = G_CONSTANT i64 1
- %2:gpr(s32) = G_TRUNC %1
- %3:gpr(s64) = G_SEXT %2
- %4:fpr(s64) = COPY %3(s64)
- %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
- $h0 = COPY %5(s16)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:gpr(i64) = G_CONSTANT i64 1
+ %2:gpr(i32) = G_TRUNC %1
+ %3:gpr(i64) = G_SEXT %2
+ %4:fpr(i64) = COPY %3(i64)
+ %5:fpr(i16) = G_EXTRACT_VECTOR_ELT %0(<8 x i16>), %4(i64)
+ $h0 = COPY %5(i16)
RET_ReallyLR implicit $h0
...
---
@@ -237,12 +237,12 @@ body: |
; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 0
; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<16 x s8>) = COPY $q0
- %2:gpr(s64) = G_CONSTANT i64 0
- %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %2(s64)
- %4:gpr(s8) = COPY %1(s8)
- %3:gpr(s32) = G_ANYEXT %4(s8)
- $w0 = COPY %3(s32)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %1:fpr(i8) = G_EXTRACT_VECTOR_ELT %0(<16 x i8>), %2(i64)
+ %4:gpr(i8) = COPY %1(i8)
+ %3:gpr(i32) = G_ANYEXT %4(i8)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
@@ -267,12 +267,12 @@ body: |
; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 0
; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<8 x s8>) = COPY $d0
- %2:gpr(s64) = G_CONSTANT i64 0
- %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %2(s64)
- %4:gpr(s8) = COPY %1(s8)
- %3:gpr(s32) = G_ANYEXT %4(s8)
- $w0 = COPY %3(s32)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %1:fpr(i8) = G_EXTRACT_VECTOR_ELT %0(<8 x i8>), %2(i64)
+ %4:gpr(i8) = COPY %1(i8)
+ %3:gpr(i32) = G_ANYEXT %4(i8)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
@@ -294,8 +294,8 @@ body: |
; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<2 x p0>) = COPY $q0
- %2:gpr(s64) = G_CONSTANT i64 1
- %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)
+ %2:gpr(i64) = G_CONSTANT i64 1
+ %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(i64)
$d0 = COPY %1(p0)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract.mir
index d3795e36bd049..d7f67dc06aab3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract.mir
@@ -19,11 +19,11 @@ body: |
; CHECK-NEXT: $d3 = COPY [[COPY1]]
; CHECK-NEXT: $d4 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d3
- %0:fpr(s128) = COPY $q0
- %2:fpr(s64) = G_EXTRACT %0(s128), 0
- %3:fpr(s64) = G_EXTRACT %0(s128), 64
- $d3 = COPY %2(s64)
- $d4 = COPY %3(s64)
+ %0:fpr(i128) = COPY $q0
+ %2:fpr(i64) = G_EXTRACT %0(i128), 0
+ %3:fpr(i64) = G_EXTRACT %0(i128), 64
+ $d3 = COPY %2(i64)
+ $d4 = COPY %3(i64)
RET_ReallyLR implicit $d3
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir
index b485cd2e88edd..0af08af070701 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir
@@ -16,15 +16,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub
; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
- $h0 = COPY %2(s16)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (i8))
+ $h0 = COPY %2(i16)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -43,15 +43,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub
; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
- $s0 = COPY %2(s32)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (i8))
+ $s0 = COPY %2(i32)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -70,15 +70,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub
; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
- $d0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (i8))
+ $d0 = COPY %2(i64)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -97,15 +97,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (i16))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub
; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))
- $s0 = COPY %2(s32)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (i16))
+ $s0 = COPY %2(i32)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -124,15 +124,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (i16))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub
; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))
- $d0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (i16))
+ $d0 = COPY %2(i64)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -151,15 +151,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpost [[COPY]], 4 :: (load (s32))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpost [[COPY]], 4 :: (load (i32))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub
; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s32))
- $d0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (i32))
+ $d0 = COPY %2(i64)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -178,15 +178,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub
; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
- $h0 = COPY %2(s16)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (i8))
+ $h0 = COPY %2(i16)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -205,15 +205,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub
; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
- $s0 = COPY %2(s32)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (i8))
+ $s0 = COPY %2(i32)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -232,15 +232,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub
; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
- $d0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (i8))
+ $d0 = COPY %2(i64)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -259,15 +259,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (i16))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub
; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))
- $s0 = COPY %2(s32)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (i16))
+ $s0 = COPY %2(i32)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -286,15 +286,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (i16))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub
; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))
- $d0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (i16))
+ $d0 = COPY %2(i64)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
@@ -313,15 +313,15 @@ body: |
; CHECK: liveins: $d0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpre [[COPY]], 4 :: (load (s32))
+ ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpre [[COPY]], 4 :: (load (i32))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub
; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s32))
- $d0 = COPY %2(s64)
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:fpr(i64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (i32))
+ $d0 = COPY %2(i64)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
index 1ca06aa2c70ea..b047f7acac6b9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
@@ -173,7 +173,7 @@ body: |
; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<8 x f16>) = COPY $q0
- %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16), %6:fpr(f16), %7:fpr(f16), %8:fpr(f16), %9:fpr(f16) = G_UNMERGE_VALUES %0(<8 x s16>)
+ %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16), %6:fpr(f16), %7:fpr(f16), %8:fpr(f16), %9:fpr(f16) = G_UNMERGE_VALUES %0(<8 x f16>)
%32:fpr(f32) = G_FPEXT %2(f16)
%33:fpr(f32) = G_FRINT %32
%10:fpr(f16) = G_FPTRUNC %33(f32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
index caa1f7e7ef19b..a6521f730bb9c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
@@ -41,9 +41,9 @@ body: |
; STATIC-NEXT: [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @foo2, 32
; STATIC-NEXT: [[MOVKXi5:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @foo2, 48
; STATIC-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[MOVKXi5]]
- ; STATIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (s32) into %ir.retval)
- ; STATIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from @foo1)
- ; STATIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (s32) from @foo2)
+ ; STATIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (i32) into %ir.retval)
+ ; STATIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32) from @foo1)
+ ; STATIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (i32) from @foo2)
; STATIC-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
; STATIC-NEXT: $w0 = COPY [[ADDWrr]]
; STATIC-NEXT: RET_ReallyLR implicit $w0
@@ -53,21 +53,21 @@ body: |
; PIC-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY [[MOVaddr]]
; PIC-NEXT: [[MOVaddr1:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @foo2, target-flags(aarch64-pageoff, aarch64-nc) @foo2
; PIC-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[MOVaddr1]]
- ; PIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (s32) into %ir.retval)
- ; PIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from @foo1)
- ; PIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (s32) from @foo2)
+ ; PIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (i32) into %ir.retval)
+ ; PIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32) from @foo1)
+ ; PIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (i32) from @foo2)
; PIC-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
; PIC-NEXT: $w0 = COPY [[ADDWrr]]
; PIC-NEXT: RET_ReallyLR implicit $w0
- %1:gpr(s32) = G_CONSTANT i32 0
+ %1:gpr(i32) = G_CONSTANT i32 0
%4:gpr(p0) = G_GLOBAL_VALUE @foo1
%3:gpr(p0) = COPY %4(p0)
%7:gpr(p0) = G_GLOBAL_VALUE @foo2
%6:gpr(p0) = COPY %7(p0)
%0:gpr(p0) = G_FRAME_INDEX %stack.0.retval
- G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.retval)
- %2:gpr(i32) = G_LOAD %3(p0) :: (load (s32) from @foo1)
- %5:gpr(i32) = G_LOAD %6(p0) :: (load (s32) from @foo2)
+ G_STORE %1(i32), %0(p0) :: (store (i32) into %ir.retval)
+ %2:gpr(i32) = G_LOAD %3(p0) :: (load (i32) from @foo1)
+ %5:gpr(i32) = G_LOAD %6(p0) :: (load (i32) from @foo2)
%8:gpr(i32) = G_ADD %2, %5
$w0 = COPY %8(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
index 65e85f37c21e3..1ba04037aa133 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
@@ -34,21 +34,21 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY [[ADR]]
; CHECK-NEXT: [[ADR1:%[0-9]+]]:gpr64 = ADR @foo2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[ADR1]]
- ; CHECK-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (s32) into %ir.retval)
- ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from @foo1)
- ; CHECK-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (s32) from @foo2)
+ ; CHECK-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (i32) into %ir.retval)
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32) from @foo1)
+ ; CHECK-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (i32) from @foo2)
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %1:gpr(s32) = G_CONSTANT i32 0
+ %1:gpr(i32) = G_CONSTANT i32 0
%4:gpr(p0) = G_GLOBAL_VALUE @foo1
%3:gpr(p0) = COPY %4(p0)
%7:gpr(p0) = G_GLOBAL_VALUE @foo2
%6:gpr(p0) = COPY %7(p0)
%0:gpr(p0) = G_FRAME_INDEX %stack.0.retval
- G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.retval)
- %2:gpr(i32) = G_LOAD %3(p0) :: (load (s32) from @foo1)
- %5:gpr(i32) = G_LOAD %6(p0) :: (load (s32) from @foo2)
+ G_STORE %1(i32), %0(p0) :: (store (i32) into %ir.retval)
+ %2:gpr(i32) = G_LOAD %3(p0) :: (load (i32) from @foo1)
+ %5:gpr(i32) = G_LOAD %6(p0) :: (load (i32) from @foo2)
%8:gpr(i32) = G_ADD %2, %5
$w0 = COPY %8(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
index 99e864a287f2b..d7efa669bf35c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
@@ -19,9 +19,9 @@ body: |
; CHECK-NEXT: %copy:gpr32 = COPY $w0
; CHECK-NEXT: $w1 = COPY %copy
; CHECK-NEXT: RET_ReallyLR implicit $w1
- %copy:gpr(s32) = COPY $w0
- %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
- $w1 = COPY %copy_assert_zext(s32)
+ %copy:gpr(i32) = COPY $w0
+ %copy_assert_zext:gpr(i32) = G_ASSERT_ZEXT %copy, 16
+ $w1 = COPY %copy_assert_zext(i32)
RET_ReallyLR implicit $w1
...
@@ -40,9 +40,9 @@ body: |
; CHECK-NEXT: %copy:fpr32 = COPY $s0
; CHECK-NEXT: $s1 = COPY %copy
; CHECK-NEXT: RET_ReallyLR implicit $s1
- %copy:fpr(s32) = COPY $s0
- %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
- $s1 = COPY %copy_assert_zext(s32)
+ %copy:fpr(i32) = COPY $s0
+ %copy_assert_zext:fpr(i32) = G_ASSERT_ZEXT %copy, 16
+ $s1 = COPY %copy_assert_zext(i32)
RET_ReallyLR implicit $s1
...
@@ -61,9 +61,9 @@ body: |
; CHECK-NEXT: %copy:fpr32 = COPY $s0
; CHECK-NEXT: $w1 = COPY %copy
; CHECK-NEXT: RET_ReallyLR implicit $w1
- %copy:fpr(s32) = COPY $s0
- %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
- $w1 = COPY %copy_assert_zext(s32)
+ %copy:fpr(i32) = COPY $s0
+ %copy_assert_zext:fpr(i32) = G_ASSERT_ZEXT %copy, 16
+ $w1 = COPY %copy_assert_zext(i32)
RET_ReallyLR implicit $w1
...
@@ -85,10 +85,10 @@ body: |
; CHECK-NEXT: %copy_with_rc:gpr32sp = COPY $w2
; CHECK-NEXT: $w1 = COPY %copy_with_rc
; CHECK-NEXT: RET_ReallyLR implicit $w1
- %copy:gpr(s32) = COPY $w0
- %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
- %copy_with_rc:gpr32sp(s32) = COPY $w2
- $w1 = COPY %copy_with_rc(s32)
+ %copy:gpr(i32) = COPY $w0
+ %copy_assert_zext:gpr(i32) = G_ASSERT_ZEXT %copy, 16
+ %copy_with_rc:gpr32sp(i32) = COPY $w2
+ $w1 = COPY %copy_with_rc(i32)
RET_ReallyLR implicit $w1
...
@@ -107,9 +107,9 @@ body: |
; CHECK-NEXT: %copy:gpr32 = COPY $w0
; CHECK-NEXT: $w1 = COPY %copy
; CHECK-NEXT: RET_ReallyLR implicit $w1
- %copy:gpr(s32) = COPY $w0
- %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
- $w1 = COPY %copy_assert_sext(s32)
+ %copy:gpr(i32) = COPY $w0
+ %copy_assert_sext:gpr(i32) = G_ASSERT_SEXT %copy, 16
+ $w1 = COPY %copy_assert_sext(i32)
RET_ReallyLR implicit $w1
...
@@ -128,9 +128,9 @@ body: |
; CHECK-NEXT: %copy:fpr32 = COPY $s0
; CHECK-NEXT: $s1 = COPY %copy
; CHECK-NEXT: RET_ReallyLR implicit $s1
- %copy:fpr(s32) = COPY $s0
- %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
- $s1 = COPY %copy_assert_sext(s32)
+ %copy:fpr(i32) = COPY $s0
+ %copy_assert_sext:fpr(i32) = G_ASSERT_SEXT %copy, 16
+ $s1 = COPY %copy_assert_sext(i32)
RET_ReallyLR implicit $s1
...
@@ -149,9 +149,9 @@ body: |
; CHECK-NEXT: %copy:fpr32 = COPY $s0
; CHECK-NEXT: $w1 = COPY %copy
; CHECK-NEXT: RET_ReallyLR implicit $w1
- %copy:fpr(s32) = COPY $s0
- %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
- $w1 = COPY %copy_assert_sext(s32)
+ %copy:fpr(i32) = COPY $s0
+ %copy_assert_sext:fpr(i32) = G_ASSERT_SEXT %copy, 16
+ $w1 = COPY %copy_assert_sext(i32)
RET_ReallyLR implicit $w1
...
@@ -173,8 +173,8 @@ body: |
; CHECK-NEXT: %copy_with_rc:gpr32sp = COPY $w2
; CHECK-NEXT: $w1 = COPY %copy_with_rc
; CHECK-NEXT: RET_ReallyLR implicit $w1
- %copy:gpr(s32) = COPY $w0
- %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
- %copy_with_rc:gpr32sp(s32) = COPY $w2
- $w1 = COPY %copy_with_rc(s32)
+ %copy:gpr(i32) = COPY $w0
+ %copy_assert_sext:gpr(i32) = G_ASSERT_SEXT %copy, 16
+ %copy_with_rc:gpr32sp(i32) = COPY $w2
+ $w1 = COPY %copy_with_rc(i32)
RET_ReallyLR implicit $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
index 07e2e189b4c03..798326206bd28 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
@@ -41,8 +41,8 @@ body: |
; CHECK-TINY-NEXT: {{ $}}
; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1234
; CHECK-TINY-NEXT: $w0 = COPY [[MOVi32imm]]
- %0(s32) = G_CONSTANT i32 -1234
- $w0 = COPY %0(s32)
+ %0(i32) = G_CONSTANT i32 -1234
+ $w0 = COPY %0(i32)
...
---
@@ -71,8 +71,8 @@ body: |
; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234
; CHECK-TINY-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
; CHECK-TINY-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
- %0(s64) = G_CONSTANT i64 1234
- $x0 = COPY %0(s64)
+ %0(i64) = G_CONSTANT i64 1234
+ $x0 = COPY %0(i64)
...
# 64b FP immediates need to be loaded.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
index 78d86a6821877..04d5ce0160b73 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
@@ -21,13 +21,13 @@ body: |
; CHECK-NEXT: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 51, 31
; CHECK-NEXT: $x0 = COPY [[BFMXri]]
; CHECK-NEXT: $x1 = COPY [[BFMXri1]]
- %0:gpr(s32) = COPY $w0
+ %0:gpr(i32) = COPY $w0
- %1:gpr(s64) = G_IMPLICIT_DEF
+ %1:gpr(i64) = G_IMPLICIT_DEF
- %2:gpr(s64) = G_INSERT %1, %0, 0
+ %2:gpr(i64) = G_INSERT %1, %0, 0
- %3:gpr(s64) = G_INSERT %1, %0, 13
+ %3:gpr(i64) = G_INSERT %1, %0, 13
$x0 = COPY %2
$x1 = COPY %3
@@ -50,14 +50,14 @@ body: |
; CHECK-NEXT: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY]], 16, 15
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[BFMWri1]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %1:gpr(s32) = COPY $w0
- %2:gpr(s32) = COPY $w1
- %3:gpr(s16) = G_TRUNC %1(s32)
- %4:gpr(s16) = G_TRUNC %1(s32)
- %5:gpr(s32) = G_IMPLICIT_DEF
- %6:gpr(s32) = G_INSERT %5, %3(s16), 0
- %7:gpr(s32) = G_INSERT %6, %4(s16), 16
- %0:gpr(s32) = COPY %7(s32)
+ %1:gpr(i32) = COPY $w0
+ %2:gpr(i32) = COPY $w1
+ %3:gpr(i16) = G_TRUNC %1(i32)
+ %4:gpr(i16) = G_TRUNC %1(i32)
+ %5:gpr(i32) = G_IMPLICIT_DEF
+ %6:gpr(i32) = G_INSERT %5, %3(i16), 0
+ %7:gpr(i32) = G_INSERT %6, %4(i16), 16
+ %0:gpr(i32) = COPY %7(i32)
$w0 = COPY %0
...
@@ -80,11 +80,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[UBFMXri1]].sub_32
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: $w1 = COPY [[COPY2]]
- %0:gpr(s64) = COPY $x0
+ %0:gpr(i64) = COPY $x0
- %1:gpr(s32) = G_EXTRACT %0, 0
+ %1:gpr(i32) = G_EXTRACT %0, 0
- %2:gpr(s32) = G_EXTRACT %0, 13
+ %2:gpr(i32) = G_EXTRACT %0, 13
$w0 = COPY %1
$w1 = COPY %2
@@ -111,11 +111,11 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr16 = COPY [[COPY3]].hsub
; CHECK-NEXT: $h1 = COPY [[COPY4]]
- %0:gpr(s32) = COPY $w0
+ %0:gpr(i32) = COPY $w0
- %1:gpr(s16) = G_EXTRACT %0, 0
+ %1:gpr(i16) = G_EXTRACT %0, 0
- %2:gpr(s16) = G_EXTRACT %0, 15
+ %2:gpr(i16) = G_EXTRACT %0, 15
$h0 = COPY %1
$h1 = COPY %2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
index e761c3a808980..e6252a30f2651 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
@@ -18,13 +18,13 @@ body: |
; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[COPY1]], 1, [[COPY]]
; CHECK-NEXT: $q0 = COPY [[INSvi8gpr]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:gpr(s32) = COPY $w0
- %trunc:gpr(s8) = G_TRUNC %0
- %1:fpr(<16 x s8>) = COPY $q1
- %3:gpr(s64) = G_CONSTANT i64 1
- %4:gpr(s32) = G_ANYEXT %trunc
- %2:fpr(<16 x s8>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64)
- $q0 = COPY %2(<16 x s8>)
+ %0:gpr(i32) = COPY $w0
+ %trunc:gpr(i8) = G_TRUNC %0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %4:gpr(i32) = G_ANYEXT %trunc
+ %2:fpr(<16 x i8>) = G_INSERT_VECTOR_ELT %1, %4:gpr(i32), %3:gpr(i64)
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -49,12 +49,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:gpr(s32) = COPY $w0
- %trunc:gpr(s8) = G_TRUNC %0
- %1:fpr(<8 x s8>) = COPY $d0
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %trunc(s8), %3(s64)
- $d0 = COPY %2(<8 x s8>)
+ %0:gpr(i32) = COPY $w0
+ %trunc:gpr(i8) = G_TRUNC %0
+ %1:fpr(<8 x i8>) = COPY $d0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<8 x i8>) = G_INSERT_VECTOR_ELT %1, %trunc(i8), %3(i64)
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -79,13 +79,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:gpr(s32) = COPY $w0
- %trunc:gpr(s8) = G_TRUNC %0
- %1:fpr(<8 x s8>) = COPY $d0
- %3:gpr(s64) = G_CONSTANT i64 1
- %4:gpr(s32) = G_ANYEXT %trunc
- %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64)
- $d0 = COPY %2(<8 x s8>)
+ %0:gpr(i32) = COPY $w0
+ %trunc:gpr(i8) = G_TRUNC %0
+ %1:fpr(<8 x i8>) = COPY $d0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %4:gpr(i32) = G_ANYEXT %trunc
+ %2:fpr(<8 x i8>) = G_INSERT_VECTOR_ELT %1, %4(i32), %3(i64)
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -107,13 +107,13 @@ body: |
; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
; CHECK-NEXT: $q0 = COPY [[INSvi16gpr]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:gpr(s32) = COPY $w0
- %trunc:gpr(s16) = G_TRUNC %0
- %1:fpr(<8 x s16>) = COPY $q1
- %3:gpr(s64) = G_CONSTANT i64 1
- %4:gpr(s32) = G_ANYEXT %trunc
- %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64)
- $q0 = COPY %2(<8 x s16>)
+ %0:gpr(i32) = COPY $w0
+ %trunc:gpr(i16) = G_TRUNC %0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %4:gpr(i32) = G_ANYEXT %trunc
+ %2:fpr(<8 x i16>) = G_INSERT_VECTOR_ELT %1, %4:gpr(i32), %3:gpr(i64)
+ $q0 = COPY %2(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -165,11 +165,11 @@ body: |
; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi32lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(s32) = COPY $s0
- %1:fpr(<4 x s32>) = COPY $q1
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(i32) = COPY $s0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<4 x i32>) = G_INSERT_VECTOR_ELT %1, %0(i32), %3(i64)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -191,11 +191,11 @@ body: |
; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
; CHECK-NEXT: $q0 = COPY [[INSvi32gpr]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:gpr(s32) = COPY $w0
- %1:fpr(<4 x s32>) = COPY $q0
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
- $q0 = COPY %2(<4 x s32>)
+ %0:gpr(i32) = COPY $w0
+ %1:fpr(<4 x i32>) = COPY $q0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<4 x i32>) = G_INSERT_VECTOR_ELT %1, %0(i32), %3(i64)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -220,13 +220,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16gpr]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:gpr(s32) = COPY $w0
- %trunc:gpr(s16) = G_TRUNC %0
- %1:fpr(<4 x s16>) = COPY $d0
- %3:gpr(s64) = G_CONSTANT i64 1
- %4:gpr(s32) = G_ANYEXT %trunc
- %2:fpr(<4 x s16>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64)
- $d0 = COPY %2(<4 x s16>)
+ %0:gpr(i32) = COPY $w0
+ %trunc:gpr(i16) = G_TRUNC %0
+ %1:fpr(<4 x i16>) = COPY $d0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %4:gpr(i32) = G_ANYEXT %trunc
+ %2:fpr(<4 x i16>) = G_INSERT_VECTOR_ELT %1, %4(i32), %3(i64)
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -250,11 +250,11 @@ body: |
; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(s64) = COPY $d0
- %1:fpr(<2 x s64>) = COPY $q1
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(i64) = COPY $d0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<2 x i64>) = G_INSERT_VECTOR_ELT %1, %0(i64), %3(i64)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -276,11 +276,11 @@ body: |
; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:gpr(s64) = COPY $x0
- %1:fpr(<2 x s64>) = COPY $q0
- %3:gpr(s64) = G_CONSTANT i64 0
- %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)
- $q0 = COPY %2(<2 x s64>)
+ %0:gpr(i64) = COPY $x0
+ %1:fpr(<2 x i64>) = COPY $q0
+ %3:gpr(i64) = G_CONSTANT i64 0
+ %2:fpr(<2 x i64>) = G_INSERT_VECTOR_ELT %1, %0(i64), %3(i64)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -307,11 +307,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s32) = COPY $s0
- %1:fpr(<2 x s32>) = COPY $d1
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(i32) = COPY $s0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<2 x i32>) = G_INSERT_VECTOR_ELT %1, %0(i32), %3(i64)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -336,11 +336,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:gpr(s32) = COPY $w0
- %1:fpr(<2 x s32>) = COPY $d0
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
- $d0 = COPY %2(<2 x s32>)
+ %0:gpr(i32) = COPY $w0
+ %1:fpr(<2 x i32>) = COPY $d0
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<2 x i32>) = G_INSERT_VECTOR_ELT %1, %0(i32), %3(i64)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index e50f0fd21e7a9..ac5575b88fc31 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -30,7 +30,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
; CHECK-NEXT: $x0 = COPY [[COPY]]
- %0(s64) = COPY $x0
+ %0(i64) = COPY $x0
%1(p0) = G_INTTOPTR %0
$x0 = COPY %1(p0)
...
@@ -52,8 +52,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: $x0 = COPY [[COPY]]
%0(p0) = COPY $x0
- %1(s64) = G_PTRTOINT %0
- $x0 = COPY %1(s64)
+ %1(i64) = G_PTRTOINT %0
+ $x0 = COPY %1(i64)
...
---
@@ -104,8 +104,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $h0
%ptr:gpr(p0) = COPY $x0
%ptr2int:gpr(i64) = G_PTRTOINT %ptr(p0)
- %int:gpr(s16) = G_TRUNC %ptr2int(i64)
- $h0 = COPY %int(s16)
+ %int:gpr(i16) = G_TRUNC %ptr2int(i64)
+ $h0 = COPY %int(i16)
RET_ReallyLR implicit $h0
...
@@ -131,8 +131,8 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $b0
%ptr:gpr(p0) = COPY $x0
%ptr2int:gpr(i64) = G_PTRTOINT %ptr(p0)
- %int:gpr(s8) = G_TRUNC %ptr2int(i64)
- $b0 = COPY %int(s8)
+ %int:gpr(i8) = G_TRUNC %ptr2int(i64)
+ $b0 = COPY %int(i8)
RET_ReallyLR implicit $b0
...
@@ -179,10 +179,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: $x0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %1:fpr(<2 x s64>) = COPY $q0
- %2:fpr(<2 x p0>) = G_INTTOPTR %1(<2 x s64>)
- %4:gpr(s64) = G_CONSTANT i64 0
- %3:fpr(p0) = G_EXTRACT_VECTOR_ELT %2(<2 x p0>), %4(s64)
+ %1:fpr(<2 x i64>) = COPY $q0
+ %2:fpr(<2 x p0>) = G_INTTOPTR %1(<2 x i64>)
+ %4:gpr(i64) = G_CONSTANT i64 0
+ %3:fpr(p0) = G_EXTRACT_VECTOR_ELT %2(<2 x p0>), %4(i64)
$x0 = COPY %3(p0)
RET_ReallyLR implicit $x0
...
@@ -202,7 +202,7 @@ body: |
; CHECK-NEXT: $q0 = COPY %ptr
; CHECK-NEXT: RET_ReallyLR implicit $q0
%ptr:fpr(<2 x p0>) = COPY $q0
- %int:fpr(<2 x s64>) = G_PTRTOINT %ptr(<2 x p0>)
- $q0 = COPY %int(<2 x s64>)
+ %int:fpr(<2 x i64>) = G_PTRTOINT %ptr(<2 x p0>)
+ $q0 = COPY %int(<2 x i64>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
index c63f99218f05c..cc904bca9bf88 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
@@ -24,6 +24,6 @@ body: |
bb.0:
liveins: $w0
- %0(s32) = G_CONSTANT i32 1
+ %0(i32) = G_CONSTANT i32 1
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.hint), %0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
index 7d17336ad7543..06aa66678f071 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[AESErr:%[0-9]+]]:fpr128 = AESErr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[AESMCrrTied:%[0-9]+]]:fpr128 = AESMCrrTied [[AESErr]]
; CHECK-NEXT: $q0 = COPY [[AESMCrrTied]]
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %0, %1
- %3:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %2
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %0, %1
+ %3:fpr(<16 x i8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %2
+ $q0 = COPY %3(<16 x i8>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
index 92121b0b42162..0bd939e217e54 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
@@ -25,7 +25,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 8, %bb.3, implicit $nzcv
@@ -47,16 +47,16 @@ body: |
; CHECK-NEXT: RET_ReallyLR
bb.1:
%1:gpr(p0) = G_IMPLICIT_DEF
- %5:gpr(s64) = G_ZEXTLOAD %1(p0) :: (load (s8))
- %7:gpr(s64) = G_CONSTANT i64 8
- %16:gpr(s32) = G_ICMP intpred(ugt), %5(s64), %7
+ %5:gpr(i64) = G_ZEXTLOAD %1(p0) :: (load (i8))
+ %7:gpr(i64) = G_CONSTANT i64 8
+ %16:gpr(i32) = G_ICMP intpred(ugt), %5(i64), %7
G_BRCOND %16, %bb.4
bb.2:
successors: %bb.3, %bb.4
%9:gpr(p0) = G_JUMP_TABLE %jump-table.0
- G_BRJT %9(p0), %jump-table.0, %5(s64)
+ G_BRJT %9(p0), %jump-table.0, %5(i64)
bb.3:
G_BR %bb.4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ld2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ld2.mir
index 933dcb9628314..7d4b72d428fdf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ld2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ld2.mir
@@ -13,16 +13,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD2Twov8b:%[0-9]+]]:dd = LD2Twov8b %ptr :: (load (<8 x s64>))
+ ; CHECK-NEXT: [[LD2Twov8b:%[0-9]+]]:dd = LD2Twov8b %ptr :: (load (<8 x i64>))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD2Twov8b]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD2Twov8b]].dsub1
; CHECK-NEXT: $d0 = COPY %dst1
; CHECK-NEXT: $d1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<8 x s8>), %dst2:fpr(<8 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x s64>))
- $d0 = COPY %dst1(<8 x s8>)
- $d1 = COPY %dst2(<8 x s8>)
+ %dst1:fpr(<8 x i8>), %dst2:fpr(<8 x i8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x i64>))
+ $d0 = COPY %dst1(<8 x i8>)
+ $d1 = COPY %dst2(<8 x i8>)
RET_ReallyLR implicit $d0, implicit $d1
...
---
@@ -37,16 +37,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD2Twov16b:%[0-9]+]]:qq = LD2Twov16b %ptr :: (load (<16 x s64>))
+ ; CHECK-NEXT: [[LD2Twov16b:%[0-9]+]]:qq = LD2Twov16b %ptr :: (load (<16 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov16b]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov16b]].qsub1
; CHECK-NEXT: $q0 = COPY %dst1
; CHECK-NEXT: $q1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<16 x s8>), %dst2:fpr(<16 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<16 x s64>))
- $q0 = COPY %dst1(<16 x s8>)
- $q1 = COPY %dst2(<16 x s8>)
+ %dst1:fpr(<16 x i8>), %dst2:fpr(<16 x i8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<16 x i64>))
+ $q0 = COPY %dst1(<16 x i8>)
+ $q1 = COPY %dst2(<16 x i8>)
RET_ReallyLR implicit $q0, implicit $q1
...
---
@@ -61,16 +61,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD2Twov4h:%[0-9]+]]:dd = LD2Twov4h %ptr :: (load (<4 x s64>))
+ ; CHECK-NEXT: [[LD2Twov4h:%[0-9]+]]:dd = LD2Twov4h %ptr :: (load (<4 x i64>))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD2Twov4h]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD2Twov4h]].dsub1
; CHECK-NEXT: $d0 = COPY %dst1
; CHECK-NEXT: $d1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<4 x s16>), %dst2:fpr(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x s64>))
- $d0 = COPY %dst1(<4 x s16>)
- $d1 = COPY %dst2(<4 x s16>)
+ %dst1:fpr(<4 x i16>), %dst2:fpr(<4 x i16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x i64>))
+ $d0 = COPY %dst1(<4 x i16>)
+ $d1 = COPY %dst2(<4 x i16>)
RET_ReallyLR implicit $d0, implicit $d1
...
---
@@ -85,16 +85,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD2Twov8h:%[0-9]+]]:qq = LD2Twov8h %ptr :: (load (<8 x s64>))
+ ; CHECK-NEXT: [[LD2Twov8h:%[0-9]+]]:qq = LD2Twov8h %ptr :: (load (<8 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov8h]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov8h]].qsub1
; CHECK-NEXT: $q0 = COPY %dst1
; CHECK-NEXT: $q1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<8 x s16>), %dst2:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x s64>))
- $q0 = COPY %dst1(<8 x s16>)
- $q1 = COPY %dst2(<8 x s16>)
+ %dst1:fpr(<8 x i16>), %dst2:fpr(<8 x i16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x i64>))
+ $q0 = COPY %dst1(<8 x i16>)
+ $q1 = COPY %dst2(<8 x i16>)
RET_ReallyLR implicit $q0, implicit $q1
...
---
@@ -109,16 +109,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD2Twov2s:%[0-9]+]]:dd = LD2Twov2s %ptr :: (load (<2 x s64>))
+ ; CHECK-NEXT: [[LD2Twov2s:%[0-9]+]]:dd = LD2Twov2s %ptr :: (load (<2 x i64>))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD2Twov2s]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD2Twov2s]].dsub1
; CHECK-NEXT: $d0 = COPY %dst1
; CHECK-NEXT: $d1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<2 x s32>), %dst2:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x s64>))
- $d0 = COPY %dst1(<2 x s32>)
- $d1 = COPY %dst2(<2 x s32>)
+ %dst1:fpr(<2 x i32>), %dst2:fpr(<2 x i32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x i64>))
+ $d0 = COPY %dst1(<2 x i32>)
+ $d1 = COPY %dst2(<2 x i32>)
RET_ReallyLR implicit $d0, implicit $d1
...
---
@@ -133,16 +133,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD2Twov4s:%[0-9]+]]:qq = LD2Twov4s %ptr :: (load (<4 x s64>))
+ ; CHECK-NEXT: [[LD2Twov4s:%[0-9]+]]:qq = LD2Twov4s %ptr :: (load (<4 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov4s]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov4s]].qsub1
; CHECK-NEXT: $q0 = COPY %dst1
; CHECK-NEXT: $q1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<4 x s32>), %dst2:fpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x s64>))
- $q0 = COPY %dst1(<4 x s32>)
- $q1 = COPY %dst2(<4 x s32>)
+ %dst1:fpr(<4 x i32>), %dst2:fpr(<4 x i32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x i64>))
+ $q0 = COPY %dst1(<4 x i32>)
+ $q1 = COPY %dst2(<4 x i32>)
RET_ReallyLR implicit $q0, implicit $q1
...
---
@@ -157,16 +157,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD2Twov2d:%[0-9]+]]:qq = LD2Twov2d %ptr :: (load (<2 x s64>))
+ ; CHECK-NEXT: [[LD2Twov2d:%[0-9]+]]:qq = LD2Twov2d %ptr :: (load (<2 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov2d]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov2d]].qsub1
; CHECK-NEXT: $q0 = COPY %dst1
; CHECK-NEXT: $q1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<2 x s64>), %dst2:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x s64>))
- $q0 = COPY %dst1(<2 x s64>)
- $q1 = COPY %dst2(<2 x s64>)
+ %dst1:fpr(<2 x i64>), %dst2:fpr(<2 x i64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x i64>))
+ $q0 = COPY %dst1(<2 x i64>)
+ $q1 = COPY %dst2(<2 x i64>)
RET_ReallyLR implicit $q0, implicit $q1
...
---
@@ -205,16 +205,16 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD1Twov1d:%[0-9]+]]:dd = LD1Twov1d %ptr :: (load (s64))
+ ; CHECK-NEXT: [[LD1Twov1d:%[0-9]+]]:dd = LD1Twov1d %ptr :: (load (i64))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD1Twov1d]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD1Twov1d]].dsub1
; CHECK-NEXT: $d0 = COPY %dst1
; CHECK-NEXT: $d1 = COPY %dst2
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(s64), %dst2:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (s64))
- $d0 = COPY %dst1(s64)
- $d1 = COPY %dst2(s64)
+ %dst1:fpr(i64), %dst2:fpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (i64))
+ $d0 = COPY %dst1(i64)
+ $d1 = COPY %dst2(i64)
RET_ReallyLR implicit $d0, implicit $d1
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ld4.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ld4.mir
index 03e271e15e991..cd15b7b4b0e2d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ld4.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ld4.mir
@@ -13,7 +13,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD4Fourv8b:%[0-9]+]]:dddd = LD4Fourv8b %ptr :: (load (<8 x s64>))
+ ; CHECK-NEXT: [[LD4Fourv8b:%[0-9]+]]:dddd = LD4Fourv8b %ptr :: (load (<8 x i64>))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD4Fourv8b]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD4Fourv8b]].dsub1
; CHECK-NEXT: %dst3:fpr64 = COPY [[LD4Fourv8b]].dsub2
@@ -24,11 +24,11 @@ body: |
; CHECK-NEXT: $d3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<8 x s8>), %dst2:fpr(<8 x s8>), %dst3:fpr(<8 x s8>), %dst4:fpr(<8 x s8>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x s64>))
- $d0 = COPY %dst1(<8 x s8>)
- $d1 = COPY %dst2(<8 x s8>)
- $d2 = COPY %dst3(<8 x s8>)
- $d3 = COPY %dst4(<8 x s8>)
+ %dst1:fpr(<8 x i8>), %dst2:fpr(<8 x i8>), %dst3:fpr(<8 x i8>), %dst4:fpr(<8 x i8>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x i64>))
+ $d0 = COPY %dst1(<8 x i8>)
+ $d1 = COPY %dst2(<8 x i8>)
+ $d2 = COPY %dst3(<8 x i8>)
+ $d3 = COPY %dst4(<8 x i8>)
RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
...
---
@@ -43,7 +43,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD4Fourv16b:%[0-9]+]]:qqqq = LD4Fourv16b %ptr :: (load (<16 x s64>))
+ ; CHECK-NEXT: [[LD4Fourv16b:%[0-9]+]]:qqqq = LD4Fourv16b %ptr :: (load (<16 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv16b]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv16b]].qsub1
; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv16b]].qsub2
@@ -54,11 +54,11 @@ body: |
; CHECK-NEXT: $q3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<16 x s8>), %dst2:fpr(<16 x s8>), %dst3:fpr(<16 x s8>), %dst4:fpr(<16 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<16 x s64>))
- $q0 = COPY %dst1(<16 x s8>)
- $q1 = COPY %dst2(<16 x s8>)
- $q2 = COPY %dst3(<16 x s8>)
- $q3 = COPY %dst4(<16 x s8>)
+ %dst1:fpr(<16 x i8>), %dst2:fpr(<16 x i8>), %dst3:fpr(<16 x i8>), %dst4:fpr(<16 x i8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<16 x i64>))
+ $q0 = COPY %dst1(<16 x i8>)
+ $q1 = COPY %dst2(<16 x i8>)
+ $q2 = COPY %dst3(<16 x i8>)
+ $q3 = COPY %dst4(<16 x i8>)
RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
...
---
@@ -73,7 +73,7 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD4Fourv4h:%[0-9]+]]:dddd = LD4Fourv4h %ptr :: (load (<4 x s64>))
+ ; CHECK-NEXT: [[LD4Fourv4h:%[0-9]+]]:dddd = LD4Fourv4h %ptr :: (load (<4 x i64>))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD4Fourv4h]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD4Fourv4h]].dsub1
; CHECK-NEXT: %dst3:fpr64 = COPY [[LD4Fourv4h]].dsub2
@@ -84,11 +84,11 @@ body: |
; CHECK-NEXT: $d3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<4 x s16>), %dst2:fpr(<4 x s16>), %dst3:fpr(<4 x s16>), %dst4:fpr(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x s64>))
- $d0 = COPY %dst1(<4 x s16>)
- $d1 = COPY %dst2(<4 x s16>)
- $d2 = COPY %dst3(<4 x s16>)
- $d3 = COPY %dst4(<4 x s16>)
+ %dst1:fpr(<4 x i16>), %dst2:fpr(<4 x i16>), %dst3:fpr(<4 x i16>), %dst4:fpr(<4 x i16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x i64>))
+ $d0 = COPY %dst1(<4 x i16>)
+ $d1 = COPY %dst2(<4 x i16>)
+ $d2 = COPY %dst3(<4 x i16>)
+ $d3 = COPY %dst4(<4 x i16>)
RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
...
---
@@ -103,7 +103,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD4Fourv8h:%[0-9]+]]:qqqq = LD4Fourv8h %ptr :: (load (<8 x s64>))
+ ; CHECK-NEXT: [[LD4Fourv8h:%[0-9]+]]:qqqq = LD4Fourv8h %ptr :: (load (<8 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv8h]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv8h]].qsub1
; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv8h]].qsub2
@@ -114,11 +114,11 @@ body: |
; CHECK-NEXT: $q3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<8 x s16>), %dst2:fpr(<8 x s16>), %dst3:fpr(<8 x s16>), %dst4:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x s64>))
- $q0 = COPY %dst1(<8 x s16>)
- $q1 = COPY %dst2(<8 x s16>)
- $q2 = COPY %dst3(<8 x s16>)
- $q3 = COPY %dst4(<8 x s16>)
+ %dst1:fpr(<8 x i16>), %dst2:fpr(<8 x i16>), %dst3:fpr(<8 x i16>), %dst4:fpr(<8 x i16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x i64>))
+ $q0 = COPY %dst1(<8 x i16>)
+ $q1 = COPY %dst2(<8 x i16>)
+ $q2 = COPY %dst3(<8 x i16>)
+ $q3 = COPY %dst4(<8 x i16>)
RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
...
---
@@ -133,7 +133,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD4Fourv2s:%[0-9]+]]:dddd = LD4Fourv2s %ptr :: (load (<2 x s64>))
+ ; CHECK-NEXT: [[LD4Fourv2s:%[0-9]+]]:dddd = LD4Fourv2s %ptr :: (load (<2 x i64>))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD4Fourv2s]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD4Fourv2s]].dsub1
; CHECK-NEXT: %dst3:fpr64 = COPY [[LD4Fourv2s]].dsub2
@@ -144,11 +144,11 @@ body: |
; CHECK-NEXT: $d3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<2 x s32>), %dst2:fpr(<2 x s32>), %dst3:fpr(<2 x s32>), %dst4:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x s64>))
- $d0 = COPY %dst1(<2 x s32>)
- $d1 = COPY %dst2(<2 x s32>)
- $d2 = COPY %dst3(<2 x s32>)
- $d3 = COPY %dst4(<2 x s32>)
+ %dst1:fpr(<2 x i32>), %dst2:fpr(<2 x i32>), %dst3:fpr(<2 x i32>), %dst4:fpr(<2 x i32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x i64>))
+ $d0 = COPY %dst1(<2 x i32>)
+ $d1 = COPY %dst2(<2 x i32>)
+ $d2 = COPY %dst3(<2 x i32>)
+ $d3 = COPY %dst4(<2 x i32>)
RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
...
---
@@ -163,7 +163,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD4Fourv4s:%[0-9]+]]:qqqq = LD4Fourv4s %ptr :: (load (<4 x s64>))
+ ; CHECK-NEXT: [[LD4Fourv4s:%[0-9]+]]:qqqq = LD4Fourv4s %ptr :: (load (<4 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv4s]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv4s]].qsub1
; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv4s]].qsub2
@@ -174,11 +174,11 @@ body: |
; CHECK-NEXT: $q3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<4 x s32>), %dst2:fpr(<4 x s32>), %dst3:fpr(<4 x s32>), %dst4:fpr(<4 x s32>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x s64>))
- $q0 = COPY %dst1(<4 x s32>)
- $q1 = COPY %dst2(<4 x s32>)
- $q2 = COPY %dst3(<4 x s32>)
- $q3 = COPY %dst4(<4 x s32>)
+ %dst1:fpr(<4 x i32>), %dst2:fpr(<4 x i32>), %dst3:fpr(<4 x i32>), %dst4:fpr(<4 x i32>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x i64>))
+ $q0 = COPY %dst1(<4 x i32>)
+ $q1 = COPY %dst2(<4 x i32>)
+ $q2 = COPY %dst3(<4 x i32>)
+ $q3 = COPY %dst4(<4 x i32>)
RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
...
---
@@ -193,7 +193,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD4Fourv2d:%[0-9]+]]:qqqq = LD4Fourv2d %ptr :: (load (<2 x s64>))
+ ; CHECK-NEXT: [[LD4Fourv2d:%[0-9]+]]:qqqq = LD4Fourv2d %ptr :: (load (<2 x i64>))
; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv2d]].qsub0
; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv2d]].qsub1
; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv2d]].qsub2
@@ -204,11 +204,11 @@ body: |
; CHECK-NEXT: $q3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(<2 x s64>), %dst2:fpr(<2 x s64>), %dst3:fpr(<2 x s64>), %dst4:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x s64>))
- $q0 = COPY %dst1(<2 x s64>)
- $q1 = COPY %dst2(<2 x s64>)
- $q2 = COPY %dst3(<2 x s64>)
- $q3 = COPY %dst4(<2 x s64>)
+ %dst1:fpr(<2 x i64>), %dst2:fpr(<2 x i64>), %dst3:fpr(<2 x i64>), %dst4:fpr(<2 x i64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x i64>))
+ $q0 = COPY %dst1(<2 x i64>)
+ $q1 = COPY %dst2(<2 x i64>)
+ $q2 = COPY %dst3(<2 x i64>)
+ $q3 = COPY %dst4(<2 x i64>)
RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3
...
---
@@ -253,7 +253,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD1Fourv1d:%[0-9]+]]:dddd = LD1Fourv1d %ptr :: (load (s64))
+ ; CHECK-NEXT: [[LD1Fourv1d:%[0-9]+]]:dddd = LD1Fourv1d %ptr :: (load (i64))
; CHECK-NEXT: %dst1:fpr64 = COPY [[LD1Fourv1d]].dsub0
; CHECK-NEXT: %dst2:fpr64 = COPY [[LD1Fourv1d]].dsub1
; CHECK-NEXT: %dst3:fpr64 = COPY [[LD1Fourv1d]].dsub2
@@ -264,11 +264,11 @@ body: |
; CHECK-NEXT: $d3 = COPY %dst4
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
%ptr:gpr(p0) = COPY $x0
- %dst1:fpr(s64), %dst2:fpr(s64), %dst3:fpr(s64), %dst4:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (s64))
- $d0 = COPY %dst1(s64)
- $d1 = COPY %dst2(s64)
- $d2 = COPY %dst3(s64)
- $d3 = COPY %dst4(s64)
+ %dst1:fpr(i64), %dst2:fpr(i64), %dst3:fpr(i64), %dst4:fpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (i64))
+ $d0 = COPY %dst1(i64)
+ $d1 = COPY %dst2(i64)
+ $d2 = COPY %dst3(i64)
+ $d3 = COPY %dst4(i64)
RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
index 6526cd977eb55..e86536563ae9e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
@@ -21,12 +21,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDAXRB:%[0-9]+]]:gpr32 = LDAXRB [[COPY]] :: (volatile load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[LDAXRB:%[0-9]+]]:gpr32 = LDAXRB [[COPY]] :: (volatile load (i8) from %ir.addr)
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRB]], %subreg.sub_32
; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s8) from %ir.addr)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (i8) from %ir.addr)
$x1 = COPY %1
RET_ReallyLR implicit $x1
@@ -44,12 +44,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDAXRH:%[0-9]+]]:gpr32 = LDAXRH [[COPY]] :: (volatile load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDAXRH:%[0-9]+]]:gpr32 = LDAXRH [[COPY]] :: (volatile load (i16) from %ir.addr)
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRH]], %subreg.sub_32
; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s16) from %ir.addr)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (i16) from %ir.addr)
$x1 = COPY %1
RET_ReallyLR implicit $x1
@@ -67,12 +67,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDAXRW:%[0-9]+]]:gpr32 = LDAXRW [[COPY]] :: (volatile load (s32) from %ir.addr)
+ ; CHECK-NEXT: [[LDAXRW:%[0-9]+]]:gpr32 = LDAXRW [[COPY]] :: (volatile load (i32) from %ir.addr)
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRW]], %subreg.sub_32
; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s32) from %ir.addr)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (i32) from %ir.addr)
$x1 = COPY %1
RET_ReallyLR implicit $x1
@@ -90,10 +90,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDAXRX:%[0-9]+]]:gpr64 = LDAXRX [[COPY]] :: (volatile load (s64) from %ir.addr)
+ ; CHECK-NEXT: [[LDAXRX:%[0-9]+]]:gpr64 = LDAXRX [[COPY]] :: (volatile load (i64) from %ir.addr)
; CHECK-NEXT: $x1 = COPY [[LDAXRX]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s64) from %ir.addr)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (i64) from %ir.addr)
$x1 = COPY %1
RET_ReallyLR implicit $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
index 1eaafd517d986..5a654b3cfffc5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
@@ -20,13 +20,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load (i8) from %ir.addr)
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRB]], %subreg.sub_32
; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s8) from %ir.addr)
- $x1 = COPY %1(s64)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (i8) from %ir.addr)
+ $x1 = COPY %1(i64)
RET_ReallyLR implicit $x1
...
@@ -43,13 +43,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load (i16) from %ir.addr)
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRH]], %subreg.sub_32
; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s16) from %ir.addr)
- $x1 = COPY %1(s64)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (i16) from %ir.addr)
+ $x1 = COPY %1(i64)
RET_ReallyLR implicit $x1
...
@@ -66,13 +66,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load (s32) from %ir.addr)
+ ; CHECK-NEXT: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load (i32) from %ir.addr)
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRW]], %subreg.sub_32
; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s32) from %ir.addr)
- $x1 = COPY %1(s64)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (i32) from %ir.addr)
+ $x1 = COPY %1(i64)
RET_ReallyLR implicit $x1
@@ -90,10 +90,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDXRX:%[0-9]+]]:gpr64 = LDXRX [[COPY]] :: (volatile load (s64) from %ir.addr)
+ ; CHECK-NEXT: [[LDXRX:%[0-9]+]]:gpr64 = LDXRX [[COPY]] :: (volatile load (i64) from %ir.addr)
; CHECK-NEXT: $x1 = COPY [[LDXRX]]
; CHECK-NEXT: RET_ReallyLR implicit $x1
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s64) from %ir.addr)
- $x1 = COPY %1(s64)
+ %1:gpr(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (i64) from %ir.addr)
+ $x1 = COPY %1(i64)
RET_ReallyLR implicit $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
index b5e204433c4ad..d9712da595d23 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
@@ -35,12 +35,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<2 x s64>) into %ir.ptr)
+ ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<2 x i64>) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
%0:fpr(<2 x p0>) = COPY $q0
%1:gpr(p0) = COPY $x0
- %2:fpr(<2 x s64>) = G_BITCAST %0(<2 x p0>)
- G_STORE %2(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.ptr)
+ %2:fpr(<2 x i64>) = G_BITCAST %0(<2 x p0>)
+ G_STORE %2(<2 x i64>), %1(p0) :: (store (<2 x i64>) into %ir.ptr)
RET_ReallyLR
...
@@ -63,12 +63,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>) from %ir.ptr)
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x i64>) from %ir.ptr)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
- %2:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.ptr)
- %1:fpr(<2 x p0>) = G_BITCAST %2(<2 x s64>)
+ %2:fpr(<2 x i64>) = G_LOAD %0(p0) :: (load (<2 x i64>) from %ir.ptr)
+ %1:fpr(<2 x p0>) = G_BITCAST %2(<2 x i64>)
$q0 = COPY %1(<2 x p0>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
index bc094e7703b97..09db59db840ef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -62,11 +62,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load (i64) from %ir.addr)
; CHECK-NEXT: $x0 = COPY [[LDRXui]]
%0(p0) = COPY $x0
- %1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)
- $x0 = COPY %1(s64)
+ %1(i64) = G_LOAD %0 :: (load (i64) from %ir.addr)
+ $x0 = COPY %1(i64)
...
---
@@ -86,11 +86,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRWui]]
%0(p0) = COPY $x0
- %1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
- $w0 = COPY %1(s32)
+ %1(i32) = G_LOAD %0 :: (load (i32) from %ir.addr)
+ $w0 = COPY %1(i32)
...
---
@@ -106,11 +106,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_LOAD %0 :: (load (s16) from %ir.addr)
- $w0 = COPY %1(s32)
+ %1:gpr(i32) = G_LOAD %0 :: (load (i16) from %ir.addr)
+ $w0 = COPY %1(i32)
...
---
@@ -130,13 +130,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16) from %ir.addr)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
- %1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
- %2:gpr(s32) = G_ANYEXT %1
- $w0 = COPY %2(s32)
+ %1(i16) = G_LOAD %0 :: (load (i16) from %ir.addr)
+ %2:gpr(i32) = G_ANYEXT %1
+ $w0 = COPY %2(i32)
...
---
@@ -152,11 +152,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_LOAD %0 :: (load (s8) from %ir.addr)
- $w0 = COPY %1(s32)
+ %1:gpr(i32) = G_LOAD %0 :: (load (i8) from %ir.addr)
+ $w0 = COPY %1(i32)
...
---
@@ -176,13 +176,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8) from %ir.addr)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
- %1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
- %2:gpr(s32) = G_ANYEXT %1
- $w0 = COPY %2(s32)
+ %1(i8) = G_LOAD %0 :: (load (i8) from %ir.addr)
+ %2:gpr(i32) = G_ANYEXT %1
+ $w0 = COPY %2(i32)
...
---
@@ -204,11 +204,11 @@ body: |
; CHECK-LABEL: name: load_fi_s64_gpr
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load (s64))
+ ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load (i64))
; CHECK-NEXT: $x0 = COPY [[LDRXui]]
%0(p0) = G_FRAME_INDEX %stack.0.ptr0
- %1(s64) = G_LOAD %0 :: (load (s64))
- $x0 = COPY %1(s64)
+ %1(i64) = G_LOAD %0 :: (load (i64))
+ $x0 = COPY %1(i64)
...
---
@@ -230,12 +230,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load (i64) from %ir.addr)
; CHECK-NEXT: $x0 = COPY [[LDRXui]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 128
+ %1(i64) = G_CONSTANT i64 128
%2(p0) = G_PTR_ADD %0, %1
- %3(s64) = G_LOAD %2 :: (load (s64) from %ir.addr)
+ %3(i64) = G_LOAD %2 :: (load (i64) from %ir.addr)
$x0 = COPY %3
...
@@ -258,12 +258,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load (i32) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRWui]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 512
+ %1(i64) = G_CONSTANT i64 512
%2(p0) = G_PTR_ADD %0, %1
- %3(s32) = G_LOAD %2 :: (load (s32) from %ir.addr)
+ %3(i32) = G_LOAD %2 :: (load (i32) from %ir.addr)
$w0 = COPY %3
...
@@ -286,14 +286,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (i16) from %ir.addr)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 64
+ %1(i64) = G_CONSTANT i64 64
%2(p0) = G_PTR_ADD %0, %1
- %3(s16) = G_LOAD %2 :: (load (s16) from %ir.addr)
- %4:gpr(s32) = G_ANYEXT %3
+ %3(i16) = G_LOAD %2 :: (load (i16) from %ir.addr)
+ %4:gpr(i32) = G_ANYEXT %3
$w0 = COPY %4
...
@@ -316,14 +316,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (i8) from %ir.addr)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 1
+ %1(i64) = G_CONSTANT i64 1
%2(p0) = G_PTR_ADD %0, %1
- %3(s8) = G_LOAD %2 :: (load (s8) from %ir.addr)
- %4:gpr(s32) = G_ANYEXT %3
+ %3(i8) = G_LOAD %2 :: (load (i8) from %ir.addr)
+ %4:gpr(i32) = G_ANYEXT %3
$w0 = COPY %4
...
@@ -344,11 +344,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (i64) from %ir.addr)
; CHECK-NEXT: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
- %1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)
- $d0 = COPY %1(s64)
+ %1(i64) = G_LOAD %0 :: (load (i64) from %ir.addr)
+ $d0 = COPY %1(i64)
...
---
@@ -368,11 +368,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load (i32) from %ir.addr)
; CHECK-NEXT: $s0 = COPY [[LDRSui]]
%0(p0) = COPY $x0
- %1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
- $s0 = COPY %1(s32)
+ %1(i32) = G_LOAD %0 :: (load (i32) from %ir.addr)
+ $s0 = COPY %1(i32)
...
---
@@ -392,11 +392,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (i16) from %ir.addr)
; CHECK-NEXT: $h0 = COPY [[LDRHui]]
%0(p0) = COPY $x0
- %1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
- $h0 = COPY %1(s16)
+ %1(i16) = G_LOAD %0 :: (load (i16) from %ir.addr)
+ $h0 = COPY %1(i16)
...
---
@@ -416,11 +416,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (i8) from %ir.addr)
; CHECK-NEXT: $b0 = COPY [[LDRBui]]
%0(p0) = COPY $x0
- %1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
- $b0 = COPY %1(s8)
+ %1(i8) = G_LOAD %0 :: (load (i8) from %ir.addr)
+ $b0 = COPY %1(i8)
...
---
@@ -442,12 +442,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load (i64) from %ir.addr)
; CHECK-NEXT: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 8
+ %1(i64) = G_CONSTANT i64 8
%2(p0) = G_PTR_ADD %0, %1
- %3(s64) = G_LOAD %2 :: (load (s64) from %ir.addr)
+ %3(i64) = G_LOAD %2 :: (load (i64) from %ir.addr)
$d0 = COPY %3
...
@@ -470,12 +470,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load (i32) from %ir.addr)
; CHECK-NEXT: $s0 = COPY [[LDRSui]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 16
+ %1(i64) = G_CONSTANT i64 16
%2(p0) = G_PTR_ADD %0, %1
- %3(s32) = G_LOAD %2 :: (load (s32) from %ir.addr)
+ %3(i32) = G_LOAD %2 :: (load (i32) from %ir.addr)
$s0 = COPY %3
...
@@ -498,12 +498,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load (i16) from %ir.addr)
; CHECK-NEXT: $h0 = COPY [[LDRHui]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 64
+ %1(i64) = G_CONSTANT i64 64
%2(p0) = G_PTR_ADD %0, %1
- %3(s16) = G_LOAD %2 :: (load (s16) from %ir.addr)
+ %3(i16) = G_LOAD %2 :: (load (i16) from %ir.addr)
$h0 = COPY %3
...
@@ -526,12 +526,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load (i8) from %ir.addr)
; CHECK-NEXT: $b0 = COPY [[LDRBui]]
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 32
+ %1(i64) = G_CONSTANT i64 32
%2(p0) = G_PTR_ADD %0, %1
- %3(s8) = G_LOAD %2 :: (load (s8) from %ir.addr)
+ %3(i8) = G_LOAD %2 :: (load (i8) from %ir.addr)
$b0 = COPY %3
...
---
@@ -551,11 +551,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>) from %ir.addr)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x i32>) from %ir.addr)
; CHECK-NEXT: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
- %1(<2 x s32>) = G_LOAD %0 :: (load (<2 x s32>) from %ir.addr)
- $d0 = COPY %1(<2 x s32>)
+ %1(<2 x i32>) = G_LOAD %0 :: (load (<2 x i32>) from %ir.addr)
+ $d0 = COPY %1(<2 x i32>)
...
---
name: load_v2s64
@@ -574,11 +574,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>) from %ir.addr)
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x i64>) from %ir.addr)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
%0(p0) = COPY $x0
- %1(<2 x s64>) = G_LOAD %0 :: (load (<2 x s64>) from %ir.addr)
- $q0 = COPY %1(<2 x s64>)
+ %1(<2 x i64>) = G_LOAD %0 :: (load (<2 x i64>) from %ir.addr)
+ $q0 = COPY %1(<2 x i64>)
...
---
name: load_4xi16
@@ -598,12 +598,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<4 x s16>) from %ir.ptr)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<4 x i16>) from %ir.ptr)
; CHECK-NEXT: $d0 = COPY [[LDRDui]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
- %1:fpr(<4 x s16>) = G_LOAD %0(p0) :: (load (<4 x s16>) from %ir.ptr)
- $d0 = COPY %1(<4 x s16>)
+ %1:fpr(<4 x i16>) = G_LOAD %0(p0) :: (load (<4 x i16>) from %ir.ptr)
+ $d0 = COPY %1(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -625,12 +625,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>) from %ir.ptr)
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x i32>) from %ir.ptr)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
- %1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.ptr)
- $q0 = COPY %1(<4 x s32>)
+ %1:fpr(<4 x i32>) = G_LOAD %0(p0) :: (load (<4 x i32>) from %ir.ptr)
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -652,12 +652,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>) from %ir.ptr)
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x i16>) from %ir.ptr)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
- %1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.ptr)
- $q0 = COPY %1(<8 x s16>)
+ %1:fpr(<8 x i16>) = G_LOAD %0(p0) :: (load (<8 x i16>) from %ir.ptr)
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -679,12 +679,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>) from %ir.ptr)
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x i8>) from %ir.ptr)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
- %1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.ptr)
- $q0 = COPY %1(<16 x s8>)
+ %1:fpr(<16 x i8>) = G_LOAD %0(p0) :: (load (<16 x i8>) from %ir.ptr)
+ $q0 = COPY %1(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -710,15 +710,15 @@ body: |
; CHECK: liveins: $w3, $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (i16))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[LDRHui]], %subreg.hsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %16:fpr(s32) = G_LOAD %0(p0) :: (load (s16))
- %24:gpr(s32) = COPY %16(s32)
- $w0 = COPY %24(s32)
+ %16:fpr(i32) = G_LOAD %0(p0) :: (load (i16))
+ %24:gpr(i32) = COPY %16(i32)
+ $w0 = COPY %24(i32)
RET_ReallyLR
...
@@ -744,15 +744,15 @@ body: |
; CHECK: liveins: $w3, $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[LDRBui]], %subreg.bsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %16:fpr(s32) = G_LOAD %0(p0) :: (load (s8))
- %24:gpr(s32) = COPY %16(s32)
- $w0 = COPY %24(s32)
+ %16:fpr(i32) = G_LOAD %0(p0) :: (load (i8))
+ %24:gpr(i32) = COPY %16(i32)
+ $w0 = COPY %24(i32)
RET_ReallyLR
...
@@ -770,16 +770,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LD1i32_:%[0-9]+]]:fpr128 = LD1i32 [[COPY]], 0, [[COPY1]] :: (load (s32))
+ ; CHECK-NEXT: [[LD1i32_:%[0-9]+]]:fpr128 = LD1i32 [[COPY]], 0, [[COPY1]] :: (load (i32))
; CHECK-NEXT: $q0 = COPY [[LD1i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
+ %0:fpr(<4 x i32>) = COPY $q0
%1:gpr(p0) = COPY $x0
- %2:fpr(s32) = G_LOAD %1(p0) :: (load (s32))
- %3:gpr(s32) = G_CONSTANT i32 3
- %5:gpr(s64) = G_CONSTANT i64 0
- %4:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %2(s32), %5(s64)
- $q0 = COPY %4(<4 x s32>)
+ %2:fpr(i32) = G_LOAD %1(p0) :: (load (i32))
+ %3:gpr(i32) = G_CONSTANT i32 3
+ %5:gpr(i64) = G_CONSTANT i64 0
+ %4:fpr(<4 x i32>) = G_INSERT_VECTOR_ELT %0, %2(i32), %5(i64)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -798,21 +798,21 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY1]], 0 :: (load (s32))
+ ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY1]], 0 :: (load (i32))
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
- ; CHECK-NEXT: STRWui [[MOVi32imm]], [[COPY1]], 0 :: (store (s32))
+ ; CHECK-NEXT: STRWui [[MOVi32imm]], [[COPY1]], 0 :: (store (i32))
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRSui]], %subreg.ssub
; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY]], 0, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi32lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
+ %0:fpr(<4 x i32>) = COPY $q0
%1:gpr(p0) = COPY $x0
- %2:fpr(s32) = G_LOAD %1(p0) :: (load (s32))
- %3:gpr(s32) = G_CONSTANT i32 3
- G_STORE %3(s32), %1(p0) :: (store (s32))
- %5:gpr(s64) = G_CONSTANT i64 0
- %4:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %2(s32), %5(s64)
- $q0 = COPY %4(<4 x s32>)
+ %2:fpr(i32) = G_LOAD %1(p0) :: (load (i32))
+ %3:gpr(i32) = G_CONSTANT i32 3
+ G_STORE %3(i32), %1(p0) :: (store (i32))
+ %5:gpr(i64) = G_CONSTANT i64 0
+ %4:fpr(<4 x i32>) = G_INSERT_VECTOR_ELT %0, %2(i32), %5(i64)
+ $q0 = COPY %4(<4 x i32>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-modf.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-modf.mir
index 604cb96e38dc3..186f2c94ecdca 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-modf.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-modf.mir
@@ -27,21 +27,21 @@ body: |
; CHECK-NEXT: BL &modfl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $x0, implicit-def $q0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui %stack.0, 0 :: (load (i128) from %stack.0)
; CHECK-NEXT: $q0 = COPY [[COPY1]]
; CHECK-NEXT: $q1 = COPY [[LDRQui]]
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
- %0:fpr(s128) = COPY $q0
+ %0:fpr(i128) = COPY $q0
%3:gpr(p0) = G_FRAME_INDEX %stack.0
ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- $q0 = COPY %0(s128)
+ $q0 = COPY %0(i128)
$x0 = COPY %3(p0)
BL &modfl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $x0, implicit-def $q0
ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- %1:fpr(s128) = COPY $q0
- %2:fpr(s128) = G_LOAD %3(p0) :: (load (s128) from %stack.0)
- $q0 = COPY %1(s128)
- $q1 = COPY %2(s128)
+ %1:fpr(i128) = COPY $q0
+ %2:fpr(i128) = G_LOAD %3(p0) :: (load (i128) from %stack.0)
+ $q0 = COPY %1(i128)
+ $q1 = COPY %2(i128)
RET_ReallyLR implicit $q0, implicit $q1
...
---
@@ -72,21 +72,21 @@ body: |
; CHECK-NEXT: BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui %stack.0, 0 :: (load (s64) from %stack.0)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui %stack.0, 0 :: (load (i64) from %stack.0)
; CHECK-NEXT: $d0 = COPY [[COPY1]]
; CHECK-NEXT: $d1 = COPY [[LDRDui]]
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
- %0:fpr(s64) = COPY $d0
+ %0:fpr(i64) = COPY $d0
%3:gpr(p0) = G_FRAME_INDEX %stack.0
ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- $d0 = COPY %0(s64)
+ $d0 = COPY %0(i64)
$x0 = COPY %3(p0)
BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- %1:fpr(s64) = COPY $d0
- %2:fpr(s64) = G_LOAD %3(p0) :: (load (s64) from %stack.0)
- $d0 = COPY %1(s64)
- $d1 = COPY %2(s64)
+ %1:fpr(i64) = COPY $d0
+ %2:fpr(i64) = G_LOAD %3(p0) :: (load (i64) from %stack.0)
+ $d0 = COPY %1(i64)
+ $d1 = COPY %2(i64)
RET_ReallyLR implicit $d0, implicit $d1
...
---
@@ -117,20 +117,20 @@ body: |
; CHECK-NEXT: BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui %stack.0, 0 :: (load (s64) from %stack.0)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui %stack.0, 0 :: (load (i64) from %stack.0)
; CHECK-NEXT: $d0 = COPY [[COPY1]]
; CHECK-NEXT: $d1 = COPY [[LDRDui]]
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
- %0:fpr(s64) = COPY $d0
+ %0:fpr(i64) = COPY $d0
%3:gpr(p0) = G_FRAME_INDEX %stack.0
ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- $d0 = COPY %0(s64)
+ $d0 = COPY %0(i64)
$x0 = COPY %3(p0)
BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- %1:fpr(s64) = COPY $d0
- %2:fpr(s64) = G_LOAD %3(p0) :: (load (s64) from %stack.0)
- $d0 = COPY %1(s64)
- $d1 = COPY %2(s64)
+ %1:fpr(i64) = COPY $d0
+ %2:fpr(i64) = G_LOAD %3(p0) :: (load (i64) from %stack.0)
+ $d0 = COPY %1(i64)
+ $d1 = COPY %2(i64)
RET_ReallyLR implicit $d0, implicit $d1
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
index cf227cbb6f33b..640f225ea7d90 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
@@ -28,7 +28,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 12
; CHECK-NEXT: $d1 = COPY [[UCVTFd]]
- %0(s64) = COPY $d0
- %2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, 12
- $d1 = COPY %2(s64)
+ %0(i64) = COPY $d0
+ %2(f64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, 12
+ $d1 = COPY %2(f64)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
index 349513158e41c..90fbb993cc677 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
@@ -15,8 +15,8 @@ body: |
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 42, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 42
- %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
+ %1:gpr(i64) = G_CONSTANT i64 42
+ %2:gpr(p0) = G_PTR_ADD %0, %1(i64)
$x0 = COPY %2(p0)
...
@@ -35,8 +35,8 @@ body: |
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(p0) = G_PTR_ADD %0, %1(i64)
$x0 = COPY %2(p0)
...
@@ -56,8 +56,8 @@ body: |
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 10000
- %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
+ %1:gpr(i64) = G_CONSTANT i64 10000
+ %2:gpr(p0) = G_PTR_ADD %0, %1(i64)
$x0 = COPY %2(p0)
...
@@ -76,8 +76,8 @@ body: |
; CHECK-NEXT: [[ADDv2i64_:%[0-9]+]]:fpr128 = ADDv2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ADDv2i64_]]
%0:fpr(<2 x p0>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %3:fpr(<2 x p0>) = G_PTR_ADD %0, %1(<2 x s64>)
+ %1:fpr(<2 x i64>) = COPY $q1
+ %3:fpr(<2 x p0>) = G_PTR_ADD %0, %1(<2 x i64>)
$q0 = COPY %3(<2 x p0>)
...
---
@@ -95,8 +95,8 @@ body: |
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY1]], 10, 0, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXri]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 -10
- %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
+ %1:gpr(i64) = G_CONSTANT i64 -10
+ %2:gpr(p0) = G_PTR_ADD %0, %1(i64)
$x0 = COPY %2(p0)
...
---
@@ -114,12 +114,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY %ptr
; CHECK-NEXT: %ptr_add:gpr64sp = ADDXrx [[COPY]], %reg0, 18
; CHECK-NEXT: $x0 = COPY %ptr_add
- %reg0:gpr(s32) = COPY $w0
+ %reg0:gpr(i32) = COPY $w0
%ptr:gpr(p0) = COPY $x1
- %ext:gpr(s64) = G_ZEXT %reg0(s32)
- %cst:gpr(s64) = G_CONSTANT i64 2
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
- %ptr_add:gpr(p0) = G_PTR_ADD %ptr, %shift(s64)
+ %ext:gpr(i64) = G_ZEXT %reg0(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 2
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
+ %ptr_add:gpr(p0) = G_PTR_ADD %ptr, %shift(i64)
$x0 = COPY %ptr_add(p0)
...
---
@@ -137,9 +137,9 @@ body: |
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], %src, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
%0:gpr(p0) = COPY $x0
- %src:gpr(s64) = COPY $x1
- %1:gpr(s64) = G_CONSTANT i64 0
- %neg:gpr(s64) = G_SUB %1, %src
- %2:gpr(p0) = G_PTR_ADD %0, %neg(s64)
+ %src:gpr(i64) = COPY $x1
+ %1:gpr(i64) = G_CONSTANT i64 0
+ %neg:gpr(i64) = G_SUB %1, %src
+ %2:gpr(p0) = G_PTR_ADD %0, %neg(i64)
$x0 = COPY %2(p0)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
index b743cb9f7c578..e48664da8e97a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
@@ -16,14 +16,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x i8>))
; CHECK-NEXT: [[ADDVv16i8v:%[0-9]+]]:fpr8 = ADDVv16i8v [[LDRQui]]
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[ADDVv16i8v]], %subreg.bsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<16 x i8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
+ %1:fpr(<16 x i8>) = G_LOAD %0(p0) :: (load (<16 x i8>))
%2:fpr(i8) = G_VECREDUCE_ADD %1(<16 x i8>)
%4:gpr(i8) = COPY %2(i8)
%3:gpr(i32) = G_ANYEXT %4(i8)
@@ -47,14 +47,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x i16>))
; CHECK-NEXT: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]]
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[ADDVv8i16v]], %subreg.hsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<8 x i16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
+ %1:fpr(<8 x i16>) = G_LOAD %0(p0) :: (load (<8 x i16>))
%2:fpr(i16) = G_VECREDUCE_ADD %1(<8 x i16>)
%4:gpr(i16) = COPY %2(i16)
%3:gpr(i32) = G_ANYEXT %4(i16)
@@ -78,12 +78,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x i32>))
; CHECK-NEXT: [[ADDVv4i32v:%[0-9]+]]:fpr32 = ADDVv4i32v [[LDRQui]]
; CHECK-NEXT: $w0 = COPY [[ADDVv4i32v]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<4 x i32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
+ %1:fpr(<4 x i32>) = G_LOAD %0(p0) :: (load (<4 x i32>))
%2:fpr(i32) = G_VECREDUCE_ADD %1(<4 x i32>)
$w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
@@ -105,13 +105,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>))
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x i32>))
; CHECK-NEXT: [[ADDPv2i32_:%[0-9]+]]:fpr64 = ADDPv2i32 [[LDRDui]], [[LDRDui]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[ADDPv2i32_]].ssub
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<2 x i32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
+ %1:fpr(<2 x i32>) = G_LOAD %0(p0) :: (load (<2 x i32>))
%2:fpr(i32) = G_VECREDUCE_ADD %1(<2 x i32>)
$w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
@@ -133,12 +133,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x i64>))
; CHECK-NEXT: [[ADDPv2i64p:%[0-9]+]]:fpr64 = ADDPv2i64p [[LDRQui]]
; CHECK-NEXT: $x0 = COPY [[ADDPv2i64p]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %1:fpr(<2 x i64>) = G_LOAD %0(p0) :: (load (<2 x s64>))
+ %1:fpr(<2 x i64>) = G_LOAD %0(p0) :: (load (<2 x i64>))
%2:fpr(i64) = G_VECREDUCE_ADD %1(<2 x i64>)
$x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
index dc7c975edb488..3f7dc2a8b7349 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
@@ -13,14 +13,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(p0) = COPY $x0
- %2:gpr(s8) = G_LOAD %1(p0) :: (load (s8))
- %3:gpr(s32) = G_ZEXT %2(s8)
- $w0 = COPY %3(s32)
+ %2:gpr(i8) = G_LOAD %1(p0) :: (load (i8))
+ %3:gpr(i32) = G_ZEXT %2(i8)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
@@ -37,14 +37,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16))
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(p0) = COPY $x0
- %2:gpr(s16) = G_LOAD %1(p0) :: (load (s16))
- %3:gpr(s32) = G_ZEXT %2(s16)
- $w0 = COPY %3(s32)
+ %2:gpr(i16) = G_LOAD %1(p0) :: (load (i16))
+ %3:gpr(i32) = G_ZEXT %2(i16)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
index f5a94c7ad51fe..f4ce1af7f5a27 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
@@ -52,8 +52,8 @@ body: |
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s16) = G_IMPLICIT_DEF
- %3:gpr(i64) = G_ZEXT %0(s16)
+ %0:gpr(i16) = G_IMPLICIT_DEF
+ %3:gpr(i64) = G_ZEXT %0(i16)
$x0 = COPY %3(i64)
RET_ReallyLR implicit $x0
@@ -104,7 +104,7 @@ body: |
; CHECK-NEXT: $x0 = COPY %zext
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy:gpr(i32) = COPY $w0
- %bitcast0:gpr(<4 x s8>) = G_BITCAST %copy(i32)
+ %bitcast0:gpr(<4 x i8>) = G_BITCAST %copy(i32)
%bitcast1:gpr(i32) = G_BITCAST %bitcast0
%zext:gpr(i64) = G_ZEXT %bitcast1(i32)
$x0 = COPY %zext(i64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
index d011143667e48..a95d9e45a6505 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
@@ -27,9 +27,9 @@ body: |
; CHECK-NEXT: %rev:fpr64 = REV64v2i32 %copy
; CHECK-NEXT: $d0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(<2 x s32>) = COPY $d0
- %rev:fpr(<2 x s32>) = G_REV64 %copy
- $d0 = COPY %rev(<2 x s32>)
+ %copy:fpr(<2 x i32>) = COPY $d0
+ %rev:fpr(<2 x i32>) = G_REV64 %copy
+ $d0 = COPY %rev(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -49,9 +49,9 @@ body: |
; CHECK-NEXT: %rev:fpr64 = REV64v4i16 %copy
; CHECK-NEXT: $d0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(<4 x s16>) = COPY $d0
- %rev:fpr(<4 x s16>) = G_REV64 %copy
- $d0 = COPY %rev(<4 x s16>)
+ %copy:fpr(<4 x i16>) = COPY $d0
+ %rev:fpr(<4 x i16>) = G_REV64 %copy
+ $d0 = COPY %rev(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -71,9 +71,9 @@ body: |
; CHECK-NEXT: %rev:fpr128 = REV64v4i32 %copy
; CHECK-NEXT: $q0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(<4 x s32>) = COPY $q0
- %rev:fpr(<4 x s32>) = G_REV64 %copy
- $q0 = COPY %rev(<4 x s32>)
+ %copy:fpr(<4 x i32>) = COPY $q0
+ %rev:fpr(<4 x i32>) = G_REV64 %copy
+ $q0 = COPY %rev(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -93,9 +93,9 @@ body: |
; CHECK-NEXT: %rev:fpr64 = REV64v8i8 %copy
; CHECK-NEXT: $d0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(<8 x s8>) = COPY $d0
- %rev:fpr(<8 x s8>) = G_REV64 %copy
- $d0 = COPY %rev(<8 x s8>)
+ %copy:fpr(<8 x i8>) = COPY $d0
+ %rev:fpr(<8 x i8>) = G_REV64 %copy
+ $d0 = COPY %rev(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -115,9 +115,9 @@ body: |
; CHECK-NEXT: %rev:fpr128 = REV64v8i16 %copy
; CHECK-NEXT: $q0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(<8 x s16>) = COPY $q0
- %rev:fpr(<8 x s16>) = G_REV64 %copy
- $q0 = COPY %rev(<8 x s16>)
+ %copy:fpr(<8 x i16>) = COPY $q0
+ %rev:fpr(<8 x i16>) = G_REV64 %copy
+ $q0 = COPY %rev(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -137,9 +137,9 @@ body: |
; CHECK-NEXT: %rev:fpr128 = REV64v16i8 %copy
; CHECK-NEXT: $q0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(<16 x s8>) = COPY $q0
- %rev:fpr(<16 x s8>) = G_REV64 %copy
- $q0 = COPY %rev(<16 x s8>)
+ %copy:fpr(<16 x i8>) = COPY $q0
+ %rev:fpr(<16 x i8>) = G_REV64 %copy
+ $q0 = COPY %rev(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -159,9 +159,9 @@ body: |
; CHECK-NEXT: %rev:fpr64 = REV32v4i16 %copy
; CHECK-NEXT: $d0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(<4 x s16>) = COPY $d0
- %rev:fpr(<4 x s16>) = G_REV32 %copy
- $d0 = COPY %rev(<4 x s16>)
+ %copy:fpr(<4 x i16>) = COPY $d0
+ %rev:fpr(<4 x i16>) = G_REV32 %copy
+ $d0 = COPY %rev(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -181,9 +181,9 @@ body: |
; CHECK-NEXT: %rev:fpr64 = REV32v8i8 %copy
; CHECK-NEXT: $d0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(<8 x s8>) = COPY $d0
- %rev:fpr(<8 x s8>) = G_REV32 %copy
- $d0 = COPY %rev(<8 x s8>)
+ %copy:fpr(<8 x i8>) = COPY $d0
+ %rev:fpr(<8 x i8>) = G_REV32 %copy
+ $d0 = COPY %rev(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -203,9 +203,9 @@ body: |
; CHECK-NEXT: %rev:fpr128 = REV32v8i16 %copy
; CHECK-NEXT: $q0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(<8 x s16>) = COPY $q0
- %rev:fpr(<8 x s16>) = G_REV32 %copy
- $q0 = COPY %rev(<8 x s16>)
+ %copy:fpr(<8 x i16>) = COPY $q0
+ %rev:fpr(<8 x i16>) = G_REV32 %copy
+ $q0 = COPY %rev(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -225,9 +225,9 @@ body: |
; CHECK-NEXT: %rev:fpr128 = REV32v16i8 %copy
; CHECK-NEXT: $q0 = COPY %rev
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(<16 x s8>) = COPY $q0
- %rev:fpr(<16 x s8>) = G_REV32 %copy
- $q0 = COPY %rev(<16 x s8>)
+ %copy:fpr(<16 x i8>) = COPY $q0
+ %rev:fpr(<16 x i8>) = G_REV32 %copy
+ $q0 = COPY %rev(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -247,11 +247,11 @@ body: |
; CHECK-NEXT: %rev2:fpr64 = REV16v8i8 %copy
; CHECK-NEXT: $d0 = COPY %rev2
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(<8 x s8>) = COPY $d0
- %rev1:fpr(<4 x s16>) = G_BITCAST %copy
- %rev2:fpr(<4 x s16>) = G_BSWAP %rev1
- %rev:fpr(<8 x s8>) = G_BITCAST %rev2
- $d0 = COPY %rev(<8 x s8>)
+ %copy:fpr(<8 x i8>) = COPY $d0
+ %rev1:fpr(<4 x i16>) = G_BITCAST %copy
+ %rev2:fpr(<4 x i16>) = G_BSWAP %rev1
+ %rev:fpr(<8 x i8>) = G_BITCAST %rev2
+ $d0 = COPY %rev(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -271,9 +271,9 @@ body: |
; CHECK-NEXT: %rev2:fpr128 = REV16v16i8 %copy
; CHECK-NEXT: $q0 = COPY %rev2
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(<16 x s8>) = COPY $q0
- %rev1:fpr(<8 x s16>) = G_BITCAST %copy
- %rev2:fpr(<8 x s16>) = G_BSWAP %rev1
- %rev:fpr(<16 x s8>) = G_BITCAST %rev2
- $q0 = COPY %rev(<16 x s8>)
+ %copy:fpr(<16 x i8>) = COPY $q0
+ %rev1:fpr(<8 x i16>) = G_BITCAST %copy
+ %rev2:fpr(<8 x i16>) = G_BSWAP %rev1
+ %rev:fpr(<16 x i8>) = G_BITCAST %rev2
+ $q0 = COPY %rev(<16 x i8>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
index e98ab4af57097..893236c83c57d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
@@ -23,12 +23,12 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADCSXr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s64), %4:gpr(s32) = G_SADDE %0, %1, %2
- $x0 = COPY %3(s64)
- $w1 = COPY %4(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i64), %4:gpr(i32) = G_SADDE %0, %1, %2
+ $x0 = COPY %3(i64)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $x0, implicit $w1
...
...
@@ -54,12 +54,12 @@ body: |
; CHECK-NEXT: $w0 = COPY [[ADCSWr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32), %4:gpr(s32) = G_SADDE %0, %1, %2
- $w0 = COPY %3(s32)
- $w1 = COPY %4(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32), %4:gpr(i32) = G_SADDE %0, %1, %2
+ $w0 = COPY %3(i32)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $w0, implicit $w1
...
...
@@ -85,14 +85,14 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
; CHECK-NEXT: $x1 = COPY [[ADCSXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %8:gpr(s64), %12:gpr(s32) = G_UADDO %0, %2
- %9:gpr(s64), %13:gpr(s32) = G_SADDE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %8:gpr(i64), %12:gpr(i32) = G_UADDO %0, %2
+ %9:gpr(i64), %13:gpr(i32) = G_SADDE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -120,15 +120,15 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADCSXr]]
; CHECK-NEXT: $x1 = COPY [[ADCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %6:gpr(s32) = G_CONSTANT i32 1
- %8:gpr(s64), %12:gpr(s32) = G_UADDE %0, %2, %6
- %9:gpr(s64), %13:gpr(s32) = G_SADDE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %8:gpr(i64), %12:gpr(i32) = G_UADDE %0, %2, %6
+ %9:gpr(i64), %13:gpr(i32) = G_SADDE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -160,19 +160,19 @@ body: |
; CHECK-NEXT: $x1 = COPY [[ADCSXr]]
; CHECK-NEXT: $x2 = COPY [[ADCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %4:gpr(s64) = COPY $x4
- %5:gpr(s64) = COPY $x5
- %6:gpr(s64) = COPY $x6
- %7:gpr(s64), %11:gpr(s32) = G_UADDO %0, %4
- %8:gpr(s64), %12:gpr(s32) = G_UADDE %1, %5, %11
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %4:gpr(i64) = COPY $x4
+ %5:gpr(i64) = COPY $x5
+ %6:gpr(i64) = COPY $x6
+ %7:gpr(i64), %11:gpr(i32) = G_UADDO %0, %4
+ %8:gpr(i64), %12:gpr(i32) = G_UADDE %1, %5, %11
; carry-in is not produced by previous instruction
- %9:gpr(s64), %13:gpr(s32) = G_SADDE %2, %6, %11
- $x0 = COPY %7(s64)
- $x1 = COPY %8(s64)
- $x2 = COPY %9(s64)
+ %9:gpr(i64), %13:gpr(i32) = G_SADDE %2, %6, %11
+ $x0 = COPY %7(i64)
+ $x1 = COPY %8(i64)
+ $x2 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
@@ -197,12 +197,12 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %4:gpr(s64), %5:gpr(s32) = G_UADDO %0, %2
- %6:gpr(s64), %7:gpr(s32) = G_SADDE %1, %3, %5
- $w0 = COPY %7(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_UADDO %0, %2
+ %6:gpr(i64), %7:gpr(i32) = G_SADDE %1, %3, %5
+ $w0 = COPY %7(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
index fe272c68d450f..4bf7128418ae6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
@@ -22,9 +22,9 @@ body: |
; CHECK-NEXT: $w0 = COPY [[ADDSWrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %3:gpr(s32), %4:gpr(s32) = G_SADDO %0, %1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %3:gpr(i32), %4:gpr(i32) = G_SADDO %0, %1
$w0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $w0, implicit $w1
@@ -50,9 +50,9 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %3:gpr(s64), %4:gpr(s32) = G_SADDO %0, %1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %3:gpr(i64), %4:gpr(i32) = G_SADDO %0, %1
$x0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $x0, implicit $w1
@@ -75,10 +75,10 @@ body: |
; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 16
- %add:gpr(s32), %overflow:gpr(s32) = G_SADDO %copy, %constant
- $w0 = COPY %add(s32)
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %add:gpr(i32), %overflow:gpr(i32) = G_SADDO %copy, %constant
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -100,12 +100,12 @@ body: |
; CHECK-NEXT: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy1:gpr(s32) = COPY $w0
- %copy2:gpr(s32) = COPY $w1
- %constant:gpr(s32) = G_CONSTANT i32 16
- %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
- %add:gpr(s32), %overflow:gpr(s32) = G_SADDO %copy1, %shift
- $w0 = COPY %add(s32)
+ %copy1:gpr(i32) = COPY $w0
+ %copy2:gpr(i32) = COPY $w1
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %shift:gpr(i32) = G_SHL %copy2(i32), %constant(i32)
+ %add:gpr(i32), %overflow:gpr(i32) = G_SADDO %copy1, %shift
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -126,10 +126,10 @@ body: |
; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 -16
- %add:gpr(s32), %overflow:gpr(s32) = G_SADDO %copy, %constant
- $w0 = COPY %add(s32)
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 -16
+ %add:gpr(i32), %overflow:gpr(i32) = G_SADDO %copy, %constant
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -151,11 +151,11 @@ body: |
; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
; CHECK-NEXT: $x0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %reg1:gpr(s32) = COPY $w0
- %ext:gpr(s64) = G_ZEXT %reg1(s32)
- %cst:gpr(s64) = G_CONSTANT i64 2
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
- %add:gpr(s64), %flags:gpr(s32) = G_SADDO %reg0, %shift
- $x0 = COPY %add(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %reg1:gpr(i32) = COPY $w0
+ %ext:gpr(i64) = G_ZEXT %reg1(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 2
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
+ %add:gpr(i64), %flags:gpr(i32) = G_SADDO %reg0, %shift
+ $x0 = COPY %add(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir
index bbf6239b510cf..22cf6b4bab615 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-sbfx.mir
@@ -17,10 +17,10 @@ body: |
; CHECK-NEXT: %sbfx:gpr32 = SBFMWri %copy, 0, 9
; CHECK-NEXT: $w0 = COPY %sbfx
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %cst1:gpr(s32) = G_CONSTANT i32 0
- %cst2:gpr(s32) = G_CONSTANT i32 10
- %sbfx:gpr(s32) = G_SBFX %copy, %cst1, %cst2
+ %copy:gpr(i32) = COPY $w0
+ %cst1:gpr(i32) = G_CONSTANT i32 0
+ %cst2:gpr(i32) = G_CONSTANT i32 10
+ %sbfx:gpr(i32) = G_SBFX %copy, %cst1, %cst2
$w0 = COPY %sbfx
RET_ReallyLR implicit $w0
@@ -40,10 +40,10 @@ body: |
; CHECK-NEXT: %sbfx:gpr64 = SBFMXri %copy, 0, 9
; CHECK-NEXT: $x0 = COPY %sbfx
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:gpr(s64) = COPY $x0
- %cst1:gpr(s64) = G_CONSTANT i64 0
- %cst2:gpr(s64) = G_CONSTANT i64 10
- %sbfx:gpr(s64) = G_SBFX %copy, %cst1, %cst2
+ %copy:gpr(i64) = COPY $x0
+ %cst1:gpr(i64) = G_CONSTANT i64 0
+ %cst2:gpr(i64) = G_CONSTANT i64 10
+ %sbfx:gpr(i64) = G_SBFX %copy, %cst1, %cst2
$x0 = COPY %sbfx
RET_ReallyLR implicit $x0
@@ -65,10 +65,10 @@ body: |
; CHECK-NEXT: %sbfx:gpr32 = SBFMWri %copy, 31, 31
; CHECK-NEXT: $w0 = COPY %sbfx
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %cst1:gpr(s32) = G_CONSTANT i32 31
- %cst2:gpr(s32) = G_CONSTANT i32 1
- %sbfx:gpr(s32) = G_SBFX %copy, %cst1, %cst2
+ %copy:gpr(i32) = COPY $w0
+ %cst1:gpr(i32) = G_CONSTANT i32 31
+ %cst2:gpr(i32) = G_CONSTANT i32 1
+ %sbfx:gpr(i32) = G_SBFX %copy, %cst1, %cst2
$w0 = COPY %sbfx
RET_ReallyLR implicit $w0
---
@@ -85,10 +85,10 @@ body: |
; CHECK: %sbfx:gpr32 = SBFMWri %copy, 10, 14
; CHECK: $w0 = COPY %sbfx
; CHECK: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %cst1:gpr(s32) = G_CONSTANT i32 10
- %cst2:gpr(s32) = G_CONSTANT i32 5
- %sbfx:gpr(s32) = G_SBFX %copy, %cst1, %cst2
+ %copy:gpr(i32) = COPY $w0
+ %cst1:gpr(i32) = G_CONSTANT i32 10
+ %cst2:gpr(i32) = G_CONSTANT i32 5
+ %sbfx:gpr(i32) = G_SBFX %copy, %cst1, %cst2
$w0 = COPY %sbfx
RET_ReallyLR implicit $w0
---
@@ -105,9 +105,9 @@ body: |
; CHECK: %sbfx:gpr64 = SBFMXri %copy, 10, 14
; CHECK: $x0 = COPY %sbfx
; CHECK: RET_ReallyLR implicit $x0
- %copy:gpr(s64) = COPY $x0
- %cst1:gpr(s64) = G_CONSTANT i64 10
- %cst2:gpr(s64) = G_CONSTANT i64 5
- %sbfx:gpr(s64) = G_SBFX %copy, %cst1, %cst2
+ %copy:gpr(i64) = COPY $x0
+ %cst1:gpr(i64) = G_CONSTANT i64 10
+ %cst2:gpr(i64) = G_CONSTANT i64 5
+ %sbfx:gpr(i64) = G_SBFX %copy, %cst1, %cst2
$x0 = COPY %sbfx
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir
index 42b1c61949b94..85e5b1bb9e957 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir
@@ -29,8 +29,8 @@ body: |
; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[SUBREG_TO_REG]], [[SUBREG_TO_REG1]], 32, 31
; CHECK-NEXT: $x0 = COPY [[BFMXri]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- $x0 = COPY %2(s64)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i64) = G_MERGE_VALUES %0(i32), %1(i32)
+ $x0 = COPY %2(i64)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
index d2bf5839f1be7..6aca3c31774aa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
@@ -21,10 +21,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRSHWui:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRSHWui:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load (i16) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRSHWui]]
%0:gpr(p0) = COPY $x0
- %1:gpr(i32) = G_SEXTLOAD %0 :: (load (s16) from %ir.addr)
+ %1:gpr(i32) = G_SEXTLOAD %0 :: (load (i16) from %ir.addr)
$w0 = COPY %1(i32)
...
@@ -41,11 +41,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16) from %ir.addr)
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[LDRHHui]], 0, 15
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
%0:gpr(p0) = COPY $x0
- %1:gpr(i16) = G_LOAD %0 :: (load (s16) from %ir.addr)
+ %1:gpr(i16) = G_LOAD %0 :: (load (i16) from %ir.addr)
%2:gpr(i32) = G_SEXT %1
$w0 = COPY %2(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
index 345cc774f9963..666e7c059a8e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
@@ -59,10 +59,10 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
; CHECK: $d0 = COPY [[COPY2]]
; CHECK: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0)
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(1, 0)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -90,10 +90,10 @@ body: |
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
; CHECK: $q0 = COPY [[TBLv16i8Two]]
; CHECK: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 3, 0)
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(0, 1, 3, 0)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -121,10 +121,10 @@ body: |
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
; CHECK: $q0 = COPY [[TBLv16i8Two]]
; CHECK: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(5, 7, 1, 0)
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(5, 7, 1, 0)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -152,10 +152,10 @@ body: |
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
; CHECK: $q0 = COPY [[TBLv16i8Two]]
; CHECK: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 0)
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %2:fpr(<2 x i64>) = G_SHUFFLE_VECTOR %0(<2 x i64>), %1, shufflemask(1, 0)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
index a5ac0b7ff8626..86350664abf63 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
@@ -36,12 +36,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %6:gpr(s32) = G_IMPLICIT_DEF
- %7:gpr(s32) = G_IMPLICIT_DEF
- %2:fpr(<2 x s32>) = G_BUILD_VECTOR %6(s32), %7(s32)
- %1:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, undef)
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %6:gpr(i32) = G_IMPLICIT_DEF
+ %7:gpr(i32) = G_IMPLICIT_DEF
+ %2:fpr(<2 x i32>) = G_BUILD_VECTOR %6(i32), %7(i32)
+ %1:fpr(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %2, shufflemask(1, undef)
+ $d0 = COPY %1(<2 x i32>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
index a9da51781efbe..1b3ae63e0c9c4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
@@ -23,12 +23,12 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SBCSXr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s64), %4:gpr(s32) = G_SSUBE %0, %1, %2
- $x0 = COPY %3(s64)
- $w1 = COPY %4(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i64), %4:gpr(i32) = G_SSUBE %0, %1, %2
+ $x0 = COPY %3(i64)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $x0, implicit $w1
...
...
@@ -54,12 +54,12 @@ body: |
; CHECK-NEXT: $w0 = COPY [[SBCSWr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32), %4:gpr(s32) = G_SSUBE %0, %1, %2
- $w0 = COPY %3(s32)
- $w1 = COPY %4(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32), %4:gpr(i32) = G_SSUBE %0, %1, %2
+ $w0 = COPY %3(i32)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $w0, implicit $w1
...
...
@@ -85,14 +85,14 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
; CHECK-NEXT: $x1 = COPY [[SBCSXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %8:gpr(s64), %12:gpr(s32) = G_USUBO %0, %2
- %9:gpr(s64), %13:gpr(s32) = G_SSUBE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %8:gpr(i64), %12:gpr(i32) = G_USUBO %0, %2
+ %9:gpr(i64), %13:gpr(i32) = G_SSUBE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -120,15 +120,15 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SBCSXr]]
; CHECK-NEXT: $x1 = COPY [[SBCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %6:gpr(s32) = G_CONSTANT i32 1
- %8:gpr(s64), %12:gpr(s32) = G_USUBE %0, %2, %6
- %9:gpr(s64), %13:gpr(s32) = G_SSUBE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %8:gpr(i64), %12:gpr(i32) = G_USUBE %0, %2, %6
+ %9:gpr(i64), %13:gpr(i32) = G_SSUBE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -160,19 +160,19 @@ body: |
; CHECK-NEXT: $x1 = COPY [[SBCSXr]]
; CHECK-NEXT: $x2 = COPY [[SBCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %4:gpr(s64) = COPY $x4
- %5:gpr(s64) = COPY $x5
- %6:gpr(s64) = COPY $x6
- %7:gpr(s64), %11:gpr(s32) = G_USUBO %0, %4
- %8:gpr(s64), %12:gpr(s32) = G_USUBE %1, %5, %11
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %4:gpr(i64) = COPY $x4
+ %5:gpr(i64) = COPY $x5
+ %6:gpr(i64) = COPY $x6
+ %7:gpr(i64), %11:gpr(i32) = G_USUBO %0, %4
+ %8:gpr(i64), %12:gpr(i32) = G_USUBE %1, %5, %11
; carry-in is not produced by previous instruction
- %9:gpr(s64), %13:gpr(s32) = G_SSUBE %2, %6, %11
- $x0 = COPY %7(s64)
- $x1 = COPY %8(s64)
- $x2 = COPY %9(s64)
+ %9:gpr(i64), %13:gpr(i32) = G_SSUBE %2, %6, %11
+ $x0 = COPY %7(i64)
+ $x1 = COPY %8(i64)
+ $x2 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
@@ -197,12 +197,12 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %4:gpr(s64), %5:gpr(s32) = G_USUBO %0, %2
- %6:gpr(s64), %7:gpr(s32) = G_SSUBE %1, %3, %5
- $w0 = COPY %7(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_USUBO %0, %2
+ %6:gpr(i64), %7:gpr(i32) = G_SSUBE %1, %3, %5
+ $w0 = COPY %7(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
index 700a7e298ec5f..c2b116b3f77ea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
@@ -22,9 +22,9 @@ body: |
; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %3:gpr(s32), %4:gpr(s32) = G_SSUBO %0, %1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %3:gpr(i32), %4:gpr(i32) = G_SSUBO %0, %1
$w0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $w0, implicit $w1
@@ -50,9 +50,9 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %3:gpr(s64), %4:gpr(s32) = G_SSUBO %0, %1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %3:gpr(i64), %4:gpr(i32) = G_SSUBO %0, %1
$x0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $x0, implicit $w1
@@ -75,10 +75,10 @@ body: |
; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 16
- %add:gpr(s32), %overflow:gpr(s32) = G_SSUBO %copy, %constant
- $w0 = COPY %add(s32)
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %add:gpr(i32), %overflow:gpr(i32) = G_SSUBO %copy, %constant
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -100,12 +100,12 @@ body: |
; CHECK-NEXT: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy1:gpr(s32) = COPY $w0
- %copy2:gpr(s32) = COPY $w1
- %constant:gpr(s32) = G_CONSTANT i32 16
- %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
- %add:gpr(s32), %overflow:gpr(s32) = G_SSUBO %copy1, %shift
- $w0 = COPY %add(s32)
+ %copy1:gpr(i32) = COPY $w0
+ %copy2:gpr(i32) = COPY $w1
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %shift:gpr(i32) = G_SHL %copy2(i32), %constant(i32)
+ %add:gpr(i32), %overflow:gpr(i32) = G_SSUBO %copy1, %shift
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -126,10 +126,10 @@ body: |
; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 -16
- %add:gpr(s32), %overflow:gpr(s32) = G_SSUBO %copy, %constant
- $w0 = COPY %add(s32)
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 -16
+ %add:gpr(i32), %overflow:gpr(i32) = G_SSUBO %copy, %constant
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -151,11 +151,11 @@ body: |
; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
; CHECK-NEXT: $x0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %reg1:gpr(s32) = COPY $w0
- %ext:gpr(s64) = G_ZEXT %reg1(s32)
- %cst:gpr(s64) = G_CONSTANT i64 2
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
- %add:gpr(s64), %flags:gpr(s32) = G_SSUBO %reg0, %shift
- $x0 = COPY %add(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %reg1:gpr(i32) = COPY $w0
+ %ext:gpr(i64) = G_ZEXT %reg1(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 2
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
+ %add:gpr(i64), %flags:gpr(i32) = G_SSUBO %reg0, %shift
+ $x0 = COPY %add(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-st2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-st2.mir
index 3503b8e13c588..1dd0e8f1288e5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-st2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-st2.mir
@@ -18,12 +18,12 @@ body: |
; CHECK-NEXT: %src1:fpr64 = COPY $d0
; CHECK-NEXT: %src2:fpr64 = COPY $d1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
- ; CHECK-NEXT: ST2Twov8b [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
+ ; CHECK-NEXT: ST2Twov8b [[REG_SEQUENCE]], %ptr :: (store (<2 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:fpr(<8 x s8>) = COPY $d0
- %src2:fpr(<8 x s8>) = COPY $d1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s8>), %src2(<8 x s8>), %ptr(p0) :: (store (<2 x s64>))
+ %src1:fpr(<8 x i8>) = COPY $d0
+ %src2:fpr(<8 x i8>) = COPY $d1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x i8>), %src2(<8 x i8>), %ptr(p0) :: (store (<2 x i64>))
RET_ReallyLR
...
@@ -44,12 +44,12 @@ body: |
; CHECK-NEXT: %src1:fpr128 = COPY $q0
; CHECK-NEXT: %src2:fpr128 = COPY $q1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
- ; CHECK-NEXT: ST2Twov16b [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
+ ; CHECK-NEXT: ST2Twov16b [[REG_SEQUENCE]], %ptr :: (store (<4 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:fpr(<16 x s8>) = COPY $q0
- %src2:fpr(<16 x s8>) = COPY $q1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<16 x s8>), %src2(<16 x s8>), %ptr(p0) :: (store (<4 x s64>))
+ %src1:fpr(<16 x i8>) = COPY $q0
+ %src2:fpr(<16 x i8>) = COPY $q1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<16 x i8>), %src2(<16 x i8>), %ptr(p0) :: (store (<4 x i64>))
RET_ReallyLR
...
@@ -70,12 +70,12 @@ body: |
; CHECK-NEXT: %src1:fpr64 = COPY $d0
; CHECK-NEXT: %src2:fpr64 = COPY $d1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
- ; CHECK-NEXT: ST2Twov4h [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
+ ; CHECK-NEXT: ST2Twov4h [[REG_SEQUENCE]], %ptr :: (store (<2 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:fpr(<4 x s16>) = COPY $d0
- %src2:fpr(<4 x s16>) = COPY $d1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s16>), %src2(<4 x s16>), %ptr(p0) :: (store (<2 x s64>))
+ %src1:fpr(<4 x i16>) = COPY $d0
+ %src2:fpr(<4 x i16>) = COPY $d1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x i16>), %src2(<4 x i16>), %ptr(p0) :: (store (<2 x i64>))
RET_ReallyLR
...
@@ -96,12 +96,12 @@ body: |
; CHECK-NEXT: %src1:fpr128 = COPY $q0
; CHECK-NEXT: %src2:fpr128 = COPY $q1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
- ; CHECK-NEXT: ST2Twov8h [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
+ ; CHECK-NEXT: ST2Twov8h [[REG_SEQUENCE]], %ptr :: (store (<4 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:fpr(<8 x s16>) = COPY $q0
- %src2:fpr(<8 x s16>) = COPY $q1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s16>), %src2(<8 x s16>), %ptr(p0) :: (store (<4 x s64>))
+ %src1:fpr(<8 x i16>) = COPY $q0
+ %src2:fpr(<8 x i16>) = COPY $q1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x i16>), %src2(<8 x i16>), %ptr(p0) :: (store (<4 x i64>))
RET_ReallyLR
...
@@ -121,12 +121,12 @@ body: |
; CHECK-NEXT: %src1:fpr64 = COPY $d0
; CHECK-NEXT: %src2:fpr64 = COPY $d1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
- ; CHECK-NEXT: ST2Twov2s [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
+ ; CHECK-NEXT: ST2Twov2s [[REG_SEQUENCE]], %ptr :: (store (<2 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:fpr(<2 x s32>) = COPY $d0
- %src2:fpr(<2 x s32>) = COPY $d1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s32>), %src2(<2 x s32>), %ptr(p0) :: (store (<2 x s64>))
+ %src1:fpr(<2 x i32>) = COPY $d0
+ %src2:fpr(<2 x i32>) = COPY $d1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x i32>), %src2(<2 x i32>), %ptr(p0) :: (store (<2 x i64>))
RET_ReallyLR
...
@@ -146,12 +146,12 @@ body: |
; CHECK-NEXT: %src1:fpr128 = COPY $q0
; CHECK-NEXT: %src2:fpr128 = COPY $q1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
- ; CHECK-NEXT: ST2Twov4s [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
+ ; CHECK-NEXT: ST2Twov4s [[REG_SEQUENCE]], %ptr :: (store (<4 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:fpr(<4 x s32>) = COPY $q0
- %src2:fpr(<4 x s32>) = COPY $q1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s32>), %src2(<4 x s32>), %ptr(p0) :: (store (<4 x s64>))
+ %src1:fpr(<4 x i32>) = COPY $q0
+ %src2:fpr(<4 x i32>) = COPY $q1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x i32>), %src2(<4 x i32>), %ptr(p0) :: (store (<4 x i64>))
RET_ReallyLR
...
@@ -171,12 +171,12 @@ body: |
; CHECK-NEXT: %src1:fpr128 = COPY $q0
; CHECK-NEXT: %src2:fpr128 = COPY $q1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
- ; CHECK-NEXT: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
+ ; CHECK-NEXT: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:fpr(<2 x s64>) = COPY $q0
- %src2:fpr(<2 x s64>) = COPY $q1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s64>), %src2(<2 x s64>), %ptr(p0) :: (store (<4 x s64>))
+ %src1:fpr(<2 x i64>) = COPY $q0
+ %src2:fpr(<2 x i64>) = COPY $q1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x i64>), %src2(<2 x i64>), %ptr(p0) :: (store (<4 x i64>))
RET_ReallyLR
...
@@ -196,12 +196,12 @@ body: |
; CHECK-NEXT: %src1:fpr128 = COPY $q0
; CHECK-NEXT: %src2:fpr128 = COPY $q1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
- ; CHECK-NEXT: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
+ ; CHECK-NEXT: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
%src1:fpr(<2 x p0>) = COPY $q0
%src2:fpr(<2 x p0>) = COPY $q1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x p0>), %src2(<2 x p0>), %ptr(p0) :: (store (<4 x s64>))
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x p0>), %src2(<2 x p0>), %ptr(p0) :: (store (<4 x i64>))
RET_ReallyLR
...
@@ -221,12 +221,12 @@ body: |
; CHECK-NEXT: %src1:gpr64all = COPY $x0
; CHECK-NEXT: %src2:gpr64all = COPY $x1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
- ; CHECK-NEXT: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
+ ; CHECK-NEXT: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
- %src1:gpr(s64) = COPY $x0
- %src2:gpr(s64) = COPY $x1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(s64), %src2(s64), %ptr(p0) :: (store (<2 x s64>))
+ %src1:gpr(i64) = COPY $x0
+ %src2:gpr(i64) = COPY $x1
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(i64), %src2(i64), %ptr(p0) :: (store (<2 x i64>))
RET_ReallyLR
...
@@ -246,12 +246,12 @@ body: |
; CHECK-NEXT: %src1:gpr64all = COPY $x0
; CHECK-NEXT: %src2:gpr64all = COPY $x1
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
- ; CHECK-NEXT: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
+ ; CHECK-NEXT: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x i64>))
; CHECK-NEXT: RET_ReallyLR
%ptr:gpr(p0) = COPY $x0
%src1:gpr(p0) = COPY $x0
%src2:gpr(p0) = COPY $x1
- G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(p0), %src2(p0), %ptr(p0) :: (store (<2 x s64>))
+ G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(p0), %src2(p0), %ptr(p0) :: (store (<2 x i64>))
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
index df13c02374fed..10150a882e9de 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
@@ -60,7 +60,7 @@ body: |
bb.0:
liveins: $x0
%0:gpr(p0) = COPY $x0
- %const:gpr(s64) = G_CONSTANT i64 -8
+ %const:gpr(i64) = G_CONSTANT i64 -8
%1:gpr(p0) = G_PTRMASK %0, %const
$x0 = COPY %1(p0)
...
@@ -139,16 +139,16 @@ body: |
bb.0:
liveins: $w0, $x0
- %0(s32) = COPY $w0
- %1(s32) = G_ICMP intpred(eq), %0, %0
+ %0(i32) = COPY $w0
+ %1(i32) = G_ICMP intpred(eq), %0, %0
$w0 = COPY %1
- %2(s64) = COPY $x0
- %3(s32) = G_ICMP intpred(uge), %2, %2
+ %2(i64) = COPY $x0
+ %3(i32) = G_ICMP intpred(uge), %2, %2
$w0 = COPY %3
%4(p0) = COPY $x0
- %5(s32) = G_ICMP intpred(ne), %4, %4
+ %5(i32) = G_ICMP intpred(ne), %4, %4
$w0 = COPY %5
...
@@ -184,12 +184,12 @@ body: |
bb.0:
liveins: $w0, $x0
- %0(s32) = COPY $s0
- %1(s32) = G_FCMP floatpred(one), %0, %0
+ %0(f32) = COPY $s0
+ %1(i32) = G_FCMP floatpred(one), %0, %0
$w0 = COPY %1
- %2(s64) = COPY $d0
- %3(s32) = G_FCMP floatpred(uge), %2, %2
+ %2(f64) = COPY $d0
+ %3(i32) = G_FCMP floatpred(uge), %2, %2
$w0 = COPY %3
...
@@ -219,12 +219,12 @@ body: |
bb.0:
liveins: $s0, $w0
successors: %bb.1
- %0(s32) = COPY $s0
- %3:gpr(s32) = COPY $w0
+ %0(i32) = COPY $s0
+ %3:gpr(i32) = COPY $w0
bb.1:
successors: %bb.1, %bb.2
- %2(s32) = PHI %0, %bb.0, %2, %bb.1
+ %2(i32) = PHI %0, %bb.0, %2, %bb.1
G_BRCOND %3, %bb.1
bb.2:
@@ -272,17 +272,17 @@ registers:
body: |
bb.0:
liveins: $w0, $w1, $w2
- %0:gpr(s32) = COPY $w0
+ %0:gpr(i32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = COPY $w2
- %3(s32) = G_SELECT %0, %1, %2
- $w0 = COPY %3(s32)
+ %1(i32) = COPY $w1
+ %2(i32) = COPY $w2
+ %3(i32) = G_SELECT %0, %1, %2
+ $w0 = COPY %3(i32)
- %4(s64) = COPY $x0
- %5(s64) = COPY $x1
- %6(s64) = G_SELECT %0, %4, %5
- $x0 = COPY %6(s64)
+ %4(i64) = COPY $x0
+ %5(i64) = COPY $x1
+ %6(i64) = G_SELECT %0, %4, %5
+ $x0 = COPY %6(i64)
%7(p0) = COPY $x0
%8(p0) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
index 857ed9b3efbd3..f75aa7766131c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
@@ -28,12 +28,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
- ; CHECK-NEXT: early-clobber %2:gpr32 = STLXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %2:gpr32 = STLXRX [[COPY]], [[COPY1]] :: (volatile store (i64) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(i64) = COPY $x1
%2:gpr(p0) = COPY $x2
- %3:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %1(i64), %2(p0) :: (volatile store (s64) into %ir.addr)
+ %3:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %1(i64), %2(p0) :: (volatile store (i64) into %ir.addr)
$w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
@@ -52,13 +52,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
- ; CHECK-NEXT: early-clobber %3:gpr32 = STLXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %3:gpr32 = STLXRW [[COPY]], [[COPY1]] :: (volatile store (i32) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
%3:gpr(i64) = G_ZEXT %1(i32)
- %4:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %3(i64), %2(p0) :: (volatile store (s32) into %ir.addr)
+ %4:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %3(i64), %2(p0) :: (volatile store (i32) into %ir.addr)
$w0 = COPY %4(i32)
RET_ReallyLR implicit $w0
@@ -81,7 +81,7 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
- ; CHECK-NEXT: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store (i8) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:gpr(i32) = COPY $w1
@@ -89,7 +89,7 @@ body: |
%6:gpr(i64) = G_CONSTANT i64 255
%7:gpr(i64) = G_ANYEXT %3(i32)
%4:gpr(i64) = G_AND %7, %6
- %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(i64), %2(p0) :: (volatile store (s8) into %ir.addr)
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(i64), %2(p0) :: (volatile store (i8) into %ir.addr)
$w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
@@ -112,7 +112,7 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
- ; CHECK-NEXT: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store (i16) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:gpr(i32) = COPY $w1
@@ -120,6 +120,6 @@ body: |
%6:gpr(i64) = G_CONSTANT i64 65535
%7:gpr(i64) = G_ANYEXT %3(i32)
%4:gpr(i64) = G_AND %7, %6
- %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(i64), %2(p0) :: (volatile store (s16) into %ir.addr)
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(i64), %2(p0) :: (volatile store (i16) into %ir.addr)
$w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
index 5953e5773bfa3..267157d04fa1f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
@@ -48,11 +48,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
- ; CHECK-NEXT: STRSui [[COPY1]], %stack.0.alloca, 0 :: (store (s32) into %ir.alloca)
+ ; CHECK-NEXT: STRSui [[COPY1]], %stack.0.alloca, 0 :: (store (i32) into %ir.alloca)
; CHECK-NEXT: RET_ReallyLR
- %0:fpr(s64) = COPY $d0
+ %0:fpr(i64) = COPY $d0
%1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
- G_STORE %0(s64), %1(p0) :: (store (s32) into %ir.alloca)
+ G_STORE %0(i64), %1(p0) :: (store (i32) into %ir.alloca)
RET_ReallyLR
...
@@ -78,11 +78,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
- ; CHECK-NEXT: STRHui [[COPY1]], %stack.0.alloca, 0 :: (store (s16) into %ir.alloca)
+ ; CHECK-NEXT: STRHui [[COPY1]], %stack.0.alloca, 0 :: (store (i16) into %ir.alloca)
; CHECK-NEXT: RET_ReallyLR
- %0:fpr(s64) = COPY $d0
+ %0:fpr(i64) = COPY $d0
%1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
- G_STORE %0(s64), %1(p0) :: (store (s16) into %ir.alloca)
+ G_STORE %0(i64), %1(p0) :: (store (i16) into %ir.alloca)
RET_ReallyLR
...
@@ -108,11 +108,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
- ; CHECK-NEXT: STRBui [[COPY1]], %stack.0.alloca, 0 :: (store (s8) into %ir.alloca)
+ ; CHECK-NEXT: STRBui [[COPY1]], %stack.0.alloca, 0 :: (store (i8) into %ir.alloca)
; CHECK-NEXT: RET_ReallyLR
- %0:fpr(s64) = COPY $d0
+ %0:fpr(i64) = COPY $d0
%1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
- G_STORE %0(s64), %1(p0) :: (store (s8) into %ir.alloca)
+ G_STORE %0(i64), %1(p0) :: (store (i8) into %ir.alloca)
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
index ade4322f5d87e..3cc6ef4d4cb0b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -65,10 +65,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: STRXui [[COPY1]], [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRXui [[COPY1]], [[COPY]], 0 :: (store (i64) into %ir.addr)
%0(p0) = COPY $x0
- %1(s64) = COPY $x1
- G_STORE %1, %0 :: (store (s64) into %ir.addr)
+ %1(i64) = COPY $x1
+ G_STORE %1, %0 :: (store (i64) into %ir.addr)
...
@@ -90,10 +90,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: STRWui [[COPY1]], [[COPY]], 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRWui [[COPY1]], [[COPY]], 0 :: (store (i32) into %ir.addr)
%0(p0) = COPY $x0
- %1(s32) = COPY $w1
- G_STORE %1, %0 :: (store (s32) into %ir.addr)
+ %1(i32) = COPY $w1
+ G_STORE %1, %0 :: (store (i32) into %ir.addr)
...
@@ -115,11 +115,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 0 :: (store (s16) into %ir.addr)
+ ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 0 :: (store (i16) into %ir.addr)
%0(p0) = COPY $x0
- %2:gpr(s32) = COPY $w1
- %1(s16) = G_TRUNC %2
- G_STORE %1, %0 :: (store (s16) into %ir.addr)
+ %2:gpr(i32) = COPY $w1
+ %1(i16) = G_TRUNC %2
+ G_STORE %1, %0 :: (store (i16) into %ir.addr)
...
@@ -141,11 +141,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: STRBBui [[COPY1]], [[COPY]], 0 :: (store (s8) into %ir.addr)
+ ; CHECK-NEXT: STRBBui [[COPY1]], [[COPY]], 0 :: (store (i8) into %ir.addr)
%0(p0) = COPY $x0
- %2:gpr(s32) = COPY $w1
- %1(s8) = G_TRUNC %2
- G_STORE %1, %0 :: (store (s8) into %ir.addr)
+ %2:gpr(i32) = COPY $w1
+ %1(i8) = G_TRUNC %2
+ G_STORE %1, %0 :: (store (i8) into %ir.addr)
...
@@ -166,10 +166,10 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (i64) into %ir.addr)
%0(p0) = COPY $x0
- %1(s64) = G_CONSTANT i64 0
- G_STORE %1, %0 :: (store (s64) into %ir.addr)
+ %1(i64) = G_CONSTANT i64 0
+ G_STORE %1, %0 :: (store (i64) into %ir.addr)
...
@@ -190,10 +190,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRWui $wzr, [[COPY]], 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRWui $wzr, [[COPY]], 0 :: (store (i32) into %ir.addr)
%0(p0) = COPY $x0
- %1(s32) = G_CONSTANT i32 0
- G_STORE %1, %0 :: (store (s32) into %ir.addr)
+ %1(i32) = G_CONSTANT i32 0
+ G_STORE %1, %0 :: (store (i32) into %ir.addr)
...
@@ -208,10 +208,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRHHui $wzr, [[COPY]], 0 :: (store (s16))
+ ; CHECK-NEXT: STRHHui $wzr, [[COPY]], 0 :: (store (i16))
%0:gpr(p0) = COPY $x0
- %1:gpr(s16) = G_CONSTANT i16 0
- G_STORE %1(s16), %0(p0) :: (store (s16))
+ %1:gpr(i16) = G_CONSTANT i16 0
+ G_STORE %1(i16), %0(p0) :: (store (i16))
...
@@ -226,10 +226,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRBBui $wzr, [[COPY]], 0 :: (store (s8))
+ ; CHECK-NEXT: STRBBui $wzr, [[COPY]], 0 :: (store (i8))
%0:gpr(p0) = COPY $x0
- %1:gpr(s8) = G_CONSTANT i8 0
- G_STORE %1(s8), %0(p0) :: (store (s8))
+ %1:gpr(i8) = G_CONSTANT i8 0
+ G_STORE %1(i8), %0(p0) :: (store (i8))
...
---
@@ -243,11 +243,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (i64) into %ir.addr)
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s64) = G_ZEXT %1
- G_STORE %2, %0 :: (store (s64) into %ir.addr)
+ %1:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i64) = G_ZEXT %1
+ G_STORE %2, %0 :: (store (i64) into %ir.addr)
...
---
@@ -297,12 +297,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: STRXui [[COPY1]], [[COPY]], 16 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRXui [[COPY1]], [[COPY]], 16 :: (store (i64) into %ir.addr)
%0(p0) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_CONSTANT i64 128
+ %1(i64) = COPY $x1
+ %2(i64) = G_CONSTANT i64 128
%3(p0) = G_PTR_ADD %0, %2
- G_STORE %1, %3 :: (store (s64) into %ir.addr)
+ G_STORE %1, %3 :: (store (i64) into %ir.addr)
...
---
@@ -325,12 +325,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: STRWui [[COPY1]], [[COPY]], 128 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRWui [[COPY1]], [[COPY]], 128 :: (store (i32) into %ir.addr)
%0(p0) = COPY $x0
- %1(s32) = COPY $w1
- %2(s64) = G_CONSTANT i64 512
+ %1(i32) = COPY $w1
+ %2(i64) = G_CONSTANT i64 512
%3(p0) = G_PTR_ADD %0, %2
- G_STORE %1, %3 :: (store (s32) into %ir.addr)
+ G_STORE %1, %3 :: (store (i32) into %ir.addr)
...
---
@@ -353,13 +353,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 32 :: (store (s16) into %ir.addr)
+ ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 32 :: (store (i16) into %ir.addr)
%0(p0) = COPY $x0
- %4:gpr(s32) = COPY $w1
- %1(s16) = G_TRUNC %4
- %2(s64) = G_CONSTANT i64 64
+ %4:gpr(i32) = COPY $w1
+ %1(i16) = G_TRUNC %4
+ %2(i64) = G_CONSTANT i64 64
%3(p0) = G_PTR_ADD %0, %2
- G_STORE %1, %3 :: (store (s16) into %ir.addr)
+ G_STORE %1, %3 :: (store (i16) into %ir.addr)
...
---
@@ -382,13 +382,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: STRBBui [[COPY1]], [[COPY]], 1 :: (store (s8) into %ir.addr)
+ ; CHECK-NEXT: STRBBui [[COPY1]], [[COPY]], 1 :: (store (i8) into %ir.addr)
%0(p0) = COPY $x0
- %4:gpr(s32) = COPY $w1
- %1(s8) = G_TRUNC %4
- %2(s64) = G_CONSTANT i64 1
+ %4:gpr(i32) = COPY $w1
+ %1(i8) = G_TRUNC %4
+ %2(i64) = G_CONSTANT i64 1
%3(p0) = G_PTR_ADD %0, %2
- G_STORE %1, %3 :: (store (s8) into %ir.addr)
+ G_STORE %1, %3 :: (store (i8) into %ir.addr)
...
---
@@ -409,10 +409,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (i64) into %ir.addr)
%0(p0) = COPY $x0
- %1(s64) = COPY $d1
- G_STORE %1, %0 :: (store (s64) into %ir.addr)
+ %1(i64) = COPY $d1
+ G_STORE %1, %0 :: (store (i64) into %ir.addr)
...
@@ -434,10 +434,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK-NEXT: STRSui [[COPY1]], [[COPY]], 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRSui [[COPY1]], [[COPY]], 0 :: (store (i32) into %ir.addr)
%0(p0) = COPY $x0
- %1(s32) = COPY $s1
- G_STORE %1, %0 :: (store (s32) into %ir.addr)
+ %1(i32) = COPY $s1
+ G_STORE %1, %0 :: (store (i32) into %ir.addr)
...
@@ -461,12 +461,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 1 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 1 :: (store (i64) into %ir.addr)
%0(p0) = COPY $x0
- %1(s64) = COPY $d1
- %2(s64) = G_CONSTANT i64 8
+ %1(i64) = COPY $d1
+ %2(i64) = G_CONSTANT i64 8
%3(p0) = G_PTR_ADD %0, %2
- G_STORE %1, %3 :: (store (s64) into %ir.addr)
+ G_STORE %1, %3 :: (store (i64) into %ir.addr)
...
---
@@ -489,12 +489,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK-NEXT: STRSui [[COPY1]], [[COPY]], 2 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRSui [[COPY1]], [[COPY]], 2 :: (store (i32) into %ir.addr)
%0(p0) = COPY $x0
- %1(s32) = COPY $s1
- %2(s64) = G_CONSTANT i64 8
+ %1(i32) = COPY $s1
+ %2(i64) = G_CONSTANT i64 8
%3(p0) = G_PTR_ADD %0, %2
- G_STORE %1, %3 :: (store (s32) into %ir.addr)
+ G_STORE %1, %3 :: (store (i32) into %ir.addr)
...
---
name: store_v2s32
@@ -514,10 +514,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (<2 x s32>) into %ir.addr)
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (<2 x i32>) into %ir.addr)
%0(p0) = COPY $x0
- %1(<2 x s32>) = COPY $d1
- G_STORE %1, %0 :: (store (<2 x s32>) into %ir.addr)
+ %1(<2 x i32>) = COPY $d1
+ G_STORE %1, %0 :: (store (<2 x i32>) into %ir.addr)
...
---
@@ -537,10 +537,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
- ; CHECK-NEXT: STRQui [[COPY1]], [[COPY]], 0 :: (store (<2 x s64>) into %ir.addr, align 8)
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY]], 0 :: (store (<2 x i64>) into %ir.addr, align 8)
%0(p0) = COPY $x0
- %1(<2 x s64>) = COPY $q1
- G_STORE %1, %0 :: (store (<2 x s64>) into %ir.addr, align 8)
+ %1(<2 x i64>) = COPY $q1
+ G_STORE %1, %0 :: (store (<2 x i64>) into %ir.addr, align 8)
...
---
@@ -562,11 +562,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRDui [[COPY]], [[COPY1]], 0 :: (store (<4 x s16>) into %ir.ptr)
+ ; CHECK-NEXT: STRDui [[COPY]], [[COPY1]], 0 :: (store (<4 x i16>) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
- %0:fpr(<4 x s16>) = COPY $d0
+ %0:fpr(<4 x i16>) = COPY $d0
%1:gpr(p0) = COPY $x0
- G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>) into %ir.ptr)
+ G_STORE %0(<4 x i16>), %1(p0) :: (store (<4 x i16>) into %ir.ptr)
RET_ReallyLR
...
@@ -589,11 +589,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<4 x s32>) into %ir.ptr)
+ ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<4 x i32>) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
- %0:fpr(<4 x s32>) = COPY $q0
+ %0:fpr(<4 x i32>) = COPY $q0
%1:gpr(p0) = COPY $x0
- G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.ptr)
+ G_STORE %0(<4 x i32>), %1(p0) :: (store (<4 x i32>) into %ir.ptr)
RET_ReallyLR
...
@@ -616,11 +616,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<8 x s16>) into %ir.ptr)
+ ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<8 x i16>) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
- %0:fpr(<8 x s16>) = COPY $q0
+ %0:fpr(<8 x i16>) = COPY $q0
%1:gpr(p0) = COPY $x0
- G_STORE %0(<8 x s16>), %1(p0) :: (store (<8 x s16>) into %ir.ptr)
+ G_STORE %0(<8 x i16>), %1(p0) :: (store (<8 x i16>) into %ir.ptr)
RET_ReallyLR
...
@@ -643,11 +643,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<16 x s8>) into %ir.ptr)
+ ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<16 x i8>) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
- %0:fpr(<16 x s8>) = COPY $q0
+ %0:fpr(<16 x i8>) = COPY $q0
%1:gpr(p0) = COPY $x0
- G_STORE %0(<16 x s8>), %1(p0) :: (store (<16 x s8>) into %ir.ptr)
+ G_STORE %0(<16 x i8>), %1(p0) :: (store (<16 x i8>) into %ir.ptr)
RET_ReallyLR
...
@@ -728,36 +728,36 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: %val32:gpr32 = COPY $w1
; CHECK-NEXT: %val64:gpr64 = COPY $x2
- ; CHECK-NEXT: STRBBui %val32, [[COPY]], 0 :: (store (s8))
- ; CHECK-NEXT: STRBBui %val32, [[COPY]], 43 :: (store (s8))
- ; CHECK-NEXT: STRHHui %val32, [[COPY]], 0 :: (store (s16))
- ; CHECK-NEXT: STURHHi %val32, [[COPY]], 43 :: (store (s16))
+ ; CHECK-NEXT: STRBBui %val32, [[COPY]], 0 :: (store (i8))
+ ; CHECK-NEXT: STRBBui %val32, [[COPY]], 43 :: (store (i8))
+ ; CHECK-NEXT: STRHHui %val32, [[COPY]], 0 :: (store (i16))
+ ; CHECK-NEXT: STURHHi %val32, [[COPY]], 43 :: (store (i16))
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 0 :: (store (s16))
+ ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 0 :: (store (i16))
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK-NEXT: STURHHi [[COPY2]], [[COPY]], 43 :: (store (s16))
+ ; CHECK-NEXT: STURHHi [[COPY2]], [[COPY]], 43 :: (store (i16))
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 0 :: (store (s32))
+ ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 0 :: (store (i32))
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK-NEXT: STURWi [[COPY4]], [[COPY]], 43 :: (store (s32))
+ ; CHECK-NEXT: STURWi [[COPY4]], [[COPY]], 43 :: (store (i32))
%0:gpr(p0) = COPY $x0
- %val32:gpr(s32) = COPY $w1
- %val64:gpr(s64) = COPY $x2
- G_STORE %val32, %0 :: (store (s8))
+ %val32:gpr(i32) = COPY $w1
+ %val64:gpr(i64) = COPY $x2
+ G_STORE %val32, %0 :: (store (i8))
; unscaled offset:
- %cst:gpr(s64) = G_CONSTANT i64 43
+ %cst:gpr(i64) = G_CONSTANT i64 43
%newptr:gpr(p0) = G_PTR_ADD %0, %cst
- G_STORE %val32, %newptr :: (store (s8))
+ G_STORE %val32, %newptr :: (store (i8))
- G_STORE %val32, %0 :: (store (s16))
+ G_STORE %val32, %0 :: (store (i16))
; unscaled offset:
- G_STORE %val32, %newptr :: (store (s16))
+ G_STORE %val32, %newptr :: (store (i16))
- G_STORE %val64, %0 :: (store (s16))
+ G_STORE %val64, %0 :: (store (i16))
; unscaled offset:
- G_STORE %val64, %newptr :: (store (s16))
+ G_STORE %val64, %newptr :: (store (i16))
- G_STORE %val64, %0 :: (store (s32))
+ G_STORE %val64, %0 :: (store (i32))
; unscaled offset:
- G_STORE %val64, %newptr :: (store (s32))
+ G_STORE %val64, %newptr :: (store (i32))
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
index 3cc916e020095..f293c72b763d8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
@@ -26,7 +26,7 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
- ; CHECK-NEXT: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (i8) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:gpr(i32) = COPY $w1
@@ -34,7 +34,7 @@ body: |
%6:gpr(i64) = G_CONSTANT i64 255
%7:gpr(i64) = G_ANYEXT %3(i32)
%4:gpr(i64) = G_AND %7, %6
- %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (s8) into %ir.addr)
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (i8) into %ir.addr)
$w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
@@ -58,7 +58,7 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
- ; CHECK-NEXT: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store (i16) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:gpr(i32) = COPY $w1
@@ -66,7 +66,7 @@ body: |
%6:gpr(i64) = G_CONSTANT i64 65535
%7:gpr(i64) = G_ANYEXT %3(i32)
%4:gpr(i64) = G_AND %7, %6
- %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (s16) into %ir.addr)
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (i16) into %ir.addr)
$w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
@@ -87,13 +87,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
- ; CHECK-NEXT: early-clobber %3:gpr32 = STXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %3:gpr32 = STXRW [[COPY]], [[COPY1]] :: (volatile store (i32) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
%3:gpr(i64) = G_ZEXT %1(i32)
- %4:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(i64), %2(p0) :: (volatile store (s32) into %ir.addr)
+ %4:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(i64), %2(p0) :: (volatile store (i32) into %ir.addr)
$w0 = COPY %4(i32)
RET_ReallyLR implicit $w0
@@ -114,12 +114,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
- ; CHECK-NEXT: early-clobber %2:gpr32 = STXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
+ ; CHECK-NEXT: early-clobber %2:gpr32 = STXRX [[COPY]], [[COPY1]] :: (volatile store (i64) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(i64) = COPY $x1
%2:gpr(p0) = COPY $x2
- %3:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(i64), %2(p0) :: (volatile store (s64) into %ir.addr)
+ %3:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(i64), %2(p0) :: (volatile store (i64) into %ir.addr)
$w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
index 67262c27e2059..c13d607a4bcdd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
@@ -27,9 +27,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s64), %zero
+ %copy:gpr(i64) = COPY $x0
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %cmp:gpr(i32) = G_ICMP intpred(slt), %copy(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -56,9 +56,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %zero:gpr(s32) = G_CONSTANT i32 0
- %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %zero
+ %copy:gpr(i32) = COPY $w0
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %cmp:gpr(i32) = G_ICMP intpred(slt), %copy(i32), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -85,9 +85,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s64), %zero
+ %copy:gpr(i64) = COPY $x0
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %cmp:gpr(i32) = G_ICMP intpred(sge), %copy(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -114,9 +114,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %zero:gpr(s32) = G_CONSTANT i32 0
- %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s32), %zero
+ %copy:gpr(i32) = COPY $w0
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %cmp:gpr(i32) = G_ICMP intpred(sge), %copy(i32), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -144,9 +144,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %one:gpr(s32) = G_CONSTANT i32 1
- %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %one
+ %copy:gpr(i32) = COPY $w0
+ %one:gpr(i32) = G_CONSTANT i32 1
+ %cmp:gpr(i32) = G_ICMP intpred(slt), %copy(i32), %one
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -174,12 +174,12 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
- %c:gpr(s64) = G_CONSTANT i64 8
- %and:gpr(s64) = G_AND %copy, %bit
- %cmp:gpr(s32) = G_ICMP intpred(slt), %and(s64), %zero
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %c:gpr(i64) = G_CONSTANT i64 8
+ %and:gpr(i64) = G_AND %copy, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(slt), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -208,9 +208,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %cmp:gpr(s32) = G_ICMP intpred(slt), %zero, %copy(s64)
+ %copy:gpr(i64) = COPY $x0
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %cmp:gpr(i32) = G_ICMP intpred(slt), %zero, %copy(i64)
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
index 816eaf53e0d89..44395c0da7804 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
@@ -23,10 +23,10 @@ body: |
; CHECK-NEXT: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[TRN1v2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = G_TRN1 %0, %1
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<2 x i32>) = G_TRN1 %0, %1
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -47,10 +47,10 @@ body: |
; CHECK-NEXT: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN1v2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = G_TRN1 %0, %1
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %2:fpr(<2 x i64>) = G_TRN1 %0, %1
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -71,10 +71,10 @@ body: |
; CHECK-NEXT: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[TRN1v4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_TRN1 %0, %1
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_TRN1 %0, %1
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -95,10 +95,10 @@ body: |
; CHECK-NEXT: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN1v4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_TRN1 %0, %1
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_TRN1 %0, %1
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -119,10 +119,10 @@ body: |
; CHECK-NEXT: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[TRN1v8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %2:fpr(<8 x s8>) = G_TRN1 %0, %1
- $d0 = COPY %2(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %2:fpr(<8 x i8>) = G_TRN1 %0, %1
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -143,10 +143,10 @@ body: |
; CHECK-NEXT: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN1v8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = G_TRN1 %0, %1
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = G_TRN1 %0, %1
+ $q0 = COPY %2(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -167,10 +167,10 @@ body: |
; CHECK-NEXT: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN1v16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = G_TRN1 %0, %1
- $q0 = COPY %2(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = G_TRN1 %0, %1
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -191,10 +191,10 @@ body: |
; CHECK-NEXT: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[TRN2v2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = G_TRN2 %0, %1
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<2 x i32>) = G_TRN2 %0, %1
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -215,10 +215,10 @@ body: |
; CHECK-NEXT: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN2v2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = G_TRN2 %0, %1
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %2:fpr(<2 x i64>) = G_TRN2 %0, %1
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -239,10 +239,10 @@ body: |
; CHECK-NEXT: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[TRN2v4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_TRN2 %0, %1
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_TRN2 %0, %1
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -263,10 +263,10 @@ body: |
; CHECK-NEXT: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN2v4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_TRN2 %0, %1
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_TRN2 %0, %1
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -287,10 +287,10 @@ body: |
; CHECK-NEXT: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[TRN2v8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %2:fpr(<8 x s8>) = G_TRN2 %0, %1
- $d0 = COPY %2(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %2:fpr(<8 x i8>) = G_TRN2 %0, %1
+ $d0 = COPY %2(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -311,10 +311,10 @@ body: |
; CHECK-NEXT: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN2v8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = G_TRN2 %0, %1
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = G_TRN2 %0, %1
+ $q0 = COPY %2(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -335,8 +335,8 @@ body: |
; CHECK-NEXT: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[TRN2v16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = G_TRN2 %0, %1
- $q0 = COPY %2(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = G_TRN2 %0, %1
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
index c0b936332ca88..43b92865f0572 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -104,7 +104,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: $x0 = COPY [[COPY1]]
- %0(s128) = COPY $q0
+ %0(i128) = COPY $q0
%1(i64) = G_TRUNC %0
$x0 = COPY %1(i64)
...
@@ -127,7 +127,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %0(s128) = COPY $q0
+ %0(i128) = COPY $q0
%1(i32) = G_TRUNC %0
$w0 = COPY %1(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir
index 33c56c4a6d044..287b82f9c8c5c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir
@@ -27,7 +27,7 @@ body: |
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
- ; CHECK-NEXT: STLRW [[COPY2]], [[COPY]] :: (store release (s32))
+ ; CHECK-NEXT: STLRW [[COPY2]], [[COPY]] :: (store release (i32))
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: RET_ReallyLR
@@ -35,13 +35,13 @@ body: |
liveins: $w1, $x0
%0:gpr(p0) = COPY $x0
- %3:gpr(s32) = COPY $w1
+ %3:gpr(i32) = COPY $w1
G_BRCOND %3, %bb.3
G_BR %bb.2
bb.2:
- %8:gpr(s64) = G_CONSTANT i64 4
- G_STORE %8(s64), %0(p0) :: (store release (s32))
+ %8:gpr(i64) = G_CONSTANT i64 4
+ G_STORE %8(i64), %0(p0) :: (store release (i32))
bb.3:
RET_ReallyLR
@@ -73,7 +73,7 @@ body: |
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
- ; CHECK-NEXT: STLRH [[COPY2]], [[COPY]] :: (store release (s16))
+ ; CHECK-NEXT: STLRH [[COPY2]], [[COPY]] :: (store release (i16))
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: RET_ReallyLR
@@ -81,13 +81,13 @@ body: |
liveins: $w1, $x0
%0:gpr(p0) = COPY $x0
- %3:gpr(s32) = COPY $w1
+ %3:gpr(i32) = COPY $w1
G_BRCOND %3, %bb.3
G_BR %bb.2
bb.2:
- %8:gpr(s64) = G_CONSTANT i64 4
- G_STORE %8(s64), %0(p0) :: (store release (s16))
+ %8:gpr(i64) = G_CONSTANT i64 4
+ G_STORE %8(i64), %0(p0) :: (store release (i16))
bb.3:
RET_ReallyLR
@@ -119,7 +119,7 @@ body: |
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
- ; CHECK-NEXT: STLRB [[COPY2]], [[COPY]] :: (store release (s8))
+ ; CHECK-NEXT: STLRB [[COPY2]], [[COPY]] :: (store release (i8))
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: RET_ReallyLR
@@ -127,13 +127,13 @@ body: |
liveins: $w1, $x0
%0:gpr(p0) = COPY $x0
- %3:gpr(s32) = COPY $w1
+ %3:gpr(i32) = COPY $w1
G_BRCOND %3, %bb.3
G_BR %bb.2
bb.2:
- %8:gpr(s64) = G_CONSTANT i64 4
- G_STORE %8(s64), %0(p0) :: (store release (s8))
+ %8:gpr(i64) = G_CONSTANT i64 4
+ G_STORE %8(i64), %0(p0) :: (store release (i8))
bb.3:
RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
index f6f9964e6babd..7cd67b2e338f6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
@@ -23,12 +23,12 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADCSXr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s64), %4:gpr(s32) = G_UADDE %0, %1, %2
- $x0 = COPY %3(s64)
- $w1 = COPY %4(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i64), %4:gpr(i32) = G_UADDE %0, %1, %2
+ $x0 = COPY %3(i64)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $x0, implicit $w1
...
...
@@ -54,12 +54,12 @@ body: |
; CHECK-NEXT: $w0 = COPY [[ADCSWr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32), %4:gpr(s32) = G_UADDE %0, %1, %2
- $w0 = COPY %3(s32)
- $w1 = COPY %4(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32), %4:gpr(i32) = G_UADDE %0, %1, %2
+ $w0 = COPY %3(i32)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $w0, implicit $w1
...
...
@@ -85,14 +85,14 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
; CHECK-NEXT: $x1 = COPY [[ADCSXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %8:gpr(s64), %12:gpr(s32) = G_UADDO %0, %2
- %9:gpr(s64), %13:gpr(s32) = G_UADDE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %8:gpr(i64), %12:gpr(i32) = G_UADDO %0, %2
+ %9:gpr(i64), %13:gpr(i32) = G_UADDE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -120,15 +120,15 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADCSXr]]
; CHECK-NEXT: $x1 = COPY [[ADCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %6:gpr(s32) = G_CONSTANT i32 1
- %8:gpr(s64), %12:gpr(s32) = G_UADDE %0, %2, %6
- %9:gpr(s64), %13:gpr(s32) = G_UADDE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %8:gpr(i64), %12:gpr(i32) = G_UADDE %0, %2, %6
+ %9:gpr(i64), %13:gpr(i32) = G_UADDE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -160,19 +160,19 @@ body: |
; CHECK-NEXT: $x1 = COPY [[ADCSXr]]
; CHECK-NEXT: $x2 = COPY [[ADCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %4:gpr(s64) = COPY $x4
- %5:gpr(s64) = COPY $x5
- %6:gpr(s64) = COPY $x6
- %7:gpr(s64), %11:gpr(s32) = G_UADDO %0, %4
- %8:gpr(s64), %12:gpr(s32) = G_UADDE %1, %5, %11
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %4:gpr(i64) = COPY $x4
+ %5:gpr(i64) = COPY $x5
+ %6:gpr(i64) = COPY $x6
+ %7:gpr(i64), %11:gpr(i32) = G_UADDO %0, %4
+ %8:gpr(i64), %12:gpr(i32) = G_UADDE %1, %5, %11
; carry-in is not produced by previous instruction
- %9:gpr(s64), %13:gpr(s32) = G_UADDE %2, %6, %11
- $x0 = COPY %7(s64)
- $x1 = COPY %8(s64)
- $x2 = COPY %9(s64)
+ %9:gpr(i64), %13:gpr(i32) = G_UADDE %2, %6, %11
+ $x0 = COPY %7(i64)
+ $x1 = COPY %8(i64)
+ $x2 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
@@ -197,12 +197,12 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %4:gpr(s64), %5:gpr(s32) = G_UADDO %0, %2
- %6:gpr(s64), %7:gpr(s32) = G_UADDE %1, %3, %5
- $w0 = COPY %7(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_UADDO %0, %2
+ %6:gpr(i64), %7:gpr(i32) = G_UADDE %1, %3, %5
+ $w0 = COPY %7(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
index 9dcd085fc4fd5..d829f7092b07b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
@@ -22,9 +22,9 @@ body: |
; CHECK-NEXT: $w0 = COPY [[ADDSWrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %3:gpr(s32), %4:gpr(s32) = G_UADDO %0, %1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %3:gpr(i32), %4:gpr(i32) = G_UADDO %0, %1
$w0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $w0, implicit $w1
@@ -50,9 +50,9 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %3:gpr(s64), %4:gpr(s32) = G_UADDO %0, %1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %3:gpr(i64), %4:gpr(i32) = G_UADDO %0, %1
$x0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $x0, implicit $w1
@@ -75,10 +75,10 @@ body: |
; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 16
- %add:gpr(s32), %overflow:gpr(s32) = G_UADDO %copy, %constant
- $w0 = COPY %add(s32)
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %add:gpr(i32), %overflow:gpr(i32) = G_UADDO %copy, %constant
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -100,12 +100,12 @@ body: |
; CHECK-NEXT: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy1:gpr(s32) = COPY $w0
- %copy2:gpr(s32) = COPY $w1
- %constant:gpr(s32) = G_CONSTANT i32 16
- %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
- %add:gpr(s32), %overflow:gpr(s32) = G_UADDO %copy1, %shift
- $w0 = COPY %add(s32)
+ %copy1:gpr(i32) = COPY $w0
+ %copy2:gpr(i32) = COPY $w1
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %shift:gpr(i32) = G_SHL %copy2(i32), %constant(i32)
+ %add:gpr(i32), %overflow:gpr(i32) = G_UADDO %copy1, %shift
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -126,10 +126,10 @@ body: |
; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 -16
- %add:gpr(s32), %overflow:gpr(s32) = G_UADDO %copy, %constant
- $w0 = COPY %add(s32)
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 -16
+ %add:gpr(i32), %overflow:gpr(i32) = G_UADDO %copy, %constant
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -151,11 +151,11 @@ body: |
; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
; CHECK-NEXT: $x0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %reg1:gpr(s32) = COPY $w0
- %ext:gpr(s64) = G_ZEXT %reg1(s32)
- %cst:gpr(s64) = G_CONSTANT i64 2
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
- %add:gpr(s64), %flags:gpr(s32) = G_UADDO %reg0, %shift
- $x0 = COPY %add(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %reg1:gpr(i32) = COPY $w0
+ %ext:gpr(i64) = G_ZEXT %reg1(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 2
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
+ %add:gpr(i64), %flags:gpr(i32) = G_UADDO %reg0, %shift
+ $x0 = COPY %add(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ubfx.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ubfx.mir
index c15b668c5aa76..8a10c8dbbdc0a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ubfx.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ubfx.mir
@@ -16,10 +16,10 @@ body: |
; CHECK: %ubfx:gpr32 = UBFMWri %copy, 0, 9
; CHECK: $w0 = COPY %ubfx
; CHECK: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %cst1:gpr(s32) = G_CONSTANT i32 0
- %cst2:gpr(s32) = G_CONSTANT i32 10
- %ubfx:gpr(s32) = G_UBFX %copy, %cst1, %cst2
+ %copy:gpr(i32) = COPY $w0
+ %cst1:gpr(i32) = G_CONSTANT i32 0
+ %cst2:gpr(i32) = G_CONSTANT i32 10
+ %ubfx:gpr(i32) = G_UBFX %copy, %cst1, %cst2
$w0 = COPY %ubfx
RET_ReallyLR implicit $w0
@@ -38,10 +38,10 @@ body: |
; CHECK: %ubfx:gpr64 = UBFMXri %copy, 0, 9
; CHECK: $x0 = COPY %ubfx
; CHECK: RET_ReallyLR implicit $x0
- %copy:gpr(s64) = COPY $x0
- %cst1:gpr(s64) = G_CONSTANT i64 0
- %cst2:gpr(s64) = G_CONSTANT i64 10
- %ubfx:gpr(s64) = G_UBFX %copy, %cst1, %cst2
+ %copy:gpr(i64) = COPY $x0
+ %cst1:gpr(i64) = G_CONSTANT i64 0
+ %cst2:gpr(i64) = G_CONSTANT i64 10
+ %ubfx:gpr(i64) = G_UBFX %copy, %cst1, %cst2
$x0 = COPY %ubfx
RET_ReallyLR implicit $x0
@@ -63,10 +63,10 @@ body: |
; CHECK: %ubfx:gpr32 = UBFMWri %copy, 31, 31
; CHECK: $w0 = COPY %ubfx
; CHECK: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %cst1:gpr(s32) = G_CONSTANT i32 31
- %cst2:gpr(s32) = G_CONSTANT i32 1
- %ubfx:gpr(s32) = G_UBFX %copy, %cst1, %cst2
+ %copy:gpr(i32) = COPY $w0
+ %cst1:gpr(i32) = G_CONSTANT i32 31
+ %cst2:gpr(i32) = G_CONSTANT i32 1
+ %ubfx:gpr(i32) = G_UBFX %copy, %cst1, %cst2
$w0 = COPY %ubfx
RET_ReallyLR implicit $w0
---
@@ -83,10 +83,10 @@ body: |
; CHECK: %ubfx:gpr32 = UBFMWri %copy, 10, 14
; CHECK: $w0 = COPY %ubfx
; CHECK: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %cst1:gpr(s32) = G_CONSTANT i32 10
- %cst2:gpr(s32) = G_CONSTANT i32 5
- %ubfx:gpr(s32) = G_UBFX %copy, %cst1, %cst2
+ %copy:gpr(i32) = COPY $w0
+ %cst1:gpr(i32) = G_CONSTANT i32 10
+ %cst2:gpr(i32) = G_CONSTANT i32 5
+ %ubfx:gpr(i32) = G_UBFX %copy, %cst1, %cst2
$w0 = COPY %ubfx
RET_ReallyLR implicit $w0
@@ -105,9 +105,9 @@ body: |
; CHECK: %ubfx:gpr64 = UBFMXri %copy, 10, 14
; CHECK: $x0 = COPY %ubfx
; CHECK: RET_ReallyLR implicit $x0
- %copy:gpr(s64) = COPY $x0
- %cst1:gpr(s64) = G_CONSTANT i64 10
- %cst2:gpr(s64) = G_CONSTANT i64 5
- %ubfx:gpr(s64) = G_UBFX %copy, %cst1, %cst2
+ %copy:gpr(i64) = COPY $x0
+ %cst1:gpr(i64) = G_CONSTANT i64 10
+ %cst2:gpr(i64) = G_CONSTANT i64 5
+ %ubfx:gpr(i64) = G_UBFX %copy, %cst1, %cst2
$x0 = COPY %ubfx
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
index 8a9f2cac79e9f..da58fa4815d94 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
@@ -30,13 +30,13 @@ body: |
; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
+ %0:fpr(<2 x i64>) = COPY $q0
; Since 2 * 64 = 128, we can just directly copy.
- %2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
+ %2:fpr(i64), %3:fpr(i64) = G_UNMERGE_VALUES %0(<2 x i64>)
- %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
- $q0 = COPY %1(<2 x s64>)
+ %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(i64), %3(i64)
+ $q0 = COPY %1(<2 x i64>)
RET_ReallyLR implicit $q0
...
---
@@ -76,13 +76,13 @@ body: |
; CHECK-NEXT: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi32lane2]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
+ %0:fpr(<4 x i32>) = COPY $q0
; Since 4 * 32 = 128, we can just directly copy.
- %2:fpr(s32), %3:fpr(s32), %4:fpr(s32), %5:fpr(s32) = G_UNMERGE_VALUES %0(<4 x s32>)
+ %2:fpr(i32), %3:fpr(i32), %4:fpr(i32), %5:fpr(i32) = G_UNMERGE_VALUES %0(<4 x i32>)
- %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %4(s32), %5(s32)
- $q0 = COPY %1(<4 x s32>)
+ %1:fpr(<4 x i32>) = G_BUILD_VECTOR %2(i32), %3(i32), %4(i32), %5(i32)
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
---
@@ -112,15 +112,15 @@ body: |
; CHECK-NEXT: $h0 = COPY [[COPY1]]
; CHECK-NEXT: $h1 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0, implicit $h1
- %0:fpr(<2 x s16>) = COPY $s0
+ %0:fpr(<2 x i16>) = COPY $s0
; Since 2 * 16 != 128, we need to widen using implicit defs.
; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
; expects a lane > 0.
- %2:fpr(s16), %3:fpr(s16) = G_UNMERGE_VALUES %0(<2 x s16>)
+ %2:fpr(i16), %3:fpr(i16) = G_UNMERGE_VALUES %0(<2 x i16>)
- $h0 = COPY %2(s16)
- $h1 = COPY %3(s16)
+ $h0 = COPY %2(i16)
+ $h1 = COPY %3(i16)
RET_ReallyLR implicit $h0, implicit $h1
...
@@ -168,15 +168,15 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
+ %0:fpr(<4 x i16>) = COPY $d0
; Since 4 * 16 != 128, we need to widen using implicit defs.
; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
; expects a lane > 0.
- %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
+ %2:fpr(i16), %3:fpr(i16), %4:fpr(i16), %5:fpr(i16) = G_UNMERGE_VALUES %0(<4 x i16>)
- %1:fpr(<4 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16), %5(s16)
- $d0 = COPY %1(<4 x s16>)
+ %1:fpr(<4 x i16>) = G_BUILD_VECTOR %2(i16), %3(i16), %4(i16), %5(i16)
+ $d0 = COPY %1(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -236,13 +236,13 @@ body: |
; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
+ %0:fpr(<8 x i16>) = COPY $q0
; Since 8 * 16 = 128, we can just directly copy.
- %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
+ %2:fpr(i16), %3:fpr(i16), %4:fpr(i16), %5:fpr(i16), %6:fpr(i16), %7:fpr(i16), %8:fpr(i16), %9:fpr(i16) = G_UNMERGE_VALUES %0(<8 x i16>)
- %1:fpr(<8 x s16>) = G_BUILD_VECTOR %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16)
- $q0 = COPY %1(<8 x s16>)
+ %1:fpr(<8 x i16>) = G_BUILD_VECTOR %2:fpr(i16), %3:fpr(i16), %4:fpr(i16), %5:fpr(i16), %6:fpr(i16), %7:fpr(i16), %8:fpr(i16), %9:fpr(i16)
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
---
@@ -289,8 +289,8 @@ body: |
; CHECK-NEXT: $b6 = COPY [[DUPi8_5]]
; CHECK-NEXT: $b7 = COPY [[DUPi8_6]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8) = G_UNMERGE_VALUES %0(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %2:fpr(i8), %3:fpr(i8), %4:fpr(i8), %5:fpr(i8), %6:fpr(i8), %7:fpr(i8), %8:fpr(i8), %9:fpr(i8) = G_UNMERGE_VALUES %0(<8 x i8>)
$b0 = COPY %2
$b1 = COPY %3
$b2 = COPY %4
@@ -379,11 +379,11 @@ body: |
; CHECK-NEXT: [[INSvi8lane14:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane13]], 15, [[INSERT_SUBREG15]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi8lane14]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8), %10:fpr(s8), %11:fpr(s8), %12:fpr(s8), %13:fpr(s8), %14:fpr(s8), %15:fpr(s8), %16:fpr(s8), %17:fpr(s8) = G_UNMERGE_VALUES %0(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %2:fpr(i8), %3:fpr(i8), %4:fpr(i8), %5:fpr(i8), %6:fpr(i8), %7:fpr(i8), %8:fpr(i8), %9:fpr(i8), %10:fpr(i8), %11:fpr(i8), %12:fpr(i8), %13:fpr(i8), %14:fpr(i8), %15:fpr(i8), %16:fpr(i8), %17:fpr(i8) = G_UNMERGE_VALUES %0(<16 x i8>)
- %1:fpr(<16 x s8>) = G_BUILD_VECTOR %2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8), %10:fpr(s8), %11:fpr(s8), %12:fpr(s8), %13:fpr(s8), %14:fpr(s8), %15:fpr(s8), %16:fpr(s8), %17:fpr(s8)
- $q0 = COPY %1(<16 x s8>)
+ %1:fpr(<16 x i8>) = G_BUILD_VECTOR %2:fpr(i8), %3:fpr(i8), %4:fpr(i8), %5:fpr(i8), %6:fpr(i8), %7:fpr(i8), %8:fpr(i8), %9:fpr(i8), %10:fpr(i8), %11:fpr(i8), %12:fpr(i8), %13:fpr(i8), %14:fpr(i8), %15:fpr(i8), %16:fpr(i8), %17:fpr(i8)
+ $q0 = COPY %1(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -404,10 +404,10 @@ body: |
; CHECK-NEXT: $d0 = COPY [[COPY1]]
; CHECK-NEXT: $d1 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<2 x s32>), %2:fpr(<2 x s32>) = G_UNMERGE_VALUES %0(<4 x s32>)
- $d0 = COPY %1(<2 x s32>)
- $d1 = COPY %2(<2 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<2 x i32>), %2:fpr(<2 x i32>) = G_UNMERGE_VALUES %0(<4 x i32>)
+ $d0 = COPY %1(<2 x i32>)
+ $d1 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
---
@@ -430,10 +430,10 @@ body: |
; CHECK-NEXT: $s0 = COPY [[COPY1]]
; CHECK-NEXT: $s1 = COPY [[DUPi32_]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<2 x s16>), %2:fpr(<2 x s16>) = G_UNMERGE_VALUES %0(<4 x s16>)
- $s0 = COPY %1(<2 x s16>)
- $s1 = COPY %2(<2 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<2 x i16>), %2:fpr(<2 x i16>) = G_UNMERGE_VALUES %0(<4 x i16>)
+ $s0 = COPY %1(<2 x i16>)
+ $s1 = COPY %2(<2 x i16>)
RET_ReallyLR implicit $s0
...
---
@@ -454,10 +454,10 @@ body: |
; CHECK-NEXT: $d0 = COPY [[COPY1]]
; CHECK-NEXT: $d1 = COPY [[DUPi64_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
- %0:fpr(s128) = COPY $q0
- %1:fpr(s64), %2:fpr(s64) = G_UNMERGE_VALUES %0(s128)
- $d0 = COPY %1(s64)
- $d1 = COPY %2(s64)
+ %0:fpr(i128) = COPY $q0
+ %1:fpr(i64), %2:fpr(i64) = G_UNMERGE_VALUES %0(i128)
+ $d0 = COPY %1(i64)
+ $d1 = COPY %2(i64)
RET_ReallyLR implicit $d0, implicit $d1
...
---
@@ -480,10 +480,10 @@ body: |
; CHECK-NEXT: $h0 = COPY [[COPY1]]
; CHECK-NEXT: $h1 = COPY [[DUPi16_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0, implicit $h1
- %0:fpr(s32) = COPY $s0
- %1:fpr(s16), %2:fpr(s16) = G_UNMERGE_VALUES %0(s32)
- $h0 = COPY %1(s16)
- $h1 = COPY %2(s16)
+ %0:fpr(i32) = COPY $s0
+ %1:fpr(i16), %2:fpr(i16) = G_UNMERGE_VALUES %0(i32)
+ $h0 = COPY %1(i16)
+ $h1 = COPY %2(i16)
RET_ReallyLR implicit $h0, implicit $h1
...
---
@@ -506,10 +506,10 @@ body: |
; CHECK-NEXT: $s0 = COPY [[COPY1]]
; CHECK-NEXT: $s1 = COPY [[DUPi32_]]
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1
- %0:fpr(s64) = COPY $d0
- %1:fpr(s32), %2:fpr(s32) = G_UNMERGE_VALUES %0(s64)
- $s0 = COPY %1(s32)
- $s1 = COPY %2(s32)
+ %0:fpr(i64) = COPY $d0
+ %1:fpr(i32), %2:fpr(i32) = G_UNMERGE_VALUES %0(i64)
+ $s0 = COPY %1(i32)
+ $s1 = COPY %2(i32)
RET_ReallyLR implicit $s0, implicit $s1
...
---
@@ -540,12 +540,12 @@ body: |
; CHECK-NEXT: $h2 = COPY [[DUPi16_1]]
; CHECK-NEXT: $h3 = COPY [[DUPi16_2]]
; CHECK-NEXT: RET_ReallyLR implicit $h0, implicit $h1, implicit $h2, implicit $h3
- %0:fpr(s64) = COPY $d0
- %1:fpr(s16), %2:fpr(s16), %3:fpr(s16), %4:fpr(s16) = G_UNMERGE_VALUES %0(s64)
- $h0 = COPY %1(s16)
- $h1 = COPY %2(s16)
- $h2 = COPY %3(s16)
- $h3 = COPY %4(s16)
+ %0:fpr(i64) = COPY $d0
+ %1:fpr(i16), %2:fpr(i16), %3:fpr(i16), %4:fpr(i16) = G_UNMERGE_VALUES %0(i64)
+ $h0 = COPY %1(i16)
+ $h1 = COPY %2(i16)
+ $h2 = COPY %3(i16)
+ $h3 = COPY %4(i16)
RET_ReallyLR implicit $h0, implicit $h1, implicit $h2, implicit $h3
...
---
@@ -576,11 +576,11 @@ body: |
; CHECK-NEXT: $b2 = COPY [[DUPi8_1]]
; CHECK-NEXT: $b3 = COPY [[DUPi8_2]]
; CHECK-NEXT: RET_ReallyLR implicit $b0, implicit $b1, implicit $b2, implicit $b3
- %0:fpr(s32) = COPY $s0
- %1:fpr(s8), %2:fpr(s8), %3:fpr(s8), %4:fpr(s8) = G_UNMERGE_VALUES %0(s32)
- $b0 = COPY %1(s8)
- $b1 = COPY %2(s8)
- $b2 = COPY %3(s8)
- $b3 = COPY %4(s8)
+ %0:fpr(i32) = COPY $s0
+ %1:fpr(i8), %2:fpr(i8), %3:fpr(i8), %4:fpr(i8) = G_UNMERGE_VALUES %0(i32)
+ $b0 = COPY %1(i8)
+ $b1 = COPY %2(i8)
+ $b2 = COPY %3(i8)
+ $b3 = COPY %4(i8)
RET_ReallyLR implicit $b0, implicit $b1, implicit $b2, implicit $b3
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir
index fa8799653a570..aa4f602ac09d7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir
@@ -23,12 +23,12 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SBCSXr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s64), %4:gpr(s32) = G_USUBE %0, %1, %2
- $x0 = COPY %3(s64)
- $w1 = COPY %4(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i64), %4:gpr(i32) = G_USUBE %0, %1, %2
+ $x0 = COPY %3(i64)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $x0, implicit $w1
...
...
@@ -54,12 +54,12 @@ body: |
; CHECK-NEXT: $w0 = COPY [[SBCSWr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32), %4:gpr(s32) = G_USUBE %0, %1, %2
- $w0 = COPY %3(s32)
- $w1 = COPY %4(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32), %4:gpr(i32) = G_USUBE %0, %1, %2
+ $w0 = COPY %3(i32)
+ $w1 = COPY %4(i32)
RET_ReallyLR implicit $w0, implicit $w1
...
...
@@ -85,14 +85,14 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
; CHECK-NEXT: $x1 = COPY [[SBCSXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %8:gpr(s64), %12:gpr(s32) = G_USUBO %0, %2
- %9:gpr(s64), %13:gpr(s32) = G_USUBE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %8:gpr(i64), %12:gpr(i32) = G_USUBO %0, %2
+ %9:gpr(i64), %13:gpr(i32) = G_USUBE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -120,15 +120,15 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SBCSXr]]
; CHECK-NEXT: $x1 = COPY [[SBCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %6:gpr(s32) = G_CONSTANT i32 1
- %8:gpr(s64), %12:gpr(s32) = G_USUBE %0, %2, %6
- %9:gpr(s64), %13:gpr(s32) = G_USUBE %1, %3, %12
- $x0 = COPY %8(s64)
- $x1 = COPY %9(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %8:gpr(i64), %12:gpr(i32) = G_USUBE %0, %2, %6
+ %9:gpr(i64), %13:gpr(i32) = G_USUBE %1, %3, %12
+ $x0 = COPY %8(i64)
+ $x1 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1
...
...
@@ -160,19 +160,19 @@ body: |
; CHECK-NEXT: $x1 = COPY [[SBCSXr]]
; CHECK-NEXT: $x2 = COPY [[SBCSXr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %4:gpr(s64) = COPY $x4
- %5:gpr(s64) = COPY $x5
- %6:gpr(s64) = COPY $x6
- %7:gpr(s64), %11:gpr(s32) = G_USUBO %0, %4
- %8:gpr(s64), %12:gpr(s32) = G_USUBE %1, %5, %11
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %4:gpr(i64) = COPY $x4
+ %5:gpr(i64) = COPY $x5
+ %6:gpr(i64) = COPY $x6
+ %7:gpr(i64), %11:gpr(i32) = G_USUBO %0, %4
+ %8:gpr(i64), %12:gpr(i32) = G_USUBE %1, %5, %11
; carry-in is not produced by previous instruction
- %9:gpr(s64), %13:gpr(s32) = G_USUBE %2, %6, %11
- $x0 = COPY %7(s64)
- $x1 = COPY %8(s64)
- $x2 = COPY %9(s64)
+ %9:gpr(i64), %13:gpr(i32) = G_USUBE %2, %6, %11
+ $x0 = COPY %7(i64)
+ $x1 = COPY %8(i64)
+ $x2 = COPY %9(i64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
@@ -197,12 +197,12 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = COPY $x2
- %3:gpr(s64) = COPY $x3
- %4:gpr(s64), %5:gpr(s32) = G_USUBO %0, %2
- %6:gpr(s64), %7:gpr(s32) = G_USUBE %1, %3, %5
- $w0 = COPY %7(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = COPY $x2
+ %3:gpr(i64) = COPY $x3
+ %4:gpr(i64), %5:gpr(i32) = G_USUBO %0, %2
+ %6:gpr(i64), %7:gpr(i32) = G_USUBE %1, %3, %5
+ $w0 = COPY %7(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
index a9295194779c8..dd3b9453ac6b8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
@@ -22,9 +22,9 @@ body: |
; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %3:gpr(s32), %4:gpr(s32) = G_USUBO %0, %1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %3:gpr(i32), %4:gpr(i32) = G_USUBO %0, %1
$w0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $w0, implicit $w1
@@ -50,9 +50,9 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %3:gpr(s64), %4:gpr(s32) = G_USUBO %0, %1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %3:gpr(i64), %4:gpr(i32) = G_USUBO %0, %1
$x0 = COPY %3
$w1 = COPY %4
RET_ReallyLR implicit $x0, implicit $w1
@@ -75,9 +75,9 @@ body: |
; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 16
- %add:gpr(s32), %overflow:gpr(s32) = G_USUBO %copy, %constant
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %add:gpr(i32), %overflow:gpr(i32) = G_USUBO %copy, %constant
$w0 = COPY %add
RET_ReallyLR implicit $w0
@@ -100,12 +100,12 @@ body: |
; CHECK-NEXT: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy1:gpr(s32) = COPY $w0
- %copy2:gpr(s32) = COPY $w1
- %constant:gpr(s32) = G_CONSTANT i32 16
- %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
- %add:gpr(s32), %overflow:gpr(s32) = G_USUBO %copy1, %shift
- $w0 = COPY %add(s32)
+ %copy1:gpr(i32) = COPY $w0
+ %copy2:gpr(i32) = COPY $w1
+ %constant:gpr(i32) = G_CONSTANT i32 16
+ %shift:gpr(i32) = G_SHL %copy2(i32), %constant(i32)
+ %add:gpr(i32), %overflow:gpr(i32) = G_USUBO %copy1, %shift
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -126,10 +126,10 @@ body: |
; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %constant:gpr(s32) = G_CONSTANT i32 -16
- %add:gpr(s32), %overflow:gpr(s32) = G_USUBO %copy, %constant
- $w0 = COPY %add(s32)
+ %copy:gpr(i32) = COPY $w0
+ %constant:gpr(i32) = G_CONSTANT i32 -16
+ %add:gpr(i32), %overflow:gpr(i32) = G_USUBO %copy, %constant
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -151,11 +151,11 @@ body: |
; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
; CHECK-NEXT: $x0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %reg1:gpr(s32) = COPY $w0
- %ext:gpr(s64) = G_ZEXT %reg1(s32)
- %cst:gpr(s64) = G_CONSTANT i64 2
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
- %add:gpr(s64), %flags:gpr(s32) = G_USUBO %reg0, %shift
- $x0 = COPY %add(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %reg1:gpr(i32) = COPY $w0
+ %ext:gpr(i64) = G_ZEXT %reg1(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 2
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
+ %add:gpr(i64), %flags:gpr(i32) = G_USUBO %reg0, %shift
+ $x0 = COPY %add(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir
index 83ca512889cc1..e5925852058e3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-uzp.mir
@@ -22,10 +22,10 @@ body: |
; CHECK-NEXT: [[UZP1v4i32_:%[0-9]+]]:fpr128 = UZP1v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[UZP1v4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_UZP1 %0, %1
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_UZP1 %0, %1
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -46,10 +46,10 @@ body: |
; CHECK-NEXT: [[UZP2v4i32_:%[0-9]+]]:fpr128 = UZP2v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[UZP2v4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_UZP2 %0, %1
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_UZP2 %0, %1
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
index 4ee74f3a952a1..8c5cd27e41ca3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
@@ -510,12 +510,12 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %13:gpr(i32) = G_CONSTANT i32 65535
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(i32), %13(i32)
%15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%7:fpr(<2 x i32>) = G_AND %15, %14
- %10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 65535
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%8:fpr(<2 x i32>) = G_AND %12, %11
%9:fpr(<2 x i32>) = G_ICMP intpred(eq), %7(<2 x i32>), %8
@@ -800,12 +800,12 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %13:gpr(i32) = G_CONSTANT i32 65535
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(i32), %13(i32)
%15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%7:fpr(<2 x i32>) = G_AND %15, %14
- %10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 65535
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%8:fpr(<2 x i32>) = G_AND %12, %11
%9:fpr(<2 x i32>) = G_ICMP intpred(ugt), %7(<2 x i32>), %8
@@ -1090,12 +1090,12 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %13:gpr(i32) = G_CONSTANT i32 65535
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(i32), %13(i32)
%15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%7:fpr(<2 x i32>) = G_AND %15, %14
- %10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 65535
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%8:fpr(<2 x i32>) = G_AND %12, %11
%9:fpr(<2 x i32>) = G_ICMP intpred(uge), %7(<2 x i32>), %8
@@ -1380,12 +1380,12 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %13:gpr(i32) = G_CONSTANT i32 65535
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(i32), %13(i32)
%15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%7:fpr(<2 x i32>) = G_AND %15, %14
- %10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 65535
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%8:fpr(<2 x i32>) = G_AND %12, %11
%9:fpr(<2 x i32>) = G_ICMP intpred(ult), %7(<2 x i32>), %8
@@ -1670,12 +1670,12 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %13:gpr(i32) = G_CONSTANT i32 65535
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(i32), %13(i32)
%15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%7:fpr(<2 x i32>) = G_AND %15, %14
- %10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 65535
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%8:fpr(<2 x i32>) = G_AND %12, %11
%9:fpr(<2 x i32>) = G_ICMP intpred(ule), %7(<2 x i32>), %8
@@ -1966,13 +1966,13 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %14:gpr(i32) = G_CONSTANT i32 16
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(i32), %14(i32)
%16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
%7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
- %10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 16
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
%8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
@@ -2264,13 +2264,13 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %14:gpr(i32) = G_CONSTANT i32 16
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(i32), %14(i32)
%16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
%7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
- %10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 16
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
%8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
@@ -2562,13 +2562,13 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %14:gpr(i32) = G_CONSTANT i32 16
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(i32), %14(i32)
%16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
%7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
- %10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 16
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
%8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
@@ -2860,13 +2860,13 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $d0
%2:fpr(<2 x i32>) = COPY $d0
%3:fpr(<2 x i32>) = COPY $d1
- %14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %14:gpr(i32) = G_CONSTANT i32 16
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(i32), %14(i32)
%16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
%17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
%7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
- %10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %10:gpr(i32) = G_CONSTANT i32 16
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(i32), %10(i32)
%12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
%13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
%8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
index 605ab99094719..9371e2eac5e4a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
@@ -58,8 +58,8 @@ body: |
; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<2 x i32>) = COPY $d0
- %2:gpr(s32) = G_CONSTANT i32 24
- %1:fpr(<2 x i32>) = G_BUILD_VECTOR %2(s32), %2(s32)
+ %2:gpr(i32) = G_CONSTANT i32 24
+ %1:fpr(<2 x i32>) = G_BUILD_VECTOR %2(i32), %2(i32)
%3:fpr(<2 x i32>) = G_SHL %0, %1(<2 x i32>)
$d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
@@ -94,8 +94,8 @@ body: |
; CHECK-NEXT: $d0 = COPY [[USHLv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<2 x i32>) = COPY $d0
- %2:gpr(s32) = G_CONSTANT i32 40
- %1:fpr(<2 x i32>) = G_BUILD_VECTOR %2(s32), %2(s32)
+ %2:gpr(i32) = G_CONSTANT i32 40
+ %1:fpr(<2 x i32>) = G_BUILD_VECTOR %2(i32), %2(i32)
%3:fpr(<2 x i32>) = G_SHL %0, %1(<2 x i32>)
$d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
@@ -159,8 +159,8 @@ body: |
; CHECK-NEXT: $q0 = COPY [[SHLv4i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<4 x i32>) = COPY $q0
- %2:gpr(s32) = G_CONSTANT i32 24
- %1:fpr(<4 x i32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
+ %2:gpr(i32) = G_CONSTANT i32 24
+ %1:fpr(<4 x i32>) = G_BUILD_VECTOR %2(i32), %2(i32), %2(i32), %2(i32)
%3:fpr(<4 x i32>) = G_SHL %0, %1(<4 x i32>)
$q0 = COPY %3(<4 x i32>)
RET_ReallyLR implicit $q0
@@ -224,8 +224,8 @@ body: |
; CHECK-NEXT: $q0 = COPY [[SHLv2i64_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<2 x i64>) = COPY $q0
- %2:gpr(s64) = G_CONSTANT i64 24
- %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(s64), %2(s64)
+ %2:gpr(i64) = G_CONSTANT i64 24
+ %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(i64), %2(i64)
%3:fpr(<2 x i64>) = G_SHL %0, %1(<2 x i64>)
$q0 = COPY %3(<2 x i64>)
RET_ReallyLR implicit $q0
@@ -261,8 +261,8 @@ body: |
; CHECK-NEXT: $q0 = COPY [[USHLv2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:fpr(<2 x i64>) = COPY $q0
- %2:gpr(s64) = G_CONSTANT i64 70
- %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(s64), %2(s64)
+ %2:gpr(i64) = G_CONSTANT i64 70
+ %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(i64), %2(i64)
%3:fpr(<2 x i64>) = G_SHL %0, %1(<2 x i64>)
$q0 = COPY %3(<2 x i64>)
RET_ReallyLR implicit $q0
@@ -619,8 +619,8 @@ body: |
; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(<2 x i32>) = COPY $d0
- %2:gpr(s32) = G_CONSTANT i32 24
- %1:fpr(<2 x i32>) = G_DUP %2(s32)
+ %2:gpr(i32) = G_CONSTANT i32 24
+ %1:fpr(<2 x i32>) = G_DUP %2(i32)
%3:fpr(<2 x i32>) = G_SHL %0, %1(<2 x i32>)
$d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
index d22305e441936..68b396029536a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
@@ -260,11 +260,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRBBui]]
%2:gpr(p0) = COPY $x0
- %0:gpr(s32) = G_LOAD %2(p0) :: (load (s8))
- $noreg = PATCHABLE_RET %0(s32)
+ %0:gpr(i32) = G_LOAD %2(p0) :: (load (i8))
+ $noreg = PATCHABLE_RET %0(i32)
...
# The rules that generated this test has changed. The generator should be rerun
@@ -288,14 +288,14 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[LDRBui]]
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UBFMWri]]
%2:gpr(p0) = COPY $x0
- %0:fpr(s8) = G_LOAD %2(p0) :: (load (s8))
- %1:gpr(s32) = G_ZEXT %0(s8)
- $noreg = PATCHABLE_RET %1(s32)
+ %0:fpr(i8) = G_LOAD %2(p0) :: (load (i8))
+ %1:gpr(i32) = G_ZEXT %0(i8)
+ $noreg = PATCHABLE_RET %1(i32)
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
index e6b400f324133..e0964ac628db4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
@@ -23,13 +23,13 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
; CHECK-NEXT: $x0 = COPY [[ANDXri]]
%3:gpr(p0) = G_IMPLICIT_DEF
- %2:gpr(i8) = G_LOAD %3(p0) :: (load (s8))
+ %2:gpr(i8) = G_LOAD %3(p0) :: (load (i8))
%4:gpr(i64) = G_ZEXT %2(i8)
%5:gpr(i64) = G_CONSTANT i64 1
%6:gpr(i64) = G_AND %4, %5
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
index b6b386acdbd9a..3ca1335fe7524 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
@@ -13,10 +13,10 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16))
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0:gpr(p0) = COPY $x0
- %1:gpr(i32) = G_ZEXTLOAD %0 :: (load (s16))
+ %1:gpr(i32) = G_ZEXTLOAD %0 :: (load (i16))
$w0 = COPY %1(i32)
...
---
@@ -31,11 +31,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16))
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s16) = G_LOAD %0 :: (load (s16))
+ %1:gpr(i16) = G_LOAD %0 :: (load (i16))
%2:gpr(i32) = G_ZEXT %1
$w0 = COPY %2(i32)
...
@@ -51,12 +51,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32))
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRWui]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s32))
+ %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (i32))
$x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
@@ -73,12 +73,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRHHui]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (i16))
$x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
@@ -95,12 +95,12 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (i8))
$x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
@@ -117,11 +117,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8))
; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (i8))
$w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
@@ -138,11 +138,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16))
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (i16))
$w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
@@ -160,11 +160,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load unordered (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load unordered (i8))
; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (i8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -182,11 +182,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load monotonic (s8))
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load monotonic (i8))
; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (i8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -204,11 +204,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (s8))
+ ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (i8))
; CHECK-NEXT: $w0 = COPY [[LDARB]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (i8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -226,11 +226,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst (s8))
+ ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst (i8))
; CHECK-NEXT: $w0 = COPY [[LDARB]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (i8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -248,11 +248,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load unordered (s16))
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load unordered (i16))
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (i16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -270,11 +270,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load monotonic (s16))
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load monotonic (i16))
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (i16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -292,11 +292,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load acquire (s16))
+ ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load acquire (i16))
; CHECK-NEXT: $w0 = COPY [[LDARH]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (i16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -314,11 +314,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load seq_cst (s16))
+ ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load seq_cst (i16))
; CHECK-NEXT: $w0 = COPY [[LDARH]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (i16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zip.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zip.mir
index da25425708244..6f7f617782878 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zip.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zip.mir
@@ -23,10 +23,10 @@ body: |
; CHECK-NEXT: [[ZIP1v2i32_:%[0-9]+]]:fpr64 = ZIP1v2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ZIP1v2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = G_ZIP1 %0, %1
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<2 x i32>) = G_ZIP1 %0, %1
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
---
@@ -47,10 +47,10 @@ body: |
; CHECK-NEXT: [[ZIP1v2i64_:%[0-9]+]]:fpr128 = ZIP1v2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ZIP1v2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = G_ZIP1 %0, %1
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %2:fpr(<2 x i64>) = G_ZIP1 %0, %1
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
---
@@ -70,10 +70,10 @@ body: |
; CHECK-NEXT: [[ZIP1v4i32_:%[0-9]+]]:fpr128 = ZIP1v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ZIP1v4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_ZIP1 %0, %1
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_ZIP1 %0, %1
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
---
@@ -94,10 +94,10 @@ body: |
; CHECK-NEXT: [[ZIP2v2i32_:%[0-9]+]]:fpr64 = ZIP2v2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ZIP2v2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = G_ZIP2 %0, %1
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<2 x i32>) = G_ZIP2 %0, %1
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
---
@@ -118,10 +118,10 @@ body: |
; CHECK-NEXT: [[ZIP2v2i64_:%[0-9]+]]:fpr128 = ZIP2v2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ZIP2v2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = G_ZIP2 %0, %1
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %2:fpr(<2 x i64>) = G_ZIP2 %0, %1
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
---
@@ -141,8 +141,8 @@ body: |
; CHECK-NEXT: [[ZIP2v4i32_:%[0-9]+]]:fpr128 = ZIP2v4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ZIP2v4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_ZIP2 %0, %1
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_ZIP2 %0, %1
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
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