[llvm] 06499c9 - [SLP][NFC] Add regressed vectorization of reduced values, NFC

[via llvm-commits]

Author: Alexey Bataev
Date: 2026-07-09T12:51:52-04:00
New Revision: 06499c927e5012166f4553c58f8af593521ea14d

URL: https://github.com/llvm/llvm-project/commit/06499c927e5012166f4553c58f8af593521ea14d
DIFF: https://github.com/llvm/llvm-project/commit/06499c927e5012166f4553c58f8af593521ea14d.diff

LOG: [SLP][NFC] Add regressed vectorization of reduced values, NFC

Reported in https://github.com/llvm/llvm-project/pull/185320#issuecomment-4925949343

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/208504

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
new file mode 100644
index 0000000000000..b1bda3f9db86a
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -S < %s | FileCheck %s
+
+define i32 @test(ptr %p, i32 %n, ptr %p2) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: ptr [[P:%.*]], i32 [[N:%.*]], ptr [[P2:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i16>, ptr [[P]], align 2
+; CHECK-NEXT:    [[TMP1:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32>
+; CHECK-NEXT:    [[ARRAYIDX_4:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 8
+; CHECK-NEXT:    [[TMP7:%.*]] = load i16, ptr [[ARRAYIDX_4]], align 2
+; CHECK-NEXT:    [[CONV_4:%.*]] = sext i16 [[TMP7]] to i32
+; CHECK-NEXT:    [[ARRAYIDX_5:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 10
+; CHECK-NEXT:    [[TMP3:%.*]] = load i16, ptr [[ARRAYIDX_5]], align 2
+; CHECK-NEXT:    [[CONV_5:%.*]] = sext i16 [[TMP3]] to i32
+; CHECK-NEXT:    [[ARRAYIDX_6:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 12
+; CHECK-NEXT:    [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX_6]], align 2
+; CHECK-NEXT:    [[CONV_6:%.*]] = sext i16 [[TMP4]] to i32
+; CHECK-NEXT:    [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT:    [[OP_RDX:%.*]] = add i32 [[TMP5]], [[CONV_4]]
+; CHECK-NEXT:    [[OP_RDX1:%.*]] = add i32 [[CONV_5]], [[CONV_6]]
+; CHECK-NEXT:    [[OP_RDX2:%.*]] = add i32 [[OP_RDX]], [[OP_RDX1]]
+; CHECK-NEXT:    [[ARRAYIDX_7:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 14
+; CHECK-NEXT:    [[TMP6:%.*]] = load i16, ptr [[ARRAYIDX_7]], align 2
+; CHECK-NEXT:    [[CONV_7:%.*]] = sext i16 [[TMP6]] to i32
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i32 [[OP_RDX2]], [[CONV_7]]
+; CHECK-NEXT:    store i32 [[TMP2]], ptr [[P2]], align 4
+; CHECK-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[N]]
+; CHECK-NEXT:    ret i32 [[ADD1]]
+;
+entry:
+  %0 = load i16, ptr %p
+  %conv = sext i16 %0 to i32
+  %arrayidx.1 = getelementptr inbounds nuw i8, ptr %p, i64 2
+  %1 = load i16, ptr %arrayidx.1
+  %conv.1 = sext i16 %1 to i32
+  %add.1 = add nsw i32 %conv, %conv.1
+  %arrayidx.2 = getelementptr inbounds nuw i8, ptr %p, i64 4
+  %2 = load i16, ptr %arrayidx.2
+  %conv.2 = sext i16 %2 to i32
+  %add.2 = add nsw i32 %add.1, %conv.2
+  %arrayidx.3 = getelementptr inbounds nuw i8, ptr %p, i64 6
+  %3 = load i16, ptr %arrayidx.3
+  %conv.3 = sext i16 %3 to i32
+  %add.3 = add nsw i32 %add.2, %conv.3
+  %arrayidx.4 = getelementptr inbounds nuw i8, ptr %p, i64 8
+  %4 = load i16, ptr %arrayidx.4
+  %conv.4 = sext i16 %4 to i32
+  %add.4 = add nsw i32 %add.3, %conv.4
+  %arrayidx.5 = getelementptr inbounds nuw i8, ptr %p, i64 10
+  %5 = load i16, ptr %arrayidx.5
+  %conv.5 = sext i16 %5 to i32
+  %add.5 = add nsw i32 %add.4, %conv.5
+  %arrayidx.6 = getelementptr inbounds nuw i8, ptr %p, i64 12
+  %6 = load i16, ptr %arrayidx.6
+  %conv.6 = sext i16 %6 to i32
+  %add.6 = add nsw i32 %add.5, %conv.6
+  %arrayidx.7 = getelementptr inbounds nuw i8, ptr %p, i64 14
+  %7 = load i16, ptr %arrayidx.7
+  %conv.7 = sext i16 %7 to i32
+  %add.7 = add nsw i32 %add.6, %conv.7
+  store i32 %add.7, ptr %p2
+  %add1 = add nsw i32 %add.7, %n
+  ret i32 %add1
+}