[llvm] [X86][CostModel] Add vXi64 divide/remainder-by-constant costs (PR #208491)
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Thu Jul 9 08:49:45 PDT 2026
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diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 6493cd5c4..4e942d1fd 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -423,15 +423,15 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return LT.first * *KindCost;
static const CostKindTblEntry AVX512DQUniformConstCostTable[] = {
- { ISD::SDIV, MVT::v4i64, { 15 } }, // vpmullq-based MULHS sequence
- { ISD::SREM, MVT::v4i64, { 17 } }, // vpmullq-based MULHS+mul+sub sequence
- { ISD::SDIV, MVT::v8i64, { 15 } }, // vpmullq-based MULHS sequence
- { ISD::SREM, MVT::v8i64, { 17 } }, // vpmullq-based MULHS+mul+sub sequence
- // The remainder's multiply-back is a single vpmullq with DQ, just like the
- // pmulld the vXi32 entries above rely on. Without DQ it is another
- // vpmuludq schoolbook, so the AVX512/AVX2 tables charge more.
- { ISD::UREM, MVT::v4i64, { 17 } }, // MULHU + vpmullq + sub sequence
- { ISD::UREM, MVT::v8i64, { 17 } }, // MULHU + vpmullq + sub sequence
+ {ISD::SDIV, MVT::v4i64, {15}}, // vpmullq-based MULHS sequence
+ {ISD::SREM, MVT::v4i64, {17}}, // vpmullq-based MULHS+mul+sub sequence
+ {ISD::SDIV, MVT::v8i64, {15}}, // vpmullq-based MULHS sequence
+ {ISD::SREM, MVT::v8i64, {17}}, // vpmullq-based MULHS+mul+sub sequence
+ // The remainder's multiply-back is a single vpmullq with DQ, just like
+ // the pmulld the vXi32 entries above rely on. Without DQ it is another
+ // vpmuludq schoolbook, so the AVX512/AVX2 tables charge more.
+ {ISD::UREM, MVT::v4i64, {17}}, // MULHU + vpmullq + sub sequence
+ {ISD::UREM, MVT::v8i64, {17}}, // MULHU + vpmullq + sub sequence
};
if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasDQI())
@@ -441,36 +441,36 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return LT.first * *KindCost;
static const CostKindTblEntry AVX512UniformConstCostTable[] = {
- { ISD::SHL, MVT::v64i8, { 2, 12, 5, 6 } }, // psllw + pand.
- { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand.
- { ISD::SRA, MVT::v64i8, { 3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb.
-
- { ISD::SHL, MVT::v16i16, { 2, 7, 4, 4 } }, // psllw + split.
- { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split.
- { ISD::SRA, MVT::v16i16, { 2, 7, 4, 4 } }, // psraw + split.
-
- { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } }, // pslld
- { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, // psrld
- { ISD::SRA, MVT::v8i32, { 1, 1, 1, 1 } }, // psrad
- { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } }, // pslld
- { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, // psrld
- { ISD::SRA, MVT::v16i32, { 1, 1, 1, 1 } }, // psrad
-
- { ISD::SRA, MVT::v2i64, { 1, 1, 1, 1 } }, // psraq
- { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } }, // psllq
- { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, // psrlq
- { ISD::SRA, MVT::v4i64, { 1, 1, 1, 1 } }, // psraq
- { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } }, // psllq
- { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, // psrlq
- { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } }, // psraq
-
- { ISD::SDIV, MVT::v16i32, { 6 } }, // pmuludq sequence
- { ISD::SREM, MVT::v16i32, { 8 } }, // pmuludq+mul+sub sequence
- { ISD::UDIV, MVT::v16i32, { 5 } }, // pmuludq sequence
- { ISD::UREM, MVT::v16i32, { 7 } }, // pmuludq+mul+sub sequence
-
- { ISD::UDIV, MVT::v8i64, { 15 } }, // pmuludq-based MULHU sequence
- { ISD::UREM, MVT::v8i64, { 21 } }, // pmuludq-based MULHU+mul+sub sequence
+ {ISD::SHL, MVT::v64i8, {2, 12, 5, 6}}, // psllw + pand.
+ {ISD::SRL, MVT::v64i8, {2, 12, 5, 6}}, // psrlw + pand.
+ {ISD::SRA, MVT::v64i8, {3, 10, 12, 12}}, // psrlw, pand, pxor, psubb.
+
+ {ISD::SHL, MVT::v16i16, {2, 7, 4, 4}}, // psllw + split.
+ {ISD::SRL, MVT::v16i16, {2, 7, 4, 4}}, // psrlw + split.
+ {ISD::SRA, MVT::v16i16, {2, 7, 4, 4}}, // psraw + split.
+
+ {ISD::SHL, MVT::v8i32, {1, 1, 1, 1}}, // pslld
+ {ISD::SRL, MVT::v8i32, {1, 1, 1, 1}}, // psrld
+ {ISD::SRA, MVT::v8i32, {1, 1, 1, 1}}, // psrad
+ {ISD::SHL, MVT::v16i32, {1, 1, 1, 1}}, // pslld
+ {ISD::SRL, MVT::v16i32, {1, 1, 1, 1}}, // psrld
+ {ISD::SRA, MVT::v16i32, {1, 1, 1, 1}}, // psrad
+
+ {ISD::SRA, MVT::v2i64, {1, 1, 1, 1}}, // psraq
+ {ISD::SHL, MVT::v4i64, {1, 1, 1, 1}}, // psllq
+ {ISD::SRL, MVT::v4i64, {1, 1, 1, 1}}, // psrlq
+ {ISD::SRA, MVT::v4i64, {1, 1, 1, 1}}, // psraq
+ {ISD::SHL, MVT::v8i64, {1, 1, 1, 1}}, // psllq
+ {ISD::SRL, MVT::v8i64, {1, 1, 1, 1}}, // psrlq
+ {ISD::SRA, MVT::v8i64, {1, 1, 1, 1}}, // psraq
+
+ {ISD::SDIV, MVT::v16i32, {6}}, // pmuludq sequence
+ {ISD::SREM, MVT::v16i32, {8}}, // pmuludq+mul+sub sequence
+ {ISD::UDIV, MVT::v16i32, {5}}, // pmuludq sequence
+ {ISD::UREM, MVT::v16i32, {7}}, // pmuludq+mul+sub sequence
+
+ {ISD::UDIV, MVT::v8i64, {15}}, // pmuludq-based MULHU sequence
+ {ISD::UREM, MVT::v8i64, {21}}, // pmuludq-based MULHU+mul+sub sequence
};
if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX512())
@@ -480,41 +480,41 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return LT.first * *KindCost;
static const CostKindTblEntry AVX2UniformConstCostTable[] = {
- { ISD::SHL, MVT::v16i8, { 1, 8, 2, 3 } }, // psllw + pand.
- { ISD::SRL, MVT::v16i8, { 1, 8, 2, 3 } }, // psrlw + pand.
- { ISD::SRA, MVT::v16i8, { 2, 10, 5, 6 } }, // psrlw, pand, pxor, psubb.
- { ISD::SHL, MVT::v32i8, { 2, 8, 2, 4 } }, // psllw + pand.
- { ISD::SRL, MVT::v32i8, { 2, 8, 2, 4 } }, // psrlw + pand.
- { ISD::SRA, MVT::v32i8, { 3, 10, 5, 9 } }, // psrlw, pand, pxor, psubb.
-
- { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw
- { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw
- { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw
- { ISD::SHL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psllw
- { ISD::SRL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psrlw
- { ISD::SRA, MVT::v16i16,{ 2, 2, 1, 2 } }, // psraw
-
- { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld
- { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld
- { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad
- { ISD::SHL, MVT::v8i32, { 2, 2, 1, 2 } }, // pslld
- { ISD::SRL, MVT::v8i32, { 2, 2, 1, 2 } }, // psrld
- { ISD::SRA, MVT::v8i32, { 2, 2, 1, 2 } }, // psrad
-
- { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq
- { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq
- { ISD::SRA, MVT::v2i64, { 2, 3, 3, 3 } }, // psrad + shuffle.
- { ISD::SHL, MVT::v4i64, { 2, 2, 1, 2 } }, // psllq
- { ISD::SRL, MVT::v4i64, { 2, 2, 1, 2 } }, // psrlq
- { ISD::SRA, MVT::v4i64, { 4, 4, 3, 6 } }, // psrad + shuffle + split.
-
- { ISD::SDIV, MVT::v8i32, { 6 } }, // pmuludq sequence
- { ISD::SREM, MVT::v8i32, { 8 } }, // pmuludq+mul+sub sequence
- { ISD::UDIV, MVT::v8i32, { 5 } }, // pmuludq sequence
- { ISD::UREM, MVT::v8i32, { 7 } }, // pmuludq+mul+sub sequence
-
- { ISD::UDIV, MVT::v4i64, { 15 } }, // pmuludq-based MULHU sequence
- { ISD::UREM, MVT::v4i64, { 21 } }, // pmuludq-based MULHU+mul+sub sequence
+ {ISD::SHL, MVT::v16i8, {1, 8, 2, 3}}, // psllw + pand.
+ {ISD::SRL, MVT::v16i8, {1, 8, 2, 3}}, // psrlw + pand.
+ {ISD::SRA, MVT::v16i8, {2, 10, 5, 6}}, // psrlw, pand, pxor, psubb.
+ {ISD::SHL, MVT::v32i8, {2, 8, 2, 4}}, // psllw + pand.
+ {ISD::SRL, MVT::v32i8, {2, 8, 2, 4}}, // psrlw + pand.
+ {ISD::SRA, MVT::v32i8, {3, 10, 5, 9}}, // psrlw, pand, pxor, psubb.
+
+ {ISD::SHL, MVT::v8i16, {1, 1, 1, 1}}, // psllw
+ {ISD::SRL, MVT::v8i16, {1, 1, 1, 1}}, // psrlw
+ {ISD::SRA, MVT::v8i16, {1, 1, 1, 1}}, // psraw
+ {ISD::SHL, MVT::v16i16, {2, 2, 1, 2}}, // psllw
+ {ISD::SRL, MVT::v16i16, {2, 2, 1, 2}}, // psrlw
+ {ISD::SRA, MVT::v16i16, {2, 2, 1, 2}}, // psraw
+
+ {ISD::SHL, MVT::v4i32, {1, 1, 1, 1}}, // pslld
+ {ISD::SRL, MVT::v4i32, {1, 1, 1, 1}}, // psrld
+ {ISD::SRA, MVT::v4i32, {1, 1, 1, 1}}, // psrad
+ {ISD::SHL, MVT::v8i32, {2, 2, 1, 2}}, // pslld
+ {ISD::SRL, MVT::v8i32, {2, 2, 1, 2}}, // psrld
+ {ISD::SRA, MVT::v8i32, {2, 2, 1, 2}}, // psrad
+
+ {ISD::SHL, MVT::v2i64, {1, 1, 1, 1}}, // psllq
+ {ISD::SRL, MVT::v2i64, {1, 1, 1, 1}}, // psrlq
+ {ISD::SRA, MVT::v2i64, {2, 3, 3, 3}}, // psrad + shuffle.
+ {ISD::SHL, MVT::v4i64, {2, 2, 1, 2}}, // psllq
+ {ISD::SRL, MVT::v4i64, {2, 2, 1, 2}}, // psrlq
+ {ISD::SRA, MVT::v4i64, {4, 4, 3, 6}}, // psrad + shuffle + split.
+
+ {ISD::SDIV, MVT::v8i32, {6}}, // pmuludq sequence
+ {ISD::SREM, MVT::v8i32, {8}}, // pmuludq+mul+sub sequence
+ {ISD::UDIV, MVT::v8i32, {5}}, // pmuludq sequence
+ {ISD::UREM, MVT::v8i32, {7}}, // pmuludq+mul+sub sequence
+
+ {ISD::UDIV, MVT::v4i64, {15}}, // pmuludq-based MULHU sequence
+ {ISD::UREM, MVT::v4i64, {21}}, // pmuludq-based MULHU+mul+sub sequence
};
if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasAVX2())
@@ -616,14 +616,14 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return LT.first * *KindCost;
static const CostKindTblEntry AVX512DQConstCostTable[] = {
- { ISD::SDIV, MVT::v4i64, { 19 } }, // vpmullq-based MULHS sequence
- { ISD::SREM, MVT::v4i64, { 21 } }, // vpmullq-based MULHS+mul+sub sequence
- { ISD::SDIV, MVT::v8i64, { 19 } }, // vpmullq-based MULHS sequence
- { ISD::SREM, MVT::v8i64, { 21 } }, // vpmullq-based MULHS+mul+sub sequence
- // The remainder's multiply-back is a single vpmullq with DQ, whereas the
- // AVX512/AVX2 tables have to charge for another vpmuludq schoolbook.
- { ISD::UREM, MVT::v4i64, { 24 } }, // MULHU + vpmullq + sub sequence
- { ISD::UREM, MVT::v8i64, { 24 } }, // MULHU + vpmullq + sub sequence
+ {ISD::SDIV, MVT::v4i64, {19}}, // vpmullq-based MULHS sequence
+ {ISD::SREM, MVT::v4i64, {21}}, // vpmullq-based MULHS+mul+sub sequence
+ {ISD::SDIV, MVT::v8i64, {19}}, // vpmullq-based MULHS sequence
+ {ISD::SREM, MVT::v8i64, {21}}, // vpmullq-based MULHS+mul+sub sequence
+ // The remainder's multiply-back is a single vpmullq with DQ, whereas the
+ // AVX512/AVX2 tables have to charge for another vpmuludq schoolbook.
+ {ISD::UREM, MVT::v4i64, {24}}, // MULHU + vpmullq + sub sequence
+ {ISD::UREM, MVT::v8i64, {24}}, // MULHU + vpmullq + sub sequence
};
if (Op2Info.isConstant() && ST->hasDQI())
@@ -633,23 +633,23 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return LT.first * *KindCost;
static const CostKindTblEntry AVX512ConstCostTable[] = {
- { ISD::SDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
- { ISD::SREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
- { ISD::UDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
- { ISD::UREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
-
- { ISD::SDIV, MVT::v32i16, { 12 } }, // 2*vpmulhw sequence
- { ISD::SREM, MVT::v32i16, { 16 } }, // 2*vpmulhw+mul+sub sequence
- { ISD::UDIV, MVT::v32i16, { 12 } }, // 2*vpmulhuw sequence
- { ISD::UREM, MVT::v32i16, { 16 } }, // 2*vpmulhuw+mul+sub sequence
-
- { ISD::SDIV, MVT::v16i32, { 15 } }, // vpmuldq sequence
- { ISD::SREM, MVT::v16i32, { 17 } }, // vpmuldq+mul+sub sequence
- { ISD::UDIV, MVT::v16i32, { 15 } }, // vpmuludq sequence
- { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence
-
- { ISD::UDIV, MVT::v8i64, { 22 } }, // vpmuludq-based MULHU sequence
- { ISD::UREM, MVT::v8i64, { 28 } }, // vpmuludq-based MULHU+mul+sub sequence
+ {ISD::SDIV, MVT::v64i8, {28}}, // 4*ext+4*pmulhw sequence
+ {ISD::SREM, MVT::v64i8, {32}}, // 4*ext+4*pmulhw+mul+sub sequence
+ {ISD::UDIV, MVT::v64i8, {28}}, // 4*ext+4*pmulhw sequence
+ {ISD::UREM, MVT::v64i8, {32}}, // 4*ext+4*pmulhw+mul+sub sequence
+
+ {ISD::SDIV, MVT::v32i16, {12}}, // 2*vpmulhw sequence
+ {ISD::SREM, MVT::v32i16, {16}}, // 2*vpmulhw+mul+sub sequence
+ {ISD::UDIV, MVT::v32i16, {12}}, // 2*vpmulhuw sequence
+ {ISD::UREM, MVT::v32i16, {16}}, // 2*vpmulhuw+mul+sub sequence
+
+ {ISD::SDIV, MVT::v16i32, {15}}, // vpmuldq sequence
+ {ISD::SREM, MVT::v16i32, {17}}, // vpmuldq+mul+sub sequence
+ {ISD::UDIV, MVT::v16i32, {15}}, // vpmuludq sequence
+ {ISD::UREM, MVT::v16i32, {17}}, // vpmuludq+mul+sub sequence
+
+ {ISD::UDIV, MVT::v8i64, {22}}, // vpmuludq-based MULHU sequence
+ {ISD::UREM, MVT::v8i64, {28}}, // vpmuludq-based MULHU+mul+sub sequence
};
if (Op2Info.isConstant() && ST->hasAVX512())
@@ -659,23 +659,23 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return LT.first * *KindCost;
static const CostKindTblEntry AVX2ConstCostTable[] = {
- { ISD::SDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
- { ISD::SREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
- { ISD::UDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
- { ISD::UREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
-
- { ISD::SDIV, MVT::v16i16, { 6 } }, // vpmulhw sequence
- { ISD::SREM, MVT::v16i16, { 8 } }, // vpmulhw+mul+sub sequence
- { ISD::UDIV, MVT::v16i16, { 6 } }, // vpmulhuw sequence
- { ISD::UREM, MVT::v16i16, { 8 } }, // vpmulhuw+mul+sub sequence
-
- { ISD::SDIV, MVT::v8i32, { 15 } }, // vpmuldq sequence
- { ISD::SREM, MVT::v8i32, { 19 } }, // vpmuldq+mul+sub sequence
- { ISD::UDIV, MVT::v8i32, { 15 } }, // vpmuludq sequence
- { ISD::UREM, MVT::v8i32, { 19 } }, // vpmuludq+mul+sub sequence
-
- { ISD::UDIV, MVT::v4i64, { 22 } }, // vpmuludq-based MULHU sequence
- { ISD::UREM, MVT::v4i64, { 28 } }, // vpmuludq-based MULHU+mul+sub sequence
+ {ISD::SDIV, MVT::v32i8, {14}}, // 2*ext+2*pmulhw sequence
+ {ISD::SREM, MVT::v32i8, {16}}, // 2*ext+2*pmulhw+mul+sub sequence
+ {ISD::UDIV, MVT::v32i8, {14}}, // 2*ext+2*pmulhw sequence
+ {ISD::UREM, MVT::v32i8, {16}}, // 2*ext+2*pmulhw+mul+sub sequence
+
+ {ISD::SDIV, MVT::v16i16, {6}}, // vpmulhw sequence
+ {ISD::SREM, MVT::v16i16, {8}}, // vpmulhw+mul+sub sequence
+ {ISD::UDIV, MVT::v16i16, {6}}, // vpmulhuw sequence
+ {ISD::UREM, MVT::v16i16, {8}}, // vpmulhuw+mul+sub sequence
+
+ {ISD::SDIV, MVT::v8i32, {15}}, // vpmuldq sequence
+ {ISD::SREM, MVT::v8i32, {19}}, // vpmuldq+mul+sub sequence
+ {ISD::UDIV, MVT::v8i32, {15}}, // vpmuludq sequence
+ {ISD::UREM, MVT::v8i32, {19}}, // vpmuludq+mul+sub sequence
+
+ {ISD::UDIV, MVT::v4i64, {22}}, // vpmuludq-based MULHU sequence
+ {ISD::UREM, MVT::v4i64, {28}}, // vpmuludq-based MULHU+mul+sub sequence
};
if (Op2Info.isConstant() && ST->hasAVX2())
``````````
</details>
https://github.com/llvm/llvm-project/pull/208491
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