[llvm] BPF: Fix misfolding subregisters (PR #208244)

[via llvm-commits]

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@@ -89,24 +90,26 @@ void BPFMIPeephole::initialize(MachineFunction &MFParm) {
   MF = &MFParm;
   MRI = &MF->getRegInfo();
   TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
+  TRI = &TII->getRegisterInfo();
   LLVM_DEBUG(dbgs() << "*** BPF MachineSSA ZEXT Elim peephole pass ***\n\n");
 }
 
 bool BPFMIPeephole::isCopyFrom32Def(MachineInstr *CopyMI)
 {
   MachineOperand &opnd = CopyMI->getOperand(1);
 
-  if (!opnd.isReg())
-    return false;
-
   // Return false if getting value from a 32bit physical register.
   // Most likely, this physical register is aliased to
   // function call return value or current function parameters.
   Register Reg = opnd.getReg();
   if (!Reg.isVirtual())
     return false;
 
-  if (MRI->getRegClass(Reg) == &BPF::GPRRegClass)
+  const TargetRegisterClass *RC = MRI->getRegClass(Reg);
+  if (unsigned SubReg = opnd.getSubReg())
+    RC = TRI->getSubRegisterClass(RC, SubReg);
+
+  if (!RC->hasSubClassEq(&BPF::GPRRegClass))
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yonghong-song wrote:

Why this change? Seems they are equivalent?

https://github.com/llvm/llvm-project/pull/208244