[llvm] [AMDGPU] Check hasNoF16PseudoScalarTransInlineConstants in more places (PR #208459)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Frederik Harwath (frederik-h)

<details>
<summary>Changes</summary>

The isOperandLegal function already rejects inline constants violating the restriction if the subtarget returns true for hasNoF16PseudoScalarTransInlineConstants.

Adjust the behavior of the isInlineConstant overload with access to the MI and reject violations in the machine verifier.

---
Full diff: https://github.com/llvm/llvm-project/pull/208459.diff


3 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+39) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+1-15) 
- (added) llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir (+26) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index e945db946c158..47c76d80fe11a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4735,6 +4735,30 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
   }
 }
 
+bool SIInstrInfo::isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
+                                   int64_t ImmVal) const {
+  if (OpIdx >= MI.getDesc().NumOperands)
+    return false;
+
+  if (isCopyInstr(MI)) {
+    unsigned Size = getOpSize(MI, OpIdx);
+    assert(Size == 8 || Size == 4);
+
+    uint8_t OpType = (Size == 8) ? AMDGPU::OPERAND_REG_IMM_INT64
+                                 : AMDGPU::OPERAND_REG_IMM_INT32;
+    return isInlineConstant(ImmVal, OpType);
+  }
+
+  if (!isInlineConstant(ImmVal, MI.getDesc().operands()[OpIdx].OperandType))
+    return false;
+
+  if (ST.hasNoF16PseudoScalarTransInlineConstants() &&
+      isF16PseudoScalarTrans(MI.getOpcode()))
+    return false;
+
+  return true;
+}
+
 static bool compareMachineOp(const MachineOperand &Op0,
                              const MachineOperand &Op1) {
   if (Op0.getType() != Op1.getType())
@@ -5497,6 +5521,21 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
     }
   }
 
+  if (ST.hasNoF16PseudoScalarTransInlineConstants() &&
+      isF16PseudoScalarTrans(Opcode)) {
+    for (int OpIdx : {Src0Idx, Src1Idx, Src2Idx}) {
+      if (OpIdx == -1)
+        continue;
+      const MachineOperand &MO = MI.getOperand(OpIdx);
+      if (MO.isImm() &&
+          isInlineConstant(MO.getImm(), Desc.operands()[OpIdx].OperandType)) {
+        ErrInfo =
+            "F16 pseudo scalar transcendental instruction uses inline constant";
+        return false;
+      }
+    }
+  }
+
   // Special case for writelane - this can break the multiple constant bus rule,
   // but still can't use more than one SGPR register
   if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 8e15b7b45b609..03a647545bc4c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1323,21 +1323,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
   }
 
   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
-                        int64_t ImmVal) const {
-    if (OpIdx >= MI.getDesc().NumOperands)
-      return false;
-
-    if (isCopyInstr(MI)) {
-      unsigned Size = getOpSize(MI, OpIdx);
-      assert(Size == 8 || Size == 4);
-
-      uint8_t OpType = (Size == 8) ?
-        AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
-      return isInlineConstant(ImmVal, OpType);
-    }
-
-    return isInlineConstant(ImmVal, MI.getDesc().operands()[OpIdx].OperandType);
-  }
+                        int64_t ImmVal) const;
 
   bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
                         const MachineOperand &MO) const {
diff --git a/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir b/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
new file mode 100644
index 0000000000000..a4528ea77973f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
@@ -0,0 +1,26 @@
+# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass machineverifier -filetype=null %s 2>&1 | FileCheck -implicit-check-not="Bad machine code" %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass machineverifier -filetype=null %s
+
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %0:sgpr_32 = V_S_EXP_F16_e64 0, -1, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %1:sgpr_32 = V_S_LOG_F16_e64 0, 0, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %2:sgpr_32 = V_S_RCP_F16_e64 0, 1, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %3:sgpr_32 = V_S_RSQ_F16_e64 0, -16, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %4:sgpr_32 = V_S_SQRT_F16_e64 0, 64, 0, 0, implicit $mode, implicit $exec
+---
+name:            f16_pseudo_scalar_trans_inline_imm
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %0:sgpr_32 = V_S_EXP_F16_e64 0, -1, 0, 0, implicit $mode, implicit $exec
+    %1:sgpr_32 = V_S_LOG_F16_e64 0, 0, 0, 0, implicit $mode, implicit $exec
+    %2:sgpr_32 = V_S_RCP_F16_e64 0, 1, 0, 0, implicit $mode, implicit $exec
+    %3:sgpr_32 = V_S_RSQ_F16_e64 0, -16, 0, 0, implicit $mode, implicit $exec
+    %4:sgpr_32 = V_S_SQRT_F16_e64 0, 64, 0, 0, implicit $mode, implicit $exec
+    S_ENDPGM 0
+
+...

``````````

</details>


https://github.com/llvm/llvm-project/pull/208459