[llvm] [GlobalISel] Fix crash in matchCombineInsertVecElts with INLINEASM-de… (PR #208225)

[Mateusz Chudyk via llvm-commits]

https://github.com/mateuszchudyk updated https://github.com/llvm/llvm-project/pull/208225

>From 1941573852c9295209efeb375757536a1f312e2e Mon Sep 17 00:00:00 2001
From: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: Wed, 8 Jul 2026 13:22:06 +0200
Subject: [PATCH 1/2] [GlobalISel] Fix crash in matchCombineInsertVecElts with
 INLINEASM-defined base

matchCombineInsertVecElts walks the G_INSERT_VECTOR_ELT chain by
following operand 0 of the source-defining instruction. When the base
vector is defined by INLINEASM, operand 0 is the asm string (not a
register), so calling getReg() triggers an assertion:

  Assertion `isReg() && "This is not a register operand!"' failed.

Fix by using the mi_match overload that takes a MachineInstr instead
of a Register, which checks the instruction opcode before accessing
any operands.
---
 .../lib/CodeGen/GlobalISel/CombinerHelper.cpp |  2 +-
 ...r-combiner-insertvecelt-inlineasm-base.mir | 29 +++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir

diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 072f194b36d5a..b1a1f6de79c61 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -3225,7 +3225,7 @@ bool CombinerHelper::matchCombineInsertVecElts(
   Register TmpReg;
   MatchInfo.resize(NumElts);
   while (mi_match(
-      CurrInst->getOperand(0).getReg(), MRI,
+      *CurrInst, MRI,
       m_GInsertVecElt(m_MInstr(TmpInst), m_Reg(TmpReg), m_ICst(IntImm)))) {
     if (IntImm >= NumElts || IntImm < 0)
       return false;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir
new file mode 100644
index 0000000000000..a40a6db88e5ea
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir
@@ -0,0 +1,29 @@
+# REQUIRES: aarch64-registered-target
+# RUN: llc -mtriple=aarch64-unknown-linux-gnu -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+# Regression test for CombinerHelper::matchCombineInsertVecElts.
+# The base vector of G_INSERT_VECTOR_ELT is defined by INLINEASM. The combiner
+# must stop at INLINEASM and not assume that operand 0 is a register.
+
+# CHECK-LABEL: name: insertvecelt_inlineasm_base
+# CHECK: INLINEASM
+# CHECK: G_INSERT_VECTOR_ELT
+
+---
+name:            insertvecelt_inlineasm_base
+alignment:       4
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %idx:_(s64) = G_CONSTANT i64 0
+    %elt:_(s32) = G_CONSTANT i32 42
+    %addr:gpr64 = IMPLICIT_DEF
+
+    INLINEASM &"ldr $0, [$1]", sideeffect attdialect, regdef:FPR128, def %base:fpr128(<4 x s32>), reguse:GPR64, %addr:gpr64
+    %v:_(<4 x s32>) = G_INSERT_VECTOR_ELT %base:fpr128(<4 x s32>), %elt:_(s32), %idx:_(s64)
+    $q0 = COPY %v(<4 x s32>)
+    RET_ReallyLR implicit $q0
+...

>From 3288f1897c3c83a48c8e5373e9a9d21edcd20a5d Mon Sep 17 00:00:00 2001
From: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: Thu, 9 Jul 2026 15:54:11 +0200
Subject: [PATCH 2/2] Update
 llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
 .../prelegalizer-combiner-insertvecelt-inlineasm-base.mir       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir
index a40a6db88e5ea..d57e742c50688 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-insertvecelt-inlineasm-base.mir
@@ -1,5 +1,5 @@
 # REQUIRES: aarch64-registered-target
-# RUN: llc -mtriple=aarch64-unknown-linux-gnu -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-linux-gnu -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
 
 # Regression test for CombinerHelper::matchCombineInsertVecElts.
 # The base vector of G_INSERT_VECTOR_ELT is defined by INLINEASM. The combiner