[llvm] 700442d - [SLP]Add AShr as a main opcode for copyables
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 9 06:22:48 PDT 2026
Author: Alexey Bataev
Date: 2026-07-09T09:22:44-04:00
New Revision: 700442d9e4312fad3e42860bb19692fff7c94cd6
URL: https://github.com/llvm/llvm-project/commit/700442d9e4312fad3e42860bb19692fff7c94cd6
DIFF: https://github.com/llvm/llvm-project/commit/700442d9e4312fad3e42860bb19692fff7c94cd6.diff
LOG: [SLP]Add AShr as a main opcode for copyables
Added AShr opcode in analysis and minbitwidth analysis
Reviewers: RKSimon, hiraditya, bababuck
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/207841
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 30fa465e5178a..3a2846da3a98f 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -12032,12 +12032,13 @@ class InstructionsCompatibilityAnalysis {
/// elements.
static bool isSupportedOpcode(const unsigned Opcode) {
return Opcode == Instruction::Add || Opcode == Instruction::Sub ||
- Opcode == Instruction::Mul || Opcode == Instruction::LShr ||
- Opcode == Instruction::Shl || Opcode == Instruction::SDiv ||
- Opcode == Instruction::UDiv || Opcode == Instruction::And ||
- Opcode == Instruction::Or || Opcode == Instruction::Xor ||
- Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
- Opcode == Instruction::FMul || Opcode == Instruction::FDiv;
+ Opcode == Instruction::Mul || Opcode == Instruction::AShr ||
+ Opcode == Instruction::LShr || Opcode == Instruction::Shl ||
+ Opcode == Instruction::SDiv || Opcode == Instruction::UDiv ||
+ Opcode == Instruction::And || Opcode == Instruction::Or ||
+ Opcode == Instruction::Xor || Opcode == Instruction::FAdd ||
+ Opcode == Instruction::FSub || Opcode == Instruction::FMul ||
+ Opcode == Instruction::FDiv;
}
/// Identifies the best candidate value, which represents main opcode
@@ -12660,6 +12661,7 @@ class InstructionsCompatibilityAnalysis {
case Instruction::Add:
case Instruction::Sub:
case Instruction::Mul:
+ case Instruction::AShr:
case Instruction::LShr:
case Instruction::Shl:
case Instruction::SDiv:
@@ -27375,9 +27377,11 @@ bool BoUpSLP::collectValuesToDemote(
return all_of(E.Scalars, [&](Value *V) {
if (isa<PoisonValue>(V))
return true;
+ unsigned ShiftedBits = OrigBitWidth - BitWidth;
+ if (E.isCopyableElement(V))
+ return ShiftedBits < ComputeNumSignBits(V, *DL, AC, nullptr, DT);
auto *I = cast<Instruction>(V);
KnownBits AmtKnownBits = computeKnownBits(I->getOperand(1), *DL);
- unsigned ShiftedBits = OrigBitWidth - BitWidth;
return AmtKnownBits.getMaxValue().ult(BitWidth) &&
ShiftedBits <
ComputeNumSignBits(I->getOperand(0), *DL, AC, nullptr, DT);
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
index d7ae587833d2d..6c09ce4bc73fe 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
@@ -11,17 +11,17 @@ define fastcc i32 @test(i32 %0, i32 %add111.i.i, <4 x i32> %PredPel.i.sroa.86.72
; CHECK-LABEL: define fastcc i32 @test(
; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[ADD111_I_I:%.*]], <4 x i32> [[PREDPEL_I_SROA_86_72_VEC_EXTRACT:%.*]], <4 x i32> [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[LOOPARRAY_SROA_24_0_I_I3:%.*]] = ashr i32 [[TMP0]], 1
-; CHECK-NEXT: [[SHR143_5_I_I9:%.*]] = ashr i32 [[TMP0]], 1
-; CHECK-NEXT: [[ADD1392_I:%.*]] = add i32 [[TMP0]], 1
; CHECK-NEXT: [[MUL1445_I:%.*]] = shl i32 [[TMP0]], 1
; CHECK-NEXT: [[ADD2235_I17:%.*]] = or i32 [[TMP0]], 1
; CHECK-NEXT: [[ADD2323_I1:%.*]] = add i32 [[TMP0]], 1
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[ADD111_I_I]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP3]], i32 [[ADD2323_I1]], i32 2
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <3 x i32> poison, i32 [[TMP0]], i32 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <3 x i32> [[TMP5]], <3 x i32> poison, <3 x i32> zeroinitializer
+; CHECK-NEXT: [[ADD1392_I:%.*]] = add i32 [[TMP0]], 1
+; CHECK-NEXT: [[SHR143_5_I_I9:%.*]] = ashr i32 [[TMP0]], 1
+; CHECK-NEXT: [[LOOPARRAY_SROA_24_0_I_I3:%.*]] = ashr i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP10]], i32 [[ADD2323_I1]], i32 2
; CHECK-NEXT: [[TMP7:%.*]] = or <3 x i32> [[TMP4]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[PREDPEL_I_SROA_86_72_VEC_EXTRACT]], <4 x i32> [[TMP1]], <8 x i32> <i32 0, i32 poison, i32 poison, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[TMP0]], i32 4
@@ -53,17 +53,20 @@ define fastcc i32 @test(i32 %0, i32 %add111.i.i, <4 x i32> %PredPel.i.sroa.86.72
; THRESH-LABEL: define fastcc i32 @test(
; THRESH-SAME: i32 [[TMP0:%.*]], i32 [[ADD111_I_I:%.*]], <4 x i32> [[PREDPEL_I_SROA_86_72_VEC_EXTRACT:%.*]], <4 x i32> [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; THRESH-NEXT: [[ENTRY:.*:]]
-; THRESH-NEXT: [[LOOPARRAY_SROA_24_0_I_I3:%.*]] = ashr i32 [[TMP0]], 1
-; THRESH-NEXT: [[SHR143_5_I_I9:%.*]] = ashr i32 [[TMP0]], 1
-; THRESH-NEXT: [[ADD1392_I:%.*]] = add i32 [[TMP0]], 1
; THRESH-NEXT: [[MUL1445_I:%.*]] = shl i32 [[TMP0]], 1
; THRESH-NEXT: [[ADD2235_I16:%.*]] = or i32 [[TMP0]], 1
; THRESH-NEXT: [[ADD2323_I:%.*]] = add i32 [[TMP0]], 1
+; THRESH-NEXT: [[TMP30:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; THRESH-NEXT: [[TMP31:%.*]] = shufflevector <2 x i32> [[TMP30]], <2 x i32> poison, <2 x i32> zeroinitializer
+; THRESH-NEXT: [[TMP32:%.*]] = add <2 x i32> [[TMP31]], <i32 0, i32 1>
+; THRESH-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP32]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
+; THRESH-NEXT: [[TMP21:%.*]] = ashr <4 x i32> [[TMP5]], <i32 1, i32 0, i32 0, i32 1>
; THRESH-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[ADD111_I_I]], i32 0
-; THRESH-NEXT: [[TMP3:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i32 1
+; THRESH-NEXT: [[TMP33:%.*]] = shufflevector <4 x i32> [[TMP21]], <4 x i32> poison, <3 x i32> <i32 0, i32 poison, i32 poison>
+; THRESH-NEXT: [[TMP34:%.*]] = shufflevector <3 x i32> [[TMP2]], <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
+; THRESH-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP34]], <4 x i32> [[TMP21]], <3 x i32> <i32 0, i32 4, i32 poison>
; THRESH-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP3]], i32 [[ADD2323_I]], i32 2
-; THRESH-NEXT: [[TMP5:%.*]] = insertelement <3 x i32> poison, i32 [[TMP0]], i32 0
-; THRESH-NEXT: [[TMP6:%.*]] = shufflevector <3 x i32> [[TMP5]], <3 x i32> poison, <3 x i32> zeroinitializer
+; THRESH-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP31]], <2 x i32> poison, <3 x i32> zeroinitializer
; THRESH-NEXT: [[TMP7:%.*]] = or <3 x i32> [[TMP4]], [[TMP6]]
; THRESH-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[PREDPEL_I_SROA_86_72_VEC_EXTRACT]], <4 x i32> [[TMP1]], <8 x i32> <i32 0, i32 poison, i32 poison, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>
; THRESH-NEXT: [[TMP9:%.*]] = shufflevector <3 x i32> [[TMP4]], <3 x i32> poison, <8 x i32> <i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 0, i32 poison>
@@ -71,14 +74,13 @@ define fastcc i32 @test(i32 %0, i32 %add111.i.i, <4 x i32> %PredPel.i.sroa.86.72
; THRESH-NEXT: [[TMP11:%.*]] = insertelement <8 x i32> [[TMP10]], i32 [[TMP0]], i32 4
; THRESH-NEXT: [[TMP12:%.*]] = insertelement <8 x i32> [[TMP11]], i32 [[ADD2235_I16]], i32 1
; THRESH-NEXT: [[TMP13:%.*]] = insertelement <8 x i32> [[TMP12]], i32 [[MUL1445_I]], i32 5
-; THRESH-NEXT: [[TMP14:%.*]] = insertelement <8 x i32> [[TMP13]], i32 [[SHR143_5_I_I9]], i32 7
+; THRESH-NEXT: [[TMP20:%.*]] = shufflevector <4 x i32> [[TMP21]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; THRESH-NEXT: [[TMP14:%.*]] = shufflevector <8 x i32> [[TMP13]], <8 x i32> [[TMP20]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 11>
; THRESH-NEXT: [[TMP15:%.*]] = add <8 x i32> [[TMP14]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 1, i32 1>
; THRESH-NEXT: [[TMP16:%.*]] = shufflevector <8 x i32> [[TMP15]], <8 x i32> poison, <11 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison>
; THRESH-NEXT: [[TMP17:%.*]] = shufflevector <3 x i32> [[TMP7]], <3 x i32> poison, <11 x i32> <i32 0, i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THRESH-NEXT: [[TMP18:%.*]] = shufflevector <11 x i32> [[TMP16]], <11 x i32> [[TMP17]], <11 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 11, i32 12, i32 13>
; THRESH-NEXT: [[TMP19:%.*]] = lshr <11 x i32> [[TMP18]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 1, i32 1, i32 1, i32 1, i32 1>
-; THRESH-NEXT: [[TMP20:%.*]] = shufflevector <8 x i32> [[TMP14]], <8 x i32> poison, <4 x i32> <i32 2, i32 poison, i32 4, i32 7>
-; THRESH-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[ADD1392_I]], i32 1
; THRESH-NEXT: [[TMP22:%.*]] = or <4 x i32> [[TMP21]], splat (i32 1)
; THRESH-NEXT: [[TMP23:%.*]] = shufflevector <8 x i32> [[TMP14]], <8 x i32> poison, <4 x i32> <i32 4, i32 4, i32 4, i32 4>
; THRESH-NEXT: [[TMP24:%.*]] = add <4 x i32> [[TMP22]], [[TMP23]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll b/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
index 263fff4c64fa9..aa00686d399ff 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
@@ -4,7 +4,7 @@
define void @test(i32 %arg) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]]) {
-; CHECK-NEXT: [[BB:.*]]:
+; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i32> zeroinitializer, [[TMP0]]
@@ -25,7 +25,7 @@ define void @test(i32 %arg) {
; CHECK-NEXT: [[TMP11:%.*]] = lshr <2 x i32> [[TMP10]], zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i32> [[TMP10]], zeroinitializer
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[TMP11]], <2 x i32> [[TMP12]], <2 x i32> <i32 0, i32 3>
-; CHECK-NEXT: [[TMP14]] = or <2 x i32> [[TMP13]], zeroinitializer
+; CHECK-NEXT: [[TMP14]] = ashr <2 x i32> [[TMP13]], zeroinitializer
; CHECK-NEXT: br label %[[BB2]]
;
bb:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
index 7c25d04d9112d..cdd7e64d4a3cb 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
@@ -18,7 +18,7 @@ define void @test(i32 %arg) {
; CHECK-NEXT: [[TMP6:%.*]] = lshr <2 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = or <2 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], <2 x i32> <i32 2, i32 1>
-; CHECK-NEXT: [[TMP9:%.*]] = add <2 x i32> [[TMP8]], zeroinitializer
+; CHECK-NEXT: [[TMP9:%.*]] = ashr <2 x i32> [[TMP8]], zeroinitializer
; CHECK-NEXT: br label %[[BB5:.*]]
; CHECK: [[BB5]]:
; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x i32> [ [[TMP9]], %[[BB4]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll b/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
index f08344f005dc5..350a9e518d479 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s --check-prefixes=CHECK,NON-POWER_OF-2
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s --check-prefixes=CHECK,POWER_OF-2
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
define void @add0(ptr noalias %dst, ptr noalias %src) {
;
@@ -317,34 +317,13 @@ entry:
}
define void @ashr0(ptr noalias %dst, ptr noalias %src) {
-; NON-POWER_OF-2-LABEL: define void @ashr0(
-; NON-POWER_OF-2-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
-; NON-POWER_OF-2-NEXT: [[ENTRY:.*:]]
-; NON-POWER_OF-2-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 1
-; NON-POWER_OF-2-NEXT: [[TMP0:%.*]] = load i32, ptr [[SRC]], align 4
-; NON-POWER_OF-2-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 1
-; NON-POWER_OF-2-NEXT: store i32 [[TMP0]], ptr [[DST]], align 4
-; NON-POWER_OF-2-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr [[INCDEC_PTR]], align 4
-; NON-POWER_OF-2-NEXT: [[TMP2:%.*]] = ashr <3 x i32> [[TMP1]], <i32 1, i32 2, i32 3>
-; NON-POWER_OF-2-NEXT: store <3 x i32> [[TMP2]], ptr [[INCDEC_PTR1]], align 4
-; NON-POWER_OF-2-NEXT: ret void
-;
-; POWER_OF-2-LABEL: define void @ashr0(
-; POWER_OF-2-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
-; POWER_OF-2-NEXT: [[ENTRY:.*:]]
-; POWER_OF-2-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 1
-; POWER_OF-2-NEXT: [[TMP0:%.*]] = load i32, ptr [[SRC]], align 4
-; POWER_OF-2-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 1
-; POWER_OF-2-NEXT: store i32 [[TMP0]], ptr [[DST]], align 4
-; POWER_OF-2-NEXT: [[INCDEC_PTR4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 3
-; POWER_OF-2-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 3
-; POWER_OF-2-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[INCDEC_PTR]], align 4
-; POWER_OF-2-NEXT: [[TMP2:%.*]] = ashr <2 x i32> [[TMP1]], <i32 1, i32 2>
-; POWER_OF-2-NEXT: store <2 x i32> [[TMP2]], ptr [[INCDEC_PTR1]], align 4
-; POWER_OF-2-NEXT: [[TMP3:%.*]] = load i32, ptr [[INCDEC_PTR4]], align 4
-; POWER_OF-2-NEXT: [[ASHR8:%.*]] = ashr i32 [[TMP3]], 3
-; POWER_OF-2-NEXT: store i32 [[ASHR8]], ptr [[INCDEC_PTR6]], align 4
-; POWER_OF-2-NEXT: ret void
+; CHECK-LABEL: define void @ashr0(
+; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> [[TMP0]], <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[DST]], align 4
+; CHECK-NEXT: ret void
;
entry:
%incdec.ptr = getelementptr inbounds i32, ptr %src, i64 1
@@ -402,18 +381,9 @@ define void @ashr_addsub0(ptr noalias %dst, ptr noalias %src) {
; CHECK-LABEL: define void @ashr_addsub0(
; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 1
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[SRC]], align 4
-; CHECK-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 1
-; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[TMP0]], 1
-; CHECK-NEXT: store i32 [[ASHR]], ptr [[DST]], align 4
-; CHECK-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 2
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[INCDEC_PTR]], align 4
-; CHECK-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 2
-; CHECK-NEXT: store i32 [[TMP1]], ptr [[INCDEC_PTR1]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[INCDEC_PTR2]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = ashr <2 x i32> [[TMP2]], <i32 2, i32 0>
-; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[INCDEC_PTR3]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> [[TMP0]], <i32 1, i32 0, i32 2, i32 0>
+; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[DST]], align 4
; CHECK-NEXT: ret void
;
entry:
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