[llvm] 6c2f267 - [AArch64] Add missing TB(N)Z achors to arith+CBZ clustering (#207725)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 9 02:48:31 PDT 2026
Author: Tomer Shafir
Date: 2026-07-09T12:48:26+03:00
New Revision: 6c2f267a209a0b4bd0447c589a855c9334fd598c
URL: https://github.com/llvm/llvm-project/commit/6c2f267a209a0b4bd0447c589a855c9334fd598c
DIFF: https://github.com/llvm/llvm-project/commit/6c2f267a209a0b4bd0447c589a855c9334fd598c.diff
LOG: [AArch64] Add missing TB(N)Z achors to arith+CBZ clustering (#207725)
This patch adds missing TBZ+TBNZ anchors for arith+CBZ clustering. They
have similar nature to CBZ as specific kinds of it, so this patch
classifies them under the same subtarget feature name compactly. This is
better for Apple CPU. They can be reasonably expected to behave
similarly on AArch64 targets.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
index e00bbdd3db0a0..31b3e097de8ca 100644
--- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -73,7 +73,11 @@ static bool isArithmeticCbzPair(const MachineInstr *FirstMI,
if (SecondMI.getOpcode() != AArch64::CBZW &&
SecondMI.getOpcode() != AArch64::CBZX &&
SecondMI.getOpcode() != AArch64::CBNZW &&
- SecondMI.getOpcode() != AArch64::CBNZX)
+ SecondMI.getOpcode() != AArch64::CBNZX &&
+ SecondMI.getOpcode() != AArch64::TBZW &&
+ SecondMI.getOpcode() != AArch64::TBZX &&
+ SecondMI.getOpcode() != AArch64::TBNZW &&
+ SecondMI.getOpcode() != AArch64::TBNZX)
return false;
// Assume the 1st instr to be a wildcard if it is unspecified.
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
index a82fa5017a6b7..0a43aeb47d53e 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
@@ -41,6 +41,42 @@ exit:
ret void
}
+; CHECK-LABEL: addwri_tbz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @addwri_tbz(i32 %a) {
+entry:
+ %v0 = add i32 %a, 13
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addwri_tbnz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @addwri_tbnz(i32 %a) {
+entry:
+ %v0 = add i32 %a, 13
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: addwrr_cbz:
; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -75,6 +111,42 @@ exit:
ret void
}
+; CHECK-LABEL: addwrr_tbz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @addwrr_tbz(i32 %a, i32 %b) {
+entry:
+ %v0 = add i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addwrr_tbnz:
+; CHECK: add [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @addwrr_tbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = add i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: andwri_cbz:
; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -109,6 +181,10 @@ exit:
ret void
}
+; NOTE: no andwri_tbz/andwri_tbnz: a single-bit test of an immediate-AND result folds
+; through the AND, so no fused ANDri+TB(N)Z pair is expressible at the IR level.
+; The .mir test covers ANDWri + TB(N)Z directly.
+
; CHECK-LABEL: andwrr_cbz:
; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -143,6 +219,42 @@ exit:
ret void
}
+; CHECK-LABEL: andwrr_tbz:
+; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @andwrr_tbz(i32 %a, i32 %b) {
+entry:
+ %v0 = and i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andwrr_tbnz:
+; CHECK: and [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @andwrr_tbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = and i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: eorwri_cbz:
; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -177,6 +289,42 @@ exit:
ret void
}
+; CHECK-LABEL: eorwri_tbz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @eorwri_tbz(i32 %a) {
+entry:
+ %v0 = xor i32 %a, 255
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorwri_tbnz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @eorwri_tbnz(i32 %a) {
+entry:
+ %v0 = xor i32 %a, 255
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: eorwrr_cbz:
; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -211,6 +359,42 @@ exit:
ret void
}
+; CHECK-LABEL: eorwrr_tbz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @eorwrr_tbz(i32 %a, i32 %b) {
+entry:
+ %v0 = xor i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorwrr_tbnz:
+; CHECK: eor [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @eorwrr_tbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = xor i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: orrwri_cbz:
; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -245,6 +429,42 @@ exit:
ret void
}
+; CHECK-LABEL: orrwri_tbz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @orrwri_tbz(i32 %a) {
+entry:
+ %v0 = or i32 %a, 255
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrwri_tbnz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, #0xff
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @orrwri_tbnz(i32 %a) {
+entry:
+ %v0 = or i32 %a, 255
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: orrwrr_cbz:
; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -279,6 +499,42 @@ exit:
ret void
}
+; CHECK-LABEL: orrwrr_tbz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @orrwrr_tbz(i32 %a, i32 %b) {
+entry:
+ %v0 = or i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrwrr_tbnz:
+; CHECK: orr [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @orrwrr_tbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = or i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: ornwrr_cbz:
; CHECK: orn [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -315,6 +571,44 @@ exit:
ret void
}
+; CHECK-LABEL: ornwrr_tbz:
+; CHECK: orn [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @ornwrr_tbz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = or i32 %a, %n
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: ornwrr_tbnz:
+; CHECK: orn [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @ornwrr_tbnz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = or i32 %a, %n
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: bicwrr_cbz:
; CHECK: bic [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -351,6 +645,44 @@ exit:
ret void
}
+; CHECK-LABEL: bicwrr_tbz:
+; CHECK: bic [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @bicwrr_tbz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = and i32 %a, %n
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicwrr_tbnz:
+; CHECK: bic [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @bicwrr_tbnz(i32 %a, i32 %b) {
+entry:
+ %n = xor i32 %b, -1
+ %v0 = and i32 %a, %n
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: subwri_cbz:
; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -385,6 +717,42 @@ exit:
ret void
}
+; CHECK-LABEL: subwri_tbz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @subwri_tbz(i32 %a) {
+entry:
+ %v0 = sub i32 %a, 13
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subwri_tbnz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @subwri_tbnz(i32 %a) {
+entry:
+ %v0 = sub i32 %a, 13
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: subwrr_cbz:
; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -419,12 +787,118 @@ exit:
ret void
}
+; CHECK-LABEL: subwrr_tbz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @subwrr_tbz(i32 %a, i32 %b) {
+entry:
+ %v0 = sub i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp ne i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subwrr_tbnz:
+; CHECK: sub [[R:w[0-9]+]], {{w[0-9]+}}, {{w[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #8, {{.?LBB[0-9_]+}}
+define void @subwrr_tbnz(i32 %a, i32 %b) {
+entry:
+ %v0 = sub i32 %a, %b
+ %v1 = add i32 %a, 7
+ %t = and i32 %v0, 256
+ %cond = icmp eq i32 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi32(i32 %v1, i32 %v0)
+ br label %exit
+exit:
+ call void @fi32(i32 %v0, i32 %v1)
+ ret void
+}
+
; CHECK-LABEL: addxri_cbz:
; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, #13
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
define void @addxri_cbz(i64 %a) {
entry:
- %v0 = add i64 %a, 13
+ %v0 = add i64 %a, 13
+ %v1 = add i64 %a, 7
+ %cond = icmp ne i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxri_cbnz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
+define void @addxri_cbnz(i64 %a) {
+entry:
+ %v0 = add i64 %a, 13
+ %v1 = add i64 %a, 7
+ %cond = icmp eq i64 %v0, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxri_tbz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @addxri_tbz(i64 %a) {
+entry:
+ %v0 = add i64 %a, 13
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxri_tbnz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @addxri_tbnz(i64 %a) {
+entry:
+ %v0 = add i64 %a, 13
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: addxrr_cbz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
+define void @addxrr_cbz(i64 %a, i64 %b) {
+entry:
+ %v0 = add i64 %a, %b
%v1 = add i64 %a, 7
%cond = icmp ne i64 %v0, 0
br i1 %cond, label %if, label %exit
@@ -436,12 +910,12 @@ exit:
ret void
}
-; CHECK-LABEL: addxri_cbnz:
-; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-LABEL: addxrr_cbnz:
+; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
-define void @addxri_cbnz(i64 %a) {
+define void @addxrr_cbnz(i64 %a, i64 %b) {
entry:
- %v0 = add i64 %a, 13
+ %v0 = add i64 %a, %b
%v1 = add i64 %a, 7
%cond = icmp eq i64 %v0, 0
br i1 %cond, label %if, label %exit
@@ -453,14 +927,15 @@ exit:
ret void
}
-; CHECK-LABEL: addxrr_cbz:
+; CHECK-LABEL: addxrr_tbz:
; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
-; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
-define void @addxrr_cbz(i64 %a, i64 %b) {
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @addxrr_tbz(i64 %a, i64 %b) {
entry:
%v0 = add i64 %a, %b
%v1 = add i64 %a, 7
- %cond = icmp ne i64 %v0, 0
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
br i1 %cond, label %if, label %exit
if:
call void @fi64(i64 %v1, i64 %v0)
@@ -470,14 +945,15 @@ exit:
ret void
}
-; CHECK-LABEL: addxrr_cbnz:
+; CHECK-LABEL: addxrr_tbnz:
; CHECK: add [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
-; CHECK-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
-define void @addxrr_cbnz(i64 %a, i64 %b) {
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @addxrr_tbnz(i64 %a, i64 %b) {
entry:
%v0 = add i64 %a, %b
%v1 = add i64 %a, 7
- %cond = icmp eq i64 %v0, 0
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
br i1 %cond, label %if, label %exit
if:
call void @fi64(i64 %v1, i64 %v0)
@@ -521,6 +997,10 @@ exit:
ret void
}
+; NOTE: no andxri_tbz/andxri_tbnz: a single-bit test of an immediate-AND result folds
+; through the AND, so no fused ANDri+TB(N)Z pair is expressible at the IR level.
+; The .mir test covers ANDXri + TB(N)Z directly.
+
; CHECK-LABEL: andxrr_cbz:
; CHECK: and [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -555,6 +1035,42 @@ exit:
ret void
}
+; CHECK-LABEL: andxrr_tbz:
+; CHECK: and [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @andxrr_tbz(i64 %a, i64 %b) {
+entry:
+ %v0 = and i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: andxrr_tbnz:
+; CHECK: and [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @andxrr_tbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = and i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: eorxri_cbz:
; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -589,6 +1105,42 @@ exit:
ret void
}
+; CHECK-LABEL: eorxri_tbz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @eorxri_tbz(i64 %a) {
+entry:
+ %v0 = xor i64 %a, 255
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorxri_tbnz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @eorxri_tbnz(i64 %a) {
+entry:
+ %v0 = xor i64 %a, 255
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: eorxrr_cbz:
; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -623,6 +1175,42 @@ exit:
ret void
}
+; CHECK-LABEL: eorxrr_tbz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @eorxrr_tbz(i64 %a, i64 %b) {
+entry:
+ %v0 = xor i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: eorxrr_tbnz:
+; CHECK: eor [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @eorxrr_tbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = xor i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: orrxri_cbz:
; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -657,6 +1245,42 @@ exit:
ret void
}
+; CHECK-LABEL: orrxri_tbz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @orrxri_tbz(i64 %a) {
+entry:
+ %v0 = or i64 %a, 255
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrxri_tbnz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, #0xff
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @orrxri_tbnz(i64 %a) {
+entry:
+ %v0 = or i64 %a, 255
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: orrxrr_cbz:
; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -691,6 +1315,42 @@ exit:
ret void
}
+; CHECK-LABEL: orrxrr_tbz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @orrxrr_tbz(i64 %a, i64 %b) {
+entry:
+ %v0 = or i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: orrxrr_tbnz:
+; CHECK: orr [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @orrxrr_tbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = or i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: ornxrr_cbz:
; CHECK: orn [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -727,6 +1387,44 @@ exit:
ret void
}
+; CHECK-LABEL: ornxrr_tbz:
+; CHECK: orn [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @ornxrr_tbz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = or i64 %a, %n
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: ornxrr_tbnz:
+; CHECK: orn [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @ornxrr_tbnz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = or i64 %a, %n
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: bicxrr_cbz:
; CHECK: bic [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -763,6 +1461,44 @@ exit:
ret void
}
+; CHECK-LABEL: bicxrr_tbz:
+; CHECK: bic [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @bicxrr_tbz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = and i64 %a, %n
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: bicxrr_tbnz:
+; CHECK: bic [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @bicxrr_tbnz(i64 %a, i64 %b) {
+entry:
+ %n = xor i64 %b, -1
+ %v0 = and i64 %a, %n
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: subxri_cbz:
; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, #13
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -797,6 +1533,42 @@ exit:
ret void
}
+; CHECK-LABEL: subxri_tbz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @subxri_tbz(i64 %a) {
+entry:
+ %v0 = sub i64 %a, 13
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subxri_tbnz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, #13
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @subxri_tbnz(i64 %a) {
+entry:
+ %v0 = sub i64 %a, 13
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
; CHECK-LABEL: subxrr_cbz:
; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
; CHECK-NEXT: cbz [[R]], {{.?LBB[0-9_]+}}
@@ -831,3 +1603,38 @@ exit:
ret void
}
+; CHECK-LABEL: subxrr_tbz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @subxrr_tbz(i64 %a, i64 %b) {
+entry:
+ %v0 = sub i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp ne i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
+
+; CHECK-LABEL: subxrr_tbnz:
+; CHECK: sub [[R:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
+; CHECK-NEXT: tbnz [[R]], #32, {{.?LBB[0-9_]+}}
+define void @subxrr_tbnz(i64 %a, i64 %b) {
+entry:
+ %v0 = sub i64 %a, %b
+ %v1 = add i64 %a, 7
+ %t = and i64 %v0, 4294967296
+ %cond = icmp eq i64 %t, 0
+ br i1 %cond, label %if, label %exit
+if:
+ call void @fi64(i64 %v1, i64 %v0)
+ br label %exit
+exit:
+ call void @fi64(i64 %v0, i64 %v1)
+ ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
index ccbbbb7d72c90..42786416227d9 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
@@ -49,14 +49,13 @@ body: |
bb.2:
RET undef $lr
...
-
-# CHECK-LABEL: addwrr_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
+# CHECK-LABEL: addwri_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: TBZW
---
-name: addwrr_cbz
+name: addwri_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -64,22 +63,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ADDWrr $w0, $w1
+ $w0 = ADDWri $w0, 13, 0
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ TBZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: addwrr_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
+# CHECK-LABEL: addwri_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWri $w0, 13, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBNZW
---
-name: addwrr_cbnz
+name: addwri_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -87,22 +86,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ADDWrr $w0, $w1
+ $w0 = ADDWri $w0, 13, 0
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ TBNZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: addwrs_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
+# CHECK-LABEL: addwrr_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZW
---
-name: addwrs_cbz
+name: addwrr_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -110,7 +109,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ADDWrs $w0, $w1, 0
+ $w0 = ADDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
CBZW $w0, %bb.2
bb.1:
@@ -119,13 +118,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: addwrs_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
+# CHECK-LABEL: addwrr_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: addwrs_cbnz
+name: addwrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -133,7 +132,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ADDWrs $w0, $w1, 0
+ $w0 = ADDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -142,13 +141,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_addwrs
-# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 12
+# CHECK-LABEL: addwrr_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
---
-name: no_fuse_positive_shift_addwrs
+name: addwrr_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -156,22 +155,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ADDWrs $w0, $w1, 12
+ $w0 = ADDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ TBZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andwri_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
+# CHECK-LABEL: addwrr_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: TBNZW
---
-name: andwri_cbz
+name: addwrr_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -179,22 +178,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ANDWri $w0, 4096
+ $w0 = ADDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ TBNZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andwri_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
+# CHECK-LABEL: addwrs_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: CBZW
---
-name: andwri_cbnz
+name: addwrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -202,22 +201,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ANDWri $w0, 4096
+ $w0 = ADDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ CBZW $w0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andwrr_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
+# CHECK-LABEL: addwrs_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: CBNZW
---
-name: andwrr_cbz
+name: addwrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -225,22 +224,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ANDWrr $w0, $w1
+ $w0 = ADDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ CBNZW $w0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andwrr_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
+# CHECK-LABEL: addwrs_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBZW
---
-name: andwrr_cbnz
+name: addwrs_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -248,22 +247,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ANDWrr $w0, $w1
+ $w0 = ADDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ TBZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andwrs_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
+# CHECK-LABEL: addwrs_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: TBNZW
---
-name: andwrs_cbz
+name: addwrs_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -271,22 +270,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ANDWrs $w0, $w1, 0
+ $w0 = ADDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ TBNZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andwrs_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
+# CHECK-LABEL: no_fuse_positive_shift_addwrs
+# CHECK: SU({{[0-9]+}}): $w0 = ADDWrs $w0, $w1, 12
# CHECK: Successors:
-# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: andwrs_cbnz
+name: no_fuse_positive_shift_addwrs
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -294,7 +293,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ANDWrs $w0, $w1, 0
+ $w0 = ADDWrs $w0, $w1, 12
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -303,13 +302,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_andwrs
-# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 12
+# CHECK-LABEL: andwri_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
---
-name: no_fuse_positive_shift_andwrs
+name: andwri_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -317,22 +316,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ANDWrs $w0, $w1, 12
+ $w0 = ANDWri $w0, 4096
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ CBZW $w0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorwri_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
+# CHECK-LABEL: andwri_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: CBNZW
---
-name: eorwri_cbz
+name: andwri_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -340,22 +339,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWri $w0, 4096
+ $w0 = ANDWri $w0, 4096
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ CBNZW $w0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorwri_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
+# CHECK-LABEL: andwri_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBZW
---
-name: eorwri_cbnz
+name: andwri_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -363,22 +362,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWri $w0, 4096
+ $w0 = ANDWri $w0, 4096
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ TBZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorwrr_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK-LABEL: andwri_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWri $w0, 4096
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: TBNZW
---
-name: eorwrr_cbz
+name: andwri_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -386,22 +385,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWrr $w0, $w1
+ $w0 = ANDWri $w0, 4096
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ TBNZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorwrr_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK-LABEL: andwrr_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: CBZW
---
-name: eorwrr_cbnz
+name: andwrr_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -409,22 +408,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWrr $w0, $w1
+ $w0 = ANDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ CBZW $w0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorwrs_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
+# CHECK-LABEL: andwrr_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: CBNZW
---
-name: eorwrs_cbz
+name: andwrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -432,22 +431,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWrs $w0, $w1, 0
+ $w0 = ANDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ CBNZW $w0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorwrs_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
+# CHECK-LABEL: andwrr_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBZW
---
-name: eorwrs_cbnz
+name: andwrr_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -455,22 +454,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWrs $w0, $w1, 0
+ $w0 = ANDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ TBZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_eorwrs
-# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 12
+# CHECK-LABEL: andwrr_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrr $w0, $w1
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
---
-name: no_fuse_positive_shift_eorwrs
+name: andwrr_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -478,22 +477,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = EORWrs $w0, $w1, 12
+ $w0 = ANDWrr $w0, $w1
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ TBNZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: ornwrr_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1
+# CHECK-LABEL: andwrs_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZW
---
-name: ornwrr_cbz
+name: andwrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -501,7 +500,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORNWrr $w0, $w1
+ $w0 = ANDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
CBZW $w0, %bb.2
bb.1:
@@ -510,13 +509,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: ornwrr_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1
+# CHECK-LABEL: andwrs_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: ornwrr_cbnz
+name: andwrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -524,7 +523,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORNWrr $w0, $w1
+ $w0 = ANDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -533,13 +532,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: ornwrs_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0
+# CHECK-LABEL: andwrs_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: TBZW
---
-name: ornwrs_cbz
+name: andwrs_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -547,22 +546,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORNWrs $w0, $w1, 0
+ $w0 = ANDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ TBZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: ornwrs_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0
+# CHECK-LABEL: andwrs_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBNZW
---
-name: ornwrs_cbnz
+name: andwrs_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -570,22 +569,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORNWrs $w0, $w1, 0
+ $w0 = ANDWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ TBNZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_ornwrs
-# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 12
+# CHECK-LABEL: no_fuse_positive_shift_andwrs
+# CHECK: SU({{[0-9]+}}): $w0 = ANDWrs $w0, $w1, 12
# CHECK: Successors:
# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: no_fuse_positive_shift_ornwrs
+name: no_fuse_positive_shift_andwrs
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -593,7 +592,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORNWrs $w0, $w1, 12
+ $w0 = ANDWrs $w0, $w1, 12
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -602,13 +601,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: orrwri_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK-LABEL: eorwri_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZW
---
-name: orrwri_cbz
+name: eorwri_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -616,7 +615,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWri $w0, 4096
+ $w0 = EORWri $w0, 4096
$w3 = ORRWri $w2, 4096
CBZW $w0, %bb.2
bb.1:
@@ -625,13 +624,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: orrwri_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK-LABEL: eorwri_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: orrwri_cbnz
+name: eorwri_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -639,7 +638,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWri $w0, 4096
+ $w0 = EORWri $w0, 4096
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -648,13 +647,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: orrwrr_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK-LABEL: eorwri_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: TBZW
---
-name: orrwrr_cbz
+name: eorwri_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -662,22 +661,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWrr $w0, $w1
+ $w0 = EORWri $w0, 4096
$w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ TBZW $w0, 8, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: orrwrr_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK-LABEL: eorwri_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWri $w0, 4096
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBNZW
---
-name: orrwrr_cbnz
+name: eorwri_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -685,7 +684,53 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWrr $w0, $w1
+ $w0 = EORWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorwrr_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: eorwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorwrr_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: eorwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrr $w0, $w1
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -694,13 +739,59 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: orrwrs_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
+# CHECK-LABEL: eorwrr_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: eorwrr_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorwrr_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: eorwrr_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorwrs_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZW
---
-name: orrwrs_cbz
+name: eorwrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -708,7 +799,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWrs $w0, $w1, 0
+ $w0 = EORWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
CBZW $w0, %bb.2
bb.1:
@@ -717,13 +808,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: orrwrs_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
+# CHECK-LABEL: eorwrs_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: orrwrs_cbnz
+name: eorwrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -731,7 +822,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWrs $w0, $w1, 0
+ $w0 = EORWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -740,13 +831,59 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_orrwrs
-# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 12
+# CHECK-LABEL: eorwrs_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: eorwrs_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorwrs_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: eorwrs_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = EORWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: no_fuse_positive_shift_eorwrs
+# CHECK: SU({{[0-9]+}}): $w0 = EORWrs $w0, $w1, 12
# CHECK: Successors:
# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: no_fuse_positive_shift_orrwrs
+name: no_fuse_positive_shift_eorwrs
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -754,7 +891,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = ORRWrs $w0, $w1, 12
+ $w0 = EORWrs $w0, $w1, 12
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -763,13 +900,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: subwri_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK-LABEL: ornwrr_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZW
---
-name: subwri_cbz
+name: ornwrr_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -777,7 +914,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = SUBWri $w0, 13, 0
+ $w0 = ORNWrr $w0, $w1
$w3 = ORRWri $w2, 4096
CBZW $w0, %bb.2
bb.1:
@@ -786,13 +923,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: subwri_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK-LABEL: ornwrr_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: subwri_cbnz
+name: ornwrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -800,7 +937,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = SUBWri $w0, 13, 0
+ $w0 = ORNWrr $w0, $w1
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -809,13 +946,59 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: subwrr_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK-LABEL: ornwrr_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: ornwrr_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: ornwrr_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: ornwrr_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: ornwrs_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZW
---
-name: subwrr_cbz
+name: ornwrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -823,7 +1006,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = SUBWrr $w0, $w1
+ $w0 = ORNWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
CBZW $w0, %bb.2
bb.1:
@@ -832,13 +1015,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: subwrr_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK-LABEL: ornwrs_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZW
---
-name: subwrr_cbnz
+name: ornwrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -846,7 +1029,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $w0, $w1, $w2
- $w0 = SUBWrr $w0, $w1
+ $w0 = ORNWrs $w0, $w1, 0
$w3 = ORRWri $w2, 4096
CBNZW $w0, %bb.2
bb.1:
@@ -855,197 +1038,1784 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: subwrs_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK-LABEL: ornwrs_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: ornwrs_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: ornwrs_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: ornwrs_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: no_fuse_positive_shift_ornwrs
+# CHECK: SU({{[0-9]+}}): $w0 = ORNWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_ornwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORNWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwri_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: orrwri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwri_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: orrwri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwri_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: orrwri_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwri_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWri $w0, 4096
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: orrwri_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWri $w0, 4096
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrr_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: orrwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrr_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: orrwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrr_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: orrwrr_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrr_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: orrwrr_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrs_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: orrwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrs_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: orrwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrs_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: orrwrs_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: orrwrs_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: orrwrs_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: no_fuse_positive_shift_orrwrs
+# CHECK: SU({{[0-9]+}}): $w0 = ORRWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_orrwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = ORRWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwri_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: subwri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwri_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: subwri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwri_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: subwri_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwri_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWri $w0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: subwri_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWri $w0, 13, 0
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrr_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: subwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrr_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: subwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrr_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: subwrr_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrr_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: subwrr_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrs_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: subwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrs_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: subwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrs_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: subwrs_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: subwrs_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: subwrs_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: no_fuse_positive_shift_subwrs
+# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_subwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = SUBWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrr_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: bicwrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrr_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: bicwrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrr_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: bicwrr_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrr_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: bicwrr_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrr $w0, $w1
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrs_cbz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZW
+---
+name: bicwrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrs_cbnz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: bicwrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrs_tbz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZW
+---
+name: bicwrs_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: bicwrs_tbnz
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZW
+---
+name: bicwrs_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 0
+ $w3 = ORRWri $w2, 4096
+ TBNZW $w0, 8, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: no_fuse_positive_shift_bicwrs
+# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZW
+---
+name: no_fuse_positive_shift_bicwrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1, $w2
+ $w0 = BICWrs $w0, $w1, 12
+ $w3 = ORRWri $w2, 4096
+ CBNZW $w0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxri_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: addxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxri_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: addxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxri_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
+---
+name: addxri_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxri_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
+---
+name: addxri_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXri $x0, 13, 0
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrr_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: addxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrr_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: addxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrr_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
+---
+name: addxrr_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrr_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
+---
+name: addxrr_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrs_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: addxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrs_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: addxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrs_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
+---
+name: addxrs_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: addxrs_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
+---
+name: addxrs_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: no_fuse_positive_shift_addxrs
+# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_addxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ADDXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxri_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: andxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxri_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: andxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxri_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
+---
+name: andxri_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxri_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
+---
+name: andxri_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrr_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: andxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrr_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: andxrr_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrr_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
+---
+name: andxrr_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrr_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
+---
+name: andxrr_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrs_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: andxrs_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrs_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: andxrs_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrs_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
+---
+name: andxrs_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: andxrs_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
+---
+name: andxrs_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: no_fuse_positive_shift_andxrs
+# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 12
+# CHECK: Successors:
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: no_fuse_positive_shift_andxrs
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = ANDXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorxri_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: eorxri_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorxri_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
+---
+name: eorxri_cbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorxri_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
+---
+name: eorxri_tbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorxri_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
+---
+name: eorxri_tbnz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXri $x0, 8192
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorxrr_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
+# CHECK: Successors:
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBZX
+---
+name: eorxrr_cbz
+tracksRegLiveness: true
+isSSA: false
+noVRegs: true
+body: |
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
+ bb.1:
+ RET undef $lr
+ bb.2:
+ RET undef $lr
+...
+
+# CHECK-LABEL: eorxrr_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: CBNZX
---
-name: subwrs_cbz
+name: eorxrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = SUBWrs $w0, $w1, 0
- $w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: subwrs_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 0
+# CHECK-LABEL: eorxrr_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBZX
---
-name: subwrs_cbnz
+name: eorxrr_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = SUBWrs $w0, $w1, 0
- $w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_subwrs
-# CHECK: SU({{[0-9]+}}): $w0 = SUBWrs $w0, $w1, 12
+# CHECK-LABEL: eorxrr_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
---
-name: no_fuse_positive_shift_subwrs
+name: eorxrr_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = SUBWrs $w0, $w1, 12
- $w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrr $x0, $x1
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: bicwrr_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK-LABEL: eorxrs_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: CBZX
---
-name: bicwrr_cbz
+name: eorxrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = BICWrr $w0, $w1
- $w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: bicwrr_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = BICWrr $w0, $w1
+# CHECK-LABEL: eorxrs_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: CBNZX
---
-name: bicwrr_cbnz
+name: eorxrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = BICWrr $w0, $w1
- $w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: bicwrs_cbz
-# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK-LABEL: eorxrs_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZW
+# CHECK: ExitSU: TBZX
---
-name: bicwrs_cbz
+name: eorxrs_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = BICWrs $w0, $w1, 0
- $w3 = ORRWri $w2, 4096
- CBZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: bicwrs_cbnz
-# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 0
+# CHECK-LABEL: eorxrs_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: TBNZX
---
-name: bicwrs_cbnz
+name: eorxrs_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = BICWrs $w0, $w1, 0
- $w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 0
+ $x3 = ORRXri $x2, 8192
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_bicwrs
-# CHECK: SU({{[0-9]+}}): $w0 = BICWrs $w0, $w1, 12
+# CHECK-LABEL: no_fuse_positive_shift_eorxrs
+# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 12
# CHECK: Successors:
# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZW
+# CHECK: ExitSU: CBNZX
---
-name: no_fuse_positive_shift_bicwrs
+name: no_fuse_positive_shift_eorxrs
tracksRegLiveness: true
isSSA: false
noVRegs: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: $w0, $w1, $w2
- $w0 = BICWrs $w0, $w1, 12
- $w3 = ORRWri $w2, 4096
- CBNZW $w0, %bb.2
+ liveins: $x0, $x1, $x2
+ $x0 = EORXrs $x0, $x1, 12
+ $x3 = ORRXri $x2, 8192
+ CBNZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: addxri_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK-LABEL: ornxrr_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZX
---
-name: addxri_cbz
+name: ornxrr_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1053,7 +2823,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ADDXri $x0, 13, 0
+ $x0 = ORNXrr $x0, $x1
$x3 = ORRXri $x2, 8192
CBZX $x0, %bb.2
bb.1:
@@ -1062,13 +2832,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: addxri_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ADDXri $x0, 13, 0
+# CHECK-LABEL: ornxrr_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: addxri_cbnz
+name: ornxrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1076,7 +2846,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ADDXri $x0, 13, 0
+ $x0 = ORNXrr $x0, $x1
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1085,13 +2855,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: addxrr_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK-LABEL: ornxrr_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBZX
---
-name: addxrr_cbz
+name: ornxrr_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1099,22 +2869,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ADDXrr $x0, $x1
+ $x0 = ORNXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: addxrr_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ADDXrr $x0, $x1
+# CHECK-LABEL: ornxrr_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: TBNZX
---
-name: addxrr_cbnz
+name: ornxrr_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1122,22 +2892,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ADDXrr $x0, $x1
+ $x0 = ORNXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: addxrs_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK-LABEL: ornxrs_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZX
---
-name: addxrs_cbz
+name: ornxrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1145,7 +2915,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ADDXrs $x0, $x1, 0
+ $x0 = ORNXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
CBZX $x0, %bb.2
bb.1:
@@ -1154,13 +2924,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: addxrs_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 0
+# CHECK-LABEL: ornxrs_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: addxrs_cbnz
+name: ornxrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1168,7 +2938,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ADDXrs $x0, $x1, 0
+ $x0 = ORNXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1177,13 +2947,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_addxrs
-# CHECK: SU({{[0-9]+}}): $x0 = ADDXrs $x0, $x1, 12
+# CHECK-LABEL: ornxrs_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
---
-name: no_fuse_positive_shift_addxrs
+name: ornxrs_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1191,22 +2961,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ADDXrs $x0, $x1, 12
+ $x0 = ORNXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andxri_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK-LABEL: ornxrs_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBNZX
---
-name: andxri_cbz
+name: ornxrs_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1214,22 +2984,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ANDXri $x0, 8192
+ $x0 = ORNXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andxri_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ANDXri $x0, 8192
+# CHECK-LABEL: no_fuse_positive_shift_ornxrs
+# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 12
# CHECK: Successors:
-# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: andxri_cbnz
+name: no_fuse_positive_shift_ornxrs
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1237,7 +3007,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ANDXri $x0, 8192
+ $x0 = ORNXrs $x0, $x1, 12
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1246,13 +3016,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: andxrr_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK-LABEL: orrxri_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZX
---
-name: andxrr_cbz
+name: orrxri_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1260,7 +3030,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ANDXrr $x0, $x1
+ $x0 = ORRXri $x0, 8192
$x3 = ORRXri $x2, 8192
CBZX $x0, %bb.2
bb.1:
@@ -1269,13 +3039,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: andxrr_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ANDXrr $x0, $x1
+# CHECK-LABEL: orrxri_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: andxrr_cbnz
+name: orrxri_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1283,7 +3053,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ANDXrr $x0, $x1
+ $x0 = ORRXri $x0, 8192
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1292,13 +3062,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: andxrs_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK-LABEL: orrxri_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBZX
---
-name: andxrs_cbz
+name: orrxri_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1306,45 +3076,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ANDXrs $x0, $x1, 0
+ $x0 = ORRXri $x0, 8192
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: andxrs_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 0
+# CHECK-LABEL: orrxri_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
----
-name: andxrs_cbnz
-tracksRegLiveness: true
-isSSA: false
-noVRegs: true
-body: |
- bb.0:
- successors: %bb.1, %bb.2
- liveins: $x0, $x1, $x2
- $x0 = ANDXrs $x0, $x1, 0
- $x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
- bb.1:
- RET undef $lr
- bb.2:
- RET undef $lr
-...
-
-# CHECK-LABEL: no_fuse_positive_shift_andxrs
-# CHECK: SU({{[0-9]+}}): $x0 = ANDXrs $x0, $x1, 12
-# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: TBNZX
---
-name: no_fuse_positive_shift_andxrs
+name: orrxri_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1352,22 +3099,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ANDXrs $x0, $x1, 12
+ $x0 = ORRXri $x0, 8192
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorxri_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK-LABEL: orrxrr_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZX
---
-name: eorxri_cbz
+name: orrxrr_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1375,7 +3122,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXri $x0, 8192
+ $x0 = ORRXrr $x0, $x1
$x3 = ORRXri $x2, 8192
CBZX $x0, %bb.2
bb.1:
@@ -1384,13 +3131,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: eorxri_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = EORXri $x0, 8192
+# CHECK-LABEL: orrxrr_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: eorxri_cbnz
+name: orrxrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1398,7 +3145,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXri $x0, 8192
+ $x0 = ORRXrr $x0, $x1
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1407,13 +3154,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: eorxrr_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
+# CHECK-LABEL: orrxrr_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBZX
---
-name: eorxrr_cbz
+name: orrxrr_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1421,22 +3168,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXrr $x0, $x1
+ $x0 = ORRXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorxrr_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = EORXrr $x0, $x1
+# CHECK-LABEL: orrxrr_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: TBNZX
---
-name: eorxrr_cbnz
+name: orrxrr_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1444,22 +3191,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXrr $x0, $x1
+ $x0 = ORRXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: eorxrs_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
+# CHECK-LABEL: orrxrs_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZX
---
-name: eorxrs_cbz
+name: orrxrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1467,7 +3214,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXrs $x0, $x1, 0
+ $x0 = ORRXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
CBZX $x0, %bb.2
bb.1:
@@ -1476,13 +3223,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: eorxrs_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 0
+# CHECK-LABEL: orrxrs_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: eorxrs_cbnz
+name: orrxrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1490,7 +3237,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXrs $x0, $x1, 0
+ $x0 = ORRXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1499,13 +3246,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_eorxrs
-# CHECK: SU({{[0-9]+}}): $x0 = EORXrs $x0, $x1, 12
+# CHECK-LABEL: orrxrs_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
---
-name: no_fuse_positive_shift_eorxrs
+name: orrxrs_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1513,22 +3260,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = EORXrs $x0, $x1, 12
+ $x0 = ORRXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: ornxrr_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1
+# CHECK-LABEL: orrxrs_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBNZX
---
-name: ornxrr_cbz
+name: orrxrs_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1536,22 +3283,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORNXrr $x0, $x1
+ $x0 = ORRXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: ornxrr_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ORNXrr $x0, $x1
+# CHECK-LABEL: no_fuse_positive_shift_orrxrs
+# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 12
# CHECK: Successors:
-# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: ornxrr_cbnz
+name: no_fuse_positive_shift_orrxrs
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1559,7 +3306,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORNXrr $x0, $x1
+ $x0 = ORRXrs $x0, $x1, 12
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1568,13 +3315,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: ornxrs_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0
+# CHECK-LABEL: subxri_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZX
---
-name: ornxrs_cbz
+name: subxri_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1582,7 +3329,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORNXrs $x0, $x1, 0
+ $x0 = SUBXri $x0, 13, 0
$x3 = ORRXri $x2, 8192
CBZX $x0, %bb.2
bb.1:
@@ -1591,13 +3338,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: ornxrs_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 0
+# CHECK-LABEL: subxri_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: ornxrs_cbnz
+name: subxri_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1605,7 +3352,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORNXrs $x0, $x1, 0
+ $x0 = SUBXri $x0, 13, 0
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1614,13 +3361,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_ornxrs
-# CHECK: SU({{[0-9]+}}): $x0 = ORNXrs $x0, $x1, 12
+# CHECK-LABEL: subxri_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBZX
---
-name: no_fuse_positive_shift_ornxrs
+name: subxri_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1628,22 +3375,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORNXrs $x0, $x1, 12
+ $x0 = SUBXri $x0, 13, 0
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: orrxri_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
+# CHECK-LABEL: subxri_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBNZX
---
-name: orrxri_cbz
+name: subxri_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1651,22 +3398,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXri $x0, 8192
+ $x0 = SUBXri $x0, 13, 0
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: orrxri_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ORRXri $x0, 8192
+# CHECK-LABEL: subxrr_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: CBZX
---
-name: orrxri_cbnz
+name: subxrr_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1674,22 +3421,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXri $x0, 8192
+ $x0 = SUBXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ CBZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: orrxrr_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
+# CHECK-LABEL: subxrr_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: CBNZX
---
-name: orrxrr_cbz
+name: subxrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1697,22 +3444,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXrr $x0, $x1
+ $x0 = SUBXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ CBNZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: orrxrr_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ORRXrr $x0, $x1
+# CHECK-LABEL: subxrr_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: TBZX
---
-name: orrxrr_cbnz
+name: subxrr_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1720,22 +3467,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXrr $x0, $x1
+ $x0 = SUBXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: orrxrs_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
+# CHECK-LABEL: subxrr_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBNZX
---
-name: orrxrs_cbz
+name: subxrr_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1743,22 +3490,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXrs $x0, $x1, 0
+ $x0 = SUBXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: orrxrs_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 0
+# CHECK-LABEL: subxrs_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: CBZX
---
-name: orrxrs_cbnz
+name: subxrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1766,22 +3513,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXrs $x0, $x1, 0
+ $x0 = SUBXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ CBZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_orrxrs
-# CHECK: SU({{[0-9]+}}): $x0 = ORRXrs $x0, $x1, 12
+# CHECK-LABEL: subxrs_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: no_fuse_positive_shift_orrxrs
+name: subxrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1789,7 +3536,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = ORRXrs $x0, $x1, 12
+ $x0 = SUBXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -1798,13 +3545,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: subxri_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
+# CHECK-LABEL: subxrs_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBZX
---
-name: subxri_cbz
+name: subxrs_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1812,22 +3559,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = SUBXri $x0, 13, 0
+ $x0 = SUBXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: subxri_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = SUBXri $x0, 13, 0
+# CHECK-LABEL: subxrs_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: TBNZX
---
-name: subxri_cbnz
+name: subxrs_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1835,22 +3582,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = SUBXri $x0, 13, 0
+ $x0 = SUBXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: subxrr_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
+# CHECK-LABEL: no_fuse_positive_shift_subxrs
+# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 12
# CHECK: Successors:
-# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: CBNZX
---
-name: subxrr_cbz
+name: no_fuse_positive_shift_subxrs
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1858,22 +3605,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = SUBXrr $x0, $x1
+ $x0 = SUBXrs $x0, $x1, 12
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ CBNZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: subxrr_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = SUBXrr $x0, $x1
+# CHECK-LABEL: bicxrr_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: CBZX
---
-name: subxrr_cbnz
+name: bicxrr_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1881,22 +3628,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = SUBXrr $x0, $x1
+ $x0 = BICXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ CBZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: subxrs_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
+# CHECK-LABEL: bicxrr_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: CBNZX
---
-name: subxrs_cbz
+name: bicxrr_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1904,22 +3651,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = SUBXrs $x0, $x1, 0
+ $x0 = BICXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ CBNZX $x0, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: subxrs_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 0
+# CHECK-LABEL: bicxrr_tbz
+# CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: TBZX
---
-name: subxrs_cbnz
+name: bicxrr_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1927,22 +3674,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = SUBXrs $x0, $x1, 0
+ $x0 = BICXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: no_fuse_positive_shift_subxrs
-# CHECK: SU({{[0-9]+}}): $x0 = SUBXrs $x0, $x1, 12
+# CHECK-LABEL: bicxrr_tbnz
+# CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
# CHECK: Successors:
-# CHECK-NOT: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
+# CHECK: ExitSU: TBNZX
---
-name: no_fuse_positive_shift_subxrs
+name: bicxrr_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1950,22 +3697,22 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = SUBXrs $x0, $x1, 12
+ $x0 = BICXrr $x0, $x1
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: bicxrr_cbz
-# CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
+# CHECK-LABEL: bicxrs_cbz
+# CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBZX
---
-name: bicxrr_cbz
+name: bicxrs_cbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1973,7 +3720,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = BICXrr $x0, $x1
+ $x0 = BICXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
CBZX $x0, %bb.2
bb.1:
@@ -1982,13 +3729,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: bicxrr_cbnz
-# CHECK: SU({{[0-9]+}}): $x0 = BICXrr $x0, $x1
+# CHECK-LABEL: bicxrs_cbnz
+# CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
# CHECK: ExitSU: CBNZX
---
-name: bicxrr_cbnz
+name: bicxrs_cbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -1996,7 +3743,7 @@ body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $x0, $x1, $x2
- $x0 = BICXrr $x0, $x1
+ $x0 = BICXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
CBNZX $x0, %bb.2
bb.1:
@@ -2005,13 +3752,13 @@ body: |
RET undef $lr
...
-# CHECK-LABEL: bicxrs_cbz
+# CHECK-LABEL: bicxrs_tbz
# CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBZX
+# CHECK: ExitSU: TBZX
---
-name: bicxrs_cbz
+name: bicxrs_tbz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -2021,20 +3768,20 @@ body: |
liveins: $x0, $x1, $x2
$x0 = BICXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBZX $x0, %bb.2
+ TBZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
RET undef $lr
...
-# CHECK-LABEL: bicxrs_cbnz
+# CHECK-LABEL: bicxrs_tbnz
# CHECK: SU({{[0-9]+}}): $x0 = BICXrs $x0, $x1, 0
# CHECK: Successors:
# CHECK: ExitSU: Ord Latency={{[0-9]+}} Cluster
-# CHECK: ExitSU: CBNZX
+# CHECK: ExitSU: TBNZX
---
-name: bicxrs_cbnz
+name: bicxrs_tbnz
tracksRegLiveness: true
isSSA: false
noVRegs: true
@@ -2044,7 +3791,7 @@ body: |
liveins: $x0, $x1, $x2
$x0 = BICXrs $x0, $x1, 0
$x3 = ORRXri $x2, 8192
- CBNZX $x0, %bb.2
+ TBNZX $x0, 32, %bb.2
bb.1:
RET undef $lr
bb.2:
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