[llvm] [RISCV] Use DCI.CombineTo instead of DAG.ReplaceAllUsesWith in performReverseEVLCombine. (PR #208275)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

This makes sure the replaced node is deleted without relying on it still being in the worklist, schedules its users for revisiting, and prints the debug message for the replacement.

---
Full diff: https://github.com/llvm/llvm-project/pull/208275.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+5-3) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1ba7f5eca7e69..1070cf7f6dbc8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -19886,8 +19886,10 @@ static auto m_ReverseEVL = [](auto X, auto EVL) {
 // TODO: A vlse.v is not necessarily faster than a vrgather.vv on all uarchs.
 // Remove once a cost model driven transform is implemented in the loop
 // vectorizer.
-static SDValue performReverseEVLCombine(SDNode *N, SelectionDAG &DAG,
+static SDValue performReverseEVLCombine(SDNode *N,
+                                        TargetLowering::DAGCombinerInfo &DCI,
                                         const RISCVSubtarget &Subtarget) {
+  SelectionDAG &DAG = DCI.DAG;
   // Fold:
   // vp.reverse(vp.load(ADDR, REVMASK, EVL), EVL)
   // -> vp.strided.load(ADDR, -1, MASK, EVL)
@@ -19966,7 +19968,7 @@ static SDValue performReverseEVLCombine(SDNode *N, SelectionDAG &DAG,
       LoadVT, DL, VPLoad->getChain(), Base, Stride, LoadMask,
       VPLoad->getVectorLength(), MMO, VPLoad->isExpandingLoad());
 
-  DAG.ReplaceAllUsesWith(VPLoad, Ret.getNode());
+  DCI.CombineTo(VPLoad, Ret.getValue(0), Ret.getValue(1));
 
   // Remove the top level reverse.
   (void)sd_match(N, m_ReverseEVL(m_Value(Op), m_Value()));
@@ -23235,7 +23237,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   }
   case ISD::VECTOR_SPLICE_RIGHT:
   case ISD::EXPERIMENTAL_VP_REVERSE:
-    return performReverseEVLCombine(N, DAG, Subtarget);
+    return performReverseEVLCombine(N, DCI, Subtarget);
   case ISD::VP_STORE:
     return performVP_STORECombine(N, DAG, Subtarget);
   case ISD::BITCAST: {

``````````

</details>


https://github.com/llvm/llvm-project/pull/208275