[llvm] [AMDGPU] revert srl pattern for true16 mode (PR #208136)

[Guo Chen via llvm-commits]

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@@ -201,6 +201,11 @@ define <10 x i16> @bitcast_i160_to_v10i16(i160 %int) {
 ; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
 ; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
 ; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
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broxigarchen wrote:

Yes there will be regressions. However, this srl pattern is close to perf neurtal so far without addressing https://github.com/llvm/llvm-project/issues/207011. In cases that we don't have 16bit use (i.e. pure 32bit VALU use case), remove this pattern improves code quality as it removes addtional `v_mov_b16 0`.

@Sisyph mentioned that there is an idea to impl an early remat of constants pre-RA which could resolve this register coaslcer side effects. Then I think we could add this pattern back after we have these two patches in place.

https://github.com/llvm/llvm-project/pull/208136