[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[via llvm-commits]

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@@ -1429,6 +1425,30 @@ class ZPRVectorListMul<int ElementWidth, int NumRegs, string RegClassSuffix = ""
                                  # "AArch64::ZPR" # RegClassSuffix # "RegClassID" # ">";
 }
 
+class ZPRVectorListMinMax<int ElementWidth, int NumRegs, int Min, int Max,
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Lukacma wrote:

Why can't we just reuse ZPRVectorListMul here ? (Of course we would need to change the naming if we went that route)

https://github.com/llvm/llvm-project/pull/200751