[llvm] [LLVM][CodeGen][SVE] Lower to multivector stores (PR #207397)

[Benjamin Maxwell via llvm-commits]

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@@ -204,26 +204,54 @@ define <vscale x 6 x half> @interleave3_nxv6f16(<vscale x 2 x half> %vec0, <vsca
 }
 
 define <vscale x 12 x half> @interleave3_nxv12f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1, <vscale x 4 x half> %vec2) {
-; CHECK-LABEL: interleave3_nxv12f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT:    addvl sp, sp, #-5
-; CHECK-NEXT:    .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x28, 0x1e, 0x22 // sp + 16 + 40 * VG
-; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    addpl x8, sp, #4
-; CHECK-NEXT:    st3w { z0.s - z2.s }, p0, [sp]
-; CHECK-NEXT:    ldr z0, [sp, #1, mul vl]
-; CHECK-NEXT:    ldr z1, [sp]
-; CHECK-NEXT:    ldr z2, [sp, #2, mul vl]
-; CHECK-NEXT:    uzp1 z0.h, z1.h, z0.h
-; CHECK-NEXT:    st1h { z2.s }, p0, [x8, #7, mul vl]
-; CHECK-NEXT:    str z0, [sp, #3, mul vl]
-; CHECK-NEXT:    ldr z1, [sp, #4, mul vl]
-; CHECK-NEXT:    ldr z0, [sp, #3, mul vl]
-; CHECK-NEXT:    addvl sp, sp, #5
-; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
-; CHECK-NEXT:    ret
+; SVE-LABEL: interleave3_nxv12f16:
+; SVE:       // %bb.0:
+; SVE-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
+; SVE-NEXT:    addvl sp, sp, #-5
+; SVE-NEXT:    .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x28, 0x1e, 0x22 // sp + 16 + 40 * VG
+; SVE-NEXT:    .cfi_offset w29, -16
+; SVE-NEXT:    ptrue p0.s
+; SVE-NEXT:    addpl x8, sp, #4
+; SVE-NEXT:    st3w { z0.s - z2.s }, p0, [sp]
+; SVE-NEXT:    ldr z0, [sp, #1, mul vl]
+; SVE-NEXT:    ldr z1, [sp]
+; SVE-NEXT:    ldr z2, [sp, #2, mul vl]
+; SVE-NEXT:    uzp1 z0.h, z1.h, z0.h
+; SVE-NEXT:    st1h { z2.s }, p0, [x8, #7, mul vl]
+; SVE-NEXT:    str z0, [sp, #3, mul vl]
+; SVE-NEXT:    ldr z1, [sp, #4, mul vl]
+; SVE-NEXT:    ldr z0, [sp, #3, mul vl]
+; SVE-NEXT:    addvl sp, sp, #5
+; SVE-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
+; SVE-NEXT:    ret
+;
+; SME2-LABEL: interleave3_nxv12f16:
+; SME2:       // %bb.0:
+; SME2-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
+; SME2-NEXT:    addvl sp, sp, #-1
+; SME2-NEXT:    str p8, [sp, #7, mul vl] // 2-byte Spill
+; SME2-NEXT:    addvl sp, sp, #-5
+; SME2-NEXT:    .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x30, 0x1e, 0x22 // sp + 16 + 48 * VG
+; SME2-NEXT:    .cfi_offset w29, -16
+; SME2-NEXT:    ptrue p0.s
+; SME2-NEXT:    ptrue pn8.h
+; SME2-NEXT:    addvl x8, sp, #1
+; SME2-NEXT:    st3w { z0.s - z2.s }, p0, [sp]
+; SME2-NEXT:    ldr z0, [sp, #1, mul vl]
+; SME2-NEXT:    ldr z1, [sp]
+; SME2-NEXT:    ldr z2, [sp, #2, mul vl]
+; SME2-NEXT:    uzp1 z0.h, z1.h, z0.h
+; SME2-NEXT:    st1h { z0.h, z1.h }, pn8, [x8, #2, mul vl]
----------------
MacDue wrote:

These changes look like a regression, but from looking at the DAG it's actually storing `undef`.


https://github.com/llvm/llvm-project/pull/207397