[llvm] adfb3be - [X86] Add vXi64 MULHU/MULHS lowering, keeping full-width products scalar (#206983)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 8 05:03:02 PDT 2026
Author: Rito Takeuchi
Date: 2026-07-08T12:02:54Z
New Revision: adfb3be9d098e4c12895957f9ac3fc9d892b45a9
URL: https://github.com/llvm/llvm-project/commit/adfb3be9d098e4c12895957f9ac3fc9d892b45a9
DIFF: https://github.com/llvm/llvm-project/commit/adfb3be9d098e4c12895957f9ac3fc9d892b45a9.diff
LOG: [X86] Add vXi64 MULHU/MULHS lowering, keeping full-width products scalar (#206983)
Based on the discussion in the PR #169819.
This lands the unsigned (`MULHU`) and signed (`MULHS`)
`vXi64` high-multiply lowering, plus a guard so full 128-bit products
stay scalar.
### What this does
1. **Lower `ISD::MULHU` for `v4i64`/`v8i64`** via `forceExpandMultiply`
(a `vpmuludq` schoolbook), as in #169819.
2. **Lower `ISD::MULHS` for `v4i64`/`v8i64`, gated on AVX512DQ.** The
signed low multiply is `vpmullq`, so `MULHS` is only marked `Custom`
when DQ (and VL for `v4i64`) is available.
3. **Guard the full-width-product case.** When the *low* half of the
product is also used (a `wyhash`-style `lo ^ hi`), vectorizing just the
high half is redundant with the low half's wide multiply. So, this guard
let a single scalar multiply per lane yield both halves, likewise the
unpatched target already did.
This is done by marking `UMUL_LOHI`/`SMUL_LOHI` `v4i64`/`v8i64` `Custom`
(unrolled), which lets the existing DAGCombiner check decline to narrow
`trunc(srl(mul(ext,ext)))` to `MULHU`/`MULHS` when the wide multiply's
low half is used.
### Performance
Same-IR A/B (identical IR, stock vs patched `llc`), EC2 metal,
per-target `-march`/`-mtune`, turbo off, one pinned core. ns/elem,
`stock → patched (ratio)`. Full matrix:
https://github.com/llvm/llvm-project/pull/206983#issuecomment-4871421534.
| kernel (AVX-512 256b) | Cascade | Ice Lake | SPR | Zen 4 |
|---|---|---|---|---|
| `udiv` (MULHU) | 1.71x | 1.71x | 1.78x | 1.88x |
| `div` (MULHS) | 1.18x | 1.25x | 1.31x | 2.04x |
| full-128 `lo ^ hi` (guarded) | 1.00x | 1.00x | 1.00x | 1.00x |
### Testing
- New `test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll`:
`umul_lohi_both_halves` (both halves used → scalarizes) and
`mulhu_high_only` (high only → vectorizes), on AVX2 and AVX-512.
- Existing `vector-idiv-{udiv,sdiv}-{256,512}.ll`, `urem-vector-lkk.ll`,
`srem-vector-lkk.ll` show the `MULHU`/`MULHS` vectorization (the signed
ones only on AVX512DQ RUN lines).
- No regressions across `test/CodeGen/X86`.
### AI Usage Disclosure
This PR was prepared with the assistance of Claude Code.
Fixes #37771
Added:
llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/srem-vector-lkk.ll
llvm/test/CodeGen/X86/urem-vector-lkk.ll
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5c37d9c63c24c..8278b08463e83 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -12699,7 +12699,7 @@ void TargetLowering::forceExpandMultiply(SelectionDAG &DAG, const SDLoc &dl,
// Hacker's Delight (itself derived from Knuth's Algorithm M from section
// 4.3.1). If Signed is set, we can use arithmetic right shifts to propagate
// sign bits while calculating the Hi half.
- unsigned Bits = VT.getSizeInBits();
+ unsigned Bits = VT.getScalarSizeInBits();
unsigned HalfBits = Bits / 2;
SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl, VT);
SDValue LL = DAG.getNode(ISD::AND, dl, VT, LHS, Mask);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 43fd5c02b4c56..84f22d7cc409a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1751,6 +1751,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
if (HasInt256) {
+ setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
+ // Custom so the combiner keeps full products as [SU]MUL_LOHI, not
+ // MULH[SU].
+ setOperationAction(ISD::UMUL_LOHI, MVT::v4i64, Custom);
+ setOperationAction(ISD::SMUL_LOHI, MVT::v4i64, Custom);
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
// Custom legalize 2x32 to get a little better code.
@@ -2024,6 +2029,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
setOperationAction(ISD::MUL, MVT::v64i8, Custom);
+ setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
+ setOperationAction(ISD::UMUL_LOHI, MVT::v8i64, Custom);
+ setOperationAction(ISD::SMUL_LOHI, MVT::v8i64, Custom);
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
@@ -2106,9 +2114,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_UINT})
setOperationAction(Opc, MVT::v8i64, Custom);
- if (Subtarget.hasDQI())
+ if (Subtarget.hasDQI()) {
setOperationAction(ISD::MUL, MVT::v8i64, Legal);
+ // MULHS needs vpmullq (AVX512DQ) for its low multiply to be a win.
+ setOperationAction(ISD::MULHS, MVT::v8i64, Custom);
+ }
+
if (Subtarget.hasCDI()) {
// NonVLX sub-targets extend 128/256 vectors to use the 512 version.
for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
@@ -2265,6 +2277,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
setOperationAction(ISD::MUL, MVT::v2i64, Legal);
setOperationAction(ISD::MUL, MVT::v4i64, Legal);
+
+ // MULHS is only a win when the low multiply can use vpmullq; non-VLX
+ // targets handle VPMULLQ by implicit widening.
+ setOperationAction(ISD::MULHS, MVT::v4i64, Custom);
}
if (Subtarget.hasCDI()) {
@@ -30387,6 +30403,13 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget,
if ((VT == MVT::v32i16 || VT == MVT::v64i8) && !Subtarget.hasBWI())
return splitVectorIntBinary(Op, DAG, dl);
+ if (VT.isVector() && VT.getVectorElementType() == MVT::i64) {
+ SDValue Lo, Hi;
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ TLI.forceExpandMultiply(DAG, dl, IsSigned, Lo, Hi, A, B);
+ return Hi;
+ }
+
if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) {
assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) ||
(VT == MVT::v8i32 && Subtarget.hasInt256()) ||
@@ -34445,6 +34468,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
case ISD::MULHS:
case ISD::MULHU: return LowerMULH(Op, Subtarget, DAG);
+ case ISD::SMUL_LOHI:
+ case ISD::UMUL_LOHI: return DAG.UnrollVectorOp(Op.getNode());
case ISD::ROTL:
case ISD::ROTR: return LowerRotate(Op, Subtarget, DAG);
case ISD::SRA:
diff --git a/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll b/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
new file mode 100644
index 0000000000000..d85cb16fbff2f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
@@ -0,0 +1,128 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,V3
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,V4
+
+; Guard for the vXi64 MULHU lowering. The `zext to i128 / mul / lshr 64 /
+; trunc` idiom below is exactly what the loop vectorizer emits for a full
+; 128-bit product (e.g. a wyhash-style `lo ^ hi` mix). When BOTH halves are
+; used (UMUL_LOHI), vectorizing the high half via the vpmuludq schoolbook loses
+; to scalar codegen, where one multiply yields both halves; the lowering must
+; back off and let it scalarize. When only the high half is used (the
+; divide-by-constant case), it must still vectorize.
+
+; Both halves used -> must scalarize (no vpmuludq schoolbook for the high half).
+define <4 x i64> @umul_lohi_both_halves(<4 x i64> %a, <4 x i64> %b, ptr %plo) nounwind {
+;
+; V3-LABEL: umul_lohi_both_halves:
+; V3: # %bb.0:
+; V3-NEXT: pushq %rbx
+; V3-NEXT: vpextrq $1, %xmm0, %rax
+; V3-NEXT: vextracti128 $1, %ymm0, %xmm2
+; V3-NEXT: vpextrq $1, %xmm2, %rcx
+; V3-NEXT: vpextrq $1, %xmm1, %r8
+; V3-NEXT: vmovq %xmm2, %rdx
+; V3-NEXT: vextracti128 $1, %ymm1, %xmm2
+; V3-NEXT: vpextrq $1, %xmm2, %r9
+; V3-NEXT: vmovq %xmm2, %rsi
+; V3-NEXT: mulxq %rsi, %r11, %r10
+; V3-NEXT: vmovq %xmm0, %rsi
+; V3-NEXT: movq %rcx, %rdx
+; V3-NEXT: mulxq %r9, %r9, %rcx
+; V3-NEXT: vmovq %xmm1, %rbx
+; V3-NEXT: movq %rsi, %rdx
+; V3-NEXT: mulxq %rbx, %rbx, %rsi
+; V3-NEXT: movq %rax, %rdx
+; V3-NEXT: mulxq %r8, %rdx, %rax
+; V3-NEXT: vmovq %rdx, %xmm0
+; V3-NEXT: vmovq %rbx, %xmm1
+; V3-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; V3-NEXT: vmovq %r9, %xmm0
+; V3-NEXT: vmovq %r11, %xmm2
+; V3-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; V3-NEXT: vmovq %rcx, %xmm0
+; V3-NEXT: vmovq %r10, %xmm3
+; V3-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; V3-NEXT: vmovq %rax, %xmm3
+; V3-NEXT: vmovq %rsi, %xmm4
+; V3-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; V3-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0
+; V3-NEXT: vmovdqa %xmm2, 16(%rdi)
+; V3-NEXT: vmovdqa %xmm1, (%rdi)
+; V3-NEXT: popq %rbx
+; V3-NEXT: retq
+;
+; V4-LABEL: umul_lohi_both_halves:
+; V4: # %bb.0:
+; V4-NEXT: pushq %rbx
+; V4-NEXT: vpextrq $1, %xmm0, %rax
+; V4-NEXT: vmovq %xmm0, %rcx
+; V4-NEXT: vextracti128 $1, %ymm0, %xmm0
+; V4-NEXT: vpextrq $1, %xmm0, %rsi
+; V4-NEXT: vpextrq $1, %xmm1, %r8
+; V4-NEXT: vmovq %xmm0, %rdx
+; V4-NEXT: vmovq %xmm1, %r9
+; V4-NEXT: vextracti128 $1, %ymm1, %xmm0
+; V4-NEXT: vpextrq $1, %xmm0, %r10
+; V4-NEXT: vmovq %xmm0, %r11
+; V4-NEXT: mulxq %r11, %rbx, %r11
+; V4-NEXT: movq %rsi, %rdx
+; V4-NEXT: mulxq %r10, %r10, %rsi
+; V4-NEXT: movq %rcx, %rdx
+; V4-NEXT: mulxq %r9, %r9, %rcx
+; V4-NEXT: movq %rax, %rdx
+; V4-NEXT: mulxq %r8, %rdx, %rax
+; V4-NEXT: vmovq %rdx, %xmm0
+; V4-NEXT: vmovq %r9, %xmm1
+; V4-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; V4-NEXT: vmovq %r10, %xmm0
+; V4-NEXT: vmovq %rbx, %xmm2
+; V4-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; V4-NEXT: vmovq %rsi, %xmm0
+; V4-NEXT: vmovq %r11, %xmm3
+; V4-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; V4-NEXT: vmovq %rax, %xmm3
+; V4-NEXT: vmovq %rcx, %xmm4
+; V4-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; V4-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0
+; V4-NEXT: vmovdqa %xmm2, 16(%rdi)
+; V4-NEXT: vmovdqa %xmm1, (%rdi)
+; V4-NEXT: popq %rbx
+; V4-NEXT: retq
+ %za = zext <4 x i64> %a to <4 x i128>
+ %zb = zext <4 x i64> %b to <4 x i128>
+ %prod = mul nuw <4 x i128> %za, %zb
+ %lo = trunc <4 x i128> %prod to <4 x i64>
+ %shift = lshr <4 x i128> %prod, <i128 64, i128 64, i128 64, i128 64>
+ %hi = trunc <4 x i128> %shift to <4 x i64>
+ store <4 x i64> %lo, ptr %plo
+ ret <4 x i64> %hi
+}
+
+; Only the high half used -> MULHU should still vectorize (vpmuludq schoolbook).
+define <4 x i64> @mulhu_high_only(<4 x i64> %a, <4 x i64> %b) nounwind {
+;
+; CHECK-LABEL: mulhu_high_only:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpsrlq $32, %ymm0, %ymm2
+; CHECK-NEXT: vpmuludq %ymm1, %ymm2, %ymm3
+; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm4
+; CHECK-NEXT: vpsrlq $32, %ymm4, %ymm4
+; CHECK-NEXT: vpaddq %ymm4, %ymm3, %ymm3
+; CHECK-NEXT: vpsrlq $32, %ymm3, %ymm4
+; CHECK-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; CHECK-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0],ymm5[1],ymm3[2],ymm5[3],ymm3[4],ymm5[5],ymm3[6],ymm5[7]
+; CHECK-NEXT: vpsrlq $32, %ymm1, %ymm1
+; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vpaddq %ymm3, %ymm0, %ymm0
+; CHECK-NEXT: vpsrlq $32, %ymm0, %ymm0
+; CHECK-NEXT: vpmuludq %ymm1, %ymm2, %ymm1
+; CHECK-NEXT: vpaddq %ymm4, %ymm1, %ymm1
+; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; CHECK-NEXT: retq
+ %za = zext <4 x i64> %a to <4 x i128>
+ %zb = zext <4 x i64> %b to <4 x i128>
+ %prod = mul nuw <4 x i128> %za, %zb
+ %shift = lshr <4 x i128> %prod, <i128 64, i128 64, i128 64, i128 64>
+ %hi = trunc <4 x i128> %shift to <4 x i64>
+ ret <4 x i64> %hi
+}
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index 678515c3e572e..be540704f6871 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -4,6 +4,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX,AVX512DQNOVL
define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; SSE2-LABEL: fold_srem_vec_1:
@@ -79,6 +80,21 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,65412,98,64533,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: fold_srem_vec_1:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,0,0,65535,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [44151,48623,2675,32081,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm1, %xmm2, %xmm1
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm1, %xmm2
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovdw %zmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,65412,98,64533,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1
}
@@ -225,6 +241,20 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: dont_fold_srem_power_of_two:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [32769,32769,32769,44151,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm0, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm1, %xmm2
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovdw %zmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1
}
@@ -309,6 +339,23 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: dont_fold_srem_one:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3 # [0,12827,45591,12375,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm3, %xmm2
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm2, %xmm3
+; AVX512DQNOVL-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm2, %ymm2
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512DQNOVL-NEXT: vpmovdw %zmm2, %ymm2
+; AVX512DQNOVL-NEXT: vpaddw %xmm1, %xmm2, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1
}
@@ -394,13 +441,30 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,32768,23,5423,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: dont_fold_urem_i16_smax:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,65535,1,0,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [0,32767,45591,12375,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm1, %xmm2, %xmm1
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm1, %xmm2
+; AVX512DQNOVL-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512DQNOVL-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3],xmm3[4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovdw %zmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,32768,23,5423,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
ret <4 x i16> %1
}
-; Don't fold i64 srem.
-define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
-; SSE2-LABEL: dont_fold_srem_i64:
+; Fold i64 srem on AVX2+ targets.
+define <4 x i64> @fold_srem_i64(<4 x i64> %x) {
+; SSE2-LABEL: fold_srem_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: movq %xmm1, %rcx
@@ -445,7 +509,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE2-NEXT: retq
;
-; SSE4-LABEL: dont_fold_srem_i64:
+; SSE4-LABEL: fold_srem_i64:
; SSE4: # %bb.0:
; SSE4-NEXT: movdqa %xmm1, %xmm2
; SSE4-NEXT: movq %xmm1, %rcx
@@ -488,7 +552,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE4-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE4-NEXT: retq
;
-; AVX1-LABEL: dont_fold_srem_i64:
+; AVX1-LABEL: fold_srem_i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rcx
@@ -532,93 +596,103 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: dont_fold_srem_i64:
+; AVX2-LABEL: fold_srem_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $4, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (%rdx,%rdx,2), %rax
-; AVX2-NEXT: shlq $3, %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2-NEXT: movabsq $6966426675817289639, %rcx # imm = 0x60ADB826E5E517A7
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: vmovq %rdx, %xmm2
+; AVX2-NEXT: vmovq %xmm1, %rax
+; AVX2-NEXT: movabsq $-5614226457215950491, %rcx # imm = 0xB21642C8590B2165
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: vmovq %rdx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2-NEXT: movabsq $7220743857598845893, %rcx # imm = 0x64353C48064353C5
+; AVX2-NEXT: imulq %rcx
; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $11, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $8, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
+; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm2[2,3],ymm0[4,5],ymm2[6,7]
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpsrlq $63, %ymm1, %ymm3
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1],ymm3[2,3,4,5,6,7]
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [9223372036854775808,36028797018963968,576460752303423488,4503599627370496]
+; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsubq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsllq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512-LABEL: dont_fold_srem_i64:
+; AVX512-LABEL: fold_srem_i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX512-NEXT: vmovq %xmm1, %rcx
-; AVX512-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: addq %rcx, %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $4, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: leaq (%rdx,%rdx,2), %rax
-; AVX512-NEXT: shlq $3, %rax
-; AVX512-NEXT: subq %rax, %rdx
-; AVX512-NEXT: addq %rcx, %rdx
-; AVX512-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX512-NEXT: vmovq %rdx, %xmm1
-; AVX512-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $11, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: vmovq %rcx, %xmm2
-; AVX512-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm2[0]
-; AVX512-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $8, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: vmovq %rcx, %xmm1
-; AVX512-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX512-NEXT: vpsraq $32, %ymm0, %ymm1
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm2 = [0,105075653,1493901669,3856996263]
+; AVX512-NEXT: vpmullq %ymm2, %ymm1, %ymm3
+; AVX512-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512-NEXT: vpsraq $32, %ymm2, %ymm3
+; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX512-NEXT: vpblendd {{.*#+}} ymm5 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7]
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1681210440,18446744072402387656,1621997606]
+; AVX512-NEXT: vpmullq %ymm6, %ymm5, %ymm5
+; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX512-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX512-NEXT: vpsraq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpmuldq %ymm6, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm4[2,3],ymm0[4,5],ymm4[6,7]
+; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3,4,5,6,7]
+; AVX512-NEXT: vpsravq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [1,654,23,5423]
+; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: fold_srem_i64:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512DQNOVL-NEXT: vpmovzxdq {{.*#+}} ymm1 = [0,105075653,1493901669,3856996263]
+; AVX512DQNOVL-NEXT: vpsraq $32, %zmm0, %zmm2
+; AVX512DQNOVL-NEXT: vpmullq %zmm1, %zmm2, %zmm3
+; AVX512DQNOVL-NEXT: vpmuludq %ymm1, %ymm0, %ymm1
+; AVX512DQNOVL-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddq %ymm1, %ymm3, %ymm1
+; AVX512DQNOVL-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm4 = ymm1[0],ymm3[1],ymm1[2],ymm3[3],ymm1[4],ymm3[5],ymm1[6],ymm3[7]
+; AVX512DQNOVL-NEXT: vpmovsxdq {{.*#+}} ymm5 = [0,1681210440,18446744072402387656,1621997606]
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm6 = ymm0[0],ymm3[1],ymm0[2],ymm3[3],ymm0[4],ymm3[5],ymm0[6],ymm3[7]
+; AVX512DQNOVL-NEXT: vpmullq %zmm5, %zmm6, %zmm6
+; AVX512DQNOVL-NEXT: vpaddq %ymm4, %ymm6, %ymm4
+; AVX512DQNOVL-NEXT: vpsraq $32, %zmm4, %zmm4
+; AVX512DQNOVL-NEXT: vpsraq $32, %zmm1, %zmm1
+; AVX512DQNOVL-NEXT: vpmuldq %ymm5, %ymm2, %ymm2
+; AVX512DQNOVL-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm2 = ymm0[0,1],ymm3[2,3],ymm0[4,5],ymm3[6,7]
+; AVX512DQNOVL-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddq %ymm4, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3,4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmovsxbq {{.*#+}} ymm3 = [0,8,4,11]
+; AVX512DQNOVL-NEXT: vpsravq %zmm3, %zmm1, %zmm1
+; AVX512DQNOVL-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
+; AVX512DQNOVL-NEXT: vpmullq %zmm2, %zmm1, %zmm1
+; AVX512DQNOVL-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
}
diff --git a/llvm/test/CodeGen/X86/urem-vector-lkk.ll b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
index 3faa2a0720d4e..7b3d0c9e12cfc 100644
--- a/llvm/test/CodeGen/X86/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
@@ -248,9 +248,9 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
ret <4 x i16> %1
}
-; Don't fold i64 urem.
-define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
-; SSE2-LABEL: dont_fold_urem_i64:
+; Fold i64 urem on AVX2+ targets.
+define <4 x i64> @fold_urem_i64(<4 x i64> %x) {
+; SSE2-LABEL: fold_urem_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: movq %xmm1, %rcx
@@ -290,7 +290,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE2-NEXT: retq
;
-; SSE4-LABEL: dont_fold_urem_i64:
+; SSE4-LABEL: fold_urem_i64:
; SSE4: # %bb.0:
; SSE4-NEXT: movq %xmm1, %rcx
; SSE4-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
@@ -328,7 +328,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; SSE4-NEXT: movdqa %xmm2, %xmm1
; SSE4-NEXT: retq
;
-; AVX1-LABEL: dont_fold_urem_i64:
+; AVX1-LABEL: fold_urem_i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rcx
@@ -367,80 +367,75 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: dont_fold_urem_i64:
+; AVX2-LABEL: fold_urem_i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rdx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $4, %rax
-; AVX2-NEXT: leaq (%rax,%rax,2), %rdx
-; AVX2-NEXT: shlq $3, %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rdx
-; AVX2-NEXT: shrq $12, %rdx
-; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX2-NEXT: mulq %rdx
-; AVX2-NEXT: shrq $7, %rdx
-; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm2
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm3 = [0,105075653,2987803337,3419025229]
+; AVX2-NEXT: vpmuludq %ymm3, %ymm2, %ymm4
+; AVX2-NEXT: vpmuludq %ymm3, %ymm1, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm3, %ymm3
+; AVX2-NEXT: vpaddq %ymm3, %ymm4, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm3, %ymm4
+; AVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0],ymm5[1],ymm3[2],ymm5[3],ymm3[4],ymm5[5],ymm3[6],ymm5[7]
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm5 = [0,1681210440,1680639376,3243995213]
+; AVX2-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm5, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm4, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm4 = [0,0,2147483648,0]
+; AVX2-NEXT: vpmuludq %ymm4, %ymm3, %ymm3
+; AVX2-NEXT: vpmuludq %ymm4, %ymm2, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsllq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512-LABEL: dont_fold_urem_i64:
+; AVX512-LABEL: fold_urem_i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX512-NEXT: vmovq %xmm1, %rdx
-; AVX512-NEXT: movabsq $7218291159277650633, %rax # imm = 0x642C8590B21642C9
-; AVX512-NEXT: mulxq %rax, %rax, %rax
-; AVX512-NEXT: movq %rdx, %rcx
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: shrq %rcx
-; AVX512-NEXT: addq %rax, %rcx
-; AVX512-NEXT: shrq $4, %rcx
-; AVX512-NEXT: leaq (%rcx,%rcx,2), %rax
-; AVX512-NEXT: shlq $3, %rax
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: addq %rdx, %rcx
-; AVX512-NEXT: vpextrq $1, %xmm1, %rdx
-; AVX512-NEXT: movabsq $-4513890722074972339, %rax # imm = 0xC15B704DCBCA2F4D
-; AVX512-NEXT: mulxq %rax, %rax, %rax
-; AVX512-NEXT: vmovq %rcx, %xmm1
-; AVX512-NEXT: shrq $12, %rax
-; AVX512-NEXT: imulq $5423, %rax, %rax # imm = 0x152F
-; AVX512-NEXT: subq %rax, %rdx
-; AVX512-NEXT: vmovq %rdx, %xmm2
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: movq %rax, %rdx
-; AVX512-NEXT: shrq %rdx
-; AVX512-NEXT: movabsq $7220743857598845893, %rcx # imm = 0x64353C48064353C5
-; AVX512-NEXT: mulxq %rcx, %rcx, %rcx
-; AVX512-NEXT: shrq $7, %rcx
-; AVX512-NEXT: imulq $654, %rcx, %rcx # imm = 0x28E
-; AVX512-NEXT: subq %rcx, %rax
-; AVX512-NEXT: vmovq %rax, %xmm0
-; AVX512-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
-; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX512-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX512-NEXT: vpsrlq $32, %ymm1, %ymm2
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm3 = [0,105075653,2987803337,3419025229]
+; AVX512-NEXT: vpmuludq %ymm3, %ymm2, %ymm4
+; AVX512-NEXT: vpmuludq %ymm3, %ymm1, %ymm3
+; AVX512-NEXT: vpsrlq $32, %ymm3, %ymm3
+; AVX512-NEXT: vpaddq %ymm3, %ymm4, %ymm3
+; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX512-NEXT: vpblendd {{.*#+}} ymm4 = ymm3[0],ymm4[1],ymm3[2],ymm4[3],ymm3[4],ymm4[5],ymm3[6],ymm4[7]
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm5 = [0,1681210440,1680639376,3243995213]
+; AVX512-NEXT: vpsrlq $32, %ymm3, %ymm3
+; AVX512-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm4, %ymm1, %ymm1
+; AVX512-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX512-NEXT: vpmuludq %ymm5, %ymm2, %ymm2
+; AVX512-NEXT: vpaddq %ymm3, %ymm2, %ymm2
+; AVX512-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm2
+; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm4 = [0,0,2147483648,0]
+; AVX512-NEXT: vpmuludq %ymm4, %ymm3, %ymm3
+; AVX512-NEXT: vpmuludq %ymm4, %ymm2, %ymm2
+; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpor %ymm2, %ymm3, %ymm2
+; AVX512-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX512-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX512-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [1,654,23,5423]
+; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index fa5692aa9cef1..9892ba039afba 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -45,42 +45,55 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: test_div7_4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rax
-; AVX2-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: retq
+; AVX2NOBW-LABEL: test_div7_4i64:
+; AVX2NOBW: # %bb.0:
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2NOBW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm1, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm1
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2NOBW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm0
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX2NOBW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpsrad $1, %ymm0, %ymm1
+; AVX2NOBW-NEXT: vpsrlq $1, %ymm0, %ymm2
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2],ymm1[3],ymm2[4],ymm1[5],ymm2[6],ymm1[7]
+; AVX2NOBW-NEXT: vpsrlq $63, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX2NOBW-NEXT: retq
+;
+; AVX512BW-LABEL: test_div7_4i64:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX512BW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm1, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm1
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX512BW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm0
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vpsrlq $63, %ymm0, %ymm1
+; AVX512BW-NEXT: vpsraq $1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: retq
%res = sdiv <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
@@ -389,58 +402,61 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: test_rem7_4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: retq
+; AVX2NOBW-LABEL: test_rem7_4i64:
+; AVX2NOBW: # %bb.0:
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2NOBW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm1, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm1
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2NOBW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm3
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX2NOBW-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsrad $1, %ymm1, %ymm2
+; AVX2NOBW-NEXT: vpsrlq $1, %ymm1, %ymm3
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3],ymm3[4],ymm2[5],ymm3[6],ymm2[7]
+; AVX2NOBW-NEXT: vpsrlq $63, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX2NOBW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: retq
+;
+; AVX512BW-LABEL: test_rem7_4i64:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX512BW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm1, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm1
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX512BW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm3
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX512BW-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512BW-NEXT: vpsraq $1, %zmm1, %zmm1
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX512BW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: retq
%res = srem <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index b11756a5e3b4e..051c4de4fb62a 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -13,69 +13,40 @@ define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vpextrq $1, %xmm1, %rax
; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vmovq %xmm1, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrq $1, %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX-NEXT: vpextrq $1, %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm0
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $63, %zmm0, %zmm1
+; AVX-NEXT: vpsraq $1, %zmm0, %zmm0
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = sdiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
@@ -278,104 +249,46 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_rem7_8i64:
; AVX: # %bb.0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm1, %rax
+; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %xmm1, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm0, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: vmovq %rdx, %xmm4
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; AVX-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1
+; AVX-NEXT: vpsrlq $63, %zmm1, %zmm2
+; AVX-NEXT: vpsraq $1, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsllq $3, %zmm1, %zmm2
+; AVX-NEXT: vpsubq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = srem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
index ca57359183312..37c416f18736a 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
@@ -49,39 +49,25 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
;
; AVX2-LABEL: test_div7_4i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm1
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2454267027,2454267027,2454267027,2454267027]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [613566756,613566756,613566756,613566756]
+; AVX2-NEXT: vpmuludq %ymm4, %ymm0, %ymm5
+; AVX2-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpmuludq %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0
+; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrlq $2, %ymm0, %ymm0
; AVX2-NEXT: retq
%res = udiv <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
@@ -423,59 +409,29 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
;
; AVX2-LABEL: test_rem7_4i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm1
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2454267027,2454267027,2454267027,2454267027]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [613566756,613566756,613566756,613566756]
+; AVX2-NEXT: vpmuludq %ymm4, %ymm0, %ymm5
+; AVX2-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpmuludq %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $1, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpsrlq $2, %ymm1, %ymm1
+; AVX2-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX2-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
%res = urem <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
index b8a131e628007..31d70041f9d0b 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
@@ -9,73 +9,24 @@
define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_div7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm1
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $32, %zmm0, %zmm1
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027]
+; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
+; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm3
+; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm4 = [613566756,613566756,613566756,613566756,613566756,613566756,613566756,613566756]
+; AVX-NEXT: vpmuludq %zmm4, %zmm0, %zmm5
+; AVX-NEXT: vpaddq %zmm2, %zmm5, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpmuludq %zmm4, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm3, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsubq %zmm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $1, %zmm0, %zmm0
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: vpsrlq $2, %zmm0, %zmm0
; AVX-NEXT: retq
%res = udiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
@@ -295,113 +246,28 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_rem7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm1
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $32, %zmm0, %zmm1
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027]
+; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
+; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm3
+; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm4 = [613566756,613566756,613566756,613566756,613566756,613566756,613566756,613566756]
+; AVX-NEXT: vpmuludq %zmm4, %zmm0, %zmm5
+; AVX-NEXT: vpaddq %zmm2, %zmm5, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpmuludq %zmm4, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm3, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsubq %zmm1, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $1, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm1, %zmm2, %zmm1
+; AVX-NEXT: vpsrlq $2, %zmm1, %zmm1
+; AVX-NEXT: vpsllq $3, %zmm1, %zmm2
+; AVX-NEXT: vpsubq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = urem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
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