[llvm] [RISCV] Don't overcost wide load in optimized segment load/store (PR #207146)

[Philip Reames via llvm-commits]

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@@ -1124,14 +1124,16 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
           TLI->isLegalInterleavedAccessType(SubVecTy, Factor, Alignment,
                                             AddressSpace, DL)) {
 
-        // Some processors optimize segment loads/stores as one wide memory op +
-        // Factor * LMUL shuffle ops.
+        // Some processors optimize segment loads/stores as N * DLEN sized
+        // load ops + Factor * LMUL shuffle ops.
         if (ST->hasOptimizedSegmentLoadStore(Factor)) {
-          InstructionCost Cost =
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preames wrote:

I'd have expected something more like Factor * getMemoryOpCost(Opcode, SubVecTy, Alignment, AddressSpace, CostKind).  Do they work out to roughly the same result?

https://github.com/llvm/llvm-project/pull/207146