[llvm] 35db7fd - [AMDGPU] Stop adding implicit def of superreg in copyPhysReg (#125255)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 7 08:01:17 PDT 2026
Author: Jay Foad
Date: 2026-07-07T16:01:04+01:00
New Revision: 35db7fd565138b4756193b36750f052e27359baf
URL: https://github.com/llvm/llvm-project/commit/35db7fd565138b4756193b36750f052e27359baf
DIFF: https://github.com/llvm/llvm-project/commit/35db7fd565138b4756193b36750f052e27359baf.diff
LOG: [AMDGPU] Stop adding implicit def of superreg in copyPhysReg (#125255)
Previously when copyPhysReg expanded a COPY into multiple MOV
instructions it added an implicit def of the destination superreg to the
first MOV. Removing these does not cause any liveness verification
problems and still passes Vulkan CTS for correctness testing.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
llvm/test/CodeGen/AMDGPU/add.ll
llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
llvm/test/CodeGen/AMDGPU/agpr-csr.ll
llvm/test/CodeGen/AMDGPU/always-uniform.ll
llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
llvm/test/CodeGen/AMDGPU/and.ll
llvm/test/CodeGen/AMDGPU/andorn2.ll
llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
llvm/test/CodeGen/AMDGPU/bfi_int.ll
llvm/test/CodeGen/AMDGPU/bitreverse.ll
llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
llvm/test/CodeGen/AMDGPU/build_vector.ll
llvm/test/CodeGen/AMDGPU/call-argument-types.ll
llvm/test/CodeGen/AMDGPU/calling-conventions.ll
llvm/test/CodeGen/AMDGPU/carryout-selection.ll
llvm/test/CodeGen/AMDGPU/cluster_stores.ll
llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
llvm/test/CodeGen/AMDGPU/ctlz.ll
llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
llvm/test/CodeGen/AMDGPU/ctpop64.ll
llvm/test/CodeGen/AMDGPU/cttz.ll
llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
llvm/test/CodeGen/AMDGPU/dag-divergence.ll
llvm/test/CodeGen/AMDGPU/div_i128.ll
llvm/test/CodeGen/AMDGPU/div_v2i128.ll
llvm/test/CodeGen/AMDGPU/ds_read2.ll
llvm/test/CodeGen/AMDGPU/ds_write2.ll
llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
llvm/test/CodeGen/AMDGPU/fabs.f16.ll
llvm/test/CodeGen/AMDGPU/fabs.ll
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
llvm/test/CodeGen/AMDGPU/fceil64.ll
llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
llvm/test/CodeGen/AMDGPU/fdiv.ll
llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
llvm/test/CodeGen/AMDGPU/flat-scratch.ll
llvm/test/CodeGen/AMDGPU/flat_atomics.ll
llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
llvm/test/CodeGen/AMDGPU/fmaximum.ll
llvm/test/CodeGen/AMDGPU/fmaxnum.ll
llvm/test/CodeGen/AMDGPU/fmed3.ll
llvm/test/CodeGen/AMDGPU/fminimum.ll
llvm/test/CodeGen/AMDGPU/fminnum.ll
llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
llvm/test/CodeGen/AMDGPU/fnearbyint.ll
llvm/test/CodeGen/AMDGPU/fneg-combines.ll
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
llvm/test/CodeGen/AMDGPU/fneg.f16.ll
llvm/test/CodeGen/AMDGPU/fneg.ll
llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
llvm/test/CodeGen/AMDGPU/frem.ll
llvm/test/CodeGen/AMDGPU/fshl.ll
llvm/test/CodeGen/AMDGPU/fshr.ll
llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
llvm/test/CodeGen/AMDGPU/global_atomics.ll
llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
llvm/test/CodeGen/AMDGPU/half.ll
llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
llvm/test/CodeGen/AMDGPU/itofp.i128.ll
llvm/test/CodeGen/AMDGPU/kernel-args.ll
llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
llvm/test/CodeGen/AMDGPU/llvm.exp.ll
llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
llvm/test/CodeGen/AMDGPU/llvm.log.ll
llvm/test/CodeGen/AMDGPU/llvm.log10.ll
llvm/test/CodeGen/AMDGPU/llvm.log2.ll
llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
llvm/test/CodeGen/AMDGPU/load-global-f32.ll
llvm/test/CodeGen/AMDGPU/load-global-i16.ll
llvm/test/CodeGen/AMDGPU/load-global-i32.ll
llvm/test/CodeGen/AMDGPU/load-global-i8.ll
llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
llvm/test/CodeGen/AMDGPU/mad_64_32.ll
llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
llvm/test/CodeGen/AMDGPU/memory_clause.ll
llvm/test/CodeGen/AMDGPU/memset-pattern.ll
llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
llvm/test/CodeGen/AMDGPU/mfma-loop.ll
llvm/test/CodeGen/AMDGPU/min.ll
llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
llvm/test/CodeGen/AMDGPU/or.ll
llvm/test/CodeGen/AMDGPU/packed-fp64.ll
llvm/test/CodeGen/AMDGPU/packed-u64.ll
llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
llvm/test/CodeGen/AMDGPU/rem_i128.ll
llvm/test/CodeGen/AMDGPU/rotl.ll
llvm/test/CodeGen/AMDGPU/rotr.ll
llvm/test/CodeGen/AMDGPU/sad.ll
llvm/test/CodeGen/AMDGPU/saddo.ll
llvm/test/CodeGen/AMDGPU/sdiv64.ll
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
llvm/test/CodeGen/AMDGPU/sign_extend.ll
llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
llvm/test/CodeGen/AMDGPU/spill-agpr.ll
llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
llvm/test/CodeGen/AMDGPU/srem.ll
llvm/test/CodeGen/AMDGPU/srem64.ll
llvm/test/CodeGen/AMDGPU/ssubo.ll
llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
llvm/test/CodeGen/AMDGPU/store-local.128.ll
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
llvm/test/CodeGen/AMDGPU/sub.ll
llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
llvm/test/CodeGen/AMDGPU/swdev380865.ll
llvm/test/CodeGen/AMDGPU/trap-abis.ll
llvm/test/CodeGen/AMDGPU/trunc.ll
llvm/test/CodeGen/AMDGPU/uaddo.ll
llvm/test/CodeGen/AMDGPU/udiv.ll
llvm/test/CodeGen/AMDGPU/udiv64.ll
llvm/test/CodeGen/AMDGPU/udivrem.ll
llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
llvm/test/CodeGen/AMDGPU/urem64.ll
llvm/test/CodeGen/AMDGPU/usubo.ll
llvm/test/CodeGen/AMDGPU/v_cndmask.ll
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
llvm/test/CodeGen/AMDGPU/valu-i1.ll
llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
llvm/test/CodeGen/AMDGPU/wave32.ll
llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
llvm/test/CodeGen/AMDGPU/wqm.ll
llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
llvm/test/CodeGen/AMDGPU/xor.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 3eeb4cb474e43..e945db946c158 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -623,13 +623,11 @@ static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,
/// Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908. It is not
/// possible to have a direct copy in these cases on GFX908, so an intermediate
/// VGPR copy is required.
-static void indirectCopyToAGPR(const SIInstrInfo &TII,
- MachineBasicBlock &MBB,
+static void indirectCopyToAGPR(const SIInstrInfo &TII, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
RegScavenger &RS, bool RegsOverlap,
- Register ImpDefSuperReg = Register(),
Register ImpUseSuperReg = Register()) {
assert((TII.getSubtarget().hasMAIInsts() &&
!TII.getSubtarget().hasGFX90AInsts()) &&
@@ -678,10 +676,9 @@ static void indirectCopyToAGPR(const SIInstrInfo &TII,
}
MachineInstrBuilder Builder =
- BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
- .add(DefOp);
- if (ImpDefSuperReg)
- Builder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
+ BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64),
+ DestReg)
+ .add(DefOp);
if (ImpUseSuperReg) {
Builder.addReg(ImpUseSuperReg,
@@ -735,12 +732,8 @@ static void indirectCopyToAGPR(const SIInstrInfo &TII,
getKillRegState(KillSrc) | RegState::Implicit);
}
- MachineInstrBuilder DefBuilder
- = BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
- .addReg(Tmp, RegState::Kill);
-
- if (ImpDefSuperReg)
- DefBuilder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
+ BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
+ .addReg(Tmp, RegState::Kill);
}
static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
@@ -788,9 +781,6 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
if (!Forward)
std::swap(FirstMI, LastMI);
- FirstMI->addOperand(
- MachineOperand::CreateReg(DestReg, true /*IsDef*/, true /*IsImp*/));
-
if (KillSrc)
LastMI->addRegisterKilled(SrcReg, &RI);
}
@@ -1103,34 +1093,27 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
- bool IsFirstSubreg = Idx == 0;
bool UseKill = CanKillSuperReg && Idx == SubIndices.size() - 1;
if (Opcode == AMDGPU::INSTRUCTION_LIST_END) {
- Register ImpDefSuper = IsFirstSubreg ? Register(DestReg) : Register();
Register ImpUseSuper = SrcReg;
indirectCopyToAGPR(*this, MBB, MI, DL, DestSubReg, SrcSubReg, UseKill,
- *RS, Overlap, ImpDefSuper, ImpUseSuper);
+ *RS, Overlap, ImpUseSuper);
} else if (Opcode == AMDGPU::V_PK_MOV_B32) {
- MachineInstrBuilder MIB =
- BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestSubReg)
- .addImm(SISrcMods::OP_SEL_1)
- .addReg(SrcSubReg)
- .addImm(SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1)
- .addReg(SrcSubReg)
- .addImm(0) // op_sel_lo
- .addImm(0) // op_sel_hi
- .addImm(0) // neg_lo
- .addImm(0) // neg_hi
- .addImm(0) // clamp
- .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
- if (IsFirstSubreg)
- MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
+ BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestSubReg)
+ .addImm(SISrcMods::OP_SEL_1)
+ .addReg(SrcSubReg)
+ .addImm(SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1)
+ .addReg(SrcSubReg)
+ .addImm(0) // op_sel_lo
+ .addImm(0) // op_sel_hi
+ .addImm(0) // neg_lo
+ .addImm(0) // neg_hi
+ .addImm(0) // clamp
+ .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
} else {
MachineInstrBuilder Builder =
BuildMI(MBB, MI, DL, get(Opcode), DestSubReg).addReg(SrcSubReg);
- if (IsFirstSubreg)
- Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
index 262254c8a9cf7..d9da42ccbc5e2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
@@ -449,9 +449,9 @@ define void @s_uaddo_uadde(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s4, s16, s18
; GFX7-NEXT: s_addc_u32 s5, s17, s19
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_cselect_b32 s8, 1, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
@@ -466,8 +466,8 @@ define void @s_uaddo_uadde(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_add_u32 s4, s16, s18
; GFX9-NEXT: s_addc_u32 s5, s17, s19
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[4:5], off
; GFX9-NEXT: v_mov_b32_e32 v0, s6
@@ -480,8 +480,8 @@ define void @s_uaddo_uadde(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s4, s16, s18
; GFX8-NEXT: s_addc_u32 s5, s17, s19
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
; GFX8-NEXT: v_mov_b32_e32 v0, s6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
index 24daeded8be45..c1096859e98a4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
@@ -694,8 +694,8 @@ define amdgpu_ps i64 @s_saddo_i64(i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_saddo_i64:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_add_u32 s4, s0, s2
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: s_addc_u32 s5, s1, s3
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX7-NEXT: s_or_b64 s[0:1], vcc, vcc
@@ -713,8 +713,8 @@ define amdgpu_ps i64 @s_saddo_i64(i64 inreg %a, i64 inreg %b) {
; GFX8-LABEL: s_saddo_i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s4, s0, s2
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s5, s1, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
@@ -732,8 +732,8 @@ define amdgpu_ps i64 @s_saddo_i64(i64 inreg %a, i64 inreg %b) {
; GFX9-LABEL: s_saddo_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s4, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s5, s1, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
index 4cb566721348f..ae58ba0cf57ab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-atomic-optimizer %s | FileCheck -check-prefix=IR %s
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
@@ -96,8 +96,8 @@ define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -192,8 +192,8 @@ define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -294,8 +294,8 @@ define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) {
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: v_xor_b32_e32 v4, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -392,8 +392,8 @@ define amdgpu_cs void @atomic_ptr_add_and_format(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -492,8 +492,8 @@ define amdgpu_cs void @atomic_ptr_sub_and_format(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -598,8 +598,8 @@ define amdgpu_cs void @atomic_ptr_xor_and_format(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: v_xor_b32_e32 v4, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
index 0899fbc14faf5..a3d5f1ee66ad3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
@@ -1838,9 +1838,9 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1884,9 +1884,9 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
index 5f8c44e87f30a..a534dd306cb47 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
@@ -1838,9 +1838,9 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1884,9 +1884,9 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
index a346de54fce15..8add3cbf73e14 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
@@ -25,9 +25,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i32(ptr addrspace(1) %out, ptr add
; CI-NEXT: v_mov_b32_e32 v1, s2
; CI-NEXT: ds_dec_rtn_u32 v2, v1, v0
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
@@ -43,9 +43,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i32(ptr addrspace(1) %out, ptr add
; VI-NEXT: v_mov_b32_e32 v1, s2
; VI-NEXT: ds_dec_rtn_u32 v2, v1, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -108,9 +108,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i32_offset(ptr addrspace(1) %out,
; CI-NEXT: v_mov_b32_e32 v1, s2
; CI-NEXT: ds_dec_rtn_u32 v2, v1, v0 offset:16
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
@@ -126,9 +126,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i32_offset(ptr addrspace(1) %out,
; VI-NEXT: v_mov_b32_e32 v1, s2
; VI-NEXT: ds_dec_rtn_u32 v2, v1, v0 offset:16
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -1109,9 +1109,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(ptr %out, ptr %ptr) #1
; GFX11-LABEL: flat_atomic_dec_ret_i32_offset:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: flat_atomic_dec_u32 v2, v[0:1], v2 offset:16 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1208,9 +1208,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_system(ptr %out, ptr %
; GFX11-LABEL: flat_atomic_dec_ret_i32_offset_system:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: flat_atomic_dec_u32 v2, v[0:1], v2 offset:16 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1375,9 +1375,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(ptr %ptr) #1 {
; GFX11-LABEL: flat_atomic_dec_noret_i32_offset:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: flat_atomic_dec_u32 v[0:1], v2 offset:16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1461,9 +1461,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_system(ptr %ptr) #1
; GFX11-LABEL: flat_atomic_dec_noret_i32_offset_system:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: flat_atomic_dec_u32 v[0:1], v2 offset:16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1579,10 +1579,10 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(ptr %out, ptr %
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-NEXT: v_dual_mov_b32 v3, 42 :: v_dual_and_b32 v0, 0x3ff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -1689,11 +1689,11 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(ptr %ptr) #1
; GFX11-LABEL: flat_atomic_dec_noret_i32_offset_addr64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -1719,9 +1719,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(ptr %out, ptr %ptr) #1 {
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v2, s2
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1743,9 +1743,9 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64(ptr %out, ptr %ptr) #1 {
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1828,8 +1828,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(ptr %out, ptr %ptr) #1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1854,8 +1854,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(ptr %out, ptr %ptr) #1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1938,9 +1938,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(ptr %ptr) #1 {
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v3, s1
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1954,9 +1954,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64(ptr %ptr) #1 {
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2024,8 +2024,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(ptr %ptr) #1 {
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2042,8 +2042,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(ptr %ptr) #1 {
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2077,8 +2077,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(ptr %ptr) #1 {
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_u32 s0, s0, 32
; GFX10-NEXT: s_addc_u32 s1, s1, 0
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
@@ -2114,8 +2114,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_system(ptr %ptr) #1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2132,8 +2132,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_system(ptr %ptr) #1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2167,8 +2167,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_system(ptr %ptr) #1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_u32 s0, s0, 32
; GFX10-NEXT: s_addc_u32 s1, s1, 0
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
@@ -2213,8 +2213,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(ptr %out, ptr %
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: buffer_wbinvl1_vol
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: v_add_i32_e32 v4, vcc, 4, v2
@@ -2242,8 +2242,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(ptr %out, ptr %
; VI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_wbinvl1_vol
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v2
@@ -2260,16 +2260,16 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(ptr %out, ptr %
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 42
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
; GFX9-NEXT: flat_atomic_dec_x2 v[0:1], v[3:4], v[1:2] offset:40 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2296,8 +2296,8 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(ptr %out, ptr %
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2308,10 +2308,10 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(ptr %out, ptr %
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_lshlrev_b32 v4, 3, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -2319,7 +2319,7 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(ptr %out, ptr %
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
@@ -2385,8 +2385,8 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(ptr %ptr) #1
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 42
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
; GFX9-NEXT: v_mov_b32_e32 v3, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, s1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
@@ -2424,10 +2424,10 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(ptr %ptr) #1
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 3, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -2455,10 +2455,10 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(ptr addrspace(1) %out, ptr
; CI-NEXT: ds_dec_rtn_u32 v2, v1, v2 offset:8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_add_i32_e32 v3, vcc, 2, v0
-; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_add_i32_e32 v3, vcc, 2, v0
+; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: flat_store_dword v[0:1], v3
; CI-NEXT: v_mov_b32_e32 v0, s0
@@ -2476,10 +2476,10 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(ptr addrspace(1) %out, ptr
; VI-NEXT: ds_dec_rtn_u32 v2, v1, v2 offset:8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_add_u32_e32 v3, vcc, 2, v0
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_add_u32_e32 v3, vcc, 2, v0
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -2554,9 +2554,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i64(ptr addrspace(1) %out, ptr add
; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -2573,9 +2573,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i64(ptr addrspace(1) %out, ptr add
; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1]
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -2642,9 +2642,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i64_offset(ptr addrspace(1) %out,
; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1] offset:32
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -2661,9 +2661,9 @@ define amdgpu_kernel void @lds_atomic_dec_ret_i64_offset(ptr addrspace(1) %out,
; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1] offset:32
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -2851,9 +2851,9 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64(ptr addrspace(1) %out, ptr
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v2, s2
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -2870,9 +2870,9 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -2937,8 +2937,8 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(ptr addrspace(1) %ou
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -2958,8 +2958,8 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3025,8 +3025,8 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_system(ptr addrspace
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3046,8 +3046,8 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_system(ptr addrspace
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3110,9 +3110,9 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64(ptr addrspace(1) %ptr) #1
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v3, s1
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3126,9 +3126,9 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64(ptr addrspace(1) %ptr) #1
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3186,8 +3186,8 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset(ptr addrspace(1) %
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3204,8 +3204,8 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset(ptr addrspace(1) %
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3264,8 +3264,8 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_system(ptr addrspa
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3282,8 +3282,8 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_system(ptr addrspa
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_dec_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3351,8 +3351,8 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(ptr addrspace
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: buffer_wbinvl1_vol
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -3377,8 +3377,8 @@ define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(ptr addrspace
; VI-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_wbinvl1_vol
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -3534,10 +3534,10 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(ptr addrspace(1) %out,
; CI-NEXT: ds_dec_rtn_u64 v[1:2], v3, v[1:2] offset:16
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v4, s3
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: v_mov_b32_e32 v4, s3
; CI-NEXT: v_mov_b32_e32 v3, s2
; CI-NEXT: flat_store_dword v[3:4], v0
; CI-NEXT: v_mov_b32_e32 v4, s1
@@ -3556,10 +3556,10 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(ptr addrspace(1) %out,
; VI-NEXT: ds_dec_rtn_u64 v[1:2], v3, v[1:2] offset:16
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v4, s3
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: v_mov_b32_e32 v4, s3
; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: flat_store_dword v[3:4], v0
; VI-NEXT: v_mov_b32_e32 v4, s1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
index 20d7c9218105d..1f2edfaf00c1b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
@@ -26,9 +26,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i32(ptr addrspace(1) %out, ptr add
; CI-NEXT: v_mov_b32_e32 v1, s2
; CI-NEXT: ds_inc_rtn_u32 v2, v1, v0
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
@@ -44,9 +44,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i32(ptr addrspace(1) %out, ptr add
; VI-NEXT: v_mov_b32_e32 v1, s2
; VI-NEXT: ds_inc_rtn_u32 v2, v1, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -121,9 +121,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i32_offset(ptr addrspace(1) %out,
; CI-NEXT: v_mov_b32_e32 v1, s2
; CI-NEXT: ds_inc_rtn_u32 v2, v1, v0 offset:16
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
@@ -139,9 +139,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i32_offset(ptr addrspace(1) %out,
; VI-NEXT: v_mov_b32_e32 v1, s2
; VI-NEXT: ds_inc_rtn_u32 v2, v1, v0 offset:16
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -1082,10 +1082,10 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(ptr addrspace(1) %out,
; CI-NEXT: ds_inc_rtn_u32 v2, v1, v2 offset:8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_add_i32_e32 v3, vcc, 2, v0
-; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_add_i32_e32 v3, vcc, 2, v0
+; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: flat_store_dword v[0:1], v3
; CI-NEXT: v_mov_b32_e32 v0, s0
@@ -1103,10 +1103,10 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(ptr addrspace(1) %out,
; VI-NEXT: ds_inc_rtn_u32 v2, v1, v2 offset:8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_add_u32_e32 v3, vcc, 2, v0
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_add_u32_e32 v3, vcc, 2, v0
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -1198,9 +1198,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i64(ptr addrspace(1) %out, ptr add
; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -1217,9 +1217,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i64(ptr addrspace(1) %out, ptr add
; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1]
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -1299,9 +1299,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(ptr addrspace(1) %out,
; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:32
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -1318,9 +1318,9 @@ define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(ptr addrspace(1) %out,
; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:32
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -1543,9 +1543,9 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64(ptr addrspace(1) %out, ptr
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v2, s2
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1562,9 +1562,9 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1641,8 +1641,8 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(ptr addrspace(1) %ou
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1662,8 +1662,8 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1741,8 +1741,8 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_system(ptr addrspace
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1762,8 +1762,8 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_system(ptr addrspace
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1840,9 +1840,9 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64(ptr addrspace(1) %ptr) #1
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v3, s1
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1856,9 +1856,9 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64(ptr addrspace(1) %ptr) #1
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1927,8 +1927,8 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset(ptr addrspace(1) %
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1945,8 +1945,8 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset(ptr addrspace(1) %
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -2016,8 +2016,8 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_system(ptr addrspa
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -2034,8 +2034,8 @@ define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_system(ptr addrspa
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -2116,8 +2116,8 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(ptr addrspace
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: buffer_wbinvl1_vol
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2142,8 +2142,8 @@ define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(ptr addrspace
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_wbinvl1_vol
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -2502,9 +2502,9 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(ptr %out, ptr %ptr) #1
; GFX11-LABEL: flat_atomic_inc_ret_i32_offset:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: flat_atomic_inc_u32 v2, v[0:1], v2 offset:16 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -2516,9 +2516,9 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(ptr %out, ptr %ptr) #1
; GFX12-LABEL: flat_atomic_inc_ret_i32_offset:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 42
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: flat_atomic_inc_u32 v2, v[0:1], v2 offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -2614,9 +2614,9 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_system(ptr %out, ptr %
; GFX11-LABEL: flat_atomic_inc_ret_i32_offset_system:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: flat_atomic_inc_u32 v2, v[0:1], v2 offset:16 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -2628,9 +2628,9 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_system(ptr %out, ptr %
; GFX12-LABEL: flat_atomic_inc_ret_i32_offset_system:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 42
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_inc_u32 v2, v[0:1], v2 offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -2807,9 +2807,9 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(ptr %ptr) #1 {
; GFX11-LABEL: flat_atomic_inc_noret_i32_offset:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: flat_atomic_inc_u32 v[0:1], v2 offset:16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -2820,9 +2820,9 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(ptr %ptr) #1 {
; GFX12-LABEL: flat_atomic_inc_noret_i32_offset:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 42
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: flat_atomic_inc_u32 v[0:1], v2 offset:16 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -2904,9 +2904,9 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_system(ptr %ptr) #1
; GFX11-LABEL: flat_atomic_inc_noret_i32_offset_system:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: flat_atomic_inc_u32 v[0:1], v2 offset:16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -2917,9 +2917,9 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_system(ptr %ptr) #1
; GFX12-LABEL: flat_atomic_inc_noret_i32_offset_system:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 42
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_inc_u32 v[0:1], v2 offset:16 scope:SCOPE_SYS
@@ -3035,10 +3035,10 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(ptr %out, ptr %
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-NEXT: v_dual_mov_b32 v3, 42 :: v_dual_and_b32 v0, 0x3ff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -3057,10 +3057,10 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(ptr %out, ptr %
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-NEXT: v_dual_mov_b32 v3, 42 :: v_dual_and_b32 v0, 0x3ff, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -3167,11 +3167,11 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(ptr %ptr) #1
; GFX11-LABEL: flat_atomic_inc_noret_i32_offset_addr64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -3186,11 +3186,11 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(ptr %ptr) #1
; GFX12-LABEL: flat_atomic_inc_noret_i32_offset_addr64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -3218,10 +3218,10 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(ptr addrspace(1) %out,
; CI-NEXT: ds_inc_rtn_u64 v[1:2], v3, v[1:2] offset:16
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_i32 s12, s12, s17
-; CI-NEXT: v_mov_b32_e32 v4, s3
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: v_mov_b32_e32 v4, s3
; CI-NEXT: v_mov_b32_e32 v3, s2
; CI-NEXT: flat_store_dword v[3:4], v0
; CI-NEXT: v_mov_b32_e32 v4, s1
@@ -3240,10 +3240,10 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(ptr addrspace(1) %out,
; VI-NEXT: ds_inc_rtn_u64 v[1:2], v3, v[1:2] offset:16
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_i32 s12, s12, s17
-; VI-NEXT: v_mov_b32_e32 v4, s3
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: v_mov_b32_e32 v4, s3
; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: flat_store_dword v[3:4], v0
; VI-NEXT: v_mov_b32_e32 v4, s1
@@ -3334,9 +3334,9 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64(ptr %out, ptr %ptr) #1 {
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v2, s2
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3358,9 +3358,9 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64(ptr %out, ptr %ptr) #1 {
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3456,8 +3456,8 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(ptr %out, ptr %ptr) #1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3482,8 +3482,8 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(ptr %out, ptr %ptr) #1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3582,8 +3582,8 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_system(ptr %out, ptr %
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s2, s2, 32
; CI-NEXT: s_addc_u32 s3, s3, 0
-; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3608,8 +3608,8 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_system(ptr %out, ptr %
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s2, s2, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3707,9 +3707,9 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64(ptr %ptr) #1 {
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: v_mov_b32_e32 v0, 42
+; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v3, s1
-; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3723,9 +3723,9 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64(ptr %ptr) #1 {
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v0, 42
+; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3804,8 +3804,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(ptr %ptr) #1 {
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3822,8 +3822,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(ptr %ptr) #1 {
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3857,8 +3857,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(ptr %ptr) #1 {
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_u32 s0, s0, 32
; GFX10-NEXT: s_addc_u32 s1, s1, 0
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
@@ -3905,8 +3905,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_system(ptr %ptr) #1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: s_addc_u32 s1, s1, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3923,8 +3923,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_system(ptr %ptr) #1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3958,8 +3958,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_system(ptr %ptr) #1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_u32 s0, s0, 32
; GFX10-NEXT: s_addc_u32 s1, s1, 0
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1]
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
@@ -4017,8 +4017,8 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: buffer_wbinvl1_vol
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: v_add_i32_e32 v4, vcc, 4, v2
@@ -4046,8 +4046,8 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_wbinvl1_vol
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v2
@@ -4064,16 +4064,16 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 42
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[3:4], v[1:2] offset:40 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_wbinvl1_vol
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -4100,8 +4100,8 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -4112,10 +4112,10 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_lshlrev_b32 v4, 3, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -4123,7 +4123,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
@@ -4135,17 +4135,17 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v3, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_lshlrev_b32 v4, 3, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: flat_atomic_inc_u64 v[0:1], v[0:1], v[2:3] offset:40 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -4212,8 +4212,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(ptr %ptr) #1
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 42
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
; GFX9-NEXT: v_mov_b32_e32 v3, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, s1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
@@ -4251,10 +4251,10 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(ptr %ptr) #1
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 3, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -4270,10 +4270,10 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(ptr %ptr) #1
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v3, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 3, v0
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -4302,9 +4302,9 @@ define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(ptr addrspace(1) %out0,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: ds_inc_rtn_u32 v3, v1, v0
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: v_mov_b32_e32 v0, s2
@@ -4325,9 +4325,9 @@ define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(ptr addrspace(1) %out0,
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: ds_inc_rtn_u32 v3, v1, v0
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
index a62794dce8bab..3c7118df7ff0f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
@@ -9,11 +9,10 @@ define void @main(<19 x i32> %arg) {
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, 0
-; GCN-NEXT: s_mov_b32 s12, s4
; GCN-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_mov_b32 s12, s4
; GCN-NEXT: s_mov_b32 s13, s4
-; GCN-NEXT: v_mov_b32_e32 v4, s12
; GCN-NEXT: s_mov_b32 s5, s4
; GCN-NEXT: s_mov_b32 s6, s4
; GCN-NEXT: s_mov_b32 s7, s4
@@ -24,6 +23,7 @@ define void @main(<19 x i32> %arg) {
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GCN-NEXT: v_mov_b32_e32 v2, v1
; GCN-NEXT: v_mov_b32_e32 v3, v1
+; GCN-NEXT: v_mov_b32_e32 v4, s12
; GCN-NEXT: v_mov_b32_e32 v5, s13
; GCN-NEXT: image_store v[0:3], v[4:5], s[4:11] unorm
; GCN-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
index 896c32ef01c4e..cd27cac15dade 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
@@ -476,10 +476,10 @@ define amdgpu_kernel void @load_i8_to_f32(ptr addrspace(1) noalias %out, ptr add
; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v2, v3, vcc
; VI-NEXT: flat_load_ubyte v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -696,6 +696,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(ptr addrspace(1) noalias
; VI-NEXT: flat_load_ubyte v3, v[6:7]
; VI-NEXT: flat_load_ubyte v4, v[4:5]
; VI-NEXT: flat_load_ubyte v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
@@ -706,7 +707,6 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(ptr addrspace(1) noalias
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_or_b32_e32 v3, v1, v0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
@@ -1013,11 +1013,11 @@ define amdgpu_kernel void @i8_zext_inreg_i32_to_f32(ptr addrspace(1) noalias %ou
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1059,10 +1059,10 @@ define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(ptr addrspace(1) noalias %ou
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1104,10 +1104,10 @@ define amdgpu_kernel void @i8_zext_i32_to_f32(ptr addrspace(1) noalias %out, ptr
; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v2, v3, vcc
; VI-NEXT: flat_load_ubyte v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1174,6 +1174,7 @@ define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(ptr addrspace(1) noalias %ou
; VI-NEXT: flat_load_ubyte v3, v[6:7]
; VI-NEXT: flat_load_ubyte v4, v[4:5]
; VI-NEXT: flat_load_ubyte v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
@@ -1184,7 +1185,6 @@ define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(ptr addrspace(1) noalias %ou
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_or_b32_e32 v3, v1, v0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
@@ -1229,10 +1229,10 @@ define amdgpu_kernel void @extract_byte0_to_f32(ptr addrspace(1) noalias %out, p
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_ubyte v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1273,10 +1273,10 @@ define amdgpu_kernel void @extract_byte1_to_f32(ptr addrspace(1) noalias %out, p
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1318,10 +1318,10 @@ define amdgpu_kernel void @extract_byte2_to_f32(ptr addrspace(1) noalias %out, p
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1362,10 +1362,10 @@ define amdgpu_kernel void @extract_byte3_to_f32(ptr addrspace(1) noalias %out, p
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte3_e32 v2, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
index a7bafbfcff513..6a43cba0f9ec5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
@@ -559,14 +559,14 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
; GFX10-NEXT: s_mov_b32 s8, exec_lo
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 2
; GFX10-NEXT: s_andn2_b32 s1, s7, exec_lo
-; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
+; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: s_and_b32 s7, exec_lo, s8
; GFX10-NEXT: s_andn2_b32 s6, s6, exec_lo
; GFX10-NEXT: s_and_b32 s8, exec_lo, exec_lo
-; GFX10-NEXT: s_or_b32 s7, s1, s7
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v2, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo
+; GFX10-NEXT: s_or_b32 s7, s1, s7
; GFX10-NEXT: s_or_b32 s6, s6, s8
; GFX10-NEXT: global_load_dword v6, v[6:7], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -575,8 +575,8 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
; GFX10-NEXT: s_cbranch_execz .LBB7_1
; GFX10-NEXT: ; %bb.3: ; %loop.body
; GFX10-NEXT: ; in Loop: Header=BB7_2 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
+; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: s_add_i32 s2, s0, 1
; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
index a14f40d8ebbfa..66af63e968b0d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
@@ -123,8 +123,8 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
; GFX10-NEXT: s_ashr_i32 s1, s0, 31
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 2
; GFX10-NEXT: s_andn2_b32 s1, s5, exec_lo
-; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: s_and_b32 s5, exec_lo, exec_lo
; GFX10-NEXT: s_or_b32 s5, s1, s5
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v2, v4
@@ -136,8 +136,8 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
; GFX10-NEXT: s_cbranch_execz .LBB2_1
; GFX10-NEXT: ; %bb.3: ; %loop.body
; GFX10-NEXT: ; in Loop: Header=BB2_2 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: s_add_i32 s2, s0, 1
; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
@@ -145,8 +145,8 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v5, vcc_lo
; GFX10-NEXT: s_andn2_b32 s3, s5, exec_lo
; GFX10-NEXT: s_and_b32 s0, exec_lo, s0
-; GFX10-NEXT: s_or_b32 s5, s3, s0
; GFX10-NEXT: global_load_dword v6, v[4:5], off
+; GFX10-NEXT: s_or_b32 s5, s3, s0
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v6
@@ -203,8 +203,8 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_ashr_i32 s1, s0, 31
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 2
; GFX10-NEXT: s_andn2_b32 s1, s5, exec_lo
-; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
+; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: s_and_b32 s5, exec_lo, exec_lo
; GFX10-NEXT: s_or_b32 s5, s1, s5
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v2, v6
@@ -216,8 +216,8 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_cbranch_execz .LBB3_2
; GFX10-NEXT: ; %bb.4: ; %B
; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
+; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: s_mov_b32 s6, exec_lo
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v4, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v5, v7, vcc_lo
@@ -228,8 +228,8 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_cbranch_execz .LBB3_1
; GFX10-NEXT: ; %bb.5: ; %loop.body
; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
+; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: s_add_i32 s2, s0, 1
; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
@@ -237,8 +237,8 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v1, v7, vcc_lo
; GFX10-NEXT: s_andn2_b32 s3, s6, exec_lo
; GFX10-NEXT: s_and_b32 s0, exec_lo, s0
-; GFX10-NEXT: s_or_b32 s6, s3, s0
; GFX10-NEXT: global_load_dword v8, v[6:7], off
+; GFX10-NEXT: s_or_b32 s6, s3, s0
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v8
@@ -307,8 +307,8 @@ define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_ashr_i32 s1, s0, 31
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 2
; GFX10-NEXT: s_andn2_b32 s1, s5, exec_lo
-; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: v_mov_b32_e32 v8, s2
+; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: s_and_b32 s5, exec_lo, exec_lo
; GFX10-NEXT: s_or_b32 s5, s1, s5
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v2, v8
@@ -320,8 +320,8 @@ define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_cbranch_execz .LBB4_3
; GFX10-NEXT: ; %bb.5: ; %B
; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: v_mov_b32_e32 v8, s2
+; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: s_mov_b32 s6, exec_lo
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v4, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v5, v9, vcc_lo
@@ -332,8 +332,8 @@ define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_cbranch_execz .LBB4_2
; GFX10-NEXT: ; %bb.6: ; %C
; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: v_mov_b32_e32 v8, s2
+; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: s_mov_b32 s8, exec_lo
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v6, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v7, v9, vcc_lo
@@ -344,8 +344,8 @@ define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_cbranch_execz .LBB4_1
; GFX10-NEXT: ; %bb.7: ; %loop.body
; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: v_mov_b32_e32 v8, s2
+; GFX10-NEXT: v_mov_b32_e32 v9, s3
; GFX10-NEXT: s_add_i32 s2, s0, 1
; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
@@ -353,8 +353,8 @@ define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo
; GFX10-NEXT: s_andn2_b32 s3, s8, exec_lo
; GFX10-NEXT: s_and_b32 s0, exec_lo, s0
-; GFX10-NEXT: s_or_b32 s8, s3, s0
; GFX10-NEXT: global_load_dword v10, v[8:9], off
+; GFX10-NEXT: s_or_b32 s8, s3, s0
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v10
@@ -427,14 +427,14 @@ define amdgpu_cs void @loop_with_div_break_with_body(ptr addrspace(1) %x, ptr ad
; GFX10-NEXT: s_mov_b32 s8, exec_lo
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 2
; GFX10-NEXT: s_andn2_b32 s1, s7, exec_lo
-; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
+; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: s_and_b32 s7, exec_lo, s8
; GFX10-NEXT: s_andn2_b32 s6, s6, exec_lo
; GFX10-NEXT: s_and_b32 s8, exec_lo, exec_lo
-; GFX10-NEXT: s_or_b32 s7, s1, s7
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v2, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo
+; GFX10-NEXT: s_or_b32 s7, s1, s7
; GFX10-NEXT: s_or_b32 s6, s6, s8
; GFX10-NEXT: global_load_dword v6, v[6:7], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -443,8 +443,8 @@ define amdgpu_cs void @loop_with_div_break_with_body(ptr addrspace(1) %x, ptr ad
; GFX10-NEXT: s_cbranch_execz .LBB5_1
; GFX10-NEXT: ; %bb.3: ; %loop.body
; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_mov_b32_e32 v6, s2
+; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: s_add_i32 s2, s0, 1
; GFX10-NEXT: s_cmpk_lt_u32 s0, 0x64
; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
index 77a260fae6973..ec2607057ecd9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
@@ -414,8 +414,8 @@ define void @nested_loops_temporal_divergence_both(float %pre.cond.val, i32 %n.i
; GFX10-NEXT: ; %bb.3: ; %UseInst
; GFX10-NEXT: ; in Loop: Header=BB5_1 Depth=1
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s10
-; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s6
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_cmp_lt_u32_e32 vcc_lo, s6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s9
; GFX10-NEXT: s_add_i32 s6, s6, 1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
index ca9e2ca76dd08..8b5c0f19c4822 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
@@ -41,10 +41,10 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_sgpr_idx(ptr addrspace(4) inre
; GFX7-NEXT: s_and_b32 s2, s4, 3
; GFX7-NEXT: s_lshl_b32 s4, s2, 4
; GFX7-NEXT: s_mov_b32 s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, s5
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -89,10 +89,10 @@ define amdgpu_ps i128 @extractelement_vgpr_v4i128_sgpr_idx(ptr addrspace(1) %ptr
; GFX9-LABEL: extractelement_vgpr_v4i128_sgpr_idx:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s2, 3
-; GFX9-NEXT: s_mov_b32 s1, 0
; GFX9-NEXT: s_lshl_b32 s0, s0, 4
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: s_mov_b32 s1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
@@ -106,10 +106,10 @@ define amdgpu_ps i128 @extractelement_vgpr_v4i128_sgpr_idx(ptr addrspace(1) %ptr
; GFX8-LABEL: extractelement_vgpr_v4i128_sgpr_idx:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s2, 3
-; GFX8-NEXT: s_mov_b32 s1, 0
; GFX8-NEXT: s_lshl_b32 s0, s0, 4
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: s_mov_b32 s1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
index e4acee9ddda7e..40fa13cddf0cb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
@@ -35,10 +35,10 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_sgpr_idx(ptr addrspace(4) inreg
; GFX7-NEXT: s_and_b32 s2, s4, 3
; GFX7-NEXT: s_lshl_b32 s4, s2, 1
; GFX7-NEXT: s_mov_b32 s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, s5
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -74,10 +74,10 @@ define amdgpu_ps i16 @extractelement_vgpr_v4i16_sgpr_idx(ptr addrspace(1) %ptr,
; GFX9-LABEL: extractelement_vgpr_v4i16_sgpr_idx:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s2, 3
-; GFX9-NEXT: s_mov_b32 s1, 0
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: s_mov_b32 s1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_load_ushort v0, v[0:1], off
@@ -88,10 +88,10 @@ define amdgpu_ps i16 @extractelement_vgpr_v4i16_sgpr_idx(ptr addrspace(1) %ptr,
; GFX8-LABEL: extractelement_vgpr_v4i16_sgpr_idx:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s2, 3
-; GFX8-NEXT: s_mov_b32 s1, 0
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: s_mov_b32 s1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
@@ -679,10 +679,10 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_sgpr_idx(ptr addrspace(4) inreg
; GFX7-NEXT: s_and_b32 s2, s4, 7
; GFX7-NEXT: s_lshl_b32 s4, s2, 1
; GFX7-NEXT: s_mov_b32 s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, s5
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -718,10 +718,10 @@ define amdgpu_ps i16 @extractelement_vgpr_v8i16_sgpr_idx(ptr addrspace(1) %ptr,
; GFX9-LABEL: extractelement_vgpr_v8i16_sgpr_idx:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s2, 7
-; GFX9-NEXT: s_mov_b32 s1, 0
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: s_mov_b32 s1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_load_ushort v0, v[0:1], off
@@ -732,10 +732,10 @@ define amdgpu_ps i16 @extractelement_vgpr_v8i16_sgpr_idx(ptr addrspace(1) %ptr,
; GFX8-LABEL: extractelement_vgpr_v8i16_sgpr_idx:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s2, 7
-; GFX8-NEXT: s_mov_b32 s1, 0
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: s_mov_b32 s1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
index ac17dde1f9aa7..a7eb36f84531a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
@@ -35,11 +35,11 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_sgpr_idx(ptr addrspace(4) inreg %p
; GFX7: ; %bb.0:
; GFX7-NEXT: s_and_b32 s4, s4, 3
; GFX7-NEXT: s_ashr_i32 s5, s4, 31
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -79,8 +79,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v4i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s2, 3
; GFX9-NEXT: s_ashr_i32 s1, s0, 31
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_load_ubyte v0, v[0:1], off
@@ -92,8 +92,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v4i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s2, 3
; GFX8-NEXT: s_ashr_i32 s1, s0, 31
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
@@ -116,8 +116,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v4i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s0, s2, 3
; GFX10-NEXT: s_ashr_i32 s1, s0, 31
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off
@@ -130,7 +130,7 @@ define amdgpu_ps i8 @extractelement_vgpr_v4i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX11-NEXT: s_and_b32 s0, s2, 3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_ashr_i32 s1, s0, 31
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
@@ -262,8 +262,8 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_vgpr_idx(ptr addrspace(4) inreg %p
;
; GFX11-LABEL: extractelement_sgpr_v4i8_vgpr_idx:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e32 v2, 3, v0
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v2, 3, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
@@ -688,11 +688,11 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_sgpr_idx(ptr addrspace(4) inreg %p
; GFX7: ; %bb.0:
; GFX7-NEXT: s_and_b32 s4, s4, 7
; GFX7-NEXT: s_ashr_i32 s5, s4, 31
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -732,8 +732,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v8i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s2, 7
; GFX9-NEXT: s_ashr_i32 s1, s0, 31
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_load_ubyte v0, v[0:1], off
@@ -745,8 +745,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v8i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s2, 7
; GFX8-NEXT: s_ashr_i32 s1, s0, 31
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
@@ -769,8 +769,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v8i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s0, s2, 7
; GFX10-NEXT: s_ashr_i32 s1, s0, 31
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off
@@ -783,7 +783,7 @@ define amdgpu_ps i8 @extractelement_vgpr_v8i8_sgpr_idx(ptr addrspace(1) %ptr, i3
; GFX11-NEXT: s_and_b32 s0, s2, 7
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_ashr_i32 s1, s0, 31
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
@@ -915,8 +915,8 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_vgpr_idx(ptr addrspace(4) inreg %p
;
; GFX11-LABEL: extractelement_sgpr_v8i8_vgpr_idx:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e32 v2, 7, v0
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v2, 7, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
@@ -1725,11 +1725,11 @@ define amdgpu_ps i8 @extractelement_sgpr_v16i8_sgpr_idx(ptr addrspace(4) inreg %
; GFX7: ; %bb.0:
; GFX7-NEXT: s_and_b32 s4, s4, 15
; GFX7-NEXT: s_ashr_i32 s5, s4, 31
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -1769,8 +1769,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v16i8_sgpr_idx(ptr addrspace(1) %ptr, i
; GFX9: ; %bb.0:
; GFX9-NEXT: s_and_b32 s0, s2, 15
; GFX9-NEXT: s_ashr_i32 s1, s0, 31
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_load_ubyte v0, v[0:1], off
@@ -1782,8 +1782,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v16i8_sgpr_idx(ptr addrspace(1) %ptr, i
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s0, s2, 15
; GFX8-NEXT: s_ashr_i32 s1, s0, 31
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
@@ -1806,8 +1806,8 @@ define amdgpu_ps i8 @extractelement_vgpr_v16i8_sgpr_idx(ptr addrspace(1) %ptr, i
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s0, s2, 15
; GFX10-NEXT: s_ashr_i32 s1, s0, 31
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off
@@ -1820,7 +1820,7 @@ define amdgpu_ps i8 @extractelement_vgpr_v16i8_sgpr_idx(ptr addrspace(1) %ptr, i
; GFX11-NEXT: s_and_b32 s0, s2, 15
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_ashr_i32 s1, s0, 31
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
@@ -1952,8 +1952,8 @@ define amdgpu_ps i8 @extractelement_sgpr_v16i8_vgpr_idx(ptr addrspace(4) inreg %
;
; GFX11-LABEL: extractelement_sgpr_v16i8_vgpr_idx:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_and_b32_e32 v2, 15, v0
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v2, 15, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index 22cd226bf9b4c..9e11615d80ed1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -2434,31 +2434,31 @@ define amdgpu_ps double @dyn_extract_v7f64_s_v_bitcast(<14 x float> inreg %userD
; GCN-LABEL: dyn_extract_v7f64_s_v_bitcast:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: v_mov_b32_e32 v1, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s4
; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: v_mov_b32_e32 v3, s4
; GCN-NEXT: v_mov_b32_e32 v4, s5
-; GCN-NEXT: v_mov_b32_e32 v5, s6
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_mov_b32_e32 v5, s6
; GCN-NEXT: v_mov_b32_e32 v6, s7
-; GCN-NEXT: v_mov_b32_e32 v7, s8
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
+; GCN-NEXT: v_mov_b32_e32 v7, s8
; GCN-NEXT: v_mov_b32_e32 v8, s9
-; GCN-NEXT: v_mov_b32_e32 v9, s10
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
+; GCN-NEXT: v_mov_b32_e32 v9, s10
; GCN-NEXT: v_mov_b32_e32 v10, s11
-; GCN-NEXT: v_mov_b32_e32 v11, s12
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
+; GCN-NEXT: v_mov_b32_e32 v11, s12
; GCN-NEXT: v_mov_b32_e32 v12, s13
-; GCN-NEXT: v_mov_b32_e32 v13, s14
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
+; GCN-NEXT: v_mov_b32_e32 v13, s14
; GCN-NEXT: v_mov_b32_e32 v14, s15
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
@@ -2475,8 +2475,8 @@ define amdgpu_ps double @dyn_extract_v7f64_s_v_bitcast(<14 x float> inreg %userD
; GFX10-LABEL: dyn_extract_v7f64_s_v_bitcast:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_mov_b32_e32 v1, s2
-; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: v_mov_b32_e32 v2, s3
+; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v5, s6
@@ -2995,8 +2995,8 @@ define amdgpu_kernel void @dyn_extract_v5f64_s_s(ptr addrspace(1) %out, i32 %sel
; MOVREL-NEXT: s_mov_b64 s[6:7], 2.0
; MOVREL-NEXT: s_movrels_b64 s[2:3], s[4:5]
; MOVREL-NEXT: v_mov_b32_e32 v0, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s1
; MOVREL-NEXT: v_mov_b32_e32 v1, s3
+; MOVREL-NEXT: v_mov_b32_e32 v3, s1
; MOVREL-NEXT: v_mov_b32_e32 v2, s0
; MOVREL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; MOVREL-NEXT: s_endpgm
@@ -3991,10 +3991,10 @@ define amdgpu_kernel void @dyn_extract_v4f32_s_s_s(ptr addrspace(1) %out, i32 %s
; MOVREL-NEXT: s_mov_b32 m0, s6
; MOVREL-NEXT: s_mov_b32 s1, 2.0
; MOVREL-NEXT: s_movrels_b32 s0, s0
-; MOVREL-NEXT: v_mov_b32_e32 v0, s4
; MOVREL-NEXT: s_mov_b32 flat_scratch_lo, s13
; MOVREL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; MOVREL-NEXT: v_mov_b32_e32 v2, s0
+; MOVREL-NEXT: v_mov_b32_e32 v0, s4
; MOVREL-NEXT: v_mov_b32_e32 v1, s5
; MOVREL-NEXT: flat_store_dword v[0:1], v2
; MOVREL-NEXT: s_endpgm
@@ -4334,19 +4334,19 @@ define amdgpu_kernel void @dyn_extract_v4f64_s_s_s(ptr addrspace(1) %out, i32 %s
; MOVREL-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0
; MOVREL-NEXT: s_load_dword s8, s[8:9], 0x8
; MOVREL-NEXT: s_mov_b64 s[0:1], 1.0
+; MOVREL-NEXT: s_add_i32 s12, s12, s17
; MOVREL-NEXT: s_mov_b64 s[6:7], 4.0
; MOVREL-NEXT: s_mov_b32 s4, 0
-; MOVREL-NEXT: s_mov_b32 s5, 0x40080000
; MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; MOVREL-NEXT: s_mov_b32 m0, s8
+; MOVREL-NEXT: s_mov_b32 s5, 0x40080000
; MOVREL-NEXT: s_mov_b64 s[2:3], 2.0
; MOVREL-NEXT: s_movrels_b64 s[0:1], s[0:1]
-; MOVREL-NEXT: s_add_i32 s12, s12, s17
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: v_mov_b32_e32 v2, s10
; MOVREL-NEXT: s_mov_b32 flat_scratch_lo, s13
; MOVREL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; MOVREL-NEXT: v_mov_b32_e32 v0, s0
; MOVREL-NEXT: v_mov_b32_e32 v1, s1
+; MOVREL-NEXT: v_mov_b32_e32 v2, s10
; MOVREL-NEXT: v_mov_b32_e32 v3, s11
; MOVREL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; MOVREL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
index 291491d2979e3..da6578ea9aa41 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
@@ -258,7 +258,7 @@ define amdgpu_ps void @s_fabs_v2f32(<2 x float> inreg %in, ptr addrspace(1) %out
; GFX12-NEXT: s_bitset0_b32 s0, 31
; GFX12-NEXT: s_bitset0_b32 s1, 31
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_endpgm
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
index 8e4f231d841ec..a6b18b02bb830 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
@@ -10,11 +10,11 @@ define amdgpu_ps void @amdgpu_ps() {
; MESA-LABEL: amdgpu_ps:
; MESA: ; %bb.0:
; MESA-NEXT: s_mov_b64 s[0:1], src_private_base
-; MESA-NEXT: s_mov_b32 s0, 0
; MESA-NEXT: s_add_u32 flat_scratch_lo, s2, s4
-; MESA-NEXT: v_mov_b32_e32 v0, s0
+; MESA-NEXT: s_mov_b32 s0, 0
; MESA-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; MESA-NEXT: v_mov_b32_e32 v2, 0
+; MESA-NEXT: v_mov_b32_e32 v0, s0
; MESA-NEXT: v_mov_b32_e32 v1, s1
; MESA-NEXT: flat_store_dword v[0:1], v2
; MESA-NEXT: s_waitcnt vmcnt(0)
@@ -31,8 +31,8 @@ define amdgpu_ps void @amdgpu_ps() {
; PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s0
; PAL-NEXT: s_mov_b64 s[0:1], src_private_base
; PAL-NEXT: s_mov_b32 s0, 0
-; PAL-NEXT: v_mov_b32_e32 v0, s0
; PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
+; PAL-NEXT: v_mov_b32_e32 v0, s0
; PAL-NEXT: v_mov_b32_e32 v1, s1
; PAL-NEXT: flat_store_dword v[0:1], v2
; PAL-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
index df5477756460e..d6fbf92dea0a4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
@@ -1579,8 +1579,8 @@ define amdgpu_ps void @fma_s64_uniform(double inreg %a, double inreg %b, double
; GFX6-LABEL: fma_s64_uniform:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v2, s2
-; GFX6-NEXT: v_mov_b32_e32 v4, s4
; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: v_mov_b32_e32 v4, s4
; GFX6-NEXT: v_mov_b32_e32 v5, s5
; GFX6-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], v[4:5]
; GFX6-NEXT: s_mov_b32 s2, 0
@@ -1592,8 +1592,8 @@ define amdgpu_ps void @fma_s64_uniform(double inreg %a, double inreg %b, double
; GFX8-LABEL: fma_s64_uniform:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], v[4:5]
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -1602,8 +1602,8 @@ define amdgpu_ps void @fma_s64_uniform(double inreg %a, double inreg %b, double
; GFX9-LABEL: fma_s64_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], v[4:5]
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
index 18ebacf21f10e..47e591cc31faa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
@@ -258,7 +258,7 @@ define amdgpu_ps void @s_fneg_v2f32(<2 x float> inreg %in, ptr addrspace(1) %out
; GFX12-NEXT: s_xor_b32 s0, s0, 0x80000000
; GFX12-NEXT: s_xor_b32 s1, s1, 0x80000000
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_endpgm
%fneg = fneg <2 x float> %in
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
index a82ef25f16b16..cac19129c0db4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
@@ -194,34 +194,34 @@ define amdgpu_ps <2 x float> @fpext_v2f16_to_v2f32_div(<2 x half> %a) {
define amdgpu_ps void @fpext_v2f32_to_v2f64_uniform(<2 x float> inreg %a, ptr addrspace(1) %ptr) {
; GFX11-LABEL: fpext_v2f32_to_v2f64_uniform:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cvt_f64_f32_e32 v[4:5], s1
; GFX11-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-NEXT: v_cvt_f64_f32_e32 v[4:5], s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: fpext_v2f32_to_v2f64_uniform:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_cvt_f64_f32_e32 v[4:5], s1
; GFX12-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_readfirstlane_b32 s3, v5
+; GFX12-NEXT: v_cvt_f64_f32_e32 v[4:5], s1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-NEXT: s_endpgm
%result = fpext <2 x float> %a to <2 x double>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
index 7ae8c4701aa98..8bd8125fafca3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
@@ -233,8 +233,8 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: s_cselect_b32 s3, 0x7e00, s4
; VI-NEXT: s_cmp_lg_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, s3, 0x7e00
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
@@ -619,8 +619,8 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: s_cselect_b32 s4, 0x7fc00000, s4
; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
; VI-NEXT: s_cselect_b32 s2, s4, 0x7fc00000
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -1617,8 +1617,8 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_cselect_b32 s2, s4, 0x7e00
; VI-NEXT: s_lshl_b32 s2, s2, 16
; VI-NEXT: s_or_b32 s2, s3, s2
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -2505,8 +2505,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_lshl_b32 s3, s3, 16
; VI-NEXT: s_or_b32 s3, s4, s3
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -2933,8 +2933,8 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-NEXT: s_cselect_b32 s3, s6, 0x7fc00000
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -3751,10 +3751,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
; VI-NEXT: s_cselect_b32 s7, s8, 0x7fc00000
; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 9d3302a996ebd..bf7c545b31cd0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -5985,8 +5985,8 @@ define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX6-NEXT: s_and_b32 s3, s2, 63
; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX6-NEXT: s_not_b32 s2, s2
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s3
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
@@ -5998,8 +5998,8 @@ define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX8-NEXT: s_and_b32 s3, s2, 63
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX8-NEXT: s_not_b32 s2, s2
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX8-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
@@ -6011,8 +6011,8 @@ define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX9-NEXT: s_and_b32 s3, s2, 63
; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX9-NEXT: s_not_b32 s2, s2
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX9-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
@@ -6747,8 +6747,8 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX6-NEXT: v_or_b32_e32 v5, v3, v5
; GFX6-NEXT: v_lshr_b64 v[2:3], s[2:3], v9
; GFX6-NEXT: v_lshr_b64 v[0:1], s[2:3], v13
-; GFX6-NEXT: v_mov_b32_e32 v7, s1
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
+; GFX6-NEXT: v_mov_b32_e32 v7, s1
; GFX6-NEXT: v_mov_b32_e32 v6, s0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
@@ -6800,8 +6800,8 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX8-NEXT: v_or_b32_e32 v5, v3, v5
; GFX8-NEXT: v_lshrrev_b64 v[2:3], v9, s[2:3]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v13, s[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v7, s1
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
+; GFX8-NEXT: v_mov_b32_e32 v7, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
@@ -6852,8 +6852,8 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX9-NEXT: v_or_b32_e32 v5, v3, v5
; GFX9-NEXT: v_lshrrev_b64 v[2:3], v13, s[2:3]
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v12, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v7, s1
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v12
+; GFX9-NEXT: v_mov_b32_e32 v7, s1
; GFX9-NEXT: v_mov_b32_e32 v6, s0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
@@ -6897,8 +6897,8 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX10-NEXT: v_or_b32_e32 v5, v0, v9
; GFX10-NEXT: v_or_b32_e32 v9, v1, v10
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
+; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v5, s1
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v12, s[6:7]
; GFX10-NEXT: v_mov_b32_e32 v1, s5
@@ -6946,8 +6946,9 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX11-NEXT: v_cmp_gt_u32_e64 s1, 64, v12
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v11
; GFX11-NEXT: v_or_b32_e32 v5, v0, v9
+; GFX11-NEXT: v_mov_b32_e32 v0, s4
; GFX11-NEXT: v_or_b32_e32 v9, v1, v10
-; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_cndmask_b32 v7, v7, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo
; GFX11-NEXT: v_lshrrev_b64 v[2:3], v13, s[6:7]
; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v4 :: v_dual_mov_b32 v1, s5
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 0, v12
@@ -7017,17 +7018,17 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX6-NEXT: s_cmp_lg_u32 s5, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s6
-; GFX6-NEXT: s_cmp_lg_u32 s5, 0
; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: v_mov_b32_e32 v3, s1
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v5
@@ -7075,17 +7076,17 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
; GFX8-NEXT: v_or_b32_e32 v3, v3, v5
@@ -7132,17 +7133,17 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX9-NEXT: s_cmp_lg_u32 s5, 0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-NEXT: s_cmp_lg_u32 s5, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s7
-; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
@@ -7194,9 +7195,9 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
@@ -7247,14 +7248,14 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
; GFX11-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v4, v2, v0 :: v_dual_cndmask_b32 v5, v3, v1
; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_cndmask_b32 v6, 0, v8
; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_cndmask_b32 v7, 0, v9
; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
@@ -7317,8 +7318,8 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v1, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_mov_b32_e32 v3, s3
; GFX6-NEXT: v_or_b32_e32 v0, v6, v0
; GFX6-NEXT: v_or_b32_e32 v1, v7, v1
@@ -7377,8 +7378,8 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v1, v3, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_or_b32_e32 v0, v6, v0
; GFX8-NEXT: v_or_b32_e32 v1, v7, v1
@@ -7437,8 +7438,8 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: v_or_b32_e32 v0, v6, v0
; GFX9-NEXT: v_or_b32_e32 v1, v7, v1
@@ -7488,10 +7489,10 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
; GFX10-NEXT: s_cmp_lg_u32 s13, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s7, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 9d3a2accf3119..a7cd1f2898653 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -5626,8 +5626,8 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX6-NEXT: s_not_b32 s3, s2
-; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX6-NEXT: s_and_b32 s2, s2, 63
+; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s2
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
@@ -5639,8 +5639,8 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX8-NEXT: s_not_b32 s3, s2
-; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX8-NEXT: s_and_b32 s2, s2, 63
+; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX8-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
@@ -5652,8 +5652,8 @@ define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX9-NEXT: s_not_b32 s3, s2
-; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX9-NEXT: s_and_b32 s2, s2, 63
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
; GFX9-NEXT: v_lshrrev_b64 v[0:1], s2, v[0:1]
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
@@ -5696,8 +5696,8 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GFX6-NEXT: s_andn2_b32 s3, 63, s2
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s3
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
@@ -5708,8 +5708,8 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX8-NEXT: s_andn2_b32 s3, 63, s2
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX8-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
@@ -5720,8 +5720,8 @@ define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX9-NEXT: s_andn2_b32 s3, 63, s2
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX9-NEXT: v_lshlrev_b64 v[0:1], s3, v[0:1]
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
@@ -6721,17 +6721,17 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX6-NEXT: s_cmp_lg_u32 s7, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: s_cmp_lg_u32 s7, 0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
; GFX6-NEXT: v_mov_b32_e32 v2, s2
-; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX6-NEXT: v_mov_b32_e32 v3, s3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v5
@@ -6780,17 +6780,17 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX8-NEXT: s_cmp_lg_u32 s7, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_cmp_lg_u32 s7, 0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
; GFX8-NEXT: v_or_b32_e32 v3, v3, v5
@@ -6839,17 +6839,17 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX9-NEXT: s_cmp_lg_u32 s7, 0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: s_cmp_lg_u32 s7, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: s_cselect_b64 vcc, exec, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
@@ -6903,9 +6903,9 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX10-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
@@ -6958,14 +6958,14 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
; GFX11-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v4, v2, v0 :: v_dual_cndmask_b32 v5, v3, v1
; GFX11-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_cndmask_b32 v6, 0, v8
; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_cndmask_b32 v7, 0, v9
; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v1, v1, v5
; GFX11-NEXT: v_or_b32_e32 v2, v2, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
@@ -7026,8 +7026,8 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_mov_b32_e32 v3, s3
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
; GFX6-NEXT: v_or_b32_e32 v1, v5, v1
@@ -7084,8 +7084,8 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
; GFX8-NEXT: v_or_b32_e32 v1, v5, v1
@@ -7142,8 +7142,8 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: v_or_b32_e32 v0, v4, v0
; GFX9-NEXT: v_or_b32_e32 v1, v5, v1
@@ -7191,10 +7191,10 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
; GFX10-NEXT: s_cmp_lg_u32 s13, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s7, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s6
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
index fa74787f1784a..e6cd04aa41528 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
@@ -14,8 +14,8 @@ define amdgpu_kernel void @addrspacecast(ptr addrspace(5) %ptr.private, ptr addr
; GFX8V4-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX8V4-NEXT: s_add_u32 s0, s6, 0x44
; GFX8V4-NEXT: s_addc_u32 s1, s7, 0
-; GFX8V4-NEXT: v_mov_b32_e32 v0, s0
; GFX8V4-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX8V4-NEXT: v_mov_b32_e32 v0, s0
; GFX8V4-NEXT: v_mov_b32_e32 v1, s1
; GFX8V4-NEXT: flat_load_dword v0, v[0:1]
; GFX8V4-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
@@ -32,15 +32,15 @@ define amdgpu_kernel void @addrspacecast(ptr addrspace(5) %ptr.private, ptr addr
; GFX8V4-NEXT: v_mov_b32_e32 v0, s4
; GFX8V4-NEXT: v_mov_b32_e32 v1, s5
; GFX8V4-NEXT: flat_load_dword v2, v[0:1]
-; GFX8V4-NEXT: v_mov_b32_e32 v0, s2
; GFX8V4-NEXT: s_cmp_lg_u32 s1, -1
+; GFX8V4-NEXT: v_mov_b32_e32 v0, s2
; GFX8V4-NEXT: v_mov_b32_e32 v1, s3
; GFX8V4-NEXT: flat_store_dword v[0:1], v3
; GFX8V4-NEXT: s_waitcnt vmcnt(0)
; GFX8V4-NEXT: v_readfirstlane_b32 s1, v2
; GFX8V4-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
-; GFX8V4-NEXT: v_mov_b32_e32 v0, s0
; GFX8V4-NEXT: v_mov_b32_e32 v2, 2
+; GFX8V4-NEXT: v_mov_b32_e32 v0, s0
; GFX8V4-NEXT: v_mov_b32_e32 v1, s1
; GFX8V4-NEXT: flat_store_dword v[0:1], v2
; GFX8V4-NEXT: s_waitcnt vmcnt(0)
@@ -57,17 +57,17 @@ define amdgpu_kernel void @addrspacecast(ptr addrspace(5) %ptr.private, ptr addr
; GFX8V5-NEXT: s_mov_b32 s4, s0
; GFX8V5-NEXT: s_mov_b32 s5, s2
; GFX8V5-NEXT: s_cmp_lg_u32 s0, -1
-; GFX8V5-NEXT: s_cselect_b64 s[4:5], s[4:5], 0
; GFX8V5-NEXT: s_mov_b32 s2, s1
+; GFX8V5-NEXT: s_cselect_b64 s[4:5], s[4:5], 0
; GFX8V5-NEXT: s_cmp_lg_u32 s1, -1
-; GFX8V5-NEXT: v_mov_b32_e32 v0, s4
; GFX8V5-NEXT: s_cselect_b64 s[0:1], s[2:3], 0
; GFX8V5-NEXT: v_mov_b32_e32 v2, 1
+; GFX8V5-NEXT: v_mov_b32_e32 v0, s4
; GFX8V5-NEXT: v_mov_b32_e32 v1, s5
; GFX8V5-NEXT: flat_store_dword v[0:1], v2
; GFX8V5-NEXT: s_waitcnt vmcnt(0)
-; GFX8V5-NEXT: v_mov_b32_e32 v0, s0
; GFX8V5-NEXT: v_mov_b32_e32 v2, 2
+; GFX8V5-NEXT: v_mov_b32_e32 v0, s0
; GFX8V5-NEXT: v_mov_b32_e32 v1, s1
; GFX8V5-NEXT: flat_store_dword v[0:1], v2
; GFX8V5-NEXT: s_waitcnt vmcnt(0)
@@ -83,17 +83,17 @@ define amdgpu_kernel void @addrspacecast(ptr addrspace(5) %ptr.private, ptr addr
; GFX9V4-NEXT: s_waitcnt lgkmcnt(0)
; GFX9V4-NEXT: s_mov_b32 s0, s4
; GFX9V4-NEXT: s_cmp_lg_u32 s4, -1
-; GFX9V4-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
; GFX9V4-NEXT: s_mov_b32 s2, s5
+; GFX9V4-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
; GFX9V4-NEXT: s_cmp_lg_u32 s5, -1
-; GFX9V4-NEXT: v_mov_b32_e32 v0, s0
; GFX9V4-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9V4-NEXT: v_mov_b32_e32 v2, 1
+; GFX9V4-NEXT: v_mov_b32_e32 v0, s0
; GFX9V4-NEXT: v_mov_b32_e32 v1, s1
; GFX9V4-NEXT: flat_store_dword v[0:1], v2
; GFX9V4-NEXT: s_waitcnt vmcnt(0)
-; GFX9V4-NEXT: v_mov_b32_e32 v0, s2
; GFX9V4-NEXT: v_mov_b32_e32 v2, 2
+; GFX9V4-NEXT: v_mov_b32_e32 v0, s2
; GFX9V4-NEXT: v_mov_b32_e32 v1, s3
; GFX9V4-NEXT: flat_store_dword v[0:1], v2
; GFX9V4-NEXT: s_waitcnt vmcnt(0)
@@ -109,17 +109,17 @@ define amdgpu_kernel void @addrspacecast(ptr addrspace(5) %ptr.private, ptr addr
; GFX9V5-NEXT: s_waitcnt lgkmcnt(0)
; GFX9V5-NEXT: s_mov_b32 s0, s4
; GFX9V5-NEXT: s_cmp_lg_u32 s4, -1
-; GFX9V5-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
; GFX9V5-NEXT: s_mov_b32 s2, s5
+; GFX9V5-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
; GFX9V5-NEXT: s_cmp_lg_u32 s5, -1
-; GFX9V5-NEXT: v_mov_b32_e32 v0, s0
; GFX9V5-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9V5-NEXT: v_mov_b32_e32 v2, 1
+; GFX9V5-NEXT: v_mov_b32_e32 v0, s0
; GFX9V5-NEXT: v_mov_b32_e32 v1, s1
; GFX9V5-NEXT: flat_store_dword v[0:1], v2
; GFX9V5-NEXT: s_waitcnt vmcnt(0)
-; GFX9V5-NEXT: v_mov_b32_e32 v0, s2
; GFX9V5-NEXT: v_mov_b32_e32 v2, 2
+; GFX9V5-NEXT: v_mov_b32_e32 v0, s2
; GFX9V5-NEXT: v_mov_b32_e32 v1, s3
; GFX9V5-NEXT: flat_store_dword v[0:1], v2
; GFX9V5-NEXT: s_waitcnt vmcnt(0)
@@ -297,11 +297,11 @@ define amdgpu_kernel void @llvm_debugtrap() #0 {
define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) #0 {
; GFX8V4-LABEL: llvm_amdgcn_queue_ptr:
; GFX8V4: ; %bb.0:
+; GFX8V4-NEXT: s_add_u32 s0, s8, 8
; GFX8V4-NEXT: v_mov_b32_e32 v0, s6
; GFX8V4-NEXT: v_mov_b32_e32 v1, s7
-; GFX8V4-NEXT: s_add_u32 s0, s8, 8
-; GFX8V4-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V4-NEXT: s_addc_u32 s1, s9, 0
+; GFX8V4-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V4-NEXT: s_waitcnt vmcnt(0)
; GFX8V4-NEXT: v_mov_b32_e32 v0, s0
; GFX8V4-NEXT: v_mov_b32_e32 v1, s1
@@ -323,11 +323,11 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) #0 {
;
; GFX8V5-LABEL: llvm_amdgcn_queue_ptr:
; GFX8V5: ; %bb.0:
+; GFX8V5-NEXT: s_add_u32 s0, s8, 8
; GFX8V5-NEXT: v_mov_b32_e32 v0, s6
; GFX8V5-NEXT: v_mov_b32_e32 v1, s7
-; GFX8V5-NEXT: s_add_u32 s0, s8, 8
-; GFX8V5-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V5-NEXT: s_addc_u32 s1, s9, 0
+; GFX8V5-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V5-NEXT: s_waitcnt vmcnt(0)
; GFX8V5-NEXT: v_mov_b32_e32 v0, s0
; GFX8V5-NEXT: v_mov_b32_e32 v1, s1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
index aa90e5e1674ec..4b8bc3041bfd4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
@@ -968,10 +968,10 @@ define amdgpu_ps void @insertelement_s_v4i16_v_s(ptr addrspace(4) inreg %ptr, i1
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_movrels_b32 s4, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_andn2_b32 s3, s4, s3
; GFX10-NEXT: v_lshl_or_b32 v4, v0, s2, s3
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
@@ -987,11 +987,11 @@ define amdgpu_ps void @insertelement_s_v4i16_v_s(ptr addrspace(4) inreg %ptr, i1
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_movrels_b32 s4, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
; GFX11-NEXT: s_and_not1_b32 s3, s4, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshl_or_b32 v4, v0, s2, s3
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
@@ -1107,21 +1107,20 @@ define amdgpu_ps void @insertelement_s_v4i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX11-NEXT: v_and_b32_e32 v1, 1, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v0
; GFX11-NEXT: s_and_b32 s2, s4, 0xffff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v2, 4, v1
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, s2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_not_b32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v5, v5, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
@@ -1233,13 +1232,13 @@ define amdgpu_ps void @insertelement_s_v4i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v2, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v2, 4, v2
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v5
; GFX11-NEXT: v_lshlrev_b32_e64 v4, v2, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e32 v2, v2, v3
@@ -1626,9 +1625,9 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX9-NEXT: s_andn2_b32 s5, s6, s5
; GFX9-NEXT: s_or_b32 s4, s5, s4
; GFX9-NEXT: s_movreld_b32 s0, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
@@ -1649,9 +1648,9 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX8-NEXT: s_andn2_b32 s5, s6, s5
; GFX8-NEXT: s_or_b32 s4, s5, s4
; GFX8-NEXT: s_movreld_b32 s0, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
@@ -1672,8 +1671,8 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX7-NEXT: s_andn2_b32 s5, s6, s5
; GFX7-NEXT: s_or_b32 s4, s5, s4
; GFX7-NEXT: s_movreld_b32 s0, s4
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
@@ -1928,11 +1927,11 @@ define amdgpu_ps void @insertelement_s_v8i16_v_s(ptr addrspace(4) inreg %ptr, i1
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_movrels_b32 s6, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_andn2_b32 s5, s6, s5
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_lshl_or_b32 v6, v0, s4, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: v_movreld_b32_e32 v0, v6
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
@@ -1948,13 +1947,14 @@ define amdgpu_ps void @insertelement_s_v8i16_v_s(ptr addrspace(4) inreg %ptr, i1
; GFX11-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: s_movrels_b32 s6, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
; GFX11-NEXT: s_and_not1_b32 s5, s6, s5
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
; GFX11-NEXT: v_lshl_or_b32 v6, v0, s4, s5
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_movreld_b32_e32 v0, v6
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX11-NEXT: s_endpgm
@@ -1973,9 +1973,9 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
@@ -2006,9 +2006,9 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v4, s3
; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
@@ -2039,9 +2039,9 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v4, s3
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-NEXT: v_mov_b32_e32 v4, s3
; GFX7-NEXT: v_mov_b32_e32 v3, s2
; GFX7-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
@@ -2142,9 +2142,9 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v5, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
; GFX9-NEXT: v_mov_b32_e32 v4, s2
; GFX9-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
@@ -2174,9 +2174,9 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
@@ -2206,9 +2206,9 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v4, s2
; GFX7-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
@@ -2242,14 +2242,14 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: v_not_b32_e32 v5, v8
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
; GFX10-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
; GFX10-NEXT: v_and_or_b32 v8, v6, v5, v0
@@ -2271,23 +2271,23 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
-; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v2, s1
+; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v4, s3
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 4, v5
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
; GFX11-NEXT: v_lshlrev_b32_e64 v8, v5, 0xffff
; GFX11-NEXT: v_lshlrev_b32_e32 v0, v5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_not_b32_e32 v5, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v8, v6, v5, v0
; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, v8, s2
; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v8, s0
@@ -2729,16 +2729,16 @@ define amdgpu_ps void @insertelement_s_v16i16_s_s(ptr addrspace(4) inreg %ptr, i
; GFX9-NEXT: s_andn2_b32 s0, s0, s1
; GFX9-NEXT: s_or_b32 s0, s0, s2
; GFX9-NEXT: s_movreld_b32 s8, s0
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_mov_b32_e32 v3, s11
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX9-NEXT: v_mov_b32_e32 v4, 16
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s12
; GFX9-NEXT: v_mov_b32_e32 v1, s13
; GFX9-NEXT: v_mov_b32_e32 v2, s14
; GFX9-NEXT: v_mov_b32_e32 v3, s15
@@ -2759,16 +2759,16 @@ define amdgpu_ps void @insertelement_s_v16i16_s_s(ptr addrspace(4) inreg %ptr, i
; GFX8-NEXT: s_andn2_b32 s0, s0, s1
; GFX8-NEXT: s_or_b32 s0, s0, s2
; GFX8-NEXT: s_movreld_b32 s8, s0
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NEXT: v_mov_b32_e32 v3, s11
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, 16
-; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NEXT: v_mov_b32_e32 v3, s15
@@ -2789,8 +2789,8 @@ define amdgpu_ps void @insertelement_s_v16i16_s_s(ptr addrspace(4) inreg %ptr, i
; GFX7-NEXT: s_andn2_b32 s0, s0, s1
; GFX7-NEXT: s_or_b32 s0, s0, s2
; GFX7-NEXT: s_movreld_b32 s8, s0
-; GFX7-NEXT: v_mov_b32_e32 v0, s8
; GFX7-NEXT: s_mov_b64 s[0:1], 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s8
; GFX7-NEXT: v_mov_b32_e32 v1, s9
; GFX7-NEXT: v_mov_b32_e32 v2, s10
; GFX7-NEXT: v_mov_b32_e32 v3, s11
@@ -3428,9 +3428,9 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v9, s7
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v9, s7
; GFX9-NEXT: v_mov_b32_e32 v8, s6
; GFX9-NEXT: v_mov_b32_e32 v7, s5
; GFX9-NEXT: v_mov_b32_e32 v6, s4
@@ -3479,9 +3479,9 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, s7
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
; GFX8-NEXT: v_mov_b32_e32 v8, s6
; GFX8-NEXT: v_mov_b32_e32 v7, s5
; GFX8-NEXT: v_mov_b32_e32 v6, s4
@@ -3530,9 +3530,9 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v9, s7
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_mov_b32_e32 v9, s7
; GFX7-NEXT: v_mov_b32_e32 v8, s6
; GFX7-NEXT: v_mov_b32_e32 v7, s5
; GFX7-NEXT: v_mov_b32_e32 v6, s4
@@ -3587,9 +3587,9 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX10-NEXT: v_not_b32_e32 v1, v11
; GFX10-NEXT: v_mov_b32_e32 v11, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s6
; GFX10-NEXT: v_mov_b32_e32 v7, s5
; GFX10-NEXT: v_mov_b32_e32 v6, s4
@@ -3639,11 +3639,11 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
; GFX11-NEXT: v_not_b32_e32 v1, v11
; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v14
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v14
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
index 852c2188fb731..700495f474fa1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
@@ -312,8 +312,8 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: s_lshr_b32 s1, s0, 8
-; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_movreld_b32_e32 v1, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0xff
; GFX10-NEXT: v_and_b32_sdwa v0, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -332,7 +332,7 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_movreld_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.l
@@ -353,7 +353,7 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX11-FAKE16-NEXT: v_movreld_b32_e32 v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2
@@ -1700,9 +1700,9 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: s_andn2_b32 s2, s2, s3
; GFX9-NEXT: s_or_b32 s2, s2, s4
; GFX9-NEXT: s_movreld_b32 s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX9-NEXT: s_endpgm
@@ -1721,9 +1721,9 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: s_andn2_b32 s2, s2, s3
; GFX8-NEXT: s_or_b32 s2, s2, s4
; GFX8-NEXT: s_movreld_b32 s0, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm
@@ -1742,8 +1742,8 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: s_andn2_b32 s0, s0, s1
; GFX7-NEXT: s_or_b32 s0, s0, s4
; GFX7-NEXT: s_movreld_b32 s2, s0
-; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: s_mov_b64 s[0:1], 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -1987,10 +1987,10 @@ define amdgpu_ps void @insertelement_s_v8i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_movrels_b32 s4, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_andn2_b32 s3, s4, s3
; GFX10-NEXT: v_lshl_or_b32 v4, v0, s2, s3
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
@@ -2006,11 +2006,11 @@ define amdgpu_ps void @insertelement_s_v8i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_movrels_b32 s4, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
; GFX11-NEXT: s_and_not1_b32 s3, s4, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshl_or_b32 v4, v0, s2, s3
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
@@ -2126,21 +2126,20 @@ define amdgpu_ps void @insertelement_s_v8i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX11-NEXT: v_and_b32_e32 v1, 3, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v0
; GFX11-NEXT: s_and_b32 s2, s4, 0xff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v2, 3, v1
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff
; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, s2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_not_b32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v5, v5, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
@@ -2252,13 +2251,13 @@ define amdgpu_ps void @insertelement_s_v8i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v2, 3, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 2, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v2
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v2, 3, v2
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v5
; GFX11-NEXT: v_lshlrev_b32_e64 v4, v2, 0xff
; GFX11-NEXT: v_lshlrev_b32_e32 v2, v2, v3
@@ -2645,9 +2644,9 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: s_andn2_b32 s5, s6, s5
; GFX9-NEXT: s_or_b32 s4, s5, s4
; GFX9-NEXT: s_movreld_b32 s0, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
@@ -2668,9 +2667,9 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: s_andn2_b32 s5, s6, s5
; GFX8-NEXT: s_or_b32 s4, s5, s4
; GFX8-NEXT: s_movreld_b32 s0, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
@@ -2691,8 +2690,8 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: s_andn2_b32 s5, s6, s5
; GFX7-NEXT: s_or_b32 s4, s5, s4
; GFX7-NEXT: s_movreld_b32 s0, s4
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
@@ -2947,11 +2946,11 @@ define amdgpu_ps void @insertelement_s_v16i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_movrels_b32 s6, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_andn2_b32 s5, s6, s5
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_lshl_or_b32 v6, v0, s4, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: v_movreld_b32_e32 v0, v6
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
@@ -2967,13 +2966,14 @@ define amdgpu_ps void @insertelement_s_v16i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-NEXT: s_lshl_b32 s5, 0xff, s4
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: s_movrels_b32 s6, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
; GFX11-NEXT: s_and_not1_b32 s5, s6, s5
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
; GFX11-NEXT: v_lshl_or_b32 v6, v0, s4, s5
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_movreld_b32_e32 v0, v6
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX11-NEXT: s_endpgm
@@ -2992,9 +2992,9 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: v_and_b32_e32 v0, 3, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
@@ -3025,9 +3025,9 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: v_and_b32_e32 v0, 3, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v4, s3
; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
@@ -3058,9 +3058,9 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: v_and_b32_e32 v0, 3, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v4, s3
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-NEXT: v_mov_b32_e32 v4, s3
; GFX7-NEXT: v_mov_b32_e32 v3, s2
; GFX7-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
@@ -3161,9 +3161,9 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: v_and_b32_e32 v1, 3, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v5, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
; GFX9-NEXT: v_mov_b32_e32 v4, s2
; GFX9-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
@@ -3193,9 +3193,9 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: v_and_b32_e32 v1, 3, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
@@ -3225,9 +3225,9 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: v_and_b32_e32 v1, 3, v1
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v4, s2
; GFX7-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
@@ -3261,14 +3261,14 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_not_b32_e32 v5, v8
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
; GFX10-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
; GFX10-NEXT: v_and_or_b32 v8, v6, v5, v0
@@ -3290,23 +3290,23 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
-; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v2, s1
+; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v4, s3
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 3, v5
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
; GFX11-NEXT: v_lshlrev_b32_e64 v8, v5, 0xff
; GFX11-NEXT: v_lshlrev_b32_e32 v0, v5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_not_b32_e32 v5, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_or_b32 v8, v6, v5, v0
; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, v8, s2
; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v8, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
index cc433d210f985..6f2aa60ce9fe4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
@@ -384,12 +384,12 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_s(<8 x float> inreg %v
; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: v_mov_b32_e32 v8, v0
+; GFX11-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_mov_b32 m0, s10
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
-; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_mov_b32_e32 v6, s6
; GFX11-NEXT: v_movreld_b32_e32 v0, v8
; GFX11-NEXT: ; return to shader part epilog
;
@@ -870,7 +870,6 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_const_s_v_v:
; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GPRIDX-NEXT: s_mov_b64 s[4:5], 1.0
; GPRIDX-NEXT: s_mov_b32 s18, 0
; GPRIDX-NEXT: s_mov_b32 s19, 0x40200000
; GPRIDX-NEXT: s_mov_b32 s16, 0
@@ -883,6 +882,7 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GPRIDX-NEXT: s_mov_b32 s8, 0
; GPRIDX-NEXT: s_mov_b32 s9, 0x40080000
; GPRIDX-NEXT: s_mov_b64 s[6:7], 2.0
+; GPRIDX-NEXT: s_mov_b64 s[4:5], 1.0
; GPRIDX-NEXT: v_mov_b32_e32 v3, s4
; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
; GPRIDX-NEXT: v_mov_b32_e32 v5, s6
@@ -1002,9 +1002,9 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX11-LABEL: dyn_insertelement_v8f64_const_s_v_v:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_mov_b32 s15, 0x40200000
; GFX11-NEXT: s_mov_b64 s[0:1], 1.0
; GFX11-NEXT: s_mov_b32 s14, 0
+; GFX11-NEXT: s_mov_b32 s15, 0x40200000
; GFX11-NEXT: s_mov_b32 s12, 0
; GFX11-NEXT: s_mov_b32 s13, 0x401c0000
; GFX11-NEXT: s_mov_b32 s10, 0
@@ -1015,9 +1015,9 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX11-NEXT: s_mov_b32 s4, 0
; GFX11-NEXT: s_mov_b32 s5, 0x40080000
; GFX11-NEXT: s_mov_b64 s[2:3], 2.0
-; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
@@ -1056,7 +1056,6 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX8-LABEL: dyn_insertelement_v8f64_const_s_v_v:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_mov_b64 s[4:5], 1.0
; GFX8-NEXT: s_mov_b32 s18, 0
; GFX8-NEXT: s_mov_b32 s19, 0x40200000
; GFX8-NEXT: s_mov_b32 s16, 0
@@ -1069,6 +1068,7 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX8-NEXT: s_mov_b32 s8, 0
; GFX8-NEXT: s_mov_b32 s9, 0x40080000
; GFX8-NEXT: s_mov_b64 s[6:7], 2.0
+; GFX8-NEXT: s_mov_b64 s[4:5], 1.0
; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: v_mov_b32_e32 v5, s6
@@ -1134,22 +1134,22 @@ entry:
define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, double inreg %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_s_s_v:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10
+; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s10, s12
+; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14
+; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: s_mov_b32 s14, s16
+; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: v_mov_b32_e32 v16, s15
; GPRIDX-NEXT: v_mov_b32_e32 v15, s14
; GPRIDX-NEXT: v_mov_b32_e32 v14, s13
@@ -1204,26 +1204,26 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
;
; GFX10-LABEL: dyn_insertelement_v8f64_s_s_v:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 s3, s5
-; GFX10-NEXT: s_mov_b32 s5, s7
-; GFX10-NEXT: s_mov_b32 s7, s9
-; GFX10-NEXT: s_mov_b32 s9, s11
-; GFX10-NEXT: s_mov_b32 s11, s13
-; GFX10-NEXT: s_mov_b32 s13, s15
-; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
; GFX10-NEXT: s_mov_b32 s14, s16
-; GFX10-NEXT: v_mov_b32_e32 v16, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_mov_b32_e32 v16, s15
; GFX10-NEXT: v_mov_b32_e32 v15, s14
; GFX10-NEXT: v_mov_b32_e32 v14, s13
; GFX10-NEXT: v_mov_b32_e32 v13, s12
@@ -1272,25 +1272,25 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
;
; GFX11-LABEL: dyn_insertelement_v8f64_s_s_v:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 s3, s5
-; GFX11-NEXT: s_mov_b32 s5, s7
-; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: s_mov_b32 s9, s11
-; GFX11-NEXT: s_mov_b32 s11, s13
-; GFX11-NEXT: s_mov_b32 s13, s15
-; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: s_mov_b32 s14, s16
-; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
+; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12
; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10
; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8
@@ -1332,22 +1332,22 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
;
; GFX8-LABEL: dyn_insertelement_v8f64_s_s_v:
; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_mov_b32 s1, s3
-; GFX8-NEXT: s_mov_b32 s3, s5
-; GFX8-NEXT: s_mov_b32 s5, s7
-; GFX8-NEXT: s_mov_b32 s7, s9
-; GFX8-NEXT: s_mov_b32 s9, s11
-; GFX8-NEXT: s_mov_b32 s11, s13
-; GFX8-NEXT: s_mov_b32 s13, s15
-; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: v_mov_b32_e32 v16, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14
; GFX8-NEXT: v_mov_b32_e32 v14, s13
@@ -1415,22 +1415,22 @@ entry:
define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_s_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10
+; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s10, s12
+; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14
+; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: s_mov_b32 s14, s16
+; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: v_mov_b32_e32 v17, s15
; GPRIDX-NEXT: v_mov_b32_e32 v16, s14
; GPRIDX-NEXT: v_mov_b32_e32 v15, s13
@@ -1464,25 +1464,25 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do
;
; GFX10-LABEL: dyn_insertelement_v8f64_s_v_s:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 s3, s5
-; GFX10-NEXT: s_mov_b32 s5, s7
-; GFX10-NEXT: s_mov_b32 s7, s9
-; GFX10-NEXT: s_mov_b32 s9, s11
-; GFX10-NEXT: s_mov_b32 s11, s13
-; GFX10-NEXT: s_mov_b32 s13, s15
-; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
; GFX10-NEXT: s_mov_b32 s14, s16
-; GFX10-NEXT: v_mov_b32_e32 v17, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshl_b32 m0, s18, 1
+; GFX10-NEXT: v_mov_b32_e32 v17, s15
; GFX10-NEXT: v_mov_b32_e32 v16, s14
; GFX10-NEXT: v_mov_b32_e32 v15, s13
; GFX10-NEXT: v_mov_b32_e32 v14, s12
@@ -1511,25 +1511,25 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do
;
; GFX11-LABEL: dyn_insertelement_v8f64_s_v_s:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 s3, s5
-; GFX11-NEXT: s_mov_b32 s5, s7
-; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: s_mov_b32 s9, s11
-; GFX11-NEXT: s_mov_b32 s11, s13
-; GFX11-NEXT: s_mov_b32 s13, s15
-; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: s_mov_b32 s14, s16
-; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: s_lshl_b32 m0, s18, 1
+; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
@@ -1550,22 +1550,22 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do
;
; GFX8-LABEL: dyn_insertelement_v8f64_s_v_s:
; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_mov_b32 s1, s3
-; GFX8-NEXT: s_mov_b32 s3, s5
-; GFX8-NEXT: s_mov_b32 s5, s7
-; GFX8-NEXT: s_mov_b32 s7, s9
-; GFX8-NEXT: s_mov_b32 s9, s11
-; GFX8-NEXT: s_mov_b32 s11, s13
-; GFX8-NEXT: s_mov_b32 s13, s15
-; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: v_mov_b32_e32 v17, s15
; GFX8-NEXT: v_mov_b32_e32 v16, s14
; GFX8-NEXT: v_mov_b32_e32 v15, s13
@@ -1691,22 +1691,22 @@ entry:
define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_s_v_v:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10
+; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s10, s12
+; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14
+; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: s_mov_b32 s14, s16
+; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: v_mov_b32_e32 v18, s15
; GPRIDX-NEXT: v_mov_b32_e32 v17, s14
; GPRIDX-NEXT: v_mov_b32_e32 v16, s13
@@ -1759,26 +1759,26 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
;
; GFX10-LABEL: dyn_insertelement_v8f64_s_v_v:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 s3, s5
-; GFX10-NEXT: s_mov_b32 s5, s7
-; GFX10-NEXT: s_mov_b32 s7, s9
-; GFX10-NEXT: s_mov_b32 s9, s11
-; GFX10-NEXT: s_mov_b32 s11, s13
-; GFX10-NEXT: s_mov_b32 s13, s15
-; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
; GFX10-NEXT: s_mov_b32 s14, s16
-; GFX10-NEXT: v_mov_b32_e32 v18, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT: v_mov_b32_e32 v18, s15
; GFX10-NEXT: v_mov_b32_e32 v17, s14
; GFX10-NEXT: v_mov_b32_e32 v16, s13
; GFX10-NEXT: v_mov_b32_e32 v15, s12
@@ -1827,25 +1827,25 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
;
; GFX11-LABEL: dyn_insertelement_v8f64_s_v_v:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 s3, s5
-; GFX11-NEXT: s_mov_b32 s5, s7
-; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: s_mov_b32 s9, s11
-; GFX11-NEXT: s_mov_b32 s11, s13
-; GFX11-NEXT: s_mov_b32 s13, s15
-; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: s_mov_b32 s14, s16
-; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
+; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
@@ -1883,22 +1883,22 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
;
; GFX8-LABEL: dyn_insertelement_v8f64_s_v_v:
; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_mov_b32 s1, s3
-; GFX8-NEXT: s_mov_b32 s3, s5
-; GFX8-NEXT: s_mov_b32 s5, s7
-; GFX8-NEXT: s_mov_b32 s7, s9
-; GFX8-NEXT: s_mov_b32 s9, s11
-; GFX8-NEXT: s_mov_b32 s11, s13
-; GFX8-NEXT: s_mov_b32 s13, s15
-; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: v_mov_b32_e32 v18, s15
; GFX8-NEXT: v_mov_b32_e32 v17, s14
; GFX8-NEXT: v_mov_b32_e32 v16, s13
@@ -2942,33 +2942,33 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v
; GPRIDX-NEXT: s_cmp_eq_u32 s20, 1
; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
; GPRIDX-NEXT: s_cmp_eq_u32 s20, 2
-; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
; GPRIDX-NEXT: s_cmp_eq_u32 s20, 3
+; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 4
+; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 5
+; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 6
+; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
-; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
-; GPRIDX-NEXT: s_cmp_eq_u32 s20, 4
+; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 7
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
-; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GPRIDX-NEXT: v_mov_b32_e32 v0, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s20, 5
; GPRIDX-NEXT: v_mov_b32_e32 v1, s5
; GPRIDX-NEXT: v_mov_b32_e32 v2, s6
; GPRIDX-NEXT: v_mov_b32_e32 v3, s7
-; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
-; GPRIDX-NEXT: s_cmp_eq_u32 s20, 6
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
-; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
; GPRIDX-NEXT: v_mov_b32_e32 v0, s8
-; GPRIDX-NEXT: s_cmp_eq_u32 s20, 7
; GPRIDX-NEXT: v_mov_b32_e32 v1, s9
; GPRIDX-NEXT: v_mov_b32_e32 v2, s10
; GPRIDX-NEXT: v_mov_b32_e32 v3, s11
-; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, s12
@@ -3066,33 +3066,33 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v
; GFX8-NEXT: s_cmp_eq_u32 s20, 1
; GFX8-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
; GFX8-NEXT: s_cmp_eq_u32 s20, 2
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
; GFX8-NEXT: s_cmp_eq_u32 s20, 3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 4
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 5
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 6
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
-; GFX8-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
-; GFX8-NEXT: s_cmp_eq_u32 s20, 4
+; GFX8-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 7
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX8-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GFX8-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NEXT: s_cmp_eq_u32 s20, 5
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
-; GFX8-NEXT: s_cmp_eq_u32 s20, 6
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
; GFX8-NEXT: v_mov_b32_e32 v0, s8
-; GFX8-NEXT: s_cmp_eq_u32 s20, 7
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NEXT: v_mov_b32_e32 v3, s11
-; GFX8-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s12
@@ -3657,13 +3657,13 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_s_v_s(<10 x float> inreg
; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s9, s11
-; GFX11-NEXT: v_mov_b32_e32 v10, v0
+; GFX11-NEXT: v_dual_mov_b32 v10, v0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_mov_b32 m0, s12
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
-; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
-; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v8, s8
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: v_mov_b32_e32 v8, s8
; GFX11-NEXT: v_movreld_b32_e32 v0, v10
; GFX11-NEXT: ; return to shader part epilog
;
@@ -4366,14 +4366,14 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_s_v_s(<12 x float> inreg
; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: s_mov_b32 s11, s13
-; GFX11-NEXT: v_mov_b32_e32 v12, v0
+; GFX11-NEXT: v_dual_mov_b32 v12, v0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_mov_b32 m0, s14
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
-; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
-; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v8, s8
-; GFX11-NEXT: v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v10, s10
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s11
+; GFX11-NEXT: v_mov_b32_e32 v10, s10
; GFX11-NEXT: v_movreld_b32_e32 v0, v12
; GFX11-NEXT: ; return to shader part epilog
;
@@ -5406,22 +5406,22 @@ entry:
define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %vec, i32 %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v16i32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry
+; GPRIDX-NEXT: s_mov_b32 s0, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s15, s17
-; GPRIDX-NEXT: s_mov_b32 s0, s2
; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10
+; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s10, s12
+; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14
+; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: s_mov_b32 s14, s16
+; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: v_mov_b32_e32 v16, s15
; GPRIDX-NEXT: v_mov_b32_e32 v15, s14
; GPRIDX-NEXT: v_mov_b32_e32 v14, s13
@@ -5461,25 +5461,25 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %ve
;
; GFX10-LABEL: dyn_insertelement_v16i32_s_v_s:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 s3, s5
-; GFX10-NEXT: s_mov_b32 s5, s7
-; GFX10-NEXT: s_mov_b32 s7, s9
-; GFX10-NEXT: s_mov_b32 s9, s11
-; GFX10-NEXT: s_mov_b32 s11, s13
-; GFX10-NEXT: s_mov_b32 s13, s15
-; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
; GFX10-NEXT: s_mov_b32 s14, s16
-; GFX10-NEXT: v_mov_b32_e32 v16, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: s_mov_b32 m0, s18
+; GFX10-NEXT: v_mov_b32_e32 v16, s15
; GFX10-NEXT: v_mov_b32_e32 v15, s14
; GFX10-NEXT: v_mov_b32_e32 v14, s13
; GFX10-NEXT: v_mov_b32_e32 v13, s12
@@ -5515,25 +5515,25 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %ve
;
; GFX11-LABEL: dyn_insertelement_v16i32_s_v_s:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 s3, s5
-; GFX11-NEXT: s_mov_b32 s5, s7
-; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: s_mov_b32 s9, s11
-; GFX11-NEXT: s_mov_b32 s11, s13
-; GFX11-NEXT: s_mov_b32 s13, s15
-; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: s_mov_b32 s14, s16
-; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
+; GFX11-NEXT: s_mov_b32 s15, s17
; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: s_mov_b32 m0, s18
+; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12
; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10
; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8
@@ -5561,22 +5561,22 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %ve
;
; GFX8-LABEL: dyn_insertelement_v16i32_s_v_s:
; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_mov_b32 s1, s3
-; GFX8-NEXT: s_mov_b32 s3, s5
-; GFX8-NEXT: s_mov_b32 s5, s7
-; GFX8-NEXT: s_mov_b32 s7, s9
-; GFX8-NEXT: s_mov_b32 s9, s11
-; GFX8-NEXT: s_mov_b32 s11, s13
-; GFX8-NEXT: s_mov_b32 s13, s15
-; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
; GFX8-NEXT: v_mov_b32_e32 v16, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14
; GFX8-NEXT: v_mov_b32_e32 v14, s13
@@ -5715,16 +5715,16 @@ define amdgpu_ps <16 x float> @dyn_insertelement_v16f32_s_v_s(<16 x float> inreg
; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: s_mov_b32 s14, s16
; GFX11-NEXT: s_mov_b32 s15, s17
-; GFX11-NEXT: v_mov_b32_e32 v16, v0
+; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_mov_b32 m0, s18
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
-; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
-; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v8, s8
-; GFX11-NEXT: v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v10, s10
-; GFX11-NEXT: v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v12, s12
-; GFX11-NEXT: v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v14, s14
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s11
+; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v13, s13
+; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v15, s15
+; GFX11-NEXT: v_mov_b32_e32 v14, s14
; GFX11-NEXT: v_movreld_b32_e32 v0, v16
; GFX11-NEXT: ; return to shader part epilog
;
@@ -5949,24 +5949,24 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_v_s(<32 x float> inreg
; GFX11-NEXT: s_mov_b32 s29, s31
; GFX11-NEXT: s_mov_b32 s31, s33
; GFX11-NEXT: s_mov_b32 s30, s32
-; GFX11-NEXT: v_mov_b32_e32 v32, v0
+; GFX11-NEXT: v_dual_mov_b32 v32, v0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_mov_b32 m0, s34
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
-; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
-; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v8, s8
-; GFX11-NEXT: v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v10, s10
-; GFX11-NEXT: v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v12, s12
-; GFX11-NEXT: v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v14, s14
-; GFX11-NEXT: v_dual_mov_b32 v17, s17 :: v_dual_mov_b32 v16, s16
-; GFX11-NEXT: v_dual_mov_b32 v19, s19 :: v_dual_mov_b32 v18, s18
-; GFX11-NEXT: v_dual_mov_b32 v21, s21 :: v_dual_mov_b32 v20, s20
-; GFX11-NEXT: v_dual_mov_b32 v23, s23 :: v_dual_mov_b32 v22, s22
-; GFX11-NEXT: v_dual_mov_b32 v25, s25 :: v_dual_mov_b32 v24, s24
-; GFX11-NEXT: v_dual_mov_b32 v27, s27 :: v_dual_mov_b32 v26, s26
-; GFX11-NEXT: v_dual_mov_b32 v29, s29 :: v_dual_mov_b32 v28, s28
-; GFX11-NEXT: v_dual_mov_b32 v31, s31 :: v_dual_mov_b32 v30, s30
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s11
+; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v13, s13
+; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v15, s15
+; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v17, s17
+; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v19, s19
+; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v21, s21
+; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v23, s23
+; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v25, s25
+; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v27, s27
+; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v29, s29
+; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v31, s31
+; GFX11-NEXT: v_mov_b32_e32 v30, s30
; GFX11-NEXT: v_movreld_b32_e32 v0, v32
; GFX11-NEXT: ; return to shader part epilog
;
@@ -6048,40 +6048,40 @@ entry:
define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %vec, i64 %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v16i64_s_v_s:
; GPRIDX: ; %bb.0: ; %entry
+; GPRIDX-NEXT: s_mov_b32 s0, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
; GPRIDX-NEXT: s_mov_b32 s7, s9
+; GPRIDX-NEXT: s_mov_b32 s8, s10
; GPRIDX-NEXT: s_mov_b32 s9, s11
+; GPRIDX-NEXT: s_mov_b32 s10, s12
; GPRIDX-NEXT: s_mov_b32 s11, s13
+; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s13, s15
+; GPRIDX-NEXT: s_mov_b32 s14, s16
; GPRIDX-NEXT: s_mov_b32 s15, s17
+; GPRIDX-NEXT: s_mov_b32 s16, s18
; GPRIDX-NEXT: s_mov_b32 s17, s19
+; GPRIDX-NEXT: s_mov_b32 s18, s20
; GPRIDX-NEXT: s_mov_b32 s19, s21
+; GPRIDX-NEXT: s_mov_b32 s20, s22
; GPRIDX-NEXT: s_mov_b32 s21, s23
+; GPRIDX-NEXT: s_mov_b32 s22, s24
; GPRIDX-NEXT: s_mov_b32 s23, s25
+; GPRIDX-NEXT: s_mov_b32 s24, s26
; GPRIDX-NEXT: s_mov_b32 s25, s27
+; GPRIDX-NEXT: s_mov_b32 s26, s28
; GPRIDX-NEXT: s_mov_b32 s27, s29
+; GPRIDX-NEXT: s_mov_b32 s28, s30
; GPRIDX-NEXT: s_mov_b32 s29, s31
; GPRIDX-NEXT: s_mov_b32 s31, s33
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s14, s16
-; GPRIDX-NEXT: s_mov_b32 s16, s18
-; GPRIDX-NEXT: s_mov_b32 s18, s20
-; GPRIDX-NEXT: s_mov_b32 s20, s22
-; GPRIDX-NEXT: s_mov_b32 s22, s24
-; GPRIDX-NEXT: s_mov_b32 s24, s26
-; GPRIDX-NEXT: s_mov_b32 s26, s28
-; GPRIDX-NEXT: s_mov_b32 s28, s30
; GPRIDX-NEXT: s_mov_b32 s30, s32
-; GPRIDX-NEXT: v_mov_b32_e32 v33, s31
; GPRIDX-NEXT: s_lshl_b32 s33, s34, 1
+; GPRIDX-NEXT: v_mov_b32_e32 v33, s31
; GPRIDX-NEXT: v_mov_b32_e32 v32, s30
; GPRIDX-NEXT: v_mov_b32_e32 v31, s29
; GPRIDX-NEXT: v_mov_b32_e32 v30, s28
@@ -6153,41 +6153,41 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %ve
;
; GFX10-LABEL: dyn_insertelement_v16i64_s_v_s:
; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s14, s16
; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s16, s18
; GFX10-NEXT: s_mov_b32 s17, s19
+; GFX10-NEXT: s_mov_b32 s18, s20
; GFX10-NEXT: s_mov_b32 s19, s21
+; GFX10-NEXT: s_mov_b32 s20, s22
; GFX10-NEXT: s_mov_b32 s21, s23
+; GFX10-NEXT: s_mov_b32 s22, s24
; GFX10-NEXT: s_mov_b32 s23, s25
+; GFX10-NEXT: s_mov_b32 s24, s26
; GFX10-NEXT: s_mov_b32 s25, s27
+; GFX10-NEXT: s_mov_b32 s26, s28
; GFX10-NEXT: s_mov_b32 s27, s29
+; GFX10-NEXT: s_mov_b32 s28, s30
; GFX10-NEXT: s_mov_b32 s29, s31
; GFX10-NEXT: s_mov_b32 s31, s33
-; GFX10-NEXT: s_mov_b32 s0, s2
-; GFX10-NEXT: s_mov_b32 s2, s4
-; GFX10-NEXT: s_mov_b32 s4, s6
-; GFX10-NEXT: s_mov_b32 s6, s8
-; GFX10-NEXT: s_mov_b32 s8, s10
-; GFX10-NEXT: s_mov_b32 s10, s12
-; GFX10-NEXT: s_mov_b32 s12, s14
-; GFX10-NEXT: s_mov_b32 s14, s16
-; GFX10-NEXT: s_mov_b32 s16, s18
-; GFX10-NEXT: s_mov_b32 s18, s20
-; GFX10-NEXT: s_mov_b32 s20, s22
-; GFX10-NEXT: s_mov_b32 s22, s24
-; GFX10-NEXT: s_mov_b32 s24, s26
-; GFX10-NEXT: s_mov_b32 s26, s28
-; GFX10-NEXT: s_mov_b32 s28, s30
; GFX10-NEXT: s_mov_b32 s30, s32
-; GFX10-NEXT: v_mov_b32_e32 v33, s31
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshl_b32 m0, s34, 1
+; GFX10-NEXT: v_mov_b32_e32 v33, s31
; GFX10-NEXT: v_mov_b32_e32 v32, s30
; GFX10-NEXT: v_mov_b32_e32 v31, s29
; GFX10-NEXT: v_mov_b32_e32 v30, s28
@@ -6256,41 +6256,41 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %ve
;
; GFX11-LABEL: dyn_insertelement_v16i64_s_v_s:
; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s14, s16
; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s16, s18
; GFX11-NEXT: s_mov_b32 s17, s19
+; GFX11-NEXT: s_mov_b32 s18, s20
; GFX11-NEXT: s_mov_b32 s19, s21
+; GFX11-NEXT: s_mov_b32 s20, s22
; GFX11-NEXT: s_mov_b32 s21, s23
+; GFX11-NEXT: s_mov_b32 s22, s24
; GFX11-NEXT: s_mov_b32 s23, s25
+; GFX11-NEXT: s_mov_b32 s24, s26
; GFX11-NEXT: s_mov_b32 s25, s27
+; GFX11-NEXT: s_mov_b32 s26, s28
; GFX11-NEXT: s_mov_b32 s27, s29
+; GFX11-NEXT: s_mov_b32 s28, s30
; GFX11-NEXT: s_mov_b32 s29, s31
; GFX11-NEXT: s_mov_b32 s31, s33
-; GFX11-NEXT: s_mov_b32 s0, s2
-; GFX11-NEXT: s_mov_b32 s2, s4
-; GFX11-NEXT: s_mov_b32 s4, s6
-; GFX11-NEXT: s_mov_b32 s6, s8
-; GFX11-NEXT: s_mov_b32 s8, s10
-; GFX11-NEXT: s_mov_b32 s10, s12
-; GFX11-NEXT: s_mov_b32 s12, s14
-; GFX11-NEXT: s_mov_b32 s14, s16
-; GFX11-NEXT: s_mov_b32 s16, s18
-; GFX11-NEXT: s_mov_b32 s18, s20
-; GFX11-NEXT: s_mov_b32 s20, s22
-; GFX11-NEXT: s_mov_b32 s22, s24
-; GFX11-NEXT: s_mov_b32 s24, s26
-; GFX11-NEXT: s_mov_b32 s26, s28
-; GFX11-NEXT: s_mov_b32 s28, s30
; GFX11-NEXT: s_mov_b32 s30, s32
-; GFX11-NEXT: v_dual_mov_b32 v33, s31 :: v_dual_mov_b32 v32, s30
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: s_lshl_b32 m0, s34, 1
+; GFX11-NEXT: v_dual_mov_b32 v33, s31 :: v_dual_mov_b32 v32, s30
; GFX11-NEXT: v_dual_mov_b32 v31, s29 :: v_dual_mov_b32 v30, s28
; GFX11-NEXT: v_dual_mov_b32 v29, s27 :: v_dual_mov_b32 v28, s26
; GFX11-NEXT: v_dual_mov_b32 v27, s25 :: v_dual_mov_b32 v26, s24
@@ -6343,40 +6343,40 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %ve
;
; GFX8-LABEL: dyn_insertelement_v16i64_s_v_s:
; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s16, s18
; GFX8-NEXT: s_mov_b32 s17, s19
+; GFX8-NEXT: s_mov_b32 s18, s20
; GFX8-NEXT: s_mov_b32 s19, s21
+; GFX8-NEXT: s_mov_b32 s20, s22
; GFX8-NEXT: s_mov_b32 s21, s23
+; GFX8-NEXT: s_mov_b32 s22, s24
; GFX8-NEXT: s_mov_b32 s23, s25
+; GFX8-NEXT: s_mov_b32 s24, s26
; GFX8-NEXT: s_mov_b32 s25, s27
+; GFX8-NEXT: s_mov_b32 s26, s28
; GFX8-NEXT: s_mov_b32 s27, s29
+; GFX8-NEXT: s_mov_b32 s28, s30
; GFX8-NEXT: s_mov_b32 s29, s31
; GFX8-NEXT: s_mov_b32 s31, s33
-; GFX8-NEXT: s_mov_b32 s0, s2
-; GFX8-NEXT: s_mov_b32 s2, s4
-; GFX8-NEXT: s_mov_b32 s4, s6
-; GFX8-NEXT: s_mov_b32 s6, s8
-; GFX8-NEXT: s_mov_b32 s8, s10
-; GFX8-NEXT: s_mov_b32 s10, s12
-; GFX8-NEXT: s_mov_b32 s12, s14
-; GFX8-NEXT: s_mov_b32 s14, s16
-; GFX8-NEXT: s_mov_b32 s16, s18
-; GFX8-NEXT: s_mov_b32 s18, s20
-; GFX8-NEXT: s_mov_b32 s20, s22
-; GFX8-NEXT: s_mov_b32 s22, s24
-; GFX8-NEXT: s_mov_b32 s24, s26
-; GFX8-NEXT: s_mov_b32 s26, s28
-; GFX8-NEXT: s_mov_b32 s28, s30
; GFX8-NEXT: s_mov_b32 s30, s32
-; GFX8-NEXT: v_mov_b32_e32 v33, s31
; GFX8-NEXT: s_lshl_b32 m0, s34, 1
+; GFX8-NEXT: v_mov_b32_e32 v33, s31
; GFX8-NEXT: v_mov_b32_e32 v32, s30
; GFX8-NEXT: v_mov_b32_e32 v31, s29
; GFX8-NEXT: v_mov_b32_e32 v30, s28
@@ -6451,40 +6451,40 @@ entry:
define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inreg %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v16f64_s_v_s:
; GPRIDX: ; %bb.0: ; %entry
+; GPRIDX-NEXT: s_mov_b32 s0, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
; GPRIDX-NEXT: s_mov_b32 s7, s9
+; GPRIDX-NEXT: s_mov_b32 s8, s10
; GPRIDX-NEXT: s_mov_b32 s9, s11
+; GPRIDX-NEXT: s_mov_b32 s10, s12
; GPRIDX-NEXT: s_mov_b32 s11, s13
+; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s13, s15
+; GPRIDX-NEXT: s_mov_b32 s14, s16
; GPRIDX-NEXT: s_mov_b32 s15, s17
+; GPRIDX-NEXT: s_mov_b32 s16, s18
; GPRIDX-NEXT: s_mov_b32 s17, s19
+; GPRIDX-NEXT: s_mov_b32 s18, s20
; GPRIDX-NEXT: s_mov_b32 s19, s21
+; GPRIDX-NEXT: s_mov_b32 s20, s22
; GPRIDX-NEXT: s_mov_b32 s21, s23
+; GPRIDX-NEXT: s_mov_b32 s22, s24
; GPRIDX-NEXT: s_mov_b32 s23, s25
+; GPRIDX-NEXT: s_mov_b32 s24, s26
; GPRIDX-NEXT: s_mov_b32 s25, s27
+; GPRIDX-NEXT: s_mov_b32 s26, s28
; GPRIDX-NEXT: s_mov_b32 s27, s29
+; GPRIDX-NEXT: s_mov_b32 s28, s30
; GPRIDX-NEXT: s_mov_b32 s29, s31
; GPRIDX-NEXT: s_mov_b32 s31, s33
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s14, s16
-; GPRIDX-NEXT: s_mov_b32 s16, s18
-; GPRIDX-NEXT: s_mov_b32 s18, s20
-; GPRIDX-NEXT: s_mov_b32 s20, s22
-; GPRIDX-NEXT: s_mov_b32 s22, s24
-; GPRIDX-NEXT: s_mov_b32 s24, s26
-; GPRIDX-NEXT: s_mov_b32 s26, s28
-; GPRIDX-NEXT: s_mov_b32 s28, s30
; GPRIDX-NEXT: s_mov_b32 s30, s32
-; GPRIDX-NEXT: v_mov_b32_e32 v33, s31
; GPRIDX-NEXT: s_lshl_b32 s33, s34, 1
+; GPRIDX-NEXT: v_mov_b32_e32 v33, s31
; GPRIDX-NEXT: v_mov_b32_e32 v32, s30
; GPRIDX-NEXT: v_mov_b32_e32 v31, s29
; GPRIDX-NEXT: v_mov_b32_e32 v30, s28
@@ -6556,41 +6556,41 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inr
;
; GFX10-LABEL: dyn_insertelement_v16f64_s_v_s:
; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s14, s16
; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s16, s18
; GFX10-NEXT: s_mov_b32 s17, s19
+; GFX10-NEXT: s_mov_b32 s18, s20
; GFX10-NEXT: s_mov_b32 s19, s21
+; GFX10-NEXT: s_mov_b32 s20, s22
; GFX10-NEXT: s_mov_b32 s21, s23
+; GFX10-NEXT: s_mov_b32 s22, s24
; GFX10-NEXT: s_mov_b32 s23, s25
+; GFX10-NEXT: s_mov_b32 s24, s26
; GFX10-NEXT: s_mov_b32 s25, s27
+; GFX10-NEXT: s_mov_b32 s26, s28
; GFX10-NEXT: s_mov_b32 s27, s29
+; GFX10-NEXT: s_mov_b32 s28, s30
; GFX10-NEXT: s_mov_b32 s29, s31
; GFX10-NEXT: s_mov_b32 s31, s33
-; GFX10-NEXT: s_mov_b32 s0, s2
-; GFX10-NEXT: s_mov_b32 s2, s4
-; GFX10-NEXT: s_mov_b32 s4, s6
-; GFX10-NEXT: s_mov_b32 s6, s8
-; GFX10-NEXT: s_mov_b32 s8, s10
-; GFX10-NEXT: s_mov_b32 s10, s12
-; GFX10-NEXT: s_mov_b32 s12, s14
-; GFX10-NEXT: s_mov_b32 s14, s16
-; GFX10-NEXT: s_mov_b32 s16, s18
-; GFX10-NEXT: s_mov_b32 s18, s20
-; GFX10-NEXT: s_mov_b32 s20, s22
-; GFX10-NEXT: s_mov_b32 s22, s24
-; GFX10-NEXT: s_mov_b32 s24, s26
-; GFX10-NEXT: s_mov_b32 s26, s28
-; GFX10-NEXT: s_mov_b32 s28, s30
; GFX10-NEXT: s_mov_b32 s30, s32
-; GFX10-NEXT: v_mov_b32_e32 v33, s31
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshl_b32 m0, s34, 1
+; GFX10-NEXT: v_mov_b32_e32 v33, s31
; GFX10-NEXT: v_mov_b32_e32 v32, s30
; GFX10-NEXT: v_mov_b32_e32 v31, s29
; GFX10-NEXT: v_mov_b32_e32 v30, s28
@@ -6659,41 +6659,41 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inr
;
; GFX11-LABEL: dyn_insertelement_v16f64_s_v_s:
; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s14, s16
; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s16, s18
; GFX11-NEXT: s_mov_b32 s17, s19
+; GFX11-NEXT: s_mov_b32 s18, s20
; GFX11-NEXT: s_mov_b32 s19, s21
+; GFX11-NEXT: s_mov_b32 s20, s22
; GFX11-NEXT: s_mov_b32 s21, s23
+; GFX11-NEXT: s_mov_b32 s22, s24
; GFX11-NEXT: s_mov_b32 s23, s25
+; GFX11-NEXT: s_mov_b32 s24, s26
; GFX11-NEXT: s_mov_b32 s25, s27
+; GFX11-NEXT: s_mov_b32 s26, s28
; GFX11-NEXT: s_mov_b32 s27, s29
+; GFX11-NEXT: s_mov_b32 s28, s30
; GFX11-NEXT: s_mov_b32 s29, s31
; GFX11-NEXT: s_mov_b32 s31, s33
-; GFX11-NEXT: s_mov_b32 s0, s2
-; GFX11-NEXT: s_mov_b32 s2, s4
-; GFX11-NEXT: s_mov_b32 s4, s6
-; GFX11-NEXT: s_mov_b32 s6, s8
-; GFX11-NEXT: s_mov_b32 s8, s10
-; GFX11-NEXT: s_mov_b32 s10, s12
-; GFX11-NEXT: s_mov_b32 s12, s14
-; GFX11-NEXT: s_mov_b32 s14, s16
-; GFX11-NEXT: s_mov_b32 s16, s18
-; GFX11-NEXT: s_mov_b32 s18, s20
-; GFX11-NEXT: s_mov_b32 s20, s22
-; GFX11-NEXT: s_mov_b32 s22, s24
-; GFX11-NEXT: s_mov_b32 s24, s26
-; GFX11-NEXT: s_mov_b32 s26, s28
-; GFX11-NEXT: s_mov_b32 s28, s30
; GFX11-NEXT: s_mov_b32 s30, s32
-; GFX11-NEXT: v_dual_mov_b32 v33, s31 :: v_dual_mov_b32 v32, s30
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: s_lshl_b32 m0, s34, 1
+; GFX11-NEXT: v_dual_mov_b32 v33, s31 :: v_dual_mov_b32 v32, s30
; GFX11-NEXT: v_dual_mov_b32 v31, s29 :: v_dual_mov_b32 v30, s28
; GFX11-NEXT: v_dual_mov_b32 v29, s27 :: v_dual_mov_b32 v28, s26
; GFX11-NEXT: v_dual_mov_b32 v27, s25 :: v_dual_mov_b32 v26, s24
@@ -6746,40 +6746,40 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inr
;
; GFX8-LABEL: dyn_insertelement_v16f64_s_v_s:
; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s16, s18
; GFX8-NEXT: s_mov_b32 s17, s19
+; GFX8-NEXT: s_mov_b32 s18, s20
; GFX8-NEXT: s_mov_b32 s19, s21
+; GFX8-NEXT: s_mov_b32 s20, s22
; GFX8-NEXT: s_mov_b32 s21, s23
+; GFX8-NEXT: s_mov_b32 s22, s24
; GFX8-NEXT: s_mov_b32 s23, s25
+; GFX8-NEXT: s_mov_b32 s24, s26
; GFX8-NEXT: s_mov_b32 s25, s27
+; GFX8-NEXT: s_mov_b32 s26, s28
; GFX8-NEXT: s_mov_b32 s27, s29
+; GFX8-NEXT: s_mov_b32 s28, s30
; GFX8-NEXT: s_mov_b32 s29, s31
; GFX8-NEXT: s_mov_b32 s31, s33
-; GFX8-NEXT: s_mov_b32 s0, s2
-; GFX8-NEXT: s_mov_b32 s2, s4
-; GFX8-NEXT: s_mov_b32 s4, s6
-; GFX8-NEXT: s_mov_b32 s6, s8
-; GFX8-NEXT: s_mov_b32 s8, s10
-; GFX8-NEXT: s_mov_b32 s10, s12
-; GFX8-NEXT: s_mov_b32 s12, s14
-; GFX8-NEXT: s_mov_b32 s14, s16
-; GFX8-NEXT: s_mov_b32 s16, s18
-; GFX8-NEXT: s_mov_b32 s18, s20
-; GFX8-NEXT: s_mov_b32 s20, s22
-; GFX8-NEXT: s_mov_b32 s22, s24
-; GFX8-NEXT: s_mov_b32 s24, s26
-; GFX8-NEXT: s_mov_b32 s26, s28
-; GFX8-NEXT: s_mov_b32 s28, s30
; GFX8-NEXT: s_mov_b32 s30, s32
-; GFX8-NEXT: v_mov_b32_e32 v33, s31
; GFX8-NEXT: s_lshl_b32 m0, s34, 1
+; GFX8-NEXT: v_mov_b32_e32 v33, s31
; GFX8-NEXT: v_mov_b32_e32 v32, s30
; GFX8-NEXT: v_mov_b32_e32 v31, s29
; GFX8-NEXT: v_mov_b32_e32 v30, s28
@@ -7337,9 +7337,9 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s13, s15
-; GFX10-NEXT: v_mov_b32_e32 v17, s15
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshl_b32 m0, s16, 1
+; GFX10-NEXT: v_mov_b32_e32 v17, s15
; GFX10-NEXT: v_mov_b32_e32 v16, s14
; GFX10-NEXT: v_mov_b32_e32 v15, s13
; GFX10-NEXT: v_mov_b32_e32 v14, s12
@@ -7388,9 +7388,9 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s13, s15
-; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: s_lshl_b32 m0, s16, 1
+; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
@@ -8021,16 +8021,16 @@ entry:
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_s_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10
+; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: v_mov_b32_e32 v11, s9
; GPRIDX-NEXT: v_mov_b32_e32 v10, s8
; GPRIDX-NEXT: v_mov_b32_e32 v9, s7
@@ -8060,19 +8060,19 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
;
; GFX10-LABEL: dyn_insertelement_v5f64_s_v_s:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 s3, s5
-; GFX10-NEXT: s_mov_b32 s5, s7
-; GFX10-NEXT: s_mov_b32 s7, s9
-; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10
-; GFX10-NEXT: v_mov_b32_e32 v11, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshl_b32 m0, s12, 1
+; GFX10-NEXT: v_mov_b32_e32 v11, s9
; GFX10-NEXT: v_mov_b32_e32 v10, s8
; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s6
@@ -8097,19 +8097,19 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
;
; GFX11-LABEL: dyn_insertelement_v5f64_s_v_s:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 s3, s5
-; GFX11-NEXT: s_mov_b32 s5, s7
-; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10
-; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: s_lshl_b32 m0, s12, 1
+; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
@@ -8129,16 +8129,16 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
;
; GFX8-LABEL: dyn_insertelement_v5f64_s_v_s:
; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_mov_b32 s1, s3
-; GFX8-NEXT: s_mov_b32 s3, s5
-; GFX8-NEXT: s_mov_b32 s5, s7
-; GFX8-NEXT: s_mov_b32 s7, s9
-; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: v_mov_b32_e32 v11, s9
; GFX8-NEXT: v_mov_b32_e32 v10, s8
; GFX8-NEXT: v_mov_b32_e32 v9, s7
@@ -8171,17 +8171,16 @@ entry:
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_s_v_v:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: v_mov_b32_e32 v12, s9
+; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: v_mov_b32_e32 v4, s1
; GPRIDX-NEXT: v_mov_b32_e32 v3, s0
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
@@ -8195,6 +8194,7 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
+; GPRIDX-NEXT: v_mov_b32_e32 v12, s9
; GPRIDX-NEXT: v_mov_b32_e32 v11, s8
; GPRIDX-NEXT: v_mov_b32_e32 v10, s7
; GPRIDX-NEXT: v_mov_b32_e32 v9, s6
@@ -8220,18 +8220,18 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
;
; GFX10-LABEL: dyn_insertelement_v5f64_s_v_v:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 s3, s5
-; GFX10-NEXT: s_mov_b32 s5, s7
-; GFX10-NEXT: s_mov_b32 s7, s9
-; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10
-; GFX10-NEXT: v_mov_b32_e32 v12, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: v_mov_b32_e32 v11, s8
+; GFX10-NEXT: v_mov_b32_e32 v12, s9
; GFX10-NEXT: v_mov_b32_e32 v10, s7
; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s5
@@ -8269,17 +8269,17 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
;
; GFX11-LABEL: dyn_insertelement_v5f64_s_v_v:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 s3, s5
-; GFX11-NEXT: s_mov_b32 s5, s7
-; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10
-; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v12, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
@@ -8311,17 +8311,16 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
;
; GFX8-LABEL: dyn_insertelement_v5f64_s_v_v:
; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_mov_b32 s1, s3
-; GFX8-NEXT: s_mov_b32 s3, s5
-; GFX8-NEXT: s_mov_b32 s5, s7
-; GFX8-NEXT: s_mov_b32 s7, s9
-; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
; GFX8-NEXT: s_mov_b32 s8, s10
-; GFX8-NEXT: v_mov_b32_e32 v12, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
; GFX8-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
@@ -8335,6 +8334,7 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
+; GFX8-NEXT: v_mov_b32_e32 v12, s9
; GFX8-NEXT: v_mov_b32_e32 v11, s8
; GFX8-NEXT: v_mov_b32_e32 v10, s7
; GFX8-NEXT: v_mov_b32_e32 v9, s6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
index 4cc692406dee3..bb970bce13a22 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
@@ -28,8 +28,8 @@ define amdgpu_kernel void @fcmp_uniform_select(float %a, i32 %b, i32 %c, ptr add
; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], s0, 0
; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX8-NEXT: s_cselect_b32 s0, s1, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
index e4135fae40006..31f83ed2c66d7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
@@ -17,8 +17,8 @@ define amdgpu_kernel void @use_lds_globals(ptr addrspace(1) %out, ptr addrspace(
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_add_u32 s0, s0, 4
; CHECK-NEXT: s_addc_u32 s1, s1, 0
-; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
; CHECK-NEXT: v_mov_b32_e32 v1, s1
; CHECK-NEXT: v_mov_b32_e32 v3, 9
; CHECK-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
index 19882eb011d1f..2ddaa4292bad6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
@@ -179,10 +179,10 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double
; GFX7: ; %bb.0:
; GFX7-NEXT: s_cmp_eq_u32 s6, 0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-NEXT: v_mov_b32_e32 v2, s2
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: s_cselect_b64 vcc, exec, 0
; GFX7-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
@@ -194,10 +194,10 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double
; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_eq_u32 s6, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
; GFX8-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
@@ -208,8 +208,8 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double
; GFX10_W32-LABEL: s_div_fmas_f64:
; GFX10_W32: ; %bb.0:
; GFX10_W32-NEXT: v_mov_b32_e32 v0, s2
-; GFX10_W32-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W32-NEXT: v_mov_b32_e32 v1, s3
+; GFX10_W32-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W32-NEXT: v_mov_b32_e32 v3, s5
; GFX10_W32-NEXT: s_cmp_eq_u32 s6, 0
; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
@@ -221,8 +221,8 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double
; GFX10_W64-LABEL: s_div_fmas_f64:
; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2
-; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3
+; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5
; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0
; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0
@@ -245,8 +245,8 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double
; GFX11_W64-LABEL: s_div_fmas_f64:
; GFX11_W64: ; %bb.0:
; GFX11_W64-NEXT: v_mov_b32_e32 v0, s2
-; GFX11_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX11_W64-NEXT: v_mov_b32_e32 v1, s3
+; GFX11_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX11_W64-NEXT: v_mov_b32_e32 v3, s5
; GFX11_W64-NEXT: s_cmp_eq_u32 s6, 0
; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0
@@ -690,11 +690,11 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d
; GFX7-NEXT: s_load_dword s0, s[4:5], 0x8
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s10
-; GFX7-NEXT: v_mov_b32_e32 v2, s12
-; GFX7-NEXT: v_mov_b32_e32 v4, s14
; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: v_mov_b32_e32 v1, s11
+; GFX7-NEXT: v_mov_b32_e32 v2, s12
; GFX7-NEXT: v_mov_b32_e32 v3, s13
+; GFX7-NEXT: v_mov_b32_e32 v4, s14
; GFX7-NEXT: v_mov_b32_e32 v5, s15
; GFX7-NEXT: s_cselect_b64 vcc, exec, 0
; GFX7-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
@@ -709,11 +709,11 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d
; GFX8-NEXT: s_load_dword s0, s[4:5], 0x20
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s10
-; GFX8-NEXT: v_mov_b32_e32 v2, s12
-; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: v_mov_b32_e32 v1, s11
+; GFX8-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NEXT: v_mov_b32_e32 v3, s13
+; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: v_mov_b32_e32 v5, s15
; GFX8-NEXT: s_cselect_b64 vcc, exec, 0
; GFX8-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
@@ -729,8 +729,8 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d
; GFX10_W32-NEXT: s_load_dword s0, s[4:5], 0x20
; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W32-NEXT: v_mov_b32_e32 v0, s12
-; GFX10_W32-NEXT: v_mov_b32_e32 v2, s14
; GFX10_W32-NEXT: v_mov_b32_e32 v1, s13
+; GFX10_W32-NEXT: v_mov_b32_e32 v2, s14
; GFX10_W32-NEXT: v_mov_b32_e32 v3, s15
; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0
@@ -746,8 +746,8 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d
; GFX10_W64-NEXT: s_load_dword s0, s[4:5], 0x20
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s12
-; GFX10_W64-NEXT: v_mov_b32_e32 v2, s14
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s13
+; GFX10_W64-NEXT: v_mov_b32_e32 v2, s14
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s15
; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W64-NEXT: s_cselect_b64 vcc, exec, 0
@@ -778,8 +778,8 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d
; GFX11_W64-NEXT: s_load_b32 s0, s[4:5], 0x20
; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11_W64-NEXT: v_mov_b32_e32 v0, s12
-; GFX11_W64-NEXT: v_mov_b32_e32 v2, s14
; GFX11_W64-NEXT: v_mov_b32_e32 v1, s13
+; GFX11_W64-NEXT: v_mov_b32_e32 v2, s14
; GFX11_W64-NEXT: v_mov_b32_e32 v3, s15
; GFX11_W64-NEXT: s_cmp_lg_u32 s0, 0
; GFX11_W64-NEXT: s_cselect_b64 vcc, exec, 0
@@ -1149,9 +1149,9 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(ptr addrspace(1
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0
; GFX8-NEXT: s_and_b64 vcc, vcc, s[2:3]
-; GFX8-NEXT: s_nop 1
-; GFX8-NEXT: v_div_fmas_f32 v2, v1, v2, v3
; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: s_nop 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v1, v2, v3
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -1299,8 +1299,8 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, [
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x28
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: flat_load_dwordx3 v[1:3], v[1:2]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
index fb35a2ab1b3d8..93a3a9f0387b8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
@@ -379,10 +379,10 @@ define amdgpu_kernel void @test_div_scale_f32_scalar_num_1(ptr addrspace(1) %out
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v0, v0, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -453,10 +453,10 @@ define amdgpu_kernel void @test_div_scale_f32_scalar_num_2(ptr addrspace(1) %out
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], s4, v0, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -527,10 +527,10 @@ define amdgpu_kernel void @test_div_scale_f32_scalar_den_1(ptr addrspace(1) %out
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], s4, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -601,10 +601,10 @@ define amdgpu_kernel void @test_div_scale_f32_scalar_den_2(ptr addrspace(1) %out
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v0, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -1213,10 +1213,10 @@ define amdgpu_kernel void @test_div_scale_f32_inline_imm_num(ptr addrspace(1) %o
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v0, v0, 1.0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -1282,10 +1282,10 @@ define amdgpu_kernel void @test_div_scale_f32_inline_imm_den(ptr addrspace(1) %o
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], 2.0, 2.0, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
index 676bd8856ce6e..bf3262deca0c6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
@@ -66,15 +66,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r
; GFX9-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_lshl_or_b32 v11, v3, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v6, v5
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v8, v5
; GFX9-NEXT: v_mov_b32_e32 v9, v5
-; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: s_mov_b32 s0, s2
; GFX9-NEXT: s_mov_b32 s1, s3
; GFX9-NEXT: s_mov_b32 s2, s4
@@ -83,6 +81,8 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s8
; GFX9-NEXT: s_mov_b32 s7, s9
+; GFX9-NEXT: v_lshl_or_b32 v11, v3, 16, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: v_mov_b32_e32 v1, v6
; GFX9-NEXT: v_mov_b32_e32 v2, v7
; GFX9-NEXT: v_mov_b32_e32 v3, v8
@@ -190,15 +190,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre
; GFX9-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_lshl_or_b32 v11, v3, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v6, v5
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v8, v5
; GFX9-NEXT: v_mov_b32_e32 v9, v5
-; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: s_mov_b32 s0, s2
; GFX9-NEXT: s_mov_b32 s1, s3
; GFX9-NEXT: s_mov_b32 s2, s4
@@ -207,6 +205,8 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s8
; GFX9-NEXT: s_mov_b32 s7, s9
+; GFX9-NEXT: v_lshl_or_b32 v11, v3, 16, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: v_mov_b32_e32 v1, v6
; GFX9-NEXT: v_mov_b32_e32 v2, v7
; GFX9-NEXT: v_mov_b32_e32 v3, v8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
index 8d62725006b90..d2e25d601763f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
@@ -66,16 +66,14 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr
; GFX9-LABEL: load_3d_v4f32_xyzw_tfe:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_mov_b32 s0, s2
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_lshl_or_b32 v11, s0, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v6, v5
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v8, v5
; GFX9-NEXT: v_mov_b32_e32 v9, v5
-; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: s_mov_b32 s1, s3
; GFX9-NEXT: s_mov_b32 s2, s4
; GFX9-NEXT: s_mov_b32 s3, s5
@@ -83,6 +81,8 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s8
; GFX9-NEXT: s_mov_b32 s7, s9
+; GFX9-NEXT: v_lshl_or_b32 v11, s0, 16, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: v_mov_b32_e32 v1, v6
; GFX9-NEXT: v_mov_b32_e32 v2, v7
; GFX9-NEXT: v_mov_b32_e32 v3, v8
@@ -184,16 +184,14 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc,
; GFX9-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_mov_b32 s0, s2
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_lshl_or_b32 v11, s0, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v6, v5
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v8, v5
; GFX9-NEXT: v_mov_b32_e32 v9, v5
-; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: s_mov_b32 s1, s3
; GFX9-NEXT: s_mov_b32 s2, s4
; GFX9-NEXT: s_mov_b32 s3, s5
@@ -201,6 +199,8 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc,
; GFX9-NEXT: s_mov_b32 s5, s7
; GFX9-NEXT: s_mov_b32 s6, s8
; GFX9-NEXT: s_mov_b32 s7, s9
+; GFX9-NEXT: v_lshl_or_b32 v11, s0, 16, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: v_mov_b32_e32 v1, v6
; GFX9-NEXT: v_mov_b32_e32 v2, v7
; GFX9-NEXT: v_mov_b32_e32 v3, v8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
index c1c383eb583aa..48a854a71a088 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
@@ -698,7 +698,6 @@ define amdgpu_ps void @image_store_v4f32_dmask_0110(<8 x i32> inreg %rsrc, i32 %
define amdgpu_ps void @image_store_f32_dmask_1111(<8 x i32> inreg %rsrc, i32 inreg %s, i32 inreg %t, float %in) #0 {
; GFX6-LABEL: image_store_f32_dmask_1111:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v1, s10
; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, s4
@@ -707,13 +706,13 @@ define amdgpu_ps void @image_store_f32_dmask_1111(<8 x i32> inreg %rsrc, i32 inr
; GFX6-NEXT: s_mov_b32 s5, s7
; GFX6-NEXT: s_mov_b32 s6, s8
; GFX6-NEXT: s_mov_b32 s7, s9
+; GFX6-NEXT: v_mov_b32_e32 v1, s10
; GFX6-NEXT: v_mov_b32_e32 v2, s11
; GFX6-NEXT: image_store v0, v[1:2], s[0:7] dmask:0xf unorm
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: image_store_f32_dmask_1111:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v1, s10
; GFX8-NEXT: s_mov_b32 s0, s2
; GFX8-NEXT: s_mov_b32 s1, s3
; GFX8-NEXT: s_mov_b32 s2, s4
@@ -722,6 +721,7 @@ define amdgpu_ps void @image_store_f32_dmask_1111(<8 x i32> inreg %rsrc, i32 inr
; GFX8-NEXT: s_mov_b32 s5, s7
; GFX8-NEXT: s_mov_b32 s6, s8
; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: v_mov_b32_e32 v1, s10
; GFX8-NEXT: v_mov_b32_e32 v2, s11
; GFX8-NEXT: image_store v0, v[1:2], s[0:7] dmask:0xf unorm
; GFX8-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index 3c2a65084381d..2b9094d1664a3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -770,18 +770,19 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX11-NEXT: s_mov_b32 s10, 0x40a00000
; GFX11-NEXT: s_mov_b32 s9, 4.0
; GFX11-NEXT: s_mov_b32 s8, 0x40400000
-; GFX11-NEXT: s_mov_b32 s12, 0x40c00000
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX11-NEXT: s_mov_b32 s14, 0x41000000
; GFX11-NEXT: s_mov_b32 s13, 0x40e00000
-; GFX11-NEXT: v_mov_b32_e32 v6, s12
-; GFX11-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v7, s13
+; GFX11-NEXT: s_mov_b32 s12, 0x40c00000
+; GFX11-NEXT: v_mov_b32_e32 v8, s14
+; GFX11-NEXT: v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v5, s10
+; GFX11-NEXT: v_mov_b32_e32 v7, s13
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0
+; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX11-NEXT: s_mov_b32 s2, 2.0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_mov_b32 s1, 1.0
+; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -790,9 +791,9 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: flat_load_b32 v9, v[0:1]
; GFX11-NEXT: flat_load_b32 v10, v[2:3]
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8
+; GFX11-NEXT: v_mov_b32_e32 v4, s9
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[0:2], v[3:5], v[6:8]], s[4:7]
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -879,14 +880,15 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX11-NEXT: s_mov_b32 s8, 0x42004600
; GFX11-NEXT: s_mov_b32 s9, 0x44004700
; GFX11-NEXT: s_mov_b32 s10, 0x45004800
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v5, s10
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0
+; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX11-NEXT: s_mov_b32 s2, 2.0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_mov_b32 s1, 1.0
+; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -895,9 +897,9 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: flat_load_b32 v6, v[0:1]
; GFX11-NEXT: flat_load_b32 v7, v[2:3]
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8
+; GFX11-NEXT: v_mov_b32_e32 v4, s9
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -989,28 +991,28 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-NEXT: s_mov_b32 s5, 1.0
; GFX11-NEXT: s_mov_b32 s4, 0
-; GFX11-NEXT: v_mov_b32_e32 v9, 0xb36211c7
-; GFX11-NEXT: s_mov_b32 s8, 0x40400000
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX11-NEXT: s_mov_b32 s12, 0x40c00000
; GFX11-NEXT: s_mov_b32 s10, 0x40a00000
; GFX11-NEXT: s_mov_b32 s9, 4.0
+; GFX11-NEXT: s_mov_b32 s8, 0x40400000
; GFX11-NEXT: s_mov_b32 s14, 0x41000000
; GFX11-NEXT: s_mov_b32 s13, 0x40e00000
-; GFX11-NEXT: v_mov_b32_e32 v6, s12
+; GFX11-NEXT: s_mov_b32 s12, 0x40c00000
; GFX11-NEXT: v_bfrev_b32_e32 v10, 4.0
-; GFX11-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v3, s8
; GFX11-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v7, s13
+; GFX11-NEXT: v_mov_b32_e32 v6, s12
+; GFX11-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, 0xb36211c7
+; GFX11-NEXT: v_mov_b32_e32 v5, s10
+; GFX11-NEXT: v_mov_b32_e32 v3, s8
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v0, s6
-; GFX11-NEXT: v_mov_b32_e32 v1, s7
+; GFX11-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s6
; GFX11-NEXT: s_mov_b32 s6, 2.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: flat_load_b32 v11, v[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[0:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1096,21 +1098,21 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
; GFX11-NEXT: s_mov_b32 s4, 0
; GFX11-NEXT: s_mov_b32 s8, 0x42004600
; GFX11-NEXT: s_mov_b32 s9, 0x44004700
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX11-NEXT: s_mov_b32 s10, 0x45004800
-; GFX11-NEXT: v_mov_b32_e32 v6, 0xb36211c6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v5, s10
; GFX11-NEXT: v_bfrev_b32_e32 v7, 4.0
-; GFX11-NEXT: v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9
+; GFX11-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v3, s8
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v0, s6
-; GFX11-NEXT: v_mov_b32_e32 v1, s7
+; GFX11-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s6
; GFX11-NEXT: s_mov_b32 s6, 2.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: flat_load_b32 v8, v[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16
; GFX11-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
index e5d9884e5ee29..28d1bd0eb3b63 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
@@ -10,10 +10,10 @@ define amdgpu_kernel void @dpp_test(ptr addrspace(1) %out, i32 %in1, i32 %in2) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s3
-; GFX8-NEXT: s_nop 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
index 535df5e8e6a6f..fd40950ceb3c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
@@ -4,8 +4,8 @@
define amdgpu_ps i32 @test_global_p1_s32_uniform(ptr addrspace(1) inreg %ptr, i32 inreg %cmp, i32 inreg %new) {
; GFX9-LABEL: test_global_p1_s32_uniform:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s4, s3
; GFX9-NEXT: s_mov_b32 s5, s2
+; GFX9-NEXT: s_mov_b32 s4, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, 0
@@ -75,11 +75,11 @@ define amdgpu_ps i64 @test_global_p1_s64_divergent(ptr addrspace(1) %ptr, i64 %c
define amdgpu_ps i32 @test_flat_p0_s32_uniform(ptr inreg %ptr, i32 inreg %cmp, i32 inreg %new) {
; GFX9-LABEL: test_flat_p0_s32_uniform:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s4, s3
; GFX9-NEXT: s_mov_b32 s5, s2
+; GFX9-NEXT: s_mov_b32 s4, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -108,11 +108,11 @@ define amdgpu_ps i32 @test_flat_p0_s32_divergent(ptr %ptr, i32 %cmp, i32 %new) {
define amdgpu_ps i32 @test_flat_p0_s32_uniform_noalias_private(ptr inreg %ptr, i32 inreg %cmp, i32 inreg %new) {
; GFX9-LABEL: test_flat_p0_s32_uniform_noalias_private:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s4, s3
; GFX9-NEXT: s_mov_b32 s5, s2
+; GFX9-NEXT: s_mov_b32 s4, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -157,8 +157,8 @@ define amdgpu_ps i64 @test_flat_p0_s64_uniform_noalias_private(ptr inreg %ptr, i
; GFX9-NEXT: s_mov_b32 s6, s2
; GFX9-NEXT: s_mov_b32 s7, s3
; GFX9-NEXT: v_mov_b32_e32 v5, s1
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v4, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
@@ -236,8 +236,8 @@ define amdgpu_kernel void @test_region_p2_s64_uniform(ptr addrspace(2) %gds, i64
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v4, s6
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: ds_cmpst_b64 v4, v[0:1], v[2:3] gds
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
@@ -256,8 +256,8 @@ define amdgpu_kernel void @test_region_p2_s64_divergent(ptr addrspace(2) %gds_ba
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v4, s6, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: ds_cmpst_b64 v4, v[0:1], v[2:3] gds
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
@@ -303,10 +303,10 @@ define amdgpu_ps i64 @test_local_p3_s64_uniform(ptr addrspace(3) inreg %ptr, i64
; GFX9-NEXT: s_mov_b32 s7, s2
; GFX9-NEXT: s_mov_b32 s2, s3
; GFX9-NEXT: s_mov_b32 s3, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v4, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s7
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: ds_cmpst_rtn_b64 v[0:1], v4, v[0:1], v[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
index b6933acafb5f0..53cfa45632e3b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
@@ -291,10 +291,10 @@ define amdgpu_ps void @test_s_load_constant_v8i32_align1(ptr addrspace(4) inreg
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s8, v4
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_readfirstlane_b32 s9, v5
; GFX9-NEXT: v_readfirstlane_b32 s10, v6
; GFX9-NEXT: v_readfirstlane_b32 s11, v7
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
@@ -322,10 +322,10 @@ define amdgpu_ps void @test_s_load_constant_v8i32_align1(ptr addrspace(4) inreg
; GFX7-NEXT: v_readfirstlane_b32 s3, v3
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readfirstlane_b32 s8, v4
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_readfirstlane_b32 s9, v5
; GFX7-NEXT: v_readfirstlane_b32 s10, v6
; GFX7-NEXT: v_readfirstlane_b32 s11, v7
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
index f25904350d8d9..29d6615657d64 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
@@ -406,12 +406,12 @@ define amdgpu_ps void @load_uniform_P1_v2i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX7-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s2, 0
-; GFX7-NEXT: v_readfirstlane_b32 s1, v3
-; GFX7-NEXT: v_readfirstlane_b32 s5, v5
; GFX7-NEXT: v_readfirstlane_b32 s0, v2
+; GFX7-NEXT: v_readfirstlane_b32 s1, v3
; GFX7-NEXT: v_readfirstlane_b32 s4, v4
-; GFX7-NEXT: s_add_i32 s1, s1, s5
+; GFX7-NEXT: v_readfirstlane_b32 s5, v5
; GFX7-NEXT: s_add_i32 s0, s0, s4
+; GFX7-NEXT: s_add_i32 s1, s1, s5
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: s_mov_b64 s[0:1], 0
@@ -432,7 +432,7 @@ define amdgpu_ps void @load_uniform_P1_v2i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX11-NEXT: s_add_i32 s0, s0, s2
; GFX11-NEXT: s_add_i32 s1, s1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_endpgm
;
@@ -450,7 +450,7 @@ define amdgpu_ps void @load_uniform_P1_v2i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX12-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-NEXT: s_add_co_i32 s1, s1, s3
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_endpgm
%a = load <2 x i32>, ptr addrspace(1) %ptra, align 2
@@ -471,9 +471,9 @@ define amdgpu_ps void @load_uniform_P1_v3i32_gfx12(ptr addrspace(1) inreg %ptra,
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_readfirstlane_b32 s0, v2
-; GFX7-NEXT: v_readfirstlane_b32 s4, v5
; GFX7-NEXT: v_readfirstlane_b32 s1, v3
; GFX7-NEXT: v_readfirstlane_b32 s6, v4
+; GFX7-NEXT: v_readfirstlane_b32 s4, v5
; GFX7-NEXT: v_readfirstlane_b32 s5, v6
; GFX7-NEXT: v_readfirstlane_b32 s7, v7
; GFX7-NEXT: s_add_i32 s4, s0, s4
@@ -493,17 +493,17 @@ define amdgpu_ps void @load_uniform_P1_v3i32_gfx12(ptr addrspace(1) inreg %ptra,
; GFX11-NEXT: global_load_b96 v[2:4], v5, s[0:1]
; GFX11-NEXT: global_load_b96 v[5:7], v5, s[0:1] glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-NEXT: v_readfirstlane_b32 s5, v7
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: v_readfirstlane_b32 s4, v6
-; GFX11-NEXT: s_add_i32 s2, s2, s5
+; GFX11-NEXT: v_readfirstlane_b32 s5, v7
; GFX11-NEXT: s_add_i32 s0, s0, s3
; GFX11-NEXT: s_add_i32 s1, s1, s4
+; GFX11-NEXT: s_add_i32 s2, s2, s5
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off
; GFX11-NEXT: s_endpgm
@@ -515,17 +515,17 @@ define amdgpu_ps void @load_uniform_P1_v3i32_gfx12(ptr addrspace(1) inreg %ptra,
; GFX12-NEXT: global_load_b96 v[2:4], v5, s[0:1]
; GFX12-NEXT: global_load_b96 v[5:7], v5, s[0:1] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s2, v4
-; GFX12-NEXT: v_readfirstlane_b32 s5, v7
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12-NEXT: v_readfirstlane_b32 s2, v4
; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: v_readfirstlane_b32 s4, v6
-; GFX12-NEXT: s_add_co_i32 s2, s2, s5
+; GFX12-NEXT: v_readfirstlane_b32 s5, v7
; GFX12-NEXT: s_add_co_i32 s0, s0, s3
; GFX12-NEXT: s_add_co_i32 s1, s1, s4
+; GFX12-NEXT: s_add_co_i32 s2, s2, s5
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1
+; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off
; GFX12-NEXT: s_endpgm
@@ -547,10 +547,10 @@ define amdgpu_ps void @load_uniform_P1_v4i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_readfirstlane_b32 s0, v2
-; GFX7-NEXT: v_readfirstlane_b32 s4, v6
; GFX7-NEXT: v_readfirstlane_b32 s1, v3
; GFX7-NEXT: v_readfirstlane_b32 s6, v4
; GFX7-NEXT: v_readfirstlane_b32 s7, v5
+; GFX7-NEXT: v_readfirstlane_b32 s4, v6
; GFX7-NEXT: v_readfirstlane_b32 s5, v7
; GFX7-NEXT: v_readfirstlane_b32 s8, v8
; GFX7-NEXT: v_readfirstlane_b32 s9, v9
@@ -573,20 +573,20 @@ define amdgpu_ps void @load_uniform_P1_v4i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX11-NEXT: global_load_b128 v[2:5], v6, s[0:1]
; GFX11-NEXT: global_load_b128 v[6:9], v6, s[0:1] glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-NEXT: v_readfirstlane_b32 s7, v9
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: v_readfirstlane_b32 s4, v6
; GFX11-NEXT: v_readfirstlane_b32 s5, v7
; GFX11-NEXT: v_readfirstlane_b32 s6, v8
-; GFX11-NEXT: s_add_i32 s3, s3, s7
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
; GFX11-NEXT: s_add_i32 s0, s0, s4
; GFX11-NEXT: s_add_i32 s1, s1, s5
; GFX11-NEXT: s_add_i32 s2, s2, s6
+; GFX11-NEXT: s_add_i32 s3, s3, s7
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX11-NEXT: s_endpgm
@@ -598,20 +598,20 @@ define amdgpu_ps void @load_uniform_P1_v4i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX12-NEXT: global_load_b128 v[2:5], v6, s[0:1]
; GFX12-NEXT: global_load_b128 v[6:9], v6, s[0:1] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v5
-; GFX12-NEXT: v_readfirstlane_b32 s7, v9
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: v_readfirstlane_b32 s4, v6
; GFX12-NEXT: v_readfirstlane_b32 s5, v7
; GFX12-NEXT: v_readfirstlane_b32 s6, v8
-; GFX12-NEXT: s_add_co_i32 s3, s3, s7
+; GFX12-NEXT: v_readfirstlane_b32 s7, v9
; GFX12-NEXT: s_add_co_i32 s0, s0, s4
; GFX12-NEXT: s_add_co_i32 s1, s1, s5
; GFX12-NEXT: s_add_co_i32 s2, s2, s6
+; GFX12-NEXT: s_add_co_i32 s3, s3, s7
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-NEXT: s_endpgm
@@ -638,29 +638,29 @@ define amdgpu_ps void @load_uniform_P1_v8i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: v_readfirstlane_b32 s4, v2
; GFX7-NEXT: v_readfirstlane_b32 s5, v3
-; GFX7-NEXT: v_readfirstlane_b32 s12, v10
; GFX7-NEXT: v_readfirstlane_b32 s6, v4
; GFX7-NEXT: v_readfirstlane_b32 s7, v5
-; GFX7-NEXT: v_readfirstlane_b32 s8, v6
+; GFX7-NEXT: v_readfirstlane_b32 s12, v10
; GFX7-NEXT: v_readfirstlane_b32 s13, v11
; GFX7-NEXT: v_readfirstlane_b32 s14, v12
; GFX7-NEXT: v_readfirstlane_b32 s15, v13
-; GFX7-NEXT: v_readfirstlane_b32 s16, v14
-; GFX7-NEXT: s_add_i32 s4, s4, s12
+; GFX7-NEXT: v_readfirstlane_b32 s8, v6
; GFX7-NEXT: v_readfirstlane_b32 s9, v7
; GFX7-NEXT: v_readfirstlane_b32 s10, v8
; GFX7-NEXT: v_readfirstlane_b32 s11, v9
+; GFX7-NEXT: v_readfirstlane_b32 s16, v14
; GFX7-NEXT: v_readfirstlane_b32 s17, v15
; GFX7-NEXT: v_readfirstlane_b32 s18, v16
; GFX7-NEXT: v_readfirstlane_b32 s19, v17
+; GFX7-NEXT: s_add_i32 s4, s4, s12
; GFX7-NEXT: s_add_i32 s5, s5, s13
; GFX7-NEXT: s_add_i32 s6, s6, s14
; GFX7-NEXT: s_add_i32 s7, s7, s15
; GFX7-NEXT: s_add_i32 s8, s8, s16
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_add_i32 s9, s9, s17
; GFX7-NEXT: s_add_i32 s10, s10, s18
; GFX7-NEXT: s_add_i32 s11, s11, s19
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_mov_b32_e32 v4, s6
; GFX7-NEXT: v_mov_b32_e32 v5, s7
@@ -682,30 +682,30 @@ define amdgpu_ps void @load_uniform_P1_v8i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: global_load_b128 v[14:17], v14, s[0:1] offset:16 glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
-; GFX11-NEXT: v_readfirstlane_b32 s11, v13
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
; GFX11-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: v_readfirstlane_b32 s8, v10
; GFX11-NEXT: v_readfirstlane_b32 s9, v11
; GFX11-NEXT: v_readfirstlane_b32 s10, v12
-; GFX11-NEXT: v_readfirstlane_b32 s15, v17
+; GFX11-NEXT: v_readfirstlane_b32 s11, v13
; GFX11-NEXT: v_readfirstlane_b32 s4, v6
; GFX11-NEXT: v_readfirstlane_b32 s5, v7
; GFX11-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
; GFX11-NEXT: v_readfirstlane_b32 s12, v14
; GFX11-NEXT: v_readfirstlane_b32 s13, v15
; GFX11-NEXT: v_readfirstlane_b32 s14, v16
-; GFX11-NEXT: s_add_i32 s3, s3, s11
+; GFX11-NEXT: v_readfirstlane_b32 s15, v17
; GFX11-NEXT: s_add_i32 s0, s0, s8
; GFX11-NEXT: s_add_i32 s1, s1, s9
; GFX11-NEXT: s_add_i32 s2, s2, s10
-; GFX11-NEXT: s_add_i32 s7, s7, s15
+; GFX11-NEXT: s_add_i32 s3, s3, s11
; GFX11-NEXT: s_add_i32 s4, s4, s12
; GFX11-NEXT: s_add_i32 s5, s5, s13
; GFX11-NEXT: s_add_i32 s6, s6, s14
+; GFX11-NEXT: s_add_i32 s7, s7, s15
; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
@@ -725,30 +725,30 @@ define amdgpu_ps void @load_uniform_P1_v8i32(ptr addrspace(1) inreg %ptra, ptr a
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_load_b128 v[14:17], v14, s[0:1] offset:16 scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
-; GFX12-NEXT: v_readfirstlane_b32 s11, v13
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: v_readfirstlane_b32 s2, v4
-; GFX12-NEXT: v_readfirstlane_b32 s7, v9
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: v_readfirstlane_b32 s8, v10
; GFX12-NEXT: v_readfirstlane_b32 s9, v11
; GFX12-NEXT: v_readfirstlane_b32 s10, v12
-; GFX12-NEXT: v_readfirstlane_b32 s15, v17
+; GFX12-NEXT: v_readfirstlane_b32 s11, v13
; GFX12-NEXT: v_readfirstlane_b32 s4, v6
; GFX12-NEXT: v_readfirstlane_b32 s5, v7
; GFX12-NEXT: v_readfirstlane_b32 s6, v8
+; GFX12-NEXT: v_readfirstlane_b32 s7, v9
; GFX12-NEXT: v_readfirstlane_b32 s12, v14
; GFX12-NEXT: v_readfirstlane_b32 s13, v15
; GFX12-NEXT: v_readfirstlane_b32 s14, v16
-; GFX12-NEXT: s_add_co_i32 s3, s3, s11
+; GFX12-NEXT: v_readfirstlane_b32 s15, v17
; GFX12-NEXT: s_add_co_i32 s0, s0, s8
; GFX12-NEXT: s_add_co_i32 s1, s1, s9
; GFX12-NEXT: s_add_co_i32 s2, s2, s10
-; GFX12-NEXT: s_add_co_i32 s7, s7, s15
+; GFX12-NEXT: s_add_co_i32 s3, s3, s11
; GFX12-NEXT: s_add_co_i32 s4, s4, s12
; GFX12-NEXT: s_add_co_i32 s5, s5, s13
; GFX12-NEXT: s_add_co_i32 s6, s6, s14
+; GFX12-NEXT: s_add_co_i32 s7, s7, s15
; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
@@ -822,30 +822,30 @@ define amdgpu_ps void @load_uniform_P1_v16i32(ptr addrspace(1) inreg %ptra, ptr
; GFX7-NEXT: v_readfirstlane_b32 s36, v17
; GFX7-NEXT: s_add_i32 s7, s7, s23
; GFX7-NEXT: s_add_i32 s8, s8, s24
-; GFX7-NEXT: s_add_i32 s12, s12, s28
-; GFX7-NEXT: s_add_i32 s16, s16, s33
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_add_i32 s9, s9, s25
; GFX7-NEXT: s_add_i32 s10, s10, s26
; GFX7-NEXT: s_add_i32 s11, s11, s27
+; GFX7-NEXT: s_add_i32 s12, s12, s28
; GFX7-NEXT: s_add_i32 s13, s13, s29
; GFX7-NEXT: s_add_i32 s14, s14, s30
; GFX7-NEXT: s_add_i32 s15, s15, s31
+; GFX7-NEXT: s_add_i32 s16, s16, s33
; GFX7-NEXT: s_add_i32 s17, s17, s34
; GFX7-NEXT: s_add_i32 s18, s18, s35
; GFX7-NEXT: s_add_i32 s19, s19, s36
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_mov_b32_e32 v4, s6
; GFX7-NEXT: v_mov_b32_e32 v5, s7
; GFX7-NEXT: v_mov_b32_e32 v6, s8
-; GFX7-NEXT: v_mov_b32_e32 v10, s12
-; GFX7-NEXT: v_mov_b32_e32 v14, s16
; GFX7-NEXT: v_mov_b32_e32 v7, s9
; GFX7-NEXT: v_mov_b32_e32 v8, s10
; GFX7-NEXT: v_mov_b32_e32 v9, s11
+; GFX7-NEXT: v_mov_b32_e32 v10, s12
; GFX7-NEXT: v_mov_b32_e32 v11, s13
; GFX7-NEXT: v_mov_b32_e32 v12, s14
; GFX7-NEXT: v_mov_b32_e32 v13, s15
+; GFX7-NEXT: v_mov_b32_e32 v14, s16
; GFX7-NEXT: v_mov_b32_e32 v15, s17
; GFX7-NEXT: v_mov_b32_e32 v16, s18
; GFX7-NEXT: v_mov_b32_e32 v17, s19
@@ -871,57 +871,57 @@ define amdgpu_ps void @load_uniform_P1_v16i32(ptr addrspace(1) inreg %ptra, ptr
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: global_load_b128 v[30:33], v30, s[0:1] offset:48 glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
; GFX11-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-NEXT: v_readfirstlane_b32 s19, v21
-; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: v_readfirstlane_b32 s16, v18
; GFX11-NEXT: v_readfirstlane_b32 s17, v19
; GFX11-NEXT: v_readfirstlane_b32 s18, v20
-; GFX11-NEXT: v_readfirstlane_b32 s23, v25
+; GFX11-NEXT: v_readfirstlane_b32 s19, v21
; GFX11-NEXT: v_readfirstlane_b32 s4, v6
; GFX11-NEXT: v_readfirstlane_b32 s5, v7
; GFX11-NEXT: v_readfirstlane_b32 s6, v8
-; GFX11-NEXT: v_readfirstlane_b32 s11, v13
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
; GFX11-NEXT: v_readfirstlane_b32 s20, v22
; GFX11-NEXT: v_readfirstlane_b32 s21, v23
; GFX11-NEXT: v_readfirstlane_b32 s22, v24
-; GFX11-NEXT: v_readfirstlane_b32 s27, v29
+; GFX11-NEXT: v_readfirstlane_b32 s23, v25
; GFX11-NEXT: v_readfirstlane_b32 s8, v10
; GFX11-NEXT: v_readfirstlane_b32 s9, v11
; GFX11-NEXT: v_readfirstlane_b32 s10, v12
-; GFX11-NEXT: v_readfirstlane_b32 s15, v17
+; GFX11-NEXT: v_readfirstlane_b32 s11, v13
; GFX11-NEXT: v_readfirstlane_b32 s24, v26
; GFX11-NEXT: v_readfirstlane_b32 s25, v27
; GFX11-NEXT: v_readfirstlane_b32 s26, v28
-; GFX11-NEXT: v_readfirstlane_b32 s31, v33
+; GFX11-NEXT: v_readfirstlane_b32 s27, v29
; GFX11-NEXT: v_readfirstlane_b32 s12, v14
; GFX11-NEXT: v_readfirstlane_b32 s13, v15
; GFX11-NEXT: v_readfirstlane_b32 s14, v16
+; GFX11-NEXT: v_readfirstlane_b32 s15, v17
; GFX11-NEXT: v_readfirstlane_b32 s28, v30
; GFX11-NEXT: v_readfirstlane_b32 s29, v31
; GFX11-NEXT: v_readfirstlane_b32 s30, v32
-; GFX11-NEXT: s_add_i32 s3, s3, s19
+; GFX11-NEXT: v_readfirstlane_b32 s31, v33
; GFX11-NEXT: s_add_i32 s0, s0, s16
; GFX11-NEXT: s_add_i32 s1, s1, s17
; GFX11-NEXT: s_add_i32 s2, s2, s18
-; GFX11-NEXT: s_add_i32 s7, s7, s23
+; GFX11-NEXT: s_add_i32 s3, s3, s19
; GFX11-NEXT: s_add_i32 s4, s4, s20
; GFX11-NEXT: s_add_i32 s5, s5, s21
; GFX11-NEXT: s_add_i32 s6, s6, s22
-; GFX11-NEXT: s_add_i32 s11, s11, s27
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: s_add_i32 s7, s7, s23
; GFX11-NEXT: s_add_i32 s8, s8, s24
; GFX11-NEXT: s_add_i32 s9, s9, s25
; GFX11-NEXT: s_add_i32 s10, s10, s26
-; GFX11-NEXT: s_add_i32 s15, s15, s31
+; GFX11-NEXT: s_add_i32 s11, s11, s27
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: s_add_i32 s12, s12, s28
; GFX11-NEXT: s_add_i32 s13, s13, s29
; GFX11-NEXT: s_add_i32 s14, s14, s30
+; GFX11-NEXT: s_add_i32 s15, s15, s31
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
@@ -950,57 +950,57 @@ define amdgpu_ps void @load_uniform_P1_v16i32(ptr addrspace(1) inreg %ptra, ptr
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_load_b128 v[30:33], v30, s[0:1] offset:48 scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: v_readfirstlane_b32 s2, v4
-; GFX12-NEXT: v_readfirstlane_b32 s19, v21
-; GFX12-NEXT: v_readfirstlane_b32 s7, v9
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: v_readfirstlane_b32 s16, v18
; GFX12-NEXT: v_readfirstlane_b32 s17, v19
; GFX12-NEXT: v_readfirstlane_b32 s18, v20
-; GFX12-NEXT: v_readfirstlane_b32 s23, v25
+; GFX12-NEXT: v_readfirstlane_b32 s19, v21
; GFX12-NEXT: v_readfirstlane_b32 s4, v6
; GFX12-NEXT: v_readfirstlane_b32 s5, v7
; GFX12-NEXT: v_readfirstlane_b32 s6, v8
-; GFX12-NEXT: v_readfirstlane_b32 s11, v13
+; GFX12-NEXT: v_readfirstlane_b32 s7, v9
; GFX12-NEXT: v_readfirstlane_b32 s20, v22
; GFX12-NEXT: v_readfirstlane_b32 s21, v23
; GFX12-NEXT: v_readfirstlane_b32 s22, v24
-; GFX12-NEXT: v_readfirstlane_b32 s27, v29
+; GFX12-NEXT: v_readfirstlane_b32 s23, v25
; GFX12-NEXT: v_readfirstlane_b32 s8, v10
; GFX12-NEXT: v_readfirstlane_b32 s9, v11
; GFX12-NEXT: v_readfirstlane_b32 s10, v12
-; GFX12-NEXT: v_readfirstlane_b32 s15, v17
+; GFX12-NEXT: v_readfirstlane_b32 s11, v13
; GFX12-NEXT: v_readfirstlane_b32 s24, v26
; GFX12-NEXT: v_readfirstlane_b32 s25, v27
; GFX12-NEXT: v_readfirstlane_b32 s26, v28
-; GFX12-NEXT: v_readfirstlane_b32 s31, v33
+; GFX12-NEXT: v_readfirstlane_b32 s27, v29
; GFX12-NEXT: v_readfirstlane_b32 s12, v14
; GFX12-NEXT: v_readfirstlane_b32 s13, v15
; GFX12-NEXT: v_readfirstlane_b32 s14, v16
+; GFX12-NEXT: v_readfirstlane_b32 s15, v17
; GFX12-NEXT: v_readfirstlane_b32 s28, v30
; GFX12-NEXT: v_readfirstlane_b32 s29, v31
; GFX12-NEXT: v_readfirstlane_b32 s30, v32
-; GFX12-NEXT: s_add_co_i32 s3, s3, s19
+; GFX12-NEXT: v_readfirstlane_b32 s31, v33
; GFX12-NEXT: s_add_co_i32 s0, s0, s16
; GFX12-NEXT: s_add_co_i32 s1, s1, s17
; GFX12-NEXT: s_add_co_i32 s2, s2, s18
-; GFX12-NEXT: s_add_co_i32 s7, s7, s23
+; GFX12-NEXT: s_add_co_i32 s3, s3, s19
; GFX12-NEXT: s_add_co_i32 s4, s4, s20
; GFX12-NEXT: s_add_co_i32 s5, s5, s21
; GFX12-NEXT: s_add_co_i32 s6, s6, s22
-; GFX12-NEXT: s_add_co_i32 s11, s11, s27
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX12-NEXT: s_add_co_i32 s7, s7, s23
; GFX12-NEXT: s_add_co_i32 s8, s8, s24
; GFX12-NEXT: s_add_co_i32 s9, s9, s25
; GFX12-NEXT: s_add_co_i32 s10, s10, s26
-; GFX12-NEXT: s_add_co_i32 s15, s15, s31
+; GFX12-NEXT: s_add_co_i32 s11, s11, s27
+; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX12-NEXT: s_add_co_i32 s12, s12, s28
; GFX12-NEXT: s_add_co_i32 s13, s13, s29
; GFX12-NEXT: s_add_co_i32 s14, s14, s30
+; GFX12-NEXT: s_add_co_i32 s15, s15, s31
+; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX12-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX12-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
; GFX12-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
@@ -1613,11 +1613,11 @@ define amdgpu_ps void @load_uniform_P4_v2i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_readfirstlane_b32 s5, v3
; GFX7-NEXT: v_readfirstlane_b32 s4, v2
+; GFX7-NEXT: v_readfirstlane_b32 s5, v3
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_add_i32 s1, s5, s1
; GFX7-NEXT: s_add_i32 s0, s4, s0
+; GFX7-NEXT: s_add_i32 s1, s5, s1
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: s_mov_b64 s[0:1], 0
@@ -1636,7 +1636,7 @@ define amdgpu_ps void @load_uniform_P4_v2i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX11-NEXT: s_add_i32 s0, s2, s0
; GFX11-NEXT: s_add_i32 s1, s3, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_endpgm
;
@@ -1652,7 +1652,7 @@ define amdgpu_ps void @load_uniform_P4_v2i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX12-NEXT: s_add_co_i32 s0, s2, s0
; GFX12-NEXT: s_add_co_i32 s1, s3, s1
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_endpgm
%a = load <2 x i32>, ptr addrspace(4) %ptra, align 2
@@ -1691,16 +1691,15 @@ define amdgpu_ps void @load_uniform_P4_v3i32_gfx12(ptr addrspace(4) inreg %ptra,
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: global_load_b96 v[2:4], v2, s[0:1]
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s5, v4
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s3, v2
; GFX11-NEXT: v_readfirstlane_b32 s4, v3
-; GFX11-NEXT: s_add_i32 s2, s5, s2
+; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: s_add_i32 s0, s3, s0
; GFX11-NEXT: s_add_i32 s1, s4, s1
+; GFX11-NEXT: s_add_i32 s2, s5, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off
; GFX11-NEXT: s_endpgm
@@ -1711,15 +1710,15 @@ define amdgpu_ps void @load_uniform_P4_v3i32_gfx12(ptr addrspace(4) inreg %ptra,
; GFX12-NEXT: global_load_b96 v[2:4], v2, s[0:1]
; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s5, v4
; GFX12-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-NEXT: v_readfirstlane_b32 s4, v3
+; GFX12-NEXT: v_readfirstlane_b32 s5, v4
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_add_co_i32 s2, s5, s2
; GFX12-NEXT: s_add_co_i32 s0, s3, s0
; GFX12-NEXT: s_add_co_i32 s1, s4, s1
+; GFX12-NEXT: s_add_co_i32 s2, s5, s2
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v3, s1
+; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off
; GFX12-NEXT: s_endpgm
@@ -1763,17 +1762,17 @@ define amdgpu_ps void @load_uniform_P4_v4i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX11-NEXT: global_load_b128 v[2:5], v2, s[0:1]
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s7, v5
; GFX11-NEXT: v_readfirstlane_b32 s4, v2
; GFX11-NEXT: v_readfirstlane_b32 s5, v3
; GFX11-NEXT: v_readfirstlane_b32 s6, v4
+; GFX11-NEXT: v_readfirstlane_b32 s7, v5
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_add_i32 s3, s7, s3
; GFX11-NEXT: s_add_i32 s0, s4, s0
; GFX11-NEXT: s_add_i32 s1, s5, s1
; GFX11-NEXT: s_add_i32 s2, s6, s2
+; GFX11-NEXT: s_add_i32 s3, s7, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX11-NEXT: s_endpgm
@@ -1784,17 +1783,17 @@ define amdgpu_ps void @load_uniform_P4_v4i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX12-NEXT: global_load_b128 v[2:5], v2, s[0:1]
; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s7, v5
; GFX12-NEXT: v_readfirstlane_b32 s4, v2
; GFX12-NEXT: v_readfirstlane_b32 s5, v3
; GFX12-NEXT: v_readfirstlane_b32 s6, v4
+; GFX12-NEXT: v_readfirstlane_b32 s7, v5
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_add_co_i32 s3, s7, s3
; GFX12-NEXT: s_add_co_i32 s0, s4, s0
; GFX12-NEXT: s_add_co_i32 s1, s5, s1
; GFX12-NEXT: s_add_co_i32 s2, s6, s2
+; GFX12-NEXT: s_add_co_i32 s3, s7, s3
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-NEXT: s_endpgm
@@ -1823,19 +1822,19 @@ define amdgpu_ps void @load_uniform_P4_v8i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX7-NEXT: v_readfirstlane_b32 s15, v5
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readfirstlane_b32 s16, v6
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_add_i32 s4, s12, s4
; GFX7-NEXT: v_readfirstlane_b32 s17, v7
; GFX7-NEXT: v_readfirstlane_b32 s18, v8
; GFX7-NEXT: v_readfirstlane_b32 s19, v9
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_add_i32 s4, s12, s4
; GFX7-NEXT: s_add_i32 s5, s13, s5
; GFX7-NEXT: s_add_i32 s6, s14, s6
; GFX7-NEXT: s_add_i32 s7, s15, s7
; GFX7-NEXT: s_add_i32 s8, s16, s8
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_add_i32 s9, s17, s9
; GFX7-NEXT: s_add_i32 s10, s18, s10
; GFX7-NEXT: s_add_i32 s11, s19, s11
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_mov_b32_e32 v4, s6
; GFX7-NEXT: v_mov_b32_e32 v5, s7
@@ -1855,24 +1854,24 @@ define amdgpu_ps void @load_uniform_P4_v8i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX11-NEXT: global_load_b128 v[6:9], v6, s[0:1] offset:16
; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x0
; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_readfirstlane_b32 s11, v5
; GFX11-NEXT: v_readfirstlane_b32 s8, v2
; GFX11-NEXT: v_readfirstlane_b32 s9, v3
; GFX11-NEXT: v_readfirstlane_b32 s10, v4
+; GFX11-NEXT: v_readfirstlane_b32 s11, v5
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s15, v9
; GFX11-NEXT: v_readfirstlane_b32 s12, v6
; GFX11-NEXT: v_readfirstlane_b32 s13, v7
; GFX11-NEXT: v_readfirstlane_b32 s14, v8
+; GFX11-NEXT: v_readfirstlane_b32 s15, v9
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_add_i32 s3, s11, s3
; GFX11-NEXT: s_add_i32 s0, s8, s0
; GFX11-NEXT: s_add_i32 s1, s9, s1
; GFX11-NEXT: s_add_i32 s2, s10, s2
-; GFX11-NEXT: s_add_i32 s7, s15, s7
+; GFX11-NEXT: s_add_i32 s3, s11, s3
; GFX11-NEXT: s_add_i32 s4, s12, s4
; GFX11-NEXT: s_add_i32 s5, s13, s5
; GFX11-NEXT: s_add_i32 s6, s14, s6
+; GFX11-NEXT: s_add_i32 s7, s15, s7
; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
@@ -1890,24 +1889,24 @@ define amdgpu_ps void @load_uniform_P4_v8i32(ptr addrspace(4) inreg %ptra, ptr a
; GFX12-NEXT: global_load_b128 v[6:9], v6, s[0:1] offset:16
; GFX12-NEXT: s_load_b256 s[0:7], s[0:1], 0x0
; GFX12-NEXT: s_wait_loadcnt 0x1
-; GFX12-NEXT: v_readfirstlane_b32 s11, v5
; GFX12-NEXT: v_readfirstlane_b32 s8, v2
; GFX12-NEXT: v_readfirstlane_b32 s9, v3
; GFX12-NEXT: v_readfirstlane_b32 s10, v4
+; GFX12-NEXT: v_readfirstlane_b32 s11, v5
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s15, v9
; GFX12-NEXT: v_readfirstlane_b32 s12, v6
; GFX12-NEXT: v_readfirstlane_b32 s13, v7
; GFX12-NEXT: v_readfirstlane_b32 s14, v8
+; GFX12-NEXT: v_readfirstlane_b32 s15, v9
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_add_co_i32 s3, s11, s3
; GFX12-NEXT: s_add_co_i32 s0, s8, s0
; GFX12-NEXT: s_add_co_i32 s1, s9, s1
; GFX12-NEXT: s_add_co_i32 s2, s10, s2
-; GFX12-NEXT: s_add_co_i32 s7, s15, s7
+; GFX12-NEXT: s_add_co_i32 s3, s11, s3
; GFX12-NEXT: s_add_co_i32 s4, s12, s4
; GFX12-NEXT: s_add_co_i32 s5, s13, s5
; GFX12-NEXT: s_add_co_i32 s6, s14, s6
+; GFX12-NEXT: s_add_co_i32 s7, s15, s7
; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
@@ -1943,49 +1942,49 @@ define amdgpu_ps void @load_uniform_P4_v16i32(ptr addrspace(4) inreg %ptra, ptr
; GFX7-NEXT: v_readfirstlane_b32 s23, v5
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_readfirstlane_b32 s24, v6
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_readfirstlane_b32 s28, v10
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_readfirstlane_b32 s33, v14
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_add_i32 s4, s20, s4
; GFX7-NEXT: v_readfirstlane_b32 s25, v7
; GFX7-NEXT: v_readfirstlane_b32 s26, v8
; GFX7-NEXT: v_readfirstlane_b32 s27, v9
+; GFX7-NEXT: s_waitcnt vmcnt(1)
+; GFX7-NEXT: v_readfirstlane_b32 s28, v10
; GFX7-NEXT: v_readfirstlane_b32 s29, v11
; GFX7-NEXT: v_readfirstlane_b32 s30, v12
; GFX7-NEXT: v_readfirstlane_b32 s31, v13
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_readfirstlane_b32 s33, v14
; GFX7-NEXT: v_readfirstlane_b32 s34, v15
; GFX7-NEXT: v_readfirstlane_b32 s35, v16
; GFX7-NEXT: v_readfirstlane_b32 s36, v17
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_add_i32 s4, s20, s4
; GFX7-NEXT: s_add_i32 s5, s21, s5
; GFX7-NEXT: s_add_i32 s6, s22, s6
; GFX7-NEXT: s_add_i32 s7, s23, s7
; GFX7-NEXT: s_add_i32 s8, s24, s8
-; GFX7-NEXT: s_add_i32 s12, s28, s12
-; GFX7-NEXT: s_add_i32 s16, s33, s16
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_add_i32 s9, s25, s9
; GFX7-NEXT: s_add_i32 s10, s26, s10
; GFX7-NEXT: s_add_i32 s11, s27, s11
+; GFX7-NEXT: s_add_i32 s12, s28, s12
; GFX7-NEXT: s_add_i32 s13, s29, s13
; GFX7-NEXT: s_add_i32 s14, s30, s14
; GFX7-NEXT: s_add_i32 s15, s31, s15
+; GFX7-NEXT: s_add_i32 s16, s33, s16
; GFX7-NEXT: s_add_i32 s17, s34, s17
; GFX7-NEXT: s_add_i32 s18, s35, s18
; GFX7-NEXT: s_add_i32 s19, s36, s19
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_mov_b32_e32 v4, s6
; GFX7-NEXT: v_mov_b32_e32 v5, s7
; GFX7-NEXT: v_mov_b32_e32 v6, s8
-; GFX7-NEXT: v_mov_b32_e32 v10, s12
-; GFX7-NEXT: v_mov_b32_e32 v14, s16
; GFX7-NEXT: v_mov_b32_e32 v7, s9
; GFX7-NEXT: v_mov_b32_e32 v8, s10
; GFX7-NEXT: v_mov_b32_e32 v9, s11
+; GFX7-NEXT: v_mov_b32_e32 v10, s12
; GFX7-NEXT: v_mov_b32_e32 v11, s13
; GFX7-NEXT: v_mov_b32_e32 v12, s14
; GFX7-NEXT: v_mov_b32_e32 v13, s15
+; GFX7-NEXT: v_mov_b32_e32 v14, s16
; GFX7-NEXT: v_mov_b32_e32 v15, s17
; GFX7-NEXT: v_mov_b32_e32 v16, s18
; GFX7-NEXT: v_mov_b32_e32 v17, s19
@@ -2005,45 +2004,45 @@ define amdgpu_ps void @load_uniform_P4_v16i32(ptr addrspace(4) inreg %ptra, ptr
; GFX11-NEXT: global_load_b128 v[14:17], v14, s[0:1] offset:48
; GFX11-NEXT: s_load_b512 s[0:15], s[0:1], 0x0
; GFX11-NEXT: s_waitcnt vmcnt(3)
-; GFX11-NEXT: v_readfirstlane_b32 s19, v5
; GFX11-NEXT: v_readfirstlane_b32 s16, v2
; GFX11-NEXT: v_readfirstlane_b32 s17, v3
; GFX11-NEXT: v_readfirstlane_b32 s18, v4
+; GFX11-NEXT: v_readfirstlane_b32 s19, v5
; GFX11-NEXT: s_waitcnt vmcnt(2)
-; GFX11-NEXT: v_readfirstlane_b32 s23, v9
; GFX11-NEXT: v_readfirstlane_b32 s20, v6
; GFX11-NEXT: v_readfirstlane_b32 s21, v7
; GFX11-NEXT: v_readfirstlane_b32 s22, v8
+; GFX11-NEXT: v_readfirstlane_b32 s23, v9
; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_readfirstlane_b32 s27, v13
; GFX11-NEXT: v_readfirstlane_b32 s24, v10
; GFX11-NEXT: v_readfirstlane_b32 s25, v11
; GFX11-NEXT: v_readfirstlane_b32 s26, v12
+; GFX11-NEXT: v_readfirstlane_b32 s27, v13
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s31, v17
; GFX11-NEXT: v_readfirstlane_b32 s28, v14
; GFX11-NEXT: v_readfirstlane_b32 s29, v15
; GFX11-NEXT: v_readfirstlane_b32 s30, v16
+; GFX11-NEXT: v_readfirstlane_b32 s31, v17
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_add_i32 s3, s19, s3
; GFX11-NEXT: s_add_i32 s0, s16, s0
; GFX11-NEXT: s_add_i32 s1, s17, s1
; GFX11-NEXT: s_add_i32 s2, s18, s2
-; GFX11-NEXT: s_add_i32 s7, s23, s7
+; GFX11-NEXT: s_add_i32 s3, s19, s3
; GFX11-NEXT: s_add_i32 s4, s20, s4
; GFX11-NEXT: s_add_i32 s5, s21, s5
; GFX11-NEXT: s_add_i32 s6, s22, s6
-; GFX11-NEXT: s_add_i32 s11, s27, s11
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: s_add_i32 s7, s23, s7
; GFX11-NEXT: s_add_i32 s8, s24, s8
; GFX11-NEXT: s_add_i32 s9, s25, s9
; GFX11-NEXT: s_add_i32 s10, s26, s10
-; GFX11-NEXT: s_add_i32 s15, s31, s15
+; GFX11-NEXT: s_add_i32 s11, s27, s11
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: s_add_i32 s12, s28, s12
; GFX11-NEXT: s_add_i32 s13, s29, s13
; GFX11-NEXT: s_add_i32 s14, s30, s14
+; GFX11-NEXT: s_add_i32 s15, s31, s15
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
@@ -2066,45 +2065,45 @@ define amdgpu_ps void @load_uniform_P4_v16i32(ptr addrspace(4) inreg %ptra, ptr
; GFX12-NEXT: global_load_b128 v[14:17], v14, s[0:1] offset:48
; GFX12-NEXT: s_load_b512 s[0:15], s[0:1], 0x0
; GFX12-NEXT: s_wait_loadcnt 0x3
-; GFX12-NEXT: v_readfirstlane_b32 s19, v5
; GFX12-NEXT: v_readfirstlane_b32 s16, v2
; GFX12-NEXT: v_readfirstlane_b32 s17, v3
; GFX12-NEXT: v_readfirstlane_b32 s18, v4
+; GFX12-NEXT: v_readfirstlane_b32 s19, v5
; GFX12-NEXT: s_wait_loadcnt 0x2
-; GFX12-NEXT: v_readfirstlane_b32 s23, v9
; GFX12-NEXT: v_readfirstlane_b32 s20, v6
; GFX12-NEXT: v_readfirstlane_b32 s21, v7
; GFX12-NEXT: v_readfirstlane_b32 s22, v8
+; GFX12-NEXT: v_readfirstlane_b32 s23, v9
; GFX12-NEXT: s_wait_loadcnt 0x1
-; GFX12-NEXT: v_readfirstlane_b32 s27, v13
; GFX12-NEXT: v_readfirstlane_b32 s24, v10
; GFX12-NEXT: v_readfirstlane_b32 s25, v11
; GFX12-NEXT: v_readfirstlane_b32 s26, v12
+; GFX12-NEXT: v_readfirstlane_b32 s27, v13
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s31, v17
; GFX12-NEXT: v_readfirstlane_b32 s28, v14
; GFX12-NEXT: v_readfirstlane_b32 s29, v15
; GFX12-NEXT: v_readfirstlane_b32 s30, v16
+; GFX12-NEXT: v_readfirstlane_b32 s31, v17
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_add_co_i32 s3, s19, s3
; GFX12-NEXT: s_add_co_i32 s0, s16, s0
; GFX12-NEXT: s_add_co_i32 s1, s17, s1
; GFX12-NEXT: s_add_co_i32 s2, s18, s2
-; GFX12-NEXT: s_add_co_i32 s7, s23, s7
+; GFX12-NEXT: s_add_co_i32 s3, s19, s3
; GFX12-NEXT: s_add_co_i32 s4, s20, s4
; GFX12-NEXT: s_add_co_i32 s5, s21, s5
; GFX12-NEXT: s_add_co_i32 s6, s22, s6
-; GFX12-NEXT: s_add_co_i32 s11, s27, s11
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX12-NEXT: s_add_co_i32 s7, s23, s7
; GFX12-NEXT: s_add_co_i32 s8, s24, s8
; GFX12-NEXT: s_add_co_i32 s9, s25, s9
; GFX12-NEXT: s_add_co_i32 s10, s26, s10
-; GFX12-NEXT: s_add_co_i32 s15, s31, s15
+; GFX12-NEXT: s_add_co_i32 s11, s27, s11
+; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX12-NEXT: s_add_co_i32 s12, s28, s12
; GFX12-NEXT: s_add_co_i32 s13, s29, s13
; GFX12-NEXT: s_add_co_i32 s14, s30, s14
+; GFX12-NEXT: s_add_co_i32 s15, s31, s15
+; GFX12-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX12-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX12-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
; GFX12-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
index 0126efeba3e74..4fe6458f81f6d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
@@ -40,7 +40,7 @@ define amdgpu_ps void @mad_i64_uniform(i64 inreg %a, i64 inreg %b, ptr addrspace
; GFX11-NEXT: s_mul_i32 s0, s0, s2
; GFX11-NEXT: s_add_i32 s1, s3, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_endpgm
%result = mul i64 %a, %b
@@ -79,7 +79,7 @@ define amdgpu_ps void @mad_u64_u32_uniform_carry(i32 inreg %a, i32 inreg %b, i64
; GFX11-NEXT: s_add_u32 s0, s4, s2
; GFX11-NEXT: s_addc_u32 s1, s1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_endpgm
%a.ext = zext i32 %a to i64
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
index 6194b197b3850..2775beb4c38b1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
@@ -98,8 +98,9 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4294967296(ptr addrspace(1) in
; GFX12: ; %bb.0:
; GFX12-NEXT: s_add_co_u32 s0, s2, 0
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296
@@ -136,8 +137,9 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4294967297(ptr addrspace(1) in
; GFX12: ; %bb.0:
; GFX12-NEXT: s_add_co_u32 s0, s2, 4
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967297
@@ -313,12 +315,12 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg %
; GFX6: ; %bb.0:
; GFX6-NEXT: s_ashr_i32 s5, s4, 31
; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: v_mov_b32_e32 v2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; GFX6-NEXT: s_endpgm
@@ -327,12 +329,12 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg %
; GFX7: ; %bb.0:
; GFX7-NEXT: s_ashr_i32 s5, s4, 31
; GFX7-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_endpgm
@@ -911,11 +913,11 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg %
; GFX6: ; %bb.0:
; GFX6-NEXT: s_ashr_i32 s5, s4, 31
; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -925,11 +927,11 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg %
; GFX7: ; %bb.0:
; GFX7-NEXT: s_ashr_i32 s5, s4, 31
; GFX7-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -1502,8 +1504,8 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4294967296(ptr addrspace(1)
; GFX12: ; %bb.0:
; GFX12-NEXT: s_add_co_u32 s0, s2, 0
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
-; GFX12-NEXT: v_mov_b32_e32 v2, v0
-; GFX12-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
+; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, s0
+; GFX12-NEXT: v_mov_b32_e32 v4, s1
; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[3:4], v[1:2], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -1635,9 +1637,9 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_vgpr_offset(ptr addrspace(1) inre
;
; GFX12-LABEL: mubuf_cmpxchg_sgpr_ptr_vgpr_offset:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_mov_b32_e32 v3, v1
+; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX12-NEXT: v_mov_b32_e32 v5, s3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
index 976fef0e3807e..32b790d4b986b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -3975,8 +3975,8 @@ define amdgpu_kernel void @s_mul_u64_sext_with_sregs(ptr addrspace(1) %out, ptr
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX8-NEXT: s_ashr_i32 s3, s2, 31
-; GFX8-NEXT: s_mulk_i32 s2, 0x50
; GFX8-NEXT: s_mulk_i32 s3, 0x50
+; GFX8-NEXT: s_mulk_i32 s2, 0x50
; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: s_add_u32 s3, s3, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
index e0581f01dda6a..f6d518c9840b5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
@@ -645,8 +645,8 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_or_b32 s2, s2, 0x50
-; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s3
+; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm
;
@@ -659,7 +659,7 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_or_b32 s2, s2, 0x50
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -673,7 +673,7 @@ define amdgpu_kernel void @s_or_u64_zext_with_sregs(ptr addrspace(1) %out, ptr a
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_or_b32 s2, s2, 0x50
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
%val = load i32, ptr addrspace(1) %in, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
index 47610687f3d37..0183a394066da 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
@@ -94,8 +94,8 @@ define amdgpu_ps void @s_buffer_load_i96_sgpr_rsrc_sgpr_offset(<4 x i32> inreg %
; GFX12-NEXT: s_mov_b32 s8, s5
; GFX12-NEXT: s_mov_b32 s9, s6
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s0
-; GFX12-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX12-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s2
+; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: global_store_b96 v3, v[0:2], s[8:9]
; GFX12-NEXT: s_endpgm
%val = call i96 @llvm.amdgcn.s.buffer.load.i96(<4 x i32> %rsrc, i32 %soffset, i32 0)
@@ -169,12 +169,12 @@ define amdgpu_ps void @s_buffer_load_v8i32_sgpr_rsrc_sgpr_offset(<4 x i32> inreg
; GFX12-NEXT: s_mov_b32 s8, s5
; GFX12-NEXT: s_mov_b32 s9, s6
; GFX12-NEXT: s_buffer_load_b256 s[0:7], s[0:3], s4 offset:0x0
-; GFX12-NEXT: v_mov_b32_e32 v8, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX12-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
-; GFX12-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6
+; GFX12-NEXT: v_mov_b32_e32 v6, s6
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v8, v[0:3], s[8:9]
; GFX12-NEXT: global_store_b128 v8, v[4:7], s[8:9] offset:16
@@ -224,16 +224,16 @@ define amdgpu_ps void @s_buffer_load_v16i32_sgpr_rsrc_sgpr_offset(<4 x i32> inre
; GFX12-NEXT: s_mov_b32 s16, s5
; GFX12-NEXT: s_mov_b32 s17, s6
; GFX12-NEXT: s_buffer_load_b512 s[0:15], s[0:3], s4 offset:0x0
-; GFX12-NEXT: v_mov_b32_e32 v16, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX12-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
-; GFX12-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6
+; GFX12-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9
; GFX12-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s11
-; GFX12-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
+; GFX12-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v13, s13
; GFX12-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v15, s15
-; GFX12-NEXT: v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v14, s14
+; GFX12-NEXT: v_mov_b32_e32 v14, s14
; GFX12-NEXT: s_clause 0x3
; GFX12-NEXT: global_store_b128 v16, v[0:3], s[16:17]
; GFX12-NEXT: global_store_b128 v16, v[4:7], s[16:17] offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index baa3f4d9c051b..d7c290396c480 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -4489,8 +4489,8 @@ define amdgpu_ps i48 @s_saddsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX6-NEXT: s_add_u32 s4, s0, s2
; GFX6-NEXT: s_addc_u32 s5, s1, s3
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
@@ -4512,8 +4512,8 @@ define amdgpu_ps i48 @s_saddsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX8-NEXT: s_add_u32 s4, s0, s2
; GFX8-NEXT: s_addc_u32 s5, s1, s3
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
@@ -4535,8 +4535,8 @@ define amdgpu_ps i48 @s_saddsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX9-NEXT: s_add_u32 s4, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s5, s1, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
@@ -4852,8 +4852,8 @@ define amdgpu_ps i64 @s_saddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s4, s0, s2
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_addc_u32 s5, s1, s3
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
@@ -4871,8 +4871,8 @@ define amdgpu_ps i64 @s_saddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX8-LABEL: s_saddsat_i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s4, s0, s2
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s5, s1, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
@@ -4890,8 +4890,8 @@ define amdgpu_ps i64 @s_saddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX9-LABEL: s_saddsat_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s4, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s5, s1, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
@@ -5203,8 +5203,8 @@ define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX6-LABEL: s_saddsat_v2i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s8, s0, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_addc_u32 s9, s1, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
; GFX6-NEXT: v_mov_b32_e32 v0, s2
@@ -5237,8 +5237,8 @@ define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX8-LABEL: s_saddsat_v2i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s8, s0, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s9, s1, s5
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
@@ -5252,8 +5252,8 @@ define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_add_u32 s4, s2, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_addc_u32 s5, s3, s7
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], s[6:7], 0
@@ -5271,8 +5271,8 @@ define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX9-LABEL: s_saddsat_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s8, s0, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s9, s1, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
@@ -5286,8 +5286,8 @@ define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_add_u32 s4, s2, s6
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_addc_u32 s5, s3, s7
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[2:3], s[6:7], 0
@@ -5339,13 +5339,13 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s4, s0, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_addc_u32 s5, s1, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_addc_u32 s8, s2, s6
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_addc_u32 s9, s3, s7
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
@@ -5375,13 +5375,13 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX8-LABEL: s_saddsat_i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s4, s0, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s5, s1, s5
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_addc_u32 s8, s2, s6
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_addc_u32 s9, s3, s7
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
@@ -5409,13 +5409,13 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-LABEL: s_saddsat_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s4, s0, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s5, s1, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_addc_u32 s8, s2, s6
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_addc_u32 s9, s3, s7
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
@@ -6121,13 +6121,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-LABEL: s_saddsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s8, s0, s8
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_addc_u32 s9, s1, s9
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_addc_u32 s16, s2, s10
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_addc_u32 s17, s3, s11
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1]
@@ -6153,13 +6153,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[16:17]
; GFX6-NEXT: s_add_u32 s8, s4, s12
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_addc_u32 s9, s5, s13
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: s_addc_u32 s10, s6, s14
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: s_addc_u32 s11, s7, s15
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: s_or_b64 s[4:5], vcc, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
@@ -6189,13 +6189,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-LABEL: s_saddsat_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s8, s0, s8
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s9, s1, s9
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_addc_u32 s16, s2, s10
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_addc_u32 s17, s3, s11
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1]
@@ -6219,13 +6219,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[16:17]
; GFX8-NEXT: s_add_u32 s8, s4, s12
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_addc_u32 s9, s5, s13
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s10, s6, s14
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_addc_u32 s11, s7, s15
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
@@ -6253,13 +6253,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-LABEL: s_saddsat_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s8, s0, s8
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s9, s1, s9
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_addc_u32 s16, s2, s10
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_addc_u32 s17, s3, s11
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1]
@@ -6283,13 +6283,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[16:17]
; GFX9-NEXT: s_add_u32 s8, s4, s12
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_addc_u32 s9, s5, s13
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_addc_u32 s10, s6, s14
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_addc_u32 s11, s7, s15
+; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
index 1b7df5e3389fe..1453e1aae6ebd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
@@ -19,10 +19,11 @@ define amdgpu_kernel void @sdivrem_i32(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_sub_i32 s7, 0, s5
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_readfirstlane_b32 s8, v0
; GFX8-NEXT: s_mul_i32 s7, s7, s8
; GFX8-NEXT: v_mul_hi_u32 v0, v0, s7
@@ -34,7 +35,6 @@ define amdgpu_kernel void @sdivrem_i32(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mul_hi_u32 v4, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_readfirstlane_b32 s0, v4
; GFX8-NEXT: s_mul_i32 s1, s0, s5
; GFX8-NEXT: s_sub_i32 s1, s4, s1
@@ -361,16 +361,16 @@ define amdgpu_kernel void @sdivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_sub_u32 s6, s10, s6
; GFX8-NEXT: s_subb_u32 s7, s11, s7
; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: s_sub_u32 s4, s4, s8
+; GFX8-NEXT: s_subb_u32 s5, s5, s8
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
-; GFX8-NEXT: s_subb_u32 s5, s5, s8
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -536,10 +536,10 @@ define amdgpu_kernel void @sdivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX9-NEXT: s_sub_u32 s6, s10, s6
; GFX9-NEXT: s_subb_u32 s7, s11, s7
; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_sub_u32 s4, s4, s8
-; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: s_subb_u32 s5, s5, s8
+; GFX9-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
@@ -736,9 +736,10 @@ define amdgpu_kernel void @sdivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_xor_b32 s6, s6, s8
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX8-NEXT: s_sub_i32 s9, 0, s6
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_readfirstlane_b32 s10, v0
@@ -779,11 +780,10 @@ define amdgpu_kernel void @sdivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_xor_b32 s5, s5, s3
; GFX8-NEXT: v_rcp_iflag_f32_e32 v4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_sub_i32 s1, 0, s7
+; GFX8-NEXT: s_xor_b32 s0, s9, s8
; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX8-NEXT: s_xor_b32 s0, s9, s8
; GFX8-NEXT: v_readfirstlane_b32 s2, v4
; GFX8-NEXT: s_mul_i32 s1, s1, s2
; GFX8-NEXT: v_mul_hi_u32 v4, v4, s1
@@ -908,10 +908,10 @@ define amdgpu_kernel void @sdivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_xor_b32 s5, s8, s11
; GFX9-NEXT: s_xor_b32 s9, s9, s5
; GFX9-NEXT: s_sub_i32 s5, s9, s5
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_xor_b32 s7, s7, s8
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_sub_i32 s7, s7, s8
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s7
@@ -1153,10 +1153,10 @@ define amdgpu_kernel void @sdivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v8, s8
-; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
; GFX8-NEXT: v_mov_b32_e32 v11, s11
; GFX8-NEXT: s_sub_i32 s9, 0, s7
; GFX8-NEXT: v_readfirstlane_b32 s10, v0
@@ -1196,8 +1196,8 @@ define amdgpu_kernel void @sdivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_xor_b32 s9, s9, s7
; GFX8-NEXT: s_xor_b32 s10, s3, s8
; GFX8-NEXT: s_sub_i32 s3, s9, s7
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_sub_i32 s7, s10, s8
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
@@ -1369,12 +1369,12 @@ define amdgpu_kernel void @sdivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_xor_b32 s3, s12, s15
; GFX9-NEXT: s_xor_b32 s13, s13, s3
; GFX9-NEXT: s_sub_i32 s3, s13, s3
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_xor_b32 s7, s7, s12
+; GFX9-NEXT: s_sub_i32 s7, s7, s12
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-NEXT: s_sub_i32 s7, s7, s12
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
; GFX9-NEXT: s_nop 0
@@ -1935,12 +1935,12 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_sub_u32 s6, s14, s6
; GFX8-NEXT: s_subb_u32 s7, s15, s7
; GFX8-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13]
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_sub_u32 s10, s10, s12
+; GFX8-NEXT: s_subb_u32 s11, s11, s12
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NEXT: s_subb_u32 s11, s11, s12
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s8
@@ -2271,12 +2271,12 @@ define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_sub_u32 s6, s10, s6
; GFX9-NEXT: s_subb_u32 s7, s11, s7
; GFX9-NEXT: s_xor_b64 s[10:11], s[14:15], s[12:13]
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_sub_u32 s10, s10, s12
+; GFX9-NEXT: s_subb_u32 s11, s11, s12
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
-; GFX9-NEXT: s_subb_u32 s11, s11, s12
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_e32 v0, s8
@@ -2645,10 +2645,11 @@ define amdgpu_kernel void @sdiv_i8(ptr addrspace(1) %out0, ptr addrspace(1) %out
; GFX8-NEXT: s_sext_i32_i8 s4, s4
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_readfirstlane_b32 s8, v0
; GFX8-NEXT: s_mul_i32 s7, s7, s8
; GFX8-NEXT: v_mul_hi_u32 v0, v0, s7
@@ -2660,7 +2661,6 @@ define amdgpu_kernel void @sdiv_i8(ptr addrspace(1) %out0, ptr addrspace(1) %out
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mul_hi_u32 v4, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_readfirstlane_b32 s0, v4
; GFX8-NEXT: s_mul_i32 s1, s0, s6
; GFX8-NEXT: s_sub_i32 s1, s4, s1
@@ -2907,16 +2907,16 @@ define amdgpu_kernel void @sdivrem_v2i8(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_sub_i32 s1, s1, s5
; GFX8-NEXT: s_and_b32 s5, s6, 0xff
; GFX8-NEXT: s_and_b32 s0, s0, 0xff
-; GFX8-NEXT: s_lshl_b32 s5, s5, 8
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_or_b32 s0, s0, s5
+; GFX8-NEXT: s_lshl_b32 s5, s5, 8
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: s_or_b32 s0, s0, s5
; GFX8-NEXT: s_or_b32 s1, s4, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_short v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -3151,10 +3151,11 @@ define amdgpu_kernel void @sdiv_i16(ptr addrspace(1) %out0, ptr addrspace(1) %ou
; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_readfirstlane_b32 s8, v0
; GFX8-NEXT: s_mul_i32 s7, s7, s8
; GFX8-NEXT: v_mul_hi_u32 v0, v0, s7
@@ -3166,7 +3167,6 @@ define amdgpu_kernel void @sdiv_i16(ptr addrspace(1) %out0, ptr addrspace(1) %ou
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mul_hi_u32 v4, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_readfirstlane_b32 s0, v4
; GFX8-NEXT: s_mul_i32 s1, s0, s6
; GFX8-NEXT: s_sub_i32 s1, s4, s1
@@ -3408,21 +3408,21 @@ define amdgpu_kernel void @sdivrem_v2i16(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_cselect_b32 s1, s9, s1
; GFX8-NEXT: s_xor_b32 s5, s6, s5
; GFX8-NEXT: s_xor_b32 s7, s7, s5
-; GFX8-NEXT: s_sub_i32 s5, s7, s5
; GFX8-NEXT: s_xor_b32 s1, s1, s6
+; GFX8-NEXT: s_sub_i32 s5, s7, s5
+; GFX8-NEXT: s_sub_i32 s1, s1, s6
; GFX8-NEXT: s_and_b32 s5, s5, 0xffff
; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX8-NEXT: s_sub_i32 s1, s1, s6
-; GFX8-NEXT: s_lshl_b32 s5, s5, 16
; GFX8-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX8-NEXT: s_or_b32 s0, s0, s5
+; GFX8-NEXT: s_lshl_b32 s5, s5, 16
; GFX8-NEXT: s_and_b32 s4, s4, 0xffff
; GFX8-NEXT: s_lshl_b32 s1, s1, 16
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: s_or_b32 s0, s0, s5
; GFX8-NEXT: s_or_b32 s1, s4, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -3645,10 +3645,11 @@ define amdgpu_kernel void @sdivrem_i3(ptr addrspace(1) %out0, ptr addrspace(1) %
; GFX8-NEXT: s_bfe_i32 s4, s4, 0x30000
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_readfirstlane_b32 s8, v0
; GFX8-NEXT: s_mul_i32 s7, s7, s8
; GFX8-NEXT: v_mul_hi_u32 v0, v0, s7
@@ -3660,7 +3661,6 @@ define amdgpu_kernel void @sdivrem_i3(ptr addrspace(1) %out0, ptr addrspace(1) %
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mul_hi_u32 v4, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_readfirstlane_b32 s0, v4
; GFX8-NEXT: s_mul_i32 s1, s0, s6
; GFX8-NEXT: s_sub_i32 s1, s4, s1
@@ -3829,10 +3829,11 @@ define amdgpu_kernel void @sdivrem_i27(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_bfe_i32 s4, s4, 0x1b0000
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_readfirstlane_b32 s8, v0
; GFX8-NEXT: s_mul_i32 s7, s7, s8
; GFX8-NEXT: v_mul_hi_u32 v0, v0, s7
@@ -3844,7 +3845,6 @@ define amdgpu_kernel void @sdivrem_i27(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mul_hi_u32 v4, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_readfirstlane_b32 s0, v4
; GFX8-NEXT: s_mul_i32 s1, s0, s6
; GFX8-NEXT: s_sub_i32 s1, s4, s1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
index 757f85b3a69ef..adbb5b34c8be9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
@@ -258,8 +258,8 @@ define amdgpu_kernel void @mulu24_shl64(ptr addrspace(1) nocapture %arg) {
; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GFX8-NEXT: flat_store_dword v[2:3], v1
@@ -273,8 +273,8 @@ define amdgpu_kernel void @mulu24_shl64(ptr addrspace(1) nocapture %arg) {
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_mov_b32_e32 v4, s0
+; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: global_store_dword v[2:3], v1, off
@@ -288,8 +288,8 @@ define amdgpu_kernel void @mulu24_shl64(ptr addrspace(1) nocapture %arg) {
; GFX10-NEXT: v_mul_u32_u24_e32 v0, 7, v0
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v5, s1
; GFX10-NEXT: v_mov_b32_e32 v4, s0
+; GFX10-NEXT: v_mov_b32_e32 v5, s1
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo
; GFX10-NEXT: global_store_dword v[2:3], v1, off
@@ -348,9 +348,9 @@ define amdgpu_kernel void @muli24_shl64(ptr addrspace(1) nocapture %arg, ptr add
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: flat_load_dword v4, v[1:2]
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 26d853a389285..a3d4828d261dd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -4493,8 +4493,8 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX6-NEXT: s_sub_u32 s4, s0, s2
; GFX6-NEXT: s_subb_u32 s5, s1, s3
; GFX6-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x300000
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
@@ -4516,8 +4516,8 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX8-NEXT: s_sub_u32 s4, s0, s2
; GFX8-NEXT: s_subb_u32 s5, s1, s3
; GFX8-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x300000
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
@@ -4536,10 +4536,10 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
;
; GFX9-LABEL: s_ssubsat_i48:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX9-NEXT: s_sub_u32 s4, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s1, s3
@@ -4864,8 +4864,8 @@ define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
;
; GFX8-LABEL: s_ssubsat_i64:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_sub_u32 s4, s0, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_subb_u32 s5, s1, s3
@@ -4883,8 +4883,8 @@ define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
;
; GFX9-LABEL: s_ssubsat_i64:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_sub_u32 s4, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s1, s3
@@ -5199,8 +5199,8 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX6-NEXT: s_xor_b32 s4, s4, s0
; GFX6-NEXT: s_ashr_i32 s0, s9, 31
; GFX6-NEXT: s_add_i32 s1, s0, 0x80000000
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: s_cmp_lg_u32 s4, 0
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_sub_u32 s4, s2, s6
@@ -5220,8 +5220,8 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
;
; GFX8-LABEL: s_ssubsat_v2i64:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_sub_u32 s8, s0, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_subb_u32 s9, s1, s5
@@ -5234,9 +5234,9 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX8-NEXT: s_ashr_i32 s0, s9, 31
; GFX8-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_sub_u32 s4, s2, s6
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX8-NEXT: s_subb_u32 s5, s3, s7
@@ -5254,8 +5254,8 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
;
; GFX9-LABEL: s_ssubsat_v2i64:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_sub_u32 s8, s0, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s9, s1, s5
@@ -5268,9 +5268,9 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX9-NEXT: s_ashr_i32 s0, s9, 31
; GFX9-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_sub_u32 s4, s2, s6
+; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s3, s7
@@ -5323,13 +5323,13 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s8, s0, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_subb_u32 s9, s1, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: s_subb_u32 s10, s2, s6
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: s_subb_u32 s11, s3, s7
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
@@ -5359,13 +5359,13 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX8-LABEL: s_ssubsat_i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s8, s0, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_subb_u32 s9, s1, s5
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_subb_u32 s10, s2, s6
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_subb_u32 s11, s3, s7
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
@@ -5393,13 +5393,13 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-LABEL: s_ssubsat_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s8, s0, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_subb_u32 s9, s1, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_subb_u32 s10, s2, s6
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_subb_u32 s11, s3, s7
+; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
@@ -6097,13 +6097,13 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-LABEL: s_ssubsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s16, s0, s8
-; GFX6-NEXT: v_mov_b32_e32 v0, s8
; GFX6-NEXT: s_subb_u32 s17, s1, s9
+; GFX6-NEXT: v_mov_b32_e32 v0, s8
; GFX6-NEXT: v_mov_b32_e32 v1, s9
; GFX6-NEXT: s_subb_u32 s18, s2, s10
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s10
; GFX6-NEXT: s_subb_u32 s19, s3, s11
+; GFX6-NEXT: v_mov_b32_e32 v0, s10
; GFX6-NEXT: v_mov_b32_e32 v1, s11
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
@@ -6129,13 +6129,13 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[16:17]
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
; GFX6-NEXT: s_sub_u32 s8, s4, s12
-; GFX6-NEXT: v_mov_b32_e32 v0, s12
; GFX6-NEXT: s_subb_u32 s9, s5, s13
+; GFX6-NEXT: v_mov_b32_e32 v0, s12
; GFX6-NEXT: v_mov_b32_e32 v1, s13
; GFX6-NEXT: s_subb_u32 s10, s6, s14
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s14
; GFX6-NEXT: s_subb_u32 s11, s7, s15
+; GFX6-NEXT: v_mov_b32_e32 v0, s14
; GFX6-NEXT: v_mov_b32_e32 v1, s15
; GFX6-NEXT: s_or_b64 s[4:5], vcc, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
@@ -6165,13 +6165,13 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-LABEL: s_ssubsat_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s16, s0, s8
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: s_subb_u32 s17, s1, s9
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: s_subb_u32 s18, s2, s10
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s10
; GFX8-NEXT: s_subb_u32 s19, s3, s11
+; GFX8-NEXT: v_mov_b32_e32 v0, s10
; GFX8-NEXT: v_mov_b32_e32 v1, s11
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
@@ -6195,13 +6195,13 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[16:17]
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
; GFX8-NEXT: s_sub_u32 s8, s4, s12
-; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: s_subb_u32 s9, s5, s13
+; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: s_subb_u32 s10, s6, s14
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s14
; GFX8-NEXT: s_subb_u32 s11, s7, s15
+; GFX8-NEXT: v_mov_b32_e32 v0, s14
; GFX8-NEXT: v_mov_b32_e32 v1, s15
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
@@ -6229,13 +6229,13 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-LABEL: s_ssubsat_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s16, s0, s8
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: s_subb_u32 s17, s1, s9
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: s_subb_u32 s18, s2, s10
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s10
; GFX9-NEXT: s_subb_u32 s19, s3, s11
+; GFX9-NEXT: v_mov_b32_e32 v0, s10
; GFX9-NEXT: v_mov_b32_e32 v1, s11
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
@@ -6259,13 +6259,13 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[16:17]
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
; GFX9-NEXT: s_sub_u32 s8, s4, s12
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
; GFX9-NEXT: s_subb_u32 s9, s5, s13
+; GFX9-NEXT: v_mov_b32_e32 v0, s12
; GFX9-NEXT: v_mov_b32_e32 v1, s13
; GFX9-NEXT: s_subb_u32 s10, s6, s14
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s14
; GFX9-NEXT: s_subb_u32 s11, s7, s15
+; GFX9-NEXT: v_mov_b32_e32 v0, s14
; GFX9-NEXT: v_mov_b32_e32 v1, s15
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
index a807ee409c665..744f16b13037e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
@@ -339,12 +339,12 @@ define void @v_constained_fma_v4f16_fpexcept_strict_uni(<4 x half> inreg %x, <4
; GFX8-NEXT: v_fma_f16 v2, s5, v2, v3
; GFX8-NEXT: v_readfirstlane_b32 s5, v2
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX8-NEXT: s_and_b32 s5, 0xffff, s5
; GFX8-NEXT: s_and_b32 s7, 0xffff, s10
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_and_b32 s5, 0xffff, s5
-; GFX8-NEXT: s_or_b32 s4, s7, s4
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
; GFX8-NEXT: s_lshl_b32 s5, s5, 16
+; GFX8-NEXT: s_or_b32 s4, s7, s4
; GFX8-NEXT: s_or_b32 s5, s6, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
@@ -412,7 +412,7 @@ define void @v_constained_fma_v4f16_fpexcept_strict_uni(<4 x half> inreg %x, <4
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: s_pack_ll_b32_b16 s1, s17, s4
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
index 8ecd0820d7f51..dc349321d15b8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
@@ -278,10 +278,9 @@ define void @v_constained_fma_v3f32_fpexcept_strict_uni(<3 x float> inreg %x, <3
; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[2:3], v[2:3], v[4:5]
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s2, v2
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_mov_b32_e32 v4, s2
; GFX942-NEXT: v_mov_b32_e32 v3, s1
; GFX942-NEXT: v_mov_b32_e32 v2, s0
+; GFX942-NEXT: v_mov_b32_e32 v4, s2
; GFX942-NEXT: global_store_dwordx3 v[0:1], v[2:4], off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -439,9 +438,9 @@ define void @v_constained_fma_v4f32_fpexcept_strict_uni(<4 x float> inreg %x, <4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s2, v2
; GFX942-NEXT: v_readfirstlane_b32 s3, v3
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
index fee5ef15a980e..45fd066d6447e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
@@ -10,8 +10,8 @@ define void @v_constained_fma_f64_fpexcept_strict_uni(double inreg %x, double in
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, s18
-; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v5, s21
; GFX8-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5]
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -22,8 +22,8 @@ define void @v_constained_fma_f64_fpexcept_strict_uni(double inreg %x, double in
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v2, s18
-; GFX900-NEXT: v_mov_b32_e32 v4, s20
; GFX900-NEXT: v_mov_b32_e32 v3, s19
+; GFX900-NEXT: v_mov_b32_e32 v4, s20
; GFX900-NEXT: v_mov_b32_e32 v5, s21
; GFX900-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5]
; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
@@ -110,13 +110,13 @@ define void @v_constained_fma_v2f64_fpexcept_strict_uni(<2 x double> inreg %x, <
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, s20
-; GFX8-NEXT: v_mov_b32_e32 v4, s24
; GFX8-NEXT: v_mov_b32_e32 v3, s21
+; GFX8-NEXT: v_mov_b32_e32 v4, s24
; GFX8-NEXT: v_mov_b32_e32 v5, s25
; GFX8-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5]
; GFX8-NEXT: v_mov_b32_e32 v4, s22
-; GFX8-NEXT: v_mov_b32_e32 v6, s26
; GFX8-NEXT: v_mov_b32_e32 v5, s23
+; GFX8-NEXT: v_mov_b32_e32 v6, s26
; GFX8-NEXT: v_mov_b32_e32 v7, s27
; GFX8-NEXT: v_fma_f64 v[4:5], s[18:19], v[4:5], v[6:7]
; GFX8-NEXT: v_readfirstlane_b32 s4, v2
@@ -135,13 +135,13 @@ define void @v_constained_fma_v2f64_fpexcept_strict_uni(<2 x double> inreg %x, <
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v2, s20
-; GFX900-NEXT: v_mov_b32_e32 v4, s24
; GFX900-NEXT: v_mov_b32_e32 v3, s21
+; GFX900-NEXT: v_mov_b32_e32 v4, s24
; GFX900-NEXT: v_mov_b32_e32 v5, s25
; GFX900-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5]
; GFX900-NEXT: v_mov_b32_e32 v4, s22
-; GFX900-NEXT: v_mov_b32_e32 v6, s26
; GFX900-NEXT: v_mov_b32_e32 v5, s23
+; GFX900-NEXT: v_mov_b32_e32 v6, s26
; GFX900-NEXT: v_mov_b32_e32 v7, s27
; GFX900-NEXT: v_fma_f64 v[4:5], s[18:19], v[4:5], v[6:7]
; GFX900-NEXT: v_readfirstlane_b32 s4, v2
@@ -170,9 +170,9 @@ define void @v_constained_fma_v2f64_fpexcept_strict_uni(<2 x double> inreg %x, <
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s2, v2
; GFX942-NEXT: v_readfirstlane_b32 s3, v3
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -180,20 +180,20 @@ define void @v_constained_fma_v2f64_fpexcept_strict_uni(<2 x double> inreg %x, <
; GFX11-LABEL: v_constained_fma_v2f64_fpexcept_strict_uni:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21
+; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fma_f64 v[4:5], s[2:3], s[18:19], v[4:5]
; GFX11-NEXT: v_fma_f64 v[2:3], s[0:1], s[16:17], v[2:3]
+; GFX11-NEXT: v_fma_f64 v[4:5], s[2:3], s[18:19], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -204,21 +204,21 @@ define void @v_constained_fma_v2f64_fpexcept_strict_uni(<2 x double> inreg %x, <
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX12-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21
+; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_fma_f64 v[4:5], s[2:3], s[18:19], v[4:5]
; GFX12-NEXT: v_fma_f64 v[2:3], s[0:1], s[16:17], v[2:3]
+; GFX12-NEXT: v_fma_f64 v[4:5], s[2:3], s[18:19], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_readfirstlane_b32 s3, v5
-; GFX12-NEXT: v_readfirstlane_b32 s2, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -278,13 +278,13 @@ define void @v_constained_fma_v3f64_fpexcept_strict_uni(<3 x double> inreg %x, <
; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_mov_b32_e32 v0, s22
-; GFX8-NEXT: v_mov_b32_e32 v6, s28
; GFX8-NEXT: v_mov_b32_e32 v1, s23
+; GFX8-NEXT: v_mov_b32_e32 v6, s28
; GFX8-NEXT: v_mov_b32_e32 v7, s29
; GFX8-NEXT: v_fma_f64 v[0:1], s[16:17], v[0:1], v[6:7]
; GFX8-NEXT: v_mov_b32_e32 v6, s24
-; GFX8-NEXT: v_mov_b32_e32 v9, s5
; GFX8-NEXT: v_mov_b32_e32 v7, s25
+; GFX8-NEXT: v_mov_b32_e32 v9, s5
; GFX8-NEXT: v_mov_b32_e32 v8, s4
; GFX8-NEXT: v_fma_f64 v[6:7], s[18:19], v[6:7], v[8:9]
; GFX8-NEXT: v_readfirstlane_b32 s8, v2
@@ -292,8 +292,8 @@ define void @v_constained_fma_v3f64_fpexcept_strict_uni(<3 x double> inreg %x, <
; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_mov_b32_e32 v0, s26
-; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s27
+; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: v_mov_b32_e32 v3, s9
; GFX8-NEXT: v_fma_f64 v[8:9], s[20:21], v[0:1], v[2:3]
; GFX8-NEXT: v_readfirstlane_b32 s6, v6
@@ -316,20 +316,20 @@ define void @v_constained_fma_v3f64_fpexcept_strict_uni(<3 x double> inreg %x, <
; GFX900-NEXT: v_readfirstlane_b32 s4, v0
; GFX900-NEXT: v_readfirstlane_b32 s5, v1
; GFX900-NEXT: v_mov_b32_e32 v0, s22
-; GFX900-NEXT: v_mov_b32_e32 v6, s28
; GFX900-NEXT: v_mov_b32_e32 v1, s23
+; GFX900-NEXT: v_mov_b32_e32 v6, s28
; GFX900-NEXT: v_mov_b32_e32 v7, s29
; GFX900-NEXT: v_fma_f64 v[0:1], s[16:17], v[0:1], v[6:7]
; GFX900-NEXT: v_mov_b32_e32 v6, s24
-; GFX900-NEXT: v_mov_b32_e32 v9, s5
; GFX900-NEXT: v_mov_b32_e32 v7, s25
+; GFX900-NEXT: v_mov_b32_e32 v9, s5
; GFX900-NEXT: v_mov_b32_e32 v8, s4
; GFX900-NEXT: v_fma_f64 v[6:7], s[18:19], v[6:7], v[8:9]
-; GFX900-NEXT: v_readfirstlane_b32 s7, v3
; GFX900-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-NEXT: v_readfirstlane_b32 s7, v3
; GFX900-NEXT: v_mov_b32_e32 v2, s26
-; GFX900-NEXT: v_mov_b32_e32 v9, s7
; GFX900-NEXT: v_mov_b32_e32 v3, s27
+; GFX900-NEXT: v_mov_b32_e32 v9, s7
; GFX900-NEXT: v_mov_b32_e32 v8, s6
; GFX900-NEXT: v_fma_f64 v[8:9], s[20:21], v[2:3], v[8:9]
; GFX900-NEXT: v_readfirstlane_b32 s4, v0
@@ -371,22 +371,22 @@ define void @v_constained_fma_v3f64_fpexcept_strict_uni(<3 x double> inreg %x, <
; GFX11-LABEL: v_constained_fma_v3f64_fpexcept_strict_uni:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v4, s26 :: v_dual_mov_b32 v5, s27
; GFX11-NEXT: v_dual_mov_b32 v2, s24 :: v_dual_mov_b32 v3, s25
+; GFX11-NEXT: v_dual_mov_b32 v4, s26 :: v_dual_mov_b32 v5, s27
; GFX11-NEXT: v_dual_mov_b32 v6, s28 :: v_dual_mov_b32 v7, s29
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_fma_f64 v[4:5], s[2:3], s[20:21], v[4:5]
; GFX11-NEXT: v_fma_f64 v[2:3], s[0:1], s[18:19], v[2:3]
+; GFX11-NEXT: v_fma_f64 v[4:5], s[2:3], s[20:21], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_fma_f64 v[6:7], s[16:17], s[22:23], v[6:7]
-; GFX11-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_readfirstlane_b32 s2, v4
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX11-NEXT: global_store_b64 v[0:1], v[6:7], off offset:16
@@ -399,23 +399,23 @@ define void @v_constained_fma_v3f64_fpexcept_strict_uni(<3 x double> inreg %x, <
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v4, s26 :: v_dual_mov_b32 v5, s27
; GFX12-NEXT: v_dual_mov_b32 v2, s24 :: v_dual_mov_b32 v3, s25
+; GFX12-NEXT: v_dual_mov_b32 v4, s26 :: v_dual_mov_b32 v5, s27
; GFX12-NEXT: v_dual_mov_b32 v6, s28 :: v_dual_mov_b32 v7, s29
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_fma_f64 v[4:5], s[2:3], s[20:21], v[4:5]
; GFX12-NEXT: v_fma_f64 v[2:3], s[0:1], s[18:19], v[2:3]
+; GFX12-NEXT: v_fma_f64 v[4:5], s[2:3], s[20:21], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_fma_f64 v[6:7], s[16:17], s[22:23], v[6:7]
-; GFX12-NEXT: v_readfirstlane_b32 s3, v5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-NEXT: v_readfirstlane_b32 s2, v4
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-NEXT: global_store_b64 v[0:1], v[6:7], off offset:16
@@ -486,51 +486,51 @@ define void @v_constained_fma_v4f64_fpexcept_strict_uni(<4 x double> inreg %x, <
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s6, v2
+; GFX8-NEXT: v_readfirstlane_b32 s7, v3
; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1
-; GFX8-NEXT: v_readfirstlane_b32 s7, v3
-; GFX8-NEXT: v_mov_b32_e32 v0, s24
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_readfirstlane_b32 s8, v4
+; GFX8-NEXT: v_readfirstlane_b32 s9, v5
+; GFX8-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NEXT: v_mov_b32_e32 v1, s25
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NEXT: v_readfirstlane_b32 s9, v5
+; GFX8-NEXT: v_readfirstlane_b32 s10, v6
+; GFX8-NEXT: v_readfirstlane_b32 s11, v7
; GFX8-NEXT: v_fma_f64 v[0:1], s[16:17], v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v2, s26
-; GFX8-NEXT: v_mov_b32_e32 v4, s8
-; GFX8-NEXT: v_readfirstlane_b32 s10, v6
; GFX8-NEXT: v_mov_b32_e32 v3, s27
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NEXT: v_mov_b32_e32 v5, s9
-; GFX8-NEXT: v_readfirstlane_b32 s11, v7
+; GFX8-NEXT: v_readfirstlane_b32 s12, v8
+; GFX8-NEXT: v_readfirstlane_b32 s13, v9
; GFX8-NEXT: v_fma_f64 v[2:3], s[18:19], v[2:3], v[4:5]
; GFX8-NEXT: v_mov_b32_e32 v4, s28
-; GFX8-NEXT: v_mov_b32_e32 v6, s10
-; GFX8-NEXT: v_readfirstlane_b32 s12, v8
; GFX8-NEXT: v_mov_b32_e32 v5, s29
+; GFX8-NEXT: v_mov_b32_e32 v6, s10
; GFX8-NEXT: v_mov_b32_e32 v7, s11
-; GFX8-NEXT: v_readfirstlane_b32 s13, v9
; GFX8-NEXT: v_fma_f64 v[4:5], s[20:21], v[4:5], v[6:7]
; GFX8-NEXT: v_mov_b32_e32 v7, s5
-; GFX8-NEXT: v_mov_b32_e32 v8, s12
; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_mov_b32_e32 v8, s12
; GFX8-NEXT: v_mov_b32_e32 v9, s13
; GFX8-NEXT: v_fma_f64 v[6:7], s[22:23], v[6:7], v[8:9]
; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_readfirstlane_b32 s6, v2
; GFX8-NEXT: v_readfirstlane_b32 s7, v3
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_readfirstlane_b32 s8, v4
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NEXT: v_readfirstlane_b32 s9, v5
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_readfirstlane_b32 s10, v6
; GFX8-NEXT: v_readfirstlane_b32 s11, v7
-; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 16, v10
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v11, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NEXT: v_mov_b32_e32 v3, s11
@@ -542,47 +542,47 @@ define void @v_constained_fma_v4f64_fpexcept_strict_uni(<4 x double> inreg %x, <
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-NEXT: v_readfirstlane_b32 s7, v3
; GFX900-NEXT: v_readfirstlane_b32 s4, v0
; GFX900-NEXT: v_readfirstlane_b32 s5, v1
-; GFX900-NEXT: v_readfirstlane_b32 s7, v3
-; GFX900-NEXT: v_mov_b32_e32 v0, s24
-; GFX900-NEXT: v_mov_b32_e32 v2, s6
; GFX900-NEXT: v_readfirstlane_b32 s8, v4
+; GFX900-NEXT: v_readfirstlane_b32 s9, v5
+; GFX900-NEXT: v_mov_b32_e32 v0, s24
; GFX900-NEXT: v_mov_b32_e32 v1, s25
+; GFX900-NEXT: v_mov_b32_e32 v2, s6
; GFX900-NEXT: v_mov_b32_e32 v3, s7
-; GFX900-NEXT: v_readfirstlane_b32 s9, v5
+; GFX900-NEXT: v_readfirstlane_b32 s10, v6
+; GFX900-NEXT: v_readfirstlane_b32 s11, v7
; GFX900-NEXT: v_fma_f64 v[0:1], s[16:17], v[0:1], v[2:3]
; GFX900-NEXT: v_mov_b32_e32 v2, s26
-; GFX900-NEXT: v_mov_b32_e32 v4, s8
-; GFX900-NEXT: v_readfirstlane_b32 s10, v6
; GFX900-NEXT: v_mov_b32_e32 v3, s27
+; GFX900-NEXT: v_mov_b32_e32 v4, s8
; GFX900-NEXT: v_mov_b32_e32 v5, s9
-; GFX900-NEXT: v_readfirstlane_b32 s11, v7
+; GFX900-NEXT: v_readfirstlane_b32 s12, v8
+; GFX900-NEXT: v_readfirstlane_b32 s13, v9
; GFX900-NEXT: v_fma_f64 v[2:3], s[18:19], v[2:3], v[4:5]
; GFX900-NEXT: v_mov_b32_e32 v4, s28
-; GFX900-NEXT: v_mov_b32_e32 v6, s10
-; GFX900-NEXT: v_readfirstlane_b32 s12, v8
; GFX900-NEXT: v_mov_b32_e32 v5, s29
+; GFX900-NEXT: v_mov_b32_e32 v6, s10
; GFX900-NEXT: v_mov_b32_e32 v7, s11
-; GFX900-NEXT: v_readfirstlane_b32 s13, v9
; GFX900-NEXT: v_fma_f64 v[4:5], s[20:21], v[4:5], v[6:7]
; GFX900-NEXT: v_mov_b32_e32 v7, s5
-; GFX900-NEXT: v_mov_b32_e32 v8, s12
; GFX900-NEXT: v_mov_b32_e32 v6, s4
+; GFX900-NEXT: v_mov_b32_e32 v8, s12
; GFX900-NEXT: v_mov_b32_e32 v9, s13
; GFX900-NEXT: v_fma_f64 v[6:7], s[22:23], v[6:7], v[8:9]
; GFX900-NEXT: v_readfirstlane_b32 s4, v0
; GFX900-NEXT: v_readfirstlane_b32 s5, v1
; GFX900-NEXT: v_readfirstlane_b32 s6, v2
; GFX900-NEXT: v_readfirstlane_b32 s7, v3
-; GFX900-NEXT: v_mov_b32_e32 v0, s4
; GFX900-NEXT: v_readfirstlane_b32 s8, v4
-; GFX900-NEXT: v_mov_b32_e32 v1, s5
-; GFX900-NEXT: v_mov_b32_e32 v2, s6
-; GFX900-NEXT: v_mov_b32_e32 v3, s7
; GFX900-NEXT: v_readfirstlane_b32 s9, v5
+; GFX900-NEXT: v_mov_b32_e32 v0, s4
; GFX900-NEXT: v_readfirstlane_b32 s10, v6
; GFX900-NEXT: v_readfirstlane_b32 s11, v7
+; GFX900-NEXT: v_mov_b32_e32 v1, s5
+; GFX900-NEXT: v_mov_b32_e32 v2, s6
+; GFX900-NEXT: v_mov_b32_e32 v3, s7
; GFX900-NEXT: global_store_dwordx4 v[10:11], v[0:3], off
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v0, s8
@@ -621,11 +621,10 @@ define void @v_constained_fma_v4f64_fpexcept_strict_uni(<4 x double> inreg %x, <
; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[26:27]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[8:9]
; GFX942-NEXT: v_fma_f64 v[0:1], s[18:19], v[0:1], v[2:3]
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-NEXT: v_readfirstlane_b32 s6, v0
; GFX942-NEXT: v_readfirstlane_b32 s7, v1
; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-NEXT: global_store_dwordx4 v[6:7], v[0:3], off
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
@@ -639,29 +638,29 @@ define void @v_constained_fma_v4f64_fpexcept_strict_uni(<4 x double> inreg %x, <
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-NEXT: v_readfirstlane_b32 s5, v1
-; GFX11-NEXT: v_readfirstlane_b32 s8, v4
-; GFX11-NEXT: v_readfirstlane_b32 s9, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v2
; GFX11-NEXT: v_readfirstlane_b32 s7, v3
+; GFX11-NEXT: v_readfirstlane_b32 s8, v4
+; GFX11-NEXT: v_readfirstlane_b32 s9, v5
; GFX11-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29
; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
-; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_fma_f64 v[0:1], s[0:1], s[20:21], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_fma_f64 v[2:3], s[2:3], s[22:23], v[2:3]
-; GFX11-NEXT: v_fma_f64 v[8:9], s[18:19], s[26:27], v[8:9]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_fma_f64 v[4:5], s[16:17], s[24:25], v[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_fma_f64 v[8:9], s[18:19], s[26:27], v[8:9]
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3
-; GFX11-NEXT: v_readfirstlane_b32 s7, v9
; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
@@ -681,29 +680,29 @@ define void @v_constained_fma_v4f64_fpexcept_strict_uni(<4 x double> inreg %x, <
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
-; GFX12-NEXT: v_readfirstlane_b32 s8, v4
-; GFX12-NEXT: v_readfirstlane_b32 s9, v5
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
+; GFX12-NEXT: v_readfirstlane_b32 s8, v4
+; GFX12-NEXT: v_readfirstlane_b32 s9, v5
; GFX12-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
-; GFX12-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX12-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
+; GFX12-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX12-NEXT: v_fma_f64 v[0:1], s[0:1], s[20:21], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_fma_f64 v[2:3], s[2:3], s[22:23], v[2:3]
-; GFX12-NEXT: v_fma_f64 v[8:9], s[18:19], s[26:27], v[8:9]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_fma_f64 v[4:5], s[16:17], s[24:25], v[4:5]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_fma_f64 v[8:9], s[18:19], s[26:27], v[8:9]
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-NEXT: v_readfirstlane_b32 s3, v3
-; GFX12-NEXT: v_readfirstlane_b32 s7, v9
; GFX12-NEXT: v_readfirstlane_b32 s4, v4
; GFX12-NEXT: v_readfirstlane_b32 s5, v5
; GFX12-NEXT: v_readfirstlane_b32 s6, v8
+; GFX12-NEXT: v_readfirstlane_b32 s7, v9
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -784,8 +783,8 @@ define void @v_constained_fma_f64_fpexcept_strict_fneg_uni(double inreg %x, doub
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, s16
-; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v3, s17
+; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v5, s19
; GFX8-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -s[20:21]
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -796,8 +795,8 @@ define void @v_constained_fma_f64_fpexcept_strict_fneg_uni(double inreg %x, doub
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v2, s16
-; GFX900-NEXT: v_mov_b32_e32 v4, s18
; GFX900-NEXT: v_mov_b32_e32 v3, s17
+; GFX900-NEXT: v_mov_b32_e32 v4, s18
; GFX900-NEXT: v_mov_b32_e32 v5, s19
; GFX900-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -s[20:21]
; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
@@ -886,8 +885,8 @@ define void @v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni(double inreg %x,
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, s18
-; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v5, s21
; GFX8-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[4:5]
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -898,8 +897,8 @@ define void @v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni(double inreg %x,
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v2, s18
-; GFX900-NEXT: v_mov_b32_e32 v4, s20
; GFX900-NEXT: v_mov_b32_e32 v3, s19
+; GFX900-NEXT: v_mov_b32_e32 v4, s20
; GFX900-NEXT: v_mov_b32_e32 v5, s21
; GFX900-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[4:5]
; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
@@ -990,8 +989,8 @@ define void @v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni(double inreg %x,
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, s18
-; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v5, s21
; GFX8-NEXT: v_fma_f64 v[2:3], |s[16:17]|, |v[2:3]|, v[4:5]
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -1002,8 +1001,8 @@ define void @v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni(double inreg %x,
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v2, s18
-; GFX900-NEXT: v_mov_b32_e32 v4, s20
; GFX900-NEXT: v_mov_b32_e32 v3, s19
+; GFX900-NEXT: v_mov_b32_e32 v4, s20
; GFX900-NEXT: v_mov_b32_e32 v5, s21
; GFX900-NEXT: v_fma_f64 v[2:3], |s[16:17]|, |v[2:3]|, v[4:5]
; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
@@ -1094,13 +1093,13 @@ define void @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni(<2 x double> i
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, s20
-; GFX8-NEXT: v_mov_b32_e32 v6, s24
; GFX8-NEXT: v_mov_b32_e32 v3, s21
+; GFX8-NEXT: v_mov_b32_e32 v6, s24
; GFX8-NEXT: v_mov_b32_e32 v7, s25
; GFX8-NEXT: v_mov_b32_e32 v4, s22
+; GFX8-NEXT: v_mov_b32_e32 v5, s23
; GFX8-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[6:7]
; GFX8-NEXT: v_mov_b32_e32 v6, s26
-; GFX8-NEXT: v_mov_b32_e32 v5, s23
; GFX8-NEXT: v_mov_b32_e32 v7, s27
; GFX8-NEXT: v_fma_f64 v[4:5], -s[18:19], -v[4:5], v[6:7]
; GFX8-NEXT: v_readfirstlane_b32 s4, v2
@@ -1119,13 +1118,13 @@ define void @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni(<2 x double> i
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v2, s20
-; GFX900-NEXT: v_mov_b32_e32 v6, s24
; GFX900-NEXT: v_mov_b32_e32 v3, s21
+; GFX900-NEXT: v_mov_b32_e32 v6, s24
; GFX900-NEXT: v_mov_b32_e32 v7, s25
; GFX900-NEXT: v_mov_b32_e32 v4, s22
+; GFX900-NEXT: v_mov_b32_e32 v5, s23
; GFX900-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[6:7]
; GFX900-NEXT: v_mov_b32_e32 v6, s26
-; GFX900-NEXT: v_mov_b32_e32 v5, s23
; GFX900-NEXT: v_mov_b32_e32 v7, s27
; GFX900-NEXT: v_fma_f64 v[4:5], -s[18:19], -v[4:5], v[6:7]
; GFX900-NEXT: v_readfirstlane_b32 s4, v2
@@ -1154,9 +1153,9 @@ define void @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni(<2 x double> i
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s2, v2
; GFX942-NEXT: v_readfirstlane_b32 s3, v3
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1164,20 +1163,20 @@ define void @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni(<2 x double> i
; GFX11-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21
+; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fma_f64 v[4:5], -s[2:3], -s[18:19], v[4:5]
; GFX11-NEXT: v_fma_f64 v[2:3], -s[0:1], -s[16:17], v[2:3]
+; GFX11-NEXT: v_fma_f64 v[4:5], -s[2:3], -s[18:19], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1188,21 +1187,21 @@ define void @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni(<2 x double> i
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX12-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21
+; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_fma_f64 v[4:5], -s[2:3], -s[18:19], v[4:5]
; GFX12-NEXT: v_fma_f64 v[2:3], -s[0:1], -s[16:17], v[2:3]
+; GFX12-NEXT: v_fma_f64 v[4:5], -s[2:3], -s[18:19], v[4:5]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_readfirstlane_b32 s3, v5
-; GFX12-NEXT: v_readfirstlane_b32 s2, v4
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg <2 x double> %x
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
index daeb7753c94d9..f883312e029ca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
@@ -369,9 +369,9 @@ define void @s_usubo_usube(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_sub_u32 s4, s16, s18
; GFX7-NEXT: s_subb_u32 s5, s17, s19
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_cselect_b32 s8, 1, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
@@ -386,8 +386,8 @@ define void @s_usubo_usube(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_sub_u32 s4, s16, s18
; GFX9-NEXT: s_subb_u32 s5, s17, s19
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[4:5], off
; GFX9-NEXT: v_mov_b32_e32 v0, s6
@@ -400,8 +400,8 @@ define void @s_usubo_usube(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_sub_u32 s4, s16, s18
; GFX8-NEXT: s_subb_u32 s5, s17, s19
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
; GFX8-NEXT: v_mov_b32_e32 v0, s6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
index 8cd5ce14c2a09..1523478525b08 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
@@ -712,8 +712,8 @@ define amdgpu_ps i64 @s_ssubo_i64(i64 inreg %a, i64 inreg %b) {
;
; GFX8-LABEL: s_ssubo_i64:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_sub_u32 s4, s0, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_subb_u32 s5, s1, s3
@@ -731,8 +731,8 @@ define amdgpu_ps i64 @s_ssubo_i64(i64 inreg %a, i64 inreg %b) {
;
; GFX9-LABEL: s_ssubo_i64:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_sub_u32 s4, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s1, s3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
index 7610f2aea3627..f1a7348879481 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
@@ -44,12 +44,12 @@ define amdgpu_kernel void @udivrem_i32(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
; GFX8-NEXT: s_cselect_b32 s0, s6, s0
; GFX8-NEXT: s_sub_i32 s5, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_cselect_b32 s0, s5, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -311,15 +311,15 @@ define amdgpu_kernel void @udivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: s_cmp_lg_u32 s19, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX8-NEXT: s_cmp_lg_u32 s16, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -469,8 +469,8 @@ define amdgpu_kernel void @udivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX9-NEXT: s_cmp_lg_u32 s19, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX9-NEXT: s_cmp_lg_u32 s16, 0
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, s4
@@ -685,12 +685,12 @@ define amdgpu_kernel void @udivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_sub_i32 s9, 0, s7
; GFX8-NEXT: s_mul_i32 s9, s9, s8
; GFX8-NEXT: v_mul_hi_u32 v0, v1, s9
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_readfirstlane_b32 s9, v0
; GFX8-NEXT: s_add_i32 s8, s8, s9
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mul_hi_u32 v2, s5, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_readfirstlane_b32 s0, v2
; GFX8-NEXT: s_mul_i32 s1, s0, s7
; GFX8-NEXT: s_sub_i32 s1, s5, s1
@@ -708,14 +708,14 @@ define amdgpu_kernel void @udivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_cmp_lg_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s5, s5, s0
; GFX8-NEXT: s_sub_i32 s0, s1, s7
+; GFX8-NEXT: s_cmp_lg_u32 s8, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
-; GFX8-NEXT: s_cmp_lg_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s7, s0, s1
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -779,10 +779,10 @@ define amdgpu_kernel void @udivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_cmp_lg_u32 s10, 0
; GFX9-NEXT: s_cselect_b32 s5, s5, s8
; GFX9-NEXT: s_sub_i32 s7, s9, s7
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_cmp_lg_u32 s10, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_cselect_b32 s7, s7, s9
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_mov_b32_e32 v1, s7
@@ -998,11 +998,11 @@ define amdgpu_kernel void @udivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: s_cselect_b32 s15, s6, s4
; GFX8-NEXT: s_sub_i32 s4, s3, s7
+; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NEXT: v_mov_b32_e32 v3, s15
-; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: s_cselect_b32 s3, s4, s3
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s10
@@ -1130,12 +1130,12 @@ define amdgpu_kernel void @udivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_cmp_lg_u32 s14, 0
; GFX9-NEXT: s_cselect_b32 s3, s3, s12
; GFX9-NEXT: s_sub_i32 s7, s13, s7
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_cmp_lg_u32 s14, 0
+; GFX9-NEXT: s_cselect_b32 s7, s7, s13
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-NEXT: s_cselect_b32 s7, s7, s13
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_e32 v0, s4
@@ -1615,15 +1615,15 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_cmp_lg_u32 s20, 0
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
; GFX8-NEXT: s_cmp_lg_u32 s23, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: s_cselect_b64 s[10:11], s[14:15], s[16:17]
; GFX8-NEXT: s_cmp_lg_u32 s20, 0
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13]
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13]
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s8
@@ -1919,13 +1919,13 @@ define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1
; GFX9-NEXT: s_cmp_lg_u32 s20, 0
; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
; GFX9-NEXT: s_cmp_lg_u32 s23, 0
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_cselect_b64 s[10:11], s[14:15], s[16:17]
; GFX9-NEXT: s_cmp_lg_u32 s20, 0
+; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13]
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
-; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13]
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_e32 v0, s8
@@ -2285,12 +2285,12 @@ define amdgpu_kernel void @udiv_i8(ptr addrspace(1) %out0, ptr addrspace(1) %out
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
; GFX8-NEXT: s_cselect_b32 s0, s6, s0
; GFX8-NEXT: s_sub_i32 s5, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_cselect_b32 s0, s5, s1
; GFX8-NEXT: flat_store_byte v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -2472,10 +2472,10 @@ define amdgpu_kernel void @udivrem_v2i8(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_and_b32 s0, s10, 0xff
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -2690,12 +2690,12 @@ define amdgpu_kernel void @udiv_i16(ptr addrspace(1) %out0, ptr addrspace(1) %ou
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
; GFX8-NEXT: s_cselect_b32 s0, s6, s0
; GFX8-NEXT: s_sub_i32 s5, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_cselect_b32 s0, s5, s1
; GFX8-NEXT: flat_store_short v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -2870,17 +2870,17 @@ define amdgpu_kernel void @udivrem_v2i16(ptr addrspace(1) %out0, ptr addrspace(1
; GFX8-NEXT: s_and_b32 s7, s8, 0xffff
; GFX8-NEXT: s_lshl_b32 s7, s7, 16
; GFX8-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX8-NEXT: s_or_b32 s5, s5, s7
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX8-NEXT: s_or_b32 s5, s5, s7
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
+; GFX8-NEXT: s_or_b32 s4, s6, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: s_or_b32 s4, s6, s4
; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -3089,8 +3089,8 @@ define amdgpu_kernel void @udivrem_i3(ptr addrspace(1) %out0, ptr addrspace(1) %
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_and_b32 s0, s1, 7
; GFX8-NEXT: flat_store_byte v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_endpgm
@@ -3239,8 +3239,8 @@ define amdgpu_kernel void @udivrem_i27(ptr addrspace(1) %out0, ptr addrspace(1)
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_and_b32 s0, s1, 0x7ffffff
; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
index e59845121e9f6..5d2e74bbd816b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
@@ -345,10 +345,10 @@ define amdgpu_kernel void @constant_sextload_i8_align2(ptr addrspace(1) %out, pt
; GFX8-NEXT: v_readfirstlane_b32 s2, v2
; GFX8-NEXT: s_lshr_b32 s2, s2, 16
; GFX8-NEXT: s_add_u32 s0, s0, 2
-; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
index 8f8267952cbe1..759d82077eb87 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
@@ -21,15 +21,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm_non_inlineable(<8 x half>
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v17, s7 :: v_dual_mov_b32 v16, s6
+; GCN-NEXT: v_dual_mov_b32 v16, s6 :: v_dual_mov_b32 v17, s7
; GCN-NEXT: v_dual_mov_b32 v15, s5 :: v_dual_mov_b32 v14, s4
; GCN-NEXT: v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
; GCN-NEXT: v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
@@ -63,15 +63,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm_non_inlineable(<8 x i16>
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v17, s7 :: v_dual_mov_b32 v16, s6
+; GCN-NEXT: v_dual_mov_b32 v16, s6 :: v_dual_mov_b32 v17, s7
; GCN-NEXT: v_dual_mov_b32 v15, s5 :: v_dual_mov_b32 v14, s4
; GCN-NEXT: v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
; GCN-NEXT: v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
@@ -103,10 +103,10 @@ define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm_non_inlineable(<8 x half>
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x42004200
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
+; GCN-NEXT: s_mov_b32 s3, s0
+; GCN-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v13, s3
; GCN-NEXT: v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_wmma_f16_16x16x16_f16 v[10:13], v[0:3], v[4:7], v[10:13]
@@ -123,10 +123,10 @@ define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm(<8 x i16> %A, <8 x i16>
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x3f803f80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
+; GCN-NEXT: s_mov_b32 s3, s0
+; GCN-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v13, s3
; GCN-NEXT: v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_wmma_bf16_16x16x16_bf16 v[10:13], v[0:3], v[4:7], v[10:13]
@@ -143,10 +143,10 @@ define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm_non_inlineable(<8 x i16>
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x3fc03fc0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_dual_mov_b32 v13, s3 :: v_dual_mov_b32 v12, s2
+; GCN-NEXT: s_mov_b32 s3, s0
+; GCN-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v13, s3
; GCN-NEXT: v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_wmma_bf16_16x16x16_bf16 v[10:13], v[0:3], v[4:7], v[10:13]
@@ -177,15 +177,15 @@ define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm_non_inlineable(<2 x i32> %
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_movk_i32 s0, 0x80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v13, s7 :: v_dual_mov_b32 v12, s6
+; GCN-NEXT: v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
; GCN-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4
; GCN-NEXT: v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v8, s2
; GCN-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
@@ -219,15 +219,15 @@ define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm_non_inlineable(i32 %A, i32
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_movk_i32 s0, 0x80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v11, s7 :: v_dual_mov_b32 v10, s6
+; GCN-NEXT: v_dual_mov_b32 v10, s6 :: v_dual_mov_b32 v11, s7
; GCN-NEXT: v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
; GCN-NEXT: v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
; GCN-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
@@ -261,15 +261,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable(<2 x i3
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v13, s7 :: v_dual_mov_b32 v12, s6
+; GCN-NEXT: v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
; GCN-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4
; GCN-NEXT: v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v8, s2
; GCN-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
@@ -303,15 +303,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable(<2 x i3
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v13, s7 :: v_dual_mov_b32 v12, s6
+; GCN-NEXT: v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
; GCN-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4
; GCN-NEXT: v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v8, s2
; GCN-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
@@ -345,15 +345,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable(<2 x i3
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v13, s7 :: v_dual_mov_b32 v12, s6
+; GCN-NEXT: v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
; GCN-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4
; GCN-NEXT: v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v8, s2
; GCN-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
@@ -387,15 +387,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable(<2 x i3
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v13, s7 :: v_dual_mov_b32 v12, s6
+; GCN-NEXT: v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
; GCN-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4
; GCN-NEXT: v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v8, s2
; GCN-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
@@ -429,15 +429,15 @@ define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm_non_inlineable(<2 x i32> %
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_movk_i32 s0, 0x80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s0
; GCN-NEXT: s_mov_b32 s6, s0
+; GCN-NEXT: s_mov_b32 s7, s0
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v13, s7 :: v_dual_mov_b32 v12, s6
+; GCN-NEXT: v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v13, s7
; GCN-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4
; GCN-NEXT: v_dual_mov_b32 v9, s3 :: v_dual_mov_b32 v8, s2
; GCN-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
index ce9b8f9fc3c14..2e375ccdc38a0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
@@ -19,11 +19,11 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm_non_inlineable(<4 x half>
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v9, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v8, s2
+; GCN-NEXT: v_mov_b32_e32 v9, s3
; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_mov_b32_e32 v6, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -53,11 +53,11 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm_non_inlineable(<4 x i16>
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v9, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v8, s2
+; GCN-NEXT: v_mov_b32_e32 v9, s3
; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_mov_b32_e32 v6, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -86,11 +86,10 @@ define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm_non_inlineable(<4 x half>
; GCN-LABEL: test_wmma_f16_16x16x16_f16_imm_non_inlineable:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x42004200
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GCN-NEXT: s_mov_b32 s1, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_wmma_f16_16x16x16_f16 v[6:7], v[0:1], v[2:3], v[6:7]
; GCN-NEXT: global_store_b64 v[4:5], v[6:7], off
; GCN-NEXT: s_endpgm
@@ -104,11 +103,10 @@ define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm(<4 x i16> %A, <4 x i16>
; GCN-LABEL: test_wmma_bf16_16x16x16_bf16_imm:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x3f803f80
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GCN-NEXT: s_mov_b32 s1, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_wmma_bf16_16x16x16_bf16 v[6:7], v[0:1], v[2:3], v[6:7]
; GCN-NEXT: global_store_b64 v[4:5], v[6:7], off
; GCN-NEXT: s_endpgm
@@ -122,11 +120,10 @@ define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm_non_inlineable(<4 x i16>
; GCN-LABEL: test_wmma_bf16_16x16x16_bf16_imm_non_inlineable:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x3fc03fc0
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GCN-NEXT: s_mov_b32 s1, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_mov_b32_e32 v7, s1
; GCN-NEXT: v_wmma_bf16_16x16x16_bf16 v[6:7], v[0:1], v[2:3], v[6:7]
; GCN-NEXT: global_store_b64 v[4:5], v[6:7], off
; GCN-NEXT: s_endpgm
@@ -153,11 +150,11 @@ define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm_non_inlineable(i32 %A, i32
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_movk_i32 s0, 0x80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -187,11 +184,11 @@ define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm_non_inlineable(i32 %A, i32
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_movk_i32 s0, 0x80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -221,11 +218,11 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable(i32 %A,
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -255,11 +252,11 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable(i32 %A,
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -289,11 +286,11 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable(i32 %A,
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -323,11 +320,11 @@ define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable(i32 %A,
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_mov_b32 s0, 0x40400000
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -357,11 +354,11 @@ define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm_non_inlineable(i32 %A, i32
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_movk_i32 s0, 0x80
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
-; GCN-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NEXT: s_mov_b32 s3, s0
; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: v_mov_b32_e32 v7, s3
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
index 4f40948cab0a2..baf389708cc93 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
@@ -559,11 +559,11 @@ define void @flat_atomic_cmpxchg_i64_ret_a_a__a(ptr %ptr) #0 {
; CHECK-NEXT: ; def a[2:3]
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: v_accvgpr_read_b32 v5, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a2
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; def a[4:5]
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: v_accvgpr_read_b32 v2, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a2
; CHECK-NEXT: v_accvgpr_read_b32 v3, a5
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; CHECK-NEXT: ; implicit-def: $agpr0_agpr1
@@ -630,11 +630,11 @@ define void @flat_atomic_cmpxchg_i64_ret_a_a__v(ptr %ptr) #0 {
; CHECK-NEXT: ; def a[0:1]
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: v_accvgpr_read_b32 v5, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a0
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; def a[2:3]
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: v_accvgpr_read_b32 v7, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a0
; CHECK-NEXT: v_accvgpr_read_b32 v6, a2
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
index 241050c7bb926..bdf139918f1f3 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
@@ -509,12 +509,12 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a2
; GFX950-NEXT: ;;#ASMEND
+; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_write_b32 a19, v31 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a20, v30 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a21, v29 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a22, v28 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: v_accvgpr_read_b32 v2, a2
; GFX950-NEXT: buffer_wbl2 sc0 sc1
@@ -2659,9 +2659,9 @@ define void @flat_atomic_xor_expansion_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_xor_b32_e32 v3, v1, v7
; GFX950-NEXT: v_xor_b32_e32 v2, v0, v6
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB32_6: ; %atomicrmw.phi
@@ -2909,9 +2909,9 @@ define void @flat_atomic_xor_expansion_i64_ret_v_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_xor_b32_e32 v3, v1, v7
; GFX950-NEXT: v_xor_b32_e32 v2, v0, v6
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB34_6: ; %atomicrmw.phi
@@ -3274,9 +3274,9 @@ define void @flat_atomic_xor_expansion_i64_ret_av_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_xor_b32_e32 v3, v1, v7
; GFX950-NEXT: v_xor_b32_e32 v2, v0, v6
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB37_6: ; %atomicrmw.phi
@@ -4254,12 +4254,12 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a2
; GFX950-NEXT: ;;#ASMEND
+; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_write_b32 a19, v31 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a20, v30 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a21, v29 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a22, v28 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: v_accvgpr_read_b32 v2, a2
; GFX950-NEXT: buffer_wbl2 sc1
@@ -4475,9 +4475,9 @@ define void @flat_atomic_xor_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_xor_b32_e32 v3, v1, v3
; GFX950-NEXT: v_xor_b32_e32 v2, v0, v2
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB53_4: ; %atomicrmw.phi
@@ -4663,9 +4663,9 @@ define void @flat_atomic_xor_i64_ret_v_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_xor_b32_e32 v3, v1, v3
; GFX950-NEXT: v_xor_b32_e32 v2, v0, v2
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB55_4: ; %atomicrmw.phi
@@ -4935,9 +4935,9 @@ define void @flat_atomic_xor_i64_ret_av_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_xor_b32_e32 v3, v1, v3
; GFX950-NEXT: v_xor_b32_e32 v2, v0, v2
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB58_4: ; %atomicrmw.phi
@@ -6490,8 +6490,8 @@ define void @flat_atomic_add_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB89_4: ; %atomicrmw.phi
@@ -6860,9 +6860,9 @@ define void @flat_atomic_and_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_and_b32_e32 v3, v1, v3
; GFX950-NEXT: v_and_b32_e32 v2, v0, v2
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB93_4: ; %atomicrmw.phi
@@ -7081,9 +7081,9 @@ define void @flat_atomic_nand_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_and_b32_e32 v2, v1, v7
; GFX950-NEXT: v_and_b32_e32 v5, v0, v6
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_not_b32_e32 v3, v2
; GFX950-NEXT: v_not_b32_e32 v2, v5
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB95_6: ; %atomicrmw.phi
@@ -7303,9 +7303,9 @@ define void @flat_atomic_or_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_or_b32_e32 v3, v1, v3
; GFX950-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB97_4: ; %atomicrmw.phi
@@ -8453,9 +8453,10 @@ define void @flat_atomic_udec_wrap_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 v4, v[0:1], off
; GFX950-NEXT: .LBB109_4: ; %atomicrmw.phi
@@ -9957,8 +9958,8 @@ define void @flat_atomic_fadd_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
@@ -10023,8 +10024,8 @@ define void @flat_atomic_fadd_f64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB127_5: ; %Flow1
@@ -10225,8 +10226,8 @@ define void @flat_atomic_fsub_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_add_f64 v[2:3], v[0:1], -v[6:7]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
@@ -10284,8 +10285,8 @@ define void @flat_atomic_fsub_f64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_add_f64 v[2:3], v[0:1], -v[6:7]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v4, v[2:3], off
; GFX950-NEXT: .LBB129_6: ; %atomicrmw.phi
@@ -10448,8 +10449,8 @@ define void @flat_atomic_fmax_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
@@ -10495,8 +10496,8 @@ define void @flat_atomic_fmax_f64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v6, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v6, v[2:3], off
; GFX950-NEXT: .LBB131_4: ; %atomicrmw.phi
@@ -10636,8 +10637,8 @@ define void @flat_atomic_fmin_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
@@ -10683,8 +10684,8 @@ define void @flat_atomic_fmin_f64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v6, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 v6, v[2:3], off
; GFX950-NEXT: .LBB133_4: ; %atomicrmw.phi
@@ -10842,8 +10843,8 @@ define void @flat_atomic_fmaximum_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX90A-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
@@ -11111,8 +11112,8 @@ define void @flat_atomic_fminimum_f64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX90A-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
@@ -14675,12 +14676,12 @@ define void @flat_atomic_add_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB195_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -14728,12 +14729,12 @@ define void @flat_atomic_add_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB195_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -14758,8 +14759,8 @@ define void @flat_atomic_add_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 0, v[0:1]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
; GFX950-NEXT: .LBB195_5: ; %atomicrmw.end
@@ -14876,12 +14877,12 @@ define void @flat_atomic_sub_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB197_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -14929,12 +14930,12 @@ define void @flat_atomic_sub_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB197_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15081,12 +15082,12 @@ define void @flat_atomic_and_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB199_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15134,12 +15135,12 @@ define void @flat_atomic_and_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB199_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15164,9 +15165,9 @@ define void @flat_atomic_and_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_and_b32_e32 v1, v3, v1
; GFX950-NEXT: v_and_b32_e32 v0, v2, v0
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
; GFX950-NEXT: .LBB199_5: ; %atomicrmw.end
@@ -15284,12 +15285,12 @@ define void @flat_atomic_nand_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: v_accvgpr_read_b32 v4, a0
; GFX90A-NEXT: s_cbranch_scc0 .LBB201_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15348,12 +15349,12 @@ define void @flat_atomic_nand_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: v_accvgpr_read_b32 v4, a0
; GFX950-NEXT: s_cbranch_scc0 .LBB201_4
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15389,9 +15390,9 @@ define void @flat_atomic_nand_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_and_b32_e32 v2, v1, v5
; GFX950-NEXT: v_and_b32_e32 v4, v0, v4
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_not_b32_e32 v3, v2
; GFX950-NEXT: v_not_b32_e32 v2, v4
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 off, v[2:3], s0
; GFX950-NEXT: .LBB201_6: ; %atomicrmw.phi
@@ -15534,12 +15535,12 @@ define void @flat_atomic_or_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB203_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15587,12 +15588,12 @@ define void @flat_atomic_or_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB203_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15617,9 +15618,9 @@ define void @flat_atomic_or_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_or_b32_e32 v1, v3, v1
; GFX950-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
; GFX950-NEXT: .LBB203_5: ; %atomicrmw.end
@@ -15737,12 +15738,12 @@ define void @flat_atomic_xor_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB205_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15790,12 +15791,12 @@ define void @flat_atomic_xor_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB205_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15820,9 +15821,9 @@ define void @flat_atomic_xor_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_xor_b32_e32 v1, v3, v1
; GFX950-NEXT: v_xor_b32_e32 v0, v2, v0
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
; GFX950-NEXT: .LBB205_5: ; %atomicrmw.end
@@ -15940,12 +15941,12 @@ define void @flat_atomic_max_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB207_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -15994,12 +15995,12 @@ define void @flat_atomic_max_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB207_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16148,12 +16149,12 @@ define void @flat_atomic_min_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB209_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16202,12 +16203,12 @@ define void @flat_atomic_min_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB209_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16356,12 +16357,12 @@ define void @flat_atomic_umax_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB211_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16410,12 +16411,12 @@ define void @flat_atomic_umax_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB211_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16564,12 +16565,12 @@ define void @flat_atomic_umin_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB213_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16618,12 +16619,12 @@ define void @flat_atomic_umin_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB213_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16772,12 +16773,12 @@ define void @flat_atomic_uinc_wrap_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB215_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16828,12 +16829,12 @@ define void @flat_atomic_uinc_wrap_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB215_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -16986,12 +16987,12 @@ define void @flat_atomic_udec_wrap_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB217_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -17043,12 +17044,12 @@ define void @flat_atomic_udec_wrap_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB217_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -17078,9 +17079,10 @@ define void @flat_atomic_udec_wrap_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_subbrev_co_u32_e32 v5, vcc, 0, v3, vcc
; GFX950-NEXT: s_or_b64 vcc, vcc, s[0:1]
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s2
; GFX950-NEXT: .LBB217_5: ; %atomicrmw.phi
@@ -17208,12 +17210,12 @@ define void @flat_atomic_usub_cond_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: v_accvgpr_read_b32 v4, a0
; GFX90A-NEXT: s_cbranch_scc0 .LBB219_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -17274,12 +17276,12 @@ define void @flat_atomic_usub_cond_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: v_accvgpr_read_b32 v4, a0
; GFX950-NEXT: s_cbranch_scc0 .LBB219_4
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -17474,12 +17476,12 @@ define void @flat_atomic_usub_sat_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: v_accvgpr_read_b32 v4, a0
; GFX90A-NEXT: s_cbranch_scc0 .LBB221_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -17538,12 +17540,12 @@ define void @flat_atomic_usub_sat_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: v_accvgpr_read_b32 v4, a0
; GFX950-NEXT: s_cbranch_scc0 .LBB221_4
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -18603,12 +18605,12 @@ define void @flat_atomic_fadd_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_shared_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB235_3
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.check.private
@@ -18644,8 +18646,8 @@ define void @flat_atomic_fadd_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v2, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v3, v6, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: v_add_f64 v[4:5], v[2:3], v[0:1]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen offset:4
@@ -18678,12 +18680,12 @@ define void @flat_atomic_fadd_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_shared_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB235_3
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.check.private
@@ -18717,8 +18719,8 @@ define void @flat_atomic_fadd_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s2, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], off, s2
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_add_f64 v[4:5], v[2:3], v[0:1]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[4:5], s2
; GFX950-NEXT: .LBB235_7: ; %Flow1
@@ -18895,12 +18897,12 @@ define void @flat_atomic_fsub_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: v_accvgpr_read_b32 v4, a0
; GFX90A-NEXT: s_cbranch_scc0 .LBB237_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -18933,8 +18935,8 @@ define void @flat_atomic_fsub_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_add_f64 v[2:3], v[0:1], -v[4:5]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
@@ -18952,12 +18954,12 @@ define void @flat_atomic_fsub_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: v_accvgpr_read_b32 v4, a0
; GFX950-NEXT: s_cbranch_scc0 .LBB237_4
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -18989,8 +18991,8 @@ define void @flat_atomic_fsub_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_add_f64 v[2:3], v[0:1], -v[4:5]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: scratch_store_dwordx2 off, v[2:3], s0
; GFX950-NEXT: .LBB237_6: ; %atomicrmw.phi
@@ -19121,12 +19123,12 @@ define void @flat_atomic_fmax_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB239_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -19155,8 +19157,8 @@ define void @flat_atomic_fmax_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: v_max_f64 v[0:1], v[4:5], v[0:1]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
@@ -19174,12 +19176,12 @@ define void @flat_atomic_fmax_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB239_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -19206,8 +19208,8 @@ define void @flat_atomic_fmax_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_max_f64 v[0:1], v[4:5], v[0:1]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
; GFX950-NEXT: .LBB239_5: ; %atomicrmw.end
@@ -19327,12 +19329,12 @@ define void @flat_atomic_fmin_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: s_cbranch_scc0 .LBB241_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -19361,8 +19363,8 @@ define void @flat_atomic_fmin_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: v_min_f64 v[0:1], v[4:5], v[0:1]
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
@@ -19380,12 +19382,12 @@ define void @flat_atomic_fmin_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: s_cbranch_scc0 .LBB241_2
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -19412,8 +19414,8 @@ define void @flat_atomic_fmin_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_max_f64 v[4:5], v[2:3], v[2:3]
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_min_f64 v[0:1], v[4:5], v[0:1]
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
; GFX950-NEXT: .LBB241_5: ; %atomicrmw.end
@@ -19533,12 +19535,12 @@ define void @flat_atomic_fmaximum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: v_accvgpr_read_b32 v4, a0
; GFX90A-NEXT: s_cbranch_scc0 .LBB243_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -19578,8 +19580,8 @@ define void @flat_atomic_fmaximum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX90A-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
@@ -19598,12 +19600,12 @@ define void @flat_atomic_fmaximum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: v_accvgpr_read_b32 v4, a0
; GFX950-NEXT: s_cbranch_scc0 .LBB243_4
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -19794,12 +19796,12 @@ define void @flat_atomic_fminimum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_mov_b64 s[6:7], src_private_base
; GFX90A-NEXT: s_addc_u32 s5, s17, 0
; GFX90A-NEXT: s_cmp_eq_u32 s5, s7
+; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_cselect_b32 s6, 1, 0
-; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: s_cmp_lg_u32 s6, 1
+; GFX90A-NEXT: v_accvgpr_read_b32 v5, a1
; GFX90A-NEXT: v_accvgpr_read_b32 v4, a0
; GFX90A-NEXT: s_cbranch_scc0 .LBB245_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
@@ -19839,8 +19841,8 @@ define void @flat_atomic_fminimum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX90A-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX90A-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
@@ -19859,12 +19861,12 @@ define void @flat_atomic_fminimum_f64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_mov_b64 s[2:3], src_private_base
; GFX950-NEXT: s_addc_u32 s1, s1, 0
; GFX950-NEXT: s_cmp_eq_u32 s1, s3
+; GFX950-NEXT: s_cselect_b32 s2, 1, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: s_cselect_b32 s2, 1, 0
-; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: s_cmp_lg_u32 s2, 1
+; GFX950-NEXT: v_accvgpr_read_b32 v5, a1
; GFX950-NEXT: v_accvgpr_read_b32 v4, a0
; GFX950-NEXT: s_cbranch_scc0 .LBB245_4
; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
index c424dcc4aa398..b95033e75c693 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
@@ -509,12 +509,12 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a2
; GFX950-NEXT: ;;#ASMEND
+; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_write_b32 a19, v31 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a20, v30 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a21, v29 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a22, v28 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: v_accvgpr_read_b32 v2, a2
; GFX950-NEXT: buffer_wbl2 sc0 sc1
@@ -3235,12 +3235,12 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a2
; GFX950-NEXT: ;;#ASMEND
+; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_write_b32 a19, v31 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a20, v30 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a21, v29 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a22, v28 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX950-NEXT: scratch_store_dwordx3 off, v[16:18], s32 offset:64 ; 12-byte Folded Spill
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: v_accvgpr_read_b32 v2, a2
; GFX950-NEXT: buffer_wbl2 sc1
@@ -10474,11 +10474,11 @@ define void @global_atomic_xchg_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX90A-LABEL: global_atomic_xchg_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10492,10 +10492,11 @@ define void @global_atomic_xchg_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX950-LABEL: global_atomic_xchg_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -10552,11 +10553,11 @@ define void @global_atomic_add_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX90A-LABEL: global_atomic_add_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_add_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10570,10 +10571,11 @@ define void @global_atomic_add_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX950-LABEL: global_atomic_add_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_add_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -10630,11 +10632,11 @@ define void @global_atomic_sub_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX90A-LABEL: global_atomic_sub_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_sub_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10648,10 +10650,11 @@ define void @global_atomic_sub_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX950-LABEL: global_atomic_sub_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_sub_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -10708,11 +10711,11 @@ define void @global_atomic_and_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX90A-LABEL: global_atomic_and_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_and_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10726,10 +10729,11 @@ define void @global_atomic_and_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX950-LABEL: global_atomic_and_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_and_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -10928,11 +10932,11 @@ define void @global_atomic_or_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX90A-LABEL: global_atomic_or_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_or_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10946,10 +10950,11 @@ define void @global_atomic_or_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX950-LABEL: global_atomic_or_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_or_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -11006,11 +11011,11 @@ define void @global_atomic_xor_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX90A-LABEL: global_atomic_xor_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_xor_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11024,10 +11029,11 @@ define void @global_atomic_xor_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX950-LABEL: global_atomic_xor_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -11084,11 +11090,11 @@ define void @global_atomic_max_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX90A-LABEL: global_atomic_max_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_smax_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11102,10 +11108,11 @@ define void @global_atomic_max_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX950-LABEL: global_atomic_max_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_smax_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -11162,11 +11169,11 @@ define void @global_atomic_min_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX90A-LABEL: global_atomic_min_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_smin_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11180,10 +11187,11 @@ define void @global_atomic_min_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #0
; GFX950-LABEL: global_atomic_min_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_smin_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -11240,11 +11248,11 @@ define void @global_atomic_umax_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX90A-LABEL: global_atomic_umax_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_umax_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11258,10 +11266,11 @@ define void @global_atomic_umax_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX950-LABEL: global_atomic_umax_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_umax_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -11318,11 +11327,11 @@ define void @global_atomic_umin_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX90A-LABEL: global_atomic_umin_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_umin_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11336,10 +11345,11 @@ define void @global_atomic_umin_i64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX950-LABEL: global_atomic_umin_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_umin_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -11396,11 +11406,11 @@ define void @global_atomic_uinc_wrap_i64_saddr_ret_a_a(ptr addrspace(1) inreg %p
; GFX90A-LABEL: global_atomic_uinc_wrap_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_inc_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11414,10 +11424,11 @@ define void @global_atomic_uinc_wrap_i64_saddr_ret_a_a(ptr addrspace(1) inreg %p
; GFX950-LABEL: global_atomic_uinc_wrap_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_inc_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -11474,11 +11485,11 @@ define void @global_atomic_udec_wrap_i64_saddr_ret_a_a(ptr addrspace(1) inreg %p
; GFX90A-LABEL: global_atomic_udec_wrap_i64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_dec_x2 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11492,10 +11503,11 @@ define void @global_atomic_udec_wrap_i64_saddr_ret_a_a(ptr addrspace(1) inreg %p
; GFX950-LABEL: global_atomic_udec_wrap_i64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_dec_x2 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -12593,11 +12605,11 @@ define void @global_atomic_fadd_f64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX90A-LABEL: global_atomic_fadd_f64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_add_f64 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12611,10 +12623,11 @@ define void @global_atomic_fadd_f64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX950-LABEL: global_atomic_fadd_f64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_add_f64 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -12803,11 +12816,11 @@ define void @global_atomic_fmax_f64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX90A-LABEL: global_atomic_fmax_f64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_max_f64 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12821,10 +12834,11 @@ define void @global_atomic_fmax_f64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX950-LABEL: global_atomic_fmax_f64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_max_f64 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
@@ -12881,11 +12895,11 @@ define void @global_atomic_fmin_f64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX90A-LABEL: global_atomic_fmin_f64_saddr_ret_a_a:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_accvgpr_read_b32 v1, a1
; GFX90A-NEXT: global_atomic_min_f64 v[0:1], v2, v[0:1], s[16:17] offset:80 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12899,10 +12913,11 @@ define void @global_atomic_fmin_f64_saddr_ret_a_a(ptr addrspace(1) inreg %ptr) #
; GFX950-LABEL: global_atomic_fmin_f64_saddr_ret_a_a:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def a[0:1]
; GFX950-NEXT: ;;#ASMEND
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: s_nop 0
; GFX950-NEXT: v_accvgpr_read_b32 v0, a0
; GFX950-NEXT: v_accvgpr_read_b32 v1, a1
; GFX950-NEXT: global_atomic_min_f64 v[0:1], v2, v[0:1], s[0:1] offset:80 sc0
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index a68c708da351e..8ff8e6c6b2a70 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -245,11 +245,11 @@ define amdgpu_kernel void @marked_kernel_use_other_sgpr(ptr addrspace(1) %ptr) #
; FIXEDABI-LABEL: marked_kernel_use_other_sgpr:
; FIXEDABI: ; %bb.0:
; FIXEDABI-NEXT: s_add_i32 s6, s6, s11
-; FIXEDABI-NEXT: s_mov_b32 flat_scratch_lo, s7
; FIXEDABI-NEXT: s_lshr_b32 flat_scratch_hi, s6, 8
+; FIXEDABI-NEXT: s_mov_b32 flat_scratch_lo, s7
; FIXEDABI-NEXT: s_add_u32 s0, s4, 8
-; FIXEDABI-NEXT: flat_load_ubyte v0, v[0:1] glc
; FIXEDABI-NEXT: s_addc_u32 s1, s5, 0
+; FIXEDABI-NEXT: flat_load_ubyte v0, v[0:1] glc
; FIXEDABI-NEXT: s_waitcnt vmcnt(0)
; FIXEDABI-NEXT: v_mov_b32_e32 v0, s0
; FIXEDABI-NEXT: v_mov_b32_e32 v1, s1
diff --git a/llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
index d22a4b978980f..b6b6559f5790a 100644
--- a/llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
@@ -88,21 +88,21 @@ body: |
; GFX908-LABEL: name: a2_to_v2
; GFX908: liveins: $agpr0_agpr1
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr0_agpr1
+ ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit killed $agpr0_agpr1, implicit $exec
; GFX908-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1
;
; GFX90A-LABEL: name: a2_to_v2
; GFX90A: liveins: $agpr0_agpr1
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr0_agpr1
+ ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit killed $agpr0_agpr1, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1
;
; GFX942-LABEL: name: a2_to_v2
; GFX942: liveins: $agpr0_agpr1
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr0_agpr1
+ ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX942-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit killed $agpr0_agpr1, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1
$vgpr0_vgpr1 = COPY killed $agpr0_agpr1, implicit $exec
@@ -119,7 +119,7 @@ body: |
; GFX908-LABEL: name: a3_to_v3
; GFX908: liveins: $agpr0_agpr1_agpr2
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $agpr0_agpr1_agpr2
+ ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2
; GFX908-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit killed $agpr0_agpr1_agpr2, implicit $exec
; GFX908-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2
@@ -127,7 +127,7 @@ body: |
; GFX90A-LABEL: name: a3_to_v3
; GFX90A: liveins: $agpr0_agpr1_agpr2
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $agpr0_agpr1_agpr2
+ ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit killed $agpr0_agpr1_agpr2, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2
@@ -135,7 +135,7 @@ body: |
; GFX942-LABEL: name: a3_to_v3
; GFX942: liveins: $agpr0_agpr1_agpr2
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $agpr0_agpr1_agpr2
+ ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2
; GFX942-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2
; GFX942-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit killed $agpr0_agpr1_agpr2, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2
@@ -152,7 +152,7 @@ body: |
; GFX908-LABEL: name: a4_to_v4
; GFX908: liveins: $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -161,7 +161,7 @@ body: |
; GFX90A-LABEL: name: a4_to_v4
; GFX90A: liveins: $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -170,7 +170,7 @@ body: |
; GFX942-LABEL: name: a4_to_v4
; GFX942: liveins: $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -189,7 +189,7 @@ body: |
; GFX908-LABEL: name: a8_to_v8
; GFX908: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
+ ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX908-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX908-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
@@ -202,7 +202,7 @@ body: |
; GFX90A-LABEL: name: a8_to_v8
; GFX90A: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
+ ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
@@ -215,7 +215,7 @@ body: |
; GFX942-LABEL: name: a8_to_v8
; GFX942: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
+ ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX942-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX942-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX942-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
@@ -237,7 +237,7 @@ body: |
; GFX908-LABEL: name: a16_to_v16
; GFX908: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
+ ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX908-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX908-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
@@ -258,7 +258,7 @@ body: |
; GFX90A-LABEL: name: a16_to_v16
; GFX90A: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
+ ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
@@ -279,7 +279,7 @@ body: |
; GFX942-LABEL: name: a16_to_v16
; GFX942: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
+ ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX942-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX942-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX942-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
@@ -336,21 +336,21 @@ body: |
; GFX908-LABEL: name: v2_to_a2
; GFX908: liveins: $vgpr0_vgpr1
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $vgpr0_vgpr1
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1, implicit $exec
; GFX908-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1
;
; GFX90A-LABEL: name: v2_to_a2
; GFX90A: liveins: $vgpr0_vgpr1
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $vgpr0_vgpr1
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1
;
; GFX942-LABEL: name: v2_to_a2
; GFX942: liveins: $vgpr0_vgpr1
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $vgpr0_vgpr1
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1
$agpr0_agpr1 = COPY killed $vgpr0_vgpr1, implicit $exec
@@ -366,7 +366,7 @@ body: |
; GFX908-LABEL: name: v3_to_a3
; GFX908: liveins: $vgpr0_vgpr1_vgpr2
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $vgpr0_vgpr1_vgpr2
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2, implicit $exec
; GFX908-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2
@@ -374,7 +374,7 @@ body: |
; GFX90A-LABEL: name: v3_to_a3
; GFX90A: liveins: $vgpr0_vgpr1_vgpr2
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $vgpr0_vgpr1_vgpr2
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2
@@ -382,7 +382,7 @@ body: |
; GFX942-LABEL: name: v3_to_a3
; GFX942: liveins: $vgpr0_vgpr1_vgpr2
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $vgpr0_vgpr1_vgpr2
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2
@@ -399,7 +399,7 @@ body: |
; GFX908-LABEL: name: v4_to_a4
; GFX908: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
@@ -408,7 +408,7 @@ body: |
; GFX90A-LABEL: name: v4_to_a4
; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
@@ -417,7 +417,7 @@ body: |
; GFX942-LABEL: name: v4_to_a4
; GFX942: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX942-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
@@ -435,7 +435,7 @@ body: |
; GFX908-LABEL: name: v8_to_a8
; GFX908: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
@@ -448,7 +448,7 @@ body: |
; GFX90A-LABEL: name: v8_to_a8
; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
@@ -461,7 +461,7 @@ body: |
; GFX942-LABEL: name: v8_to_a8
; GFX942: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX942-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
@@ -483,7 +483,7 @@ body: |
; GFX908-LABEL: name: v16_to_a16
; GFX908: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -504,7 +504,7 @@ body: |
; GFX90A-LABEL: name: v16_to_a16
; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -525,7 +525,7 @@ body: |
; GFX942-LABEL: name: v16_to_a16
; GFX942: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX942-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -584,7 +584,7 @@ body: |
; GFX908: liveins: $sgpr0_sgpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec
; GFX908-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1
@@ -592,14 +592,14 @@ body: |
; GFX90A-LABEL: name: s2_to_a2
; GFX90A: liveins: $sgpr0_sgpr1
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $sgpr0_sgpr1
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1
;
; GFX942-LABEL: name: s2_to_a2
; GFX942: liveins: $sgpr0_sgpr1
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $sgpr0_sgpr1
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1
$agpr0_agpr1 = COPY killed $sgpr0_sgpr1, implicit $exec
@@ -616,7 +616,7 @@ body: |
; GFX908: liveins: $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2
@@ -626,7 +626,7 @@ body: |
; GFX90A-LABEL: name: s3_to_a3
; GFX90A: liveins: $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2
@@ -634,7 +634,7 @@ body: |
; GFX942-LABEL: name: s3_to_a3
; GFX942: liveins: $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2
@@ -652,7 +652,7 @@ body: |
; GFX908: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
@@ -664,7 +664,7 @@ body: |
; GFX90A-LABEL: name: s4_to_a4
; GFX90A: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec
@@ -673,7 +673,7 @@ body: |
; GFX942-LABEL: name: s4_to_a4
; GFX942: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec
@@ -692,7 +692,7 @@ body: |
; GFX908: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
@@ -708,7 +708,7 @@ body: |
; GFX90A-LABEL: name: s6_to_a6
; GFX90A: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
@@ -719,7 +719,7 @@ body: |
; GFX942-LABEL: name: s6_to_a6
; GFX942: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX942-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
@@ -740,7 +740,7 @@ body: |
; GFX908: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
@@ -760,7 +760,7 @@ body: |
; GFX90A-LABEL: name: s8_to_a8
; GFX90A: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
@@ -773,7 +773,7 @@ body: |
; GFX942-LABEL: name: s8_to_a8
; GFX942: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX942-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
@@ -796,7 +796,7 @@ body: |
; GFX908: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -832,7 +832,7 @@ body: |
; GFX90A-LABEL: name: s16_to_a16
; GFX90A: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -853,7 +853,7 @@ body: |
; GFX942-LABEL: name: s16_to_a16
; GFX942: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX942-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -909,7 +909,7 @@ body: |
; GFX908: liveins: $agpr0_agpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1
- ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr1_agpr2
+ ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec
@@ -918,7 +918,7 @@ body: |
; GFX90A-LABEL: name: a2_to_a2
; GFX90A: liveins: $agpr0_agpr1
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr1_agpr2, implicit $agpr0_agpr1
+ ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1, implicit $exec
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
@@ -926,7 +926,7 @@ body: |
; GFX942-LABEL: name: a2_to_a2
; GFX942: liveins: $agpr0_agpr1
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr1_agpr2, implicit $agpr0_agpr1
+ ; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1
; GFX942-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1, implicit $exec
; GFX942-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
@@ -945,7 +945,7 @@ body: |
; GFX908: liveins: $agpr0_agpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1
- ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr1_agpr2
+ ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec
@@ -954,7 +954,7 @@ body: |
; GFX90A-LABEL: name: a2_to_a2_kill
; GFX90A: liveins: $agpr0_agpr1
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr1_agpr2, implicit $agpr0_agpr1
+ ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1, implicit $exec
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec
; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
@@ -962,7 +962,7 @@ body: |
; GFX942-LABEL: name: a2_to_a2_kill
; GFX942: liveins: $agpr0_agpr1
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr1_agpr2, implicit $agpr0_agpr1
+ ; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1
; GFX942-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1, implicit $exec
; GFX942-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec
; GFX942-NEXT: S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
@@ -985,7 +985,7 @@ body: |
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec, implicit-def $agpr1_agpr2
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr1_agpr2
- ; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr3_agpr4
+ ; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr1_agpr2
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit $exec
;
@@ -996,7 +996,7 @@ body: |
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr1_agpr2
; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec, implicit-def $agpr1_agpr2
- ; GFX90A-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit-def $agpr3_agpr4, implicit $agpr1_agpr2
+ ; GFX90A-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr1_agpr2
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit killed $agpr1_agpr2, implicit $exec
;
; GFX942-LABEL: name: a2_to_a2_implicit_defs
@@ -1006,7 +1006,7 @@ body: |
; GFX942-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr1_agpr2
; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX942-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec, implicit-def $agpr1_agpr2
- ; GFX942-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit-def $agpr3_agpr4, implicit $agpr1_agpr2
+ ; GFX942-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr1_agpr2
; GFX942-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit killed $agpr1_agpr2, implicit $exec
$vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1
$agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr1_agpr2
@@ -1025,7 +1025,7 @@ body: |
; GFX908: liveins: $agpr4_agpr5_agpr6
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr4, implicit $exec, implicit $agpr4_agpr5_agpr6
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr5, implicit $exec, implicit $agpr4_agpr5_agpr6
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec, implicit killed $agpr4_agpr5_agpr6
@@ -1035,7 +1035,7 @@ body: |
; GFX90A-LABEL: name: a3_to_a3_nonoverlap_kill
; GFX90A: liveins: $agpr4_agpr5_agpr6
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr4, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr4_agpr5_agpr6
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr4, implicit $exec, implicit $agpr4_agpr5_agpr6
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr5, implicit $exec, implicit $agpr4_agpr5_agpr6
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr6, implicit $exec, implicit killed $agpr4_agpr5_agpr6
; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2
@@ -1043,7 +1043,7 @@ body: |
; GFX942-LABEL: name: a3_to_a3_nonoverlap_kill
; GFX942: liveins: $agpr4_agpr5_agpr6
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr4, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr4_agpr5_agpr6
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr4, implicit $exec, implicit $agpr4_agpr5_agpr6
; GFX942-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr5, implicit $exec, implicit $agpr4_agpr5_agpr6
; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr6, implicit $exec, implicit killed $agpr4_agpr5_agpr6
; GFX942-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2
@@ -1061,7 +1061,7 @@ body: |
; GFX908: liveins: $agpr1_agpr2_agpr3
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr1_agpr2_agpr3
- ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr1_agpr2_agpr3
@@ -1072,7 +1072,7 @@ body: |
; GFX90A-LABEL: name: a3_to_a3_overlap_kill
; GFX90A: liveins: $agpr1_agpr2_agpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr1_agpr2_agpr3
+ ; GFX90A-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr1_agpr2_agpr3
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec
@@ -1081,7 +1081,7 @@ body: |
; GFX942-LABEL: name: a3_to_a3_overlap_kill
; GFX942: liveins: $agpr1_agpr2_agpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr1_agpr2_agpr3
+ ; GFX942-NEXT: $agpr0 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr1_agpr2_agpr3
; GFX942-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec
@@ -1099,7 +1099,7 @@ body: |
; GFX908-LABEL: name: a4_to_a4
; GFX908: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
- ; GFX908-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $agpr2_agpr3_agpr4_agpr5
+ ; GFX908-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
@@ -1110,7 +1110,7 @@ body: |
;
; GFX90A-LABEL: name: a4_to_a4
; GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF
- ; GFX90A-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX90A-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -1118,7 +1118,7 @@ body: |
;
; GFX942-LABEL: name: a4_to_a4
; GFX942: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF
- ; GFX942-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX942-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -1138,7 +1138,7 @@ body: |
; GFX908: liveins: $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
- ; GFX908-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $agpr2_agpr3_agpr4_agpr5
+ ; GFX908-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
@@ -1150,7 +1150,7 @@ body: |
; GFX90A-LABEL: name: a4_to_a4_overlap
; GFX90A: liveins: $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX90A-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -1159,7 +1159,7 @@ body: |
; GFX942-LABEL: name: a4_to_a4_overlap
; GFX942: liveins: $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX942-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -1176,7 +1176,7 @@ body: |
; GFX908-LABEL: name: a8_to_a8
; GFX908: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr7, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
- ; GFX908-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec, implicit-def $agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
+ ; GFX908-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr6, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX908-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr5, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
@@ -1195,7 +1195,7 @@ body: |
;
; GFX90A-LABEL: name: a8_to_a8
; GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: $agpr15 = V_ACCVGPR_MOV_B32 $agpr7, implicit $exec, implicit-def $agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
+ ; GFX90A-NEXT: $agpr15 = V_ACCVGPR_MOV_B32 $agpr7, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX90A-NEXT: $agpr14 = V_ACCVGPR_MOV_B32 $agpr6, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX90A-NEXT: $agpr13 = V_ACCVGPR_MOV_B32 $agpr5, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX90A-NEXT: $agpr12 = V_ACCVGPR_MOV_B32 $agpr4, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
@@ -1207,7 +1207,7 @@ body: |
;
; GFX942-LABEL: name: a8_to_a8
; GFX942: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF
- ; GFX942-NEXT: $agpr15 = V_ACCVGPR_MOV_B32 $agpr7, implicit $exec, implicit-def $agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
+ ; GFX942-NEXT: $agpr15 = V_ACCVGPR_MOV_B32 $agpr7, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX942-NEXT: $agpr14 = V_ACCVGPR_MOV_B32 $agpr6, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX942-NEXT: $agpr13 = V_ACCVGPR_MOV_B32 $agpr5, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; GFX942-NEXT: $agpr12 = V_ACCVGPR_MOV_B32 $agpr4, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
@@ -1230,7 +1230,7 @@ body: |
; GFX908-LABEL: name: a16_to_a16
; GFX908: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr15, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
- ; GFX908-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
+ ; GFX908-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr14, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX908-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr13, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
@@ -1265,7 +1265,7 @@ body: |
;
; GFX90A-LABEL: name: a16_to_a16
; GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF
- ; GFX90A-NEXT: $agpr31 = V_ACCVGPR_MOV_B32 $agpr15, implicit $exec, implicit-def $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
+ ; GFX90A-NEXT: $agpr31 = V_ACCVGPR_MOV_B32 $agpr15, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX90A-NEXT: $agpr30 = V_ACCVGPR_MOV_B32 $agpr14, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX90A-NEXT: $agpr29 = V_ACCVGPR_MOV_B32 $agpr13, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX90A-NEXT: $agpr28 = V_ACCVGPR_MOV_B32 $agpr12, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
@@ -1285,7 +1285,7 @@ body: |
;
; GFX942-LABEL: name: a16_to_a16
; GFX942: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF
- ; GFX942-NEXT: $agpr31 = V_ACCVGPR_MOV_B32 $agpr15, implicit $exec, implicit-def $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
+ ; GFX942-NEXT: $agpr31 = V_ACCVGPR_MOV_B32 $agpr15, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX942-NEXT: $agpr30 = V_ACCVGPR_MOV_B32 $agpr14, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX942-NEXT: $agpr29 = V_ACCVGPR_MOV_B32 $agpr13, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; GFX942-NEXT: $agpr28 = V_ACCVGPR_MOV_B32 $agpr12, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
@@ -1354,7 +1354,7 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: S_NOP 0, implicit-def dead $sgpr0_sgpr1
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
- ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7
+ ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX908-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
@@ -1367,7 +1367,7 @@ body: |
; GFX90A: liveins: $agpr0, $sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: S_NOP 0, implicit-def dead $sgpr0_sgpr1
- ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec
@@ -1377,7 +1377,7 @@ body: |
; GFX942: liveins: $agpr0, $sgpr2_sgpr3
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: S_NOP 0, implicit-def dead $sgpr0_sgpr1
- ; GFX942-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX942-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec
@@ -1398,7 +1398,7 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: S_NOP 0, implicit-def dead $sgpr0_sgpr1
; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
- ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7
+ ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX908-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
@@ -1411,7 +1411,7 @@ body: |
; GFX90A: liveins: $agpr0, $sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: S_NOP 0, implicit-def dead $sgpr0_sgpr1
- ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec
@@ -1421,7 +1421,7 @@ body: |
; GFX942: liveins: $agpr0, $sgpr2_sgpr3
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: S_NOP 0, implicit-def dead $sgpr0_sgpr1
- ; GFX942-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX942-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $sgpr3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX942-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 $sgpr0, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec
@@ -1443,7 +1443,7 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: S_NOP 0, implicit-def dead $agpr0_agpr1
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
- ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7
+ ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
@@ -1456,7 +1456,7 @@ body: |
; GFX90A: liveins: $agpr0, $agpr2_agpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: S_NOP 0, implicit-def dead $agpr0_agpr1
- ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr6 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -1466,7 +1466,7 @@ body: |
; GFX942: liveins: $agpr0, $agpr2_agpr3
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: S_NOP 0, implicit-def dead $agpr0_agpr1
- ; GFX942-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX942-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr6 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -1488,7 +1488,7 @@ body: |
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: S_NOP 0, implicit-def dead $agpr0_agpr1
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
- ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7
+ ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr255 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr255, implicit $exec
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
@@ -1501,7 +1501,7 @@ body: |
; GFX90A: liveins: $agpr0, $agpr2_agpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: S_NOP 0, implicit-def dead $agpr0_agpr1
- ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX90A-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr6 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -1511,7 +1511,7 @@ body: |
; GFX942: liveins: $agpr0, $agpr2_agpr3
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: S_NOP 0, implicit-def dead $agpr0_agpr1
- ; GFX942-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX942-NEXT: $agpr7 = V_ACCVGPR_MOV_B32 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr6 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr5 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX942-NEXT: $agpr4 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/add.ll b/llvm/test/CodeGen/AMDGPU/add.ll
index 6e832df650204..d8262257e75ad 100644
--- a/llvm/test/CodeGen/AMDGPU/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/add.ll
@@ -344,9 +344,9 @@ define amdgpu_kernel void @s_add_v8i32(ptr addrspace(1) %out, <8 x i32> %a, <8 x
; GFX8-NEXT: s_add_u32 s2, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s9
; GFX8-NEXT: v_mov_b32_e32 v1, s8
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
@@ -1021,8 +1021,9 @@ define amdgpu_kernel void @add64(ptr addrspace(1) %out, i64 %a, i64 %b) {
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_add_u32 s2, s2, s4
; GFX11-NEXT: s_addc_u32 s3, s3, s5
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -1033,8 +1034,9 @@ define amdgpu_kernel void @add64(ptr addrspace(1) %out, i64 %a, i64 %b) {
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -1123,8 +1125,9 @@ define amdgpu_kernel void @add64_sgpr_vgpr(ptr addrspace(1) %out, i64 %a, ptr ad
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_add_u32 s2, s2, s4
; GFX11-NEXT: s_addc_u32 s3, s3, s5
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -1137,8 +1140,9 @@ define amdgpu_kernel void @add64_sgpr_vgpr(ptr addrspace(1) %out, i64 %a, ptr ad
; GFX12-NEXT: s_load_b64 s[4:5], s[6:7], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -1173,10 +1177,10 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
; GFX6-NEXT: ; %bb.4: ; %if
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
; GFX6-NEXT: .LBB9_5: ; %endif
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
@@ -1203,10 +1207,10 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
; GFX8-NEXT: ; %bb.4: ; %if
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
; GFX8-NEXT: .LBB9_5: ; %endif
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm
@@ -1233,9 +1237,9 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
; GFX9-NEXT: ; %bb.4: ; %if
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[10:11], 0x0
; GFX9-NEXT: .LBB9_5: ; %endif
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX9-NEXT: s_endpgm
@@ -1262,9 +1266,9 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
; GFX10-NEXT: ; %bb.4: ; %if
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[10:11], 0x0
; GFX10-NEXT: .LBB9_5: ; %endif
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX10-NEXT: s_endpgm
@@ -1293,8 +1297,8 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
; GFX11-NEXT: .LBB9_5: ; %endif
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, s4
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT: v_mov_b32_e32 v0, s4
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -1321,8 +1325,8 @@ define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(
; GFX12-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
; GFX12-NEXT: .LBB9_5: ; %endif
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
+; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
index bd4e24d96b612..8f1b41e70aee0 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
@@ -576,14 +576,14 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg
; GFX908-NEXT: s_cselect_b64 s[16:17], -1, 0
; GFX908-NEXT: s_cmp_gt_i32 s3, -1
; GFX908-NEXT: v_mov_b32_e32 v4, s10
-; GFX908-NEXT: v_mov_b32_e32 v6, s10
-; GFX908-NEXT: v_mov_b32_e32 v8, s10
; GFX908-NEXT: v_mov_b32_e32 v5, s11
; GFX908-NEXT: s_cselect_b64 s[20:21], -1, 0
+; GFX908-NEXT: v_mov_b32_e32 v6, s10
; GFX908-NEXT: v_mov_b32_e32 v7, s11
+; GFX908-NEXT: v_mov_b32_e32 v8, s10
; GFX908-NEXT: v_mov_b32_e32 v9, s11
-; GFX908-NEXT: v_mov_b32_e32 v11, v5
; GFX908-NEXT: s_mov_b64 s[18:19], s[12:13]
+; GFX908-NEXT: v_mov_b32_e32 v11, v5
; GFX908-NEXT: v_mov_b32_e32 v10, v4
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_readfirstlane_b32 s9, v2
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
index 950382758ffbc..a225b39f63231 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
@@ -35,7 +35,7 @@ body: |
; GFX908: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr63 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1
- ; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec, implicit-def $agpr2_agpr3
+ ; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec
; GFX908-NEXT: $vgpr63 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec
; GFX908-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, implicit $agpr2_agpr3
@@ -43,7 +43,7 @@ body: |
; GFX90A-LABEL: name: no_free_vgprs_for_copy_a64_to_a64
; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr2_agpr3, implicit $agpr0_agpr1
+ ; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit $agpr0_agpr1
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1
; GFX90A-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, implicit $agpr2_agpr3
$agpr2_agpr3 = COPY $agpr0_agpr1
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir b/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
index c674f9a988c26..bd9cbba2b67b2 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
@@ -25,7 +25,7 @@ body: |
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec
- ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3
+ ; GFX908-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3, implicit $exec
@@ -65,7 +65,7 @@ body: |
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit killed $agpr0_agpr1
; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1
; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $agpr0_agpr1
- ; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit-def $agpr2_agpr3, implicit $agpr0_agpr1
+ ; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr0, implicit $exec, implicit $agpr0_agpr1
; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit $agpr0_agpr1, implicit $exec
; GFX908-NEXT: S_ENDPGM 0
$agpr0_agpr1 = IMPLICIT_DEF
@@ -91,7 +91,7 @@ body: |
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3
; GFX908-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
- ; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $agpr1_agpr2_agpr3_agpr4
+ ; GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec
; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec
; GFX908-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir b/llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
index a9d31c1c45b0e..3e5793dc6c0ac 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
@@ -36,7 +36,7 @@ body: |
; GFX908: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8_sgpr9
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: $vgpr63 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9
- ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec, implicit-def $agpr2_agpr3
+ ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec
; GFX908-NEXT: $vgpr63 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9
; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec
; GFX908-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, implicit $agpr2_agpr3
@@ -44,7 +44,7 @@ body: |
; GFX90A-LABEL: name: no_free_vgprs_for_copy_s64_to_a64
; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8_sgpr9
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr8, implicit $exec, implicit-def $agpr2_agpr3, implicit $sgpr8_sgpr9
+ ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9
; GFX90A-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, implicit $agpr2_agpr3
$agpr2_agpr3 = COPY $sgpr8_sgpr9
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-csr.ll b/llvm/test/CodeGen/AMDGPU/agpr-csr.ll
index 63b7b70548baf..3c9b08d26288d 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-csr.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-csr.ll
@@ -124,8 +124,8 @@ define amdgpu_kernel void @test_call_empty() #0 {
; GFX90A-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX90A-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: v_mov_b32_e32 v31, v0
+; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX90A-NEXT: s_mov_b32 s32, 0
; GFX90A-NEXT: ;;#ASMSTART
@@ -167,14 +167,14 @@ define amdgpu_kernel void @test_call_empty() #0 {
; GFX908-NEXT: s_add_u32 s4, s4, func_empty at gotpcrel32@lo+4
; GFX908-NEXT: s_addc_u32 s5, s5, func_empty at gotpcrel32@hi+12
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX908-NEXT: s_mov_b32 s14, s10
-; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: s_mov_b32 s14, s10
+; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[20:21]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX908-NEXT: s_mov_b32 s32, 0
; GFX908-NEXT: ;;#ASMSTART
@@ -259,8 +259,8 @@ define amdgpu_kernel void @test_call_areg4() #0 {
; GFX90A-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX90A-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: v_mov_b32_e32 v31, v0
+; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX90A-NEXT: s_mov_b32 s32, 0
; GFX90A-NEXT: ;;#ASMSTART
@@ -302,14 +302,14 @@ define amdgpu_kernel void @test_call_areg4() #0 {
; GFX908-NEXT: s_add_u32 s4, s4, func_areg_4 at gotpcrel32@lo+4
; GFX908-NEXT: s_addc_u32 s5, s5, func_areg_4 at gotpcrel32@hi+12
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX908-NEXT: s_mov_b32 s14, s10
-; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: s_mov_b32 s14, s10
+; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[20:21]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX908-NEXT: s_mov_b32 s32, 0
; GFX908-NEXT: ;;#ASMSTART
@@ -394,8 +394,8 @@ define amdgpu_kernel void @test_call_areg32() #0 {
; GFX90A-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX90A-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: v_mov_b32_e32 v31, v0
+; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX90A-NEXT: s_mov_b32 s32, 0
; GFX90A-NEXT: ;;#ASMSTART
@@ -437,14 +437,14 @@ define amdgpu_kernel void @test_call_areg32() #0 {
; GFX908-NEXT: s_add_u32 s4, s4, func_areg_32 at gotpcrel32@lo+4
; GFX908-NEXT: s_addc_u32 s5, s5, func_areg_32 at gotpcrel32@hi+12
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX908-NEXT: s_mov_b32 s14, s10
-; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: s_mov_b32 s14, s10
+; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[20:21]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX908-NEXT: s_mov_b32 s32, 0
; GFX908-NEXT: ;;#ASMSTART
@@ -529,8 +529,8 @@ define amdgpu_kernel void @test_call_areg64() #0 {
; GFX90A-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX90A-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: v_mov_b32_e32 v31, v0
+; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX90A-NEXT: s_mov_b32 s32, 0
; GFX90A-NEXT: ;;#ASMSTART
@@ -572,14 +572,14 @@ define amdgpu_kernel void @test_call_areg64() #0 {
; GFX908-NEXT: s_add_u32 s4, s4, func_areg_64 at gotpcrel32@lo+4
; GFX908-NEXT: s_addc_u32 s5, s5, func_areg_64 at gotpcrel32@hi+12
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX908-NEXT: s_mov_b32 s14, s10
-; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: s_mov_b32 s14, s10
+; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[20:21]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX908-NEXT: s_mov_b32 s32, 0
; GFX908-NEXT: ;;#ASMSTART
@@ -664,8 +664,8 @@ define amdgpu_kernel void @test_call_areg31_63() #0 {
; GFX90A-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX90A-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: v_mov_b32_e32 v31, v0
+; GFX90A-NEXT: s_mov_b64 s[0:1], s[20:21]
; GFX90A-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX90A-NEXT: s_mov_b32 s32, 0
; GFX90A-NEXT: ;;#ASMSTART
@@ -707,14 +707,14 @@ define amdgpu_kernel void @test_call_areg31_63() #0 {
; GFX908-NEXT: s_add_u32 s4, s4, func_areg_31_63 at gotpcrel32@lo+4
; GFX908-NEXT: s_addc_u32 s5, s5, func_areg_31_63 at gotpcrel32@hi+12
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX908-NEXT: s_mov_b32 s14, s10
-; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: s_mov_b32 s14, s10
+; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[20:21]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX908-NEXT: s_mov_b32 s32, 0
; GFX908-NEXT: ;;#ASMSTART
@@ -799,8 +799,8 @@ define amdgpu_kernel void @test_call_unknown() #0 {
; GFX90A-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX90A-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX90A-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX90A-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX90A-NEXT: v_mov_b32_e32 v31, v0
+; GFX90A-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX90A-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX90A-NEXT: s_mov_b32 s32, 0
; GFX90A-NEXT: ;;#ASMSTART
@@ -842,14 +842,14 @@ define amdgpu_kernel void @test_call_unknown() #0 {
; GFX908-NEXT: s_add_u32 s4, s4, func_unknown at gotpcrel32@lo+4
; GFX908-NEXT: s_addc_u32 s5, s5, func_unknown at gotpcrel32@hi+12
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX908-NEXT: s_mov_b32 s14, s10
-; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: s_mov_b32 s14, s10
+; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX908-NEXT: s_mov_b32 s32, 0
; GFX908-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/always-uniform.ll b/llvm/test/CodeGen/AMDGPU/always-uniform.ll
index 095409c35b0ea..b10408f8c2684 100644
--- a/llvm/test/CodeGen/AMDGPU/always-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/always-uniform.ll
@@ -16,8 +16,8 @@ define amdgpu_kernel void @readfirstlane_uniform(ptr addrspace(1) noalias nocapt
; GCN-NEXT: s_load_dword s4, s[0:1], s4
; GCN-NEXT: s_add_u32 s0, s2, 40
; GCN-NEXT: s_addc_u32 s1, s3, 0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v2, s4
diff --git a/llvm/test/CodeGen/AMDGPU/amd.endpgm.ll b/llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
index 13add9a6b0792..25133690bacdb 100644
--- a/llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
+++ b/llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
@@ -134,9 +134,9 @@ define amdgpu_kernel void @test2(ptr %p, i32 %x) {
; GFX11-GISEL-NEXT: s_cbranch_scc0 .LBB2_2
; GFX11-GISEL-NEXT: ; %bb.1: ; %else
; GFX11-GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v1, s3
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-NEXT: flat_store_b32 v[0:1], v2
; GFX11-GISEL-NEXT: s_endpgm
; GFX11-GISEL-NEXT: .LBB2_2: ; %then
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 11bd7e257bbdf..b05c72cc8bf4c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -59288,7 +59288,6 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; VI-NEXT: s_branch .LBB41_6
; VI-NEXT: .LBB41_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -59304,6 +59303,7 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
+; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -59419,7 +59419,6 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; GFX9-NEXT: s_branch .LBB41_6
; GFX9-NEXT: .LBB41_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
-; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -59435,6 +59434,7 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -59549,7 +59549,6 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; GFX11-NEXT: s_branch .LBB41_5
; GFX11-NEXT: .LBB41_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
-; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -59557,6 +59556,7 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
+; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -67335,7 +67335,6 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; VI-NEXT: s_branch .LBB45_6
; VI-NEXT: .LBB45_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -67351,6 +67350,7 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
+; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -67466,7 +67466,6 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; GFX9-NEXT: s_branch .LBB45_6
; GFX9-NEXT: .LBB45_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
-; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -67482,6 +67481,7 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -67596,7 +67596,6 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; GFX11-NEXT: s_branch .LBB45_5
; GFX11-NEXT: .LBB45_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
-; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -67604,6 +67603,7 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
+; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -70698,7 +70698,6 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; VI-NEXT: s_branch .LBB49_6
; VI-NEXT: .LBB49_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -70714,6 +70713,7 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
+; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -70829,7 +70829,6 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; GFX9-NEXT: s_branch .LBB49_6
; GFX9-NEXT: .LBB49_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
-; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -70845,6 +70844,7 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -70959,7 +70959,6 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; GFX11-NEXT: s_branch .LBB49_5
; GFX11-NEXT: .LBB49_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
-; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -70967,6 +70966,7 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
+; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -126343,7 +126343,6 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; VI-NEXT: s_branch .LBB77_6
; VI-NEXT: .LBB77_5:
; VI-NEXT: v_mov_b32_e32 v16, s36
-; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -126359,6 +126358,7 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; VI-NEXT: v_mov_b32_e32 v29, s49
; VI-NEXT: v_mov_b32_e32 v30, s50
; VI-NEXT: v_mov_b32_e32 v31, s51
+; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -126458,7 +126458,6 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; GFX9-NEXT: s_branch .LBB77_6
; GFX9-NEXT: .LBB77_5:
; GFX9-NEXT: v_mov_b32_e32 v16, s36
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -126474,6 +126473,7 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; GFX9-NEXT: v_mov_b32_e32 v29, s49
; GFX9-NEXT: v_mov_b32_e32 v30, s50
; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -126572,7 +126572,6 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; GFX11-NEXT: s_branch .LBB77_5
; GFX11-NEXT: .LBB77_4:
; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
-; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -126580,6 +126579,7 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; GFX11-NEXT: v_dual_mov_b32 v26, s46 :: v_dual_mov_b32 v27, s47
; GFX11-NEXT: v_dual_mov_b32 v28, s48 :: v_dual_mov_b32 v29, s49
; GFX11-NEXT: v_dual_mov_b32 v30, s50 :: v_dual_mov_b32 v31, s51
+; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -134280,7 +134280,6 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; VI-NEXT: s_branch .LBB81_6
; VI-NEXT: .LBB81_5:
; VI-NEXT: v_mov_b32_e32 v16, s36
-; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -134296,6 +134295,7 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; VI-NEXT: v_mov_b32_e32 v29, s49
; VI-NEXT: v_mov_b32_e32 v30, s50
; VI-NEXT: v_mov_b32_e32 v31, s51
+; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -134395,7 +134395,6 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; GFX9-NEXT: s_branch .LBB81_6
; GFX9-NEXT: .LBB81_5:
; GFX9-NEXT: v_mov_b32_e32 v16, s36
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -134411,6 +134410,7 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; GFX9-NEXT: v_mov_b32_e32 v29, s49
; GFX9-NEXT: v_mov_b32_e32 v30, s50
; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -134509,7 +134509,6 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; GFX11-NEXT: s_branch .LBB81_5
; GFX11-NEXT: .LBB81_4:
; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
-; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -134517,6 +134516,7 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; GFX11-NEXT: v_dual_mov_b32 v26, s46 :: v_dual_mov_b32 v27, s47
; GFX11-NEXT: v_dual_mov_b32 v28, s48 :: v_dual_mov_b32 v29, s49
; GFX11-NEXT: v_dual_mov_b32 v30, s50 :: v_dual_mov_b32 v31, s51
+; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -137533,7 +137533,6 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; VI-NEXT: s_branch .LBB85_6
; VI-NEXT: .LBB85_5:
; VI-NEXT: v_mov_b32_e32 v16, s36
-; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -137549,6 +137548,7 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; VI-NEXT: v_mov_b32_e32 v29, s49
; VI-NEXT: v_mov_b32_e32 v30, s50
; VI-NEXT: v_mov_b32_e32 v31, s51
+; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -137648,7 +137648,6 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; GFX9-NEXT: s_branch .LBB85_6
; GFX9-NEXT: .LBB85_5:
; GFX9-NEXT: v_mov_b32_e32 v16, s36
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -137664,6 +137663,7 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v29, s49
; GFX9-NEXT: v_mov_b32_e32 v30, s50
; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -137762,7 +137762,6 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; GFX11-NEXT: s_branch .LBB85_5
; GFX11-NEXT: .LBB85_4:
; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
-; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -137770,6 +137769,7 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; GFX11-NEXT: v_dual_mov_b32 v26, s46 :: v_dual_mov_b32 v27, s47
; GFX11-NEXT: v_dual_mov_b32 v28, s48 :: v_dual_mov_b32 v29, s49
; GFX11-NEXT: v_dual_mov_b32 v30, s50 :: v_dual_mov_b32 v31, s51
+; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -154578,8 +154578,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v25
-; GFX9-NEXT: v_mov_b32_e32 v51, v16
; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX9-NEXT: v_mov_b32_e32 v51, v16
; GFX9-NEXT: v_mov_b32_e32 v50, v15
; GFX9-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
@@ -154877,9 +154877,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; GFX9-NEXT: v_cndmask_b32_e32 v14, v31, v32, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v13
-; GFX9-NEXT: v_mov_b32_e32 v34, v16
; GFX9-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_mov_b32_e32 v34, v16
; GFX9-NEXT: v_mov_b32_e32 v33, v15
; GFX9-NEXT: v_perm_b32 v16, v54, v42, s7
; GFX9-NEXT: v_perm_b32 v15, v55, v39, s7
@@ -154987,13 +154987,13 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_e32 v60, 0x400000, v48
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v48, v48
; GFX9-NEXT: v_bfe_u32 v48, v15, 16, 1
+; GFX9-NEXT: v_perm_b32 v37, v18, v20, s7
; GFX9-NEXT: v_perm_b32 v36, v8, v17, s7
+; GFX9-NEXT: v_perm_b32 v35, v7, v6, s7
; GFX9-NEXT: v_cndmask_b32_e32 v46, v47, v60, vcc
; GFX9-NEXT: v_add3_u32 v48, v48, v15, s6
; GFX9-NEXT: v_or_b32_e32 v47, 0x400000, v15
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
-; GFX9-NEXT: v_perm_b32 v37, v18, v20, s7
-; GFX9-NEXT: v_perm_b32 v35, v7, v6, s7
; GFX9-NEXT: v_cndmask_b32_e32 v15, v48, v47, vcc
; GFX9-NEXT: v_mov_b32_e32 v49, v36
; GFX9-NEXT: v_mov_b32_e32 v48, v35
@@ -155034,14 +155034,14 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v57, v10, v5, s7
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5
; GFX9-NEXT: s_waitcnt vmcnt(23)
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v39
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v20
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v62
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
@@ -179607,6 +179607,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: v_mov_b32_e32 v28, v31
; VI-NEXT: v_or_b32_e32 v38, v27, v29
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v26
; VI-NEXT: v_or_b32_e32 v34, v31, v29
@@ -179665,9 +179666,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
; VI-NEXT: v_or_b32_e32 v32, v14, v29
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: v_mov_b32_e32 v27, v30
; VI-NEXT: v_add_f16_sdwa v25, v16, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_mov_b32_e32 v28, v31
+; VI-NEXT: v_mov_b32_e32 v27, v30
; VI-NEXT: v_or_b32_e32 v31, v13, v29
; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
; VI-NEXT: v_add_f16_sdwa v42, v15, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -179718,27 +179718,27 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v33
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v39
-; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[29:30]
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v38
+; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[29:30]
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v63
-; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v62
-; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[31:32]
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v61
+; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[31:32]
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v60
-; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v55
-; VI-NEXT: v_mov_b32_e32 v31, v28
+; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v54
+; VI-NEXT: v_mov_b32_e32 v31, v28
; VI-NEXT: v_mov_b32_e32 v30, v27
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[40:41]
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
@@ -210090,8 +210090,6 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB100_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v47, v15 :: v_dual_mov_b32 v46, v14
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v48 :: v_dual_mov_b32 v17, v49
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, v13 :: v_dual_mov_b32 v44, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v43, v11 :: v_dual_mov_b32 v42, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
@@ -210099,6 +210097,8 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, v5 :: v_dual_mov_b32 v36, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, v3 :: v_dual_mov_b32 v34, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v48 :: v_dual_mov_b32 v17, v49
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v50 :: v_dual_mov_b32 v19, v51
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v52 :: v_dual_mov_b32 v21, v53
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v54 :: v_dual_mov_b32 v23, v55
@@ -211507,6 +211507,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_mov_b32_e32 v16, v37
+; SI-NEXT: v_mov_b32_e32 v46, v12
; SI-NEXT: v_mov_b32_e32 v0, v50
; SI-NEXT: v_mov_b32_e32 v5, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
@@ -211561,15 +211562,15 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v47
; SI-NEXT: v_mov_b32_e32 v47, v13
-; SI-NEXT: v_mov_b32_e32 v46, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v19
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v0, v41
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, v42
; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v5
; SI-NEXT: v_lshr_b64 v[49:50], v[31:32], 16
@@ -211607,17 +211608,18 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: v_lshr_b64 v[29:30], v[30:31], 16
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v21
; SI-NEXT: v_lshr_b64 v[31:32], v[33:34], 16
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v21
; SI-NEXT: v_mov_b32_e32 v26, v30
; SI-NEXT: v_mov_b32_e32 v27, v31
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v60
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v2
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
@@ -212350,6 +212352,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v2
+; SI-NEXT: v_mov_b32_e32 v23, v6
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -212368,6 +212371,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, v53
; SI-NEXT: v_lshr_b64 v[52:53], v[54:55], 16
+; SI-NEXT: v_mov_b32_e32 v54, v33
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -212406,7 +212410,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, v55
; SI-NEXT: v_mov_b32_e32 v55, v34
-; SI-NEXT: v_mov_b32_e32 v54, v33
; SI-NEXT: v_lshr_b64 v[34:35], v[27:28], 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
@@ -212422,7 +212425,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v24, v7
-; SI-NEXT: v_mov_b32_e32 v23, v6
; SI-NEXT: v_lshr_b64 v[6:7], v[3:4], 16
; SI-NEXT: v_mov_b32_e32 v4, v52
; SI-NEXT: v_mov_b32_e32 v8, v6
@@ -213404,7 +213406,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: s_branch .LBB101_6
; VI-NEXT: .LBB101_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -213420,6 +213421,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
+; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -214113,7 +214115,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX9-NEXT: s_branch .LBB101_6
; GFX9-NEXT: .LBB101_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
-; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -214129,6 +214130,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -214824,7 +214826,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: s_branch .LBB101_5
; GFX11-TRUE16-NEXT: .LBB101_4:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -214832,6 +214833,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -215563,7 +215565,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: s_branch .LBB101_5
; GFX11-FAKE16-NEXT: .LBB101_4:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -215571,6 +215572,7 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -218107,7 +218109,6 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; VI-NEXT: s_branch .LBB103_6
; VI-NEXT: .LBB103_5:
; VI-NEXT: v_mov_b32_e32 v16, s36
-; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -218123,6 +218124,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; VI-NEXT: v_mov_b32_e32 v29, s49
; VI-NEXT: v_mov_b32_e32 v30, s50
; VI-NEXT: v_mov_b32_e32 v31, s51
+; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -218239,7 +218241,6 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; GFX9-NEXT: s_branch .LBB103_6
; GFX9-NEXT: .LBB103_5:
; GFX9-NEXT: v_mov_b32_e32 v16, s36
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -218255,6 +218256,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; GFX9-NEXT: v_mov_b32_e32 v29, s49
; GFX9-NEXT: v_mov_b32_e32 v30, s50
; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -218369,7 +218371,6 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; GFX11-NEXT: s_branch .LBB103_5
; GFX11-NEXT: .LBB103_4:
; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
-; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -218377,6 +218378,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; GFX11-NEXT: v_dual_mov_b32 v26, s46 :: v_dual_mov_b32 v27, s47
; GFX11-NEXT: v_dual_mov_b32 v28, s48 :: v_dual_mov_b32 v29, s49
; GFX11-NEXT: v_dual_mov_b32 v30, s50 :: v_dual_mov_b32 v31, s51
+; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -222368,6 +222370,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v37, v61
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
@@ -222630,11 +222633,14 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, v46
; SI-NEXT: v_lshr_b64 v[35:36], v[35:36], 16
-; SI-NEXT: v_mov_b32_e32 v36, v60
; SI-NEXT: v_lshr_b64 v[45:46], v[45:46], 16
-; SI-NEXT: v_mov_b32_e32 v37, v61
+; SI-NEXT: v_mov_b32_e32 v36, v60
+; SI-NEXT: v_mov_b32_e32 v60, v48
+; SI-NEXT: v_mov_b32_e32 v46, v40
+; SI-NEXT: v_mov_b32_e32 v39, v31
; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v10
; SI-NEXT: v_lshr_b64 v[61:62], v[42:43], 16
+; SI-NEXT: v_mov_b32_e32 v42, v21
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -222645,13 +222651,9 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, v59
; SI-NEXT: v_lshr_b64 v[58:59], v[58:59], 16
-; SI-NEXT: v_mov_b32_e32 v60, v48
; SI-NEXT: v_mov_b32_e32 v59, v47
; SI-NEXT: v_mov_b32_e32 v47, v41
-; SI-NEXT: v_mov_b32_e32 v46, v40
; SI-NEXT: v_mov_b32_e32 v40, v32
-; SI-NEXT: v_mov_b32_e32 v39, v31
-; SI-NEXT: v_mov_b32_e32 v42, v21
; SI-NEXT: v_mov_b32_e32 v41, v20
; SI-NEXT: v_mov_b32_e32 v31, v30
; SI-NEXT: v_mov_b32_e32 v30, v29
@@ -223610,7 +223612,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: s_branch .LBB105_6
; VI-NEXT: .LBB105_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
-; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -223626,6 +223627,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
+; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -224287,7 +224289,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_branch .LBB105_6
; GFX9-NEXT: .LBB105_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
-; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -224303,6 +224304,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_mov_b32_e32 v16, s36
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -224923,7 +224925,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: s_branch .LBB105_5
; GFX11-TRUE16-NEXT: .LBB105_4:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -224931,6 +224932,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -225587,7 +225589,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: s_branch .LBB105_5
; GFX11-FAKE16-NEXT: .LBB105_4:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -225595,6 +225596,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -227716,7 +227718,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; GFX9-NEXT: s_branch .LBB107_6
; GFX9-NEXT: .LBB107_5:
; GFX9-NEXT: v_mov_b32_e32 v16, s36
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -227732,6 +227733,7 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; GFX9-NEXT: v_mov_b32_e32 v29, s49
; GFX9-NEXT: v_mov_b32_e32 v30, s50
; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -227846,7 +227848,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; GFX11-NEXT: s_branch .LBB107_5
; GFX11-NEXT: .LBB107_4:
; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
-; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -227854,6 +227855,7 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; GFX11-NEXT: v_dual_mov_b32 v26, s46 :: v_dual_mov_b32 v27, s47
; GFX11-NEXT: v_dual_mov_b32 v28, s48 :: v_dual_mov_b32 v29, s49
; GFX11-NEXT: v_dual_mov_b32 v30, s50 :: v_dual_mov_b32 v31, s51
+; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -229478,7 +229480,6 @@ define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_branch .LBB109_6
; VI-NEXT: .LBB109_5:
; VI-NEXT: v_mov_b32_e32 v16, s36
-; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v17, s37
; VI-NEXT: v_mov_b32_e32 v18, s38
; VI-NEXT: v_mov_b32_e32 v19, s39
@@ -229494,6 +229495,7 @@ define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_mov_b32_e32 v29, s49
; VI-NEXT: v_mov_b32_e32 v30, s50
; VI-NEXT: v_mov_b32_e32 v31, s51
+; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
@@ -229610,7 +229612,6 @@ define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: s_branch .LBB109_6
; GFX9-NEXT: .LBB109_5:
; GFX9-NEXT: v_mov_b32_e32 v16, s36
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -229626,6 +229627,7 @@ define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_mov_b32_e32 v29, s49
; GFX9-NEXT: v_mov_b32_e32 v30, s50
; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -229740,7 +229742,6 @@ define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: s_branch .LBB109_5
; GFX11-NEXT: .LBB109_4:
; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
-; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -229748,6 +229749,7 @@ define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: v_dual_mov_b32 v26, s46 :: v_dual_mov_b32 v27, s47
; GFX11-NEXT: v_dual_mov_b32 v28, s48 :: v_dual_mov_b32 v29, s49
; GFX11-NEXT: v_dual_mov_b32 v30, s50 :: v_dual_mov_b32 v31, s51
+; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
@@ -232114,7 +232116,6 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; GFX9-NEXT: s_branch .LBB111_6
; GFX9-NEXT: .LBB111_5:
; GFX9-NEXT: v_mov_b32_e32 v16, s36
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v17, s37
; GFX9-NEXT: v_mov_b32_e32 v18, s38
; GFX9-NEXT: v_mov_b32_e32 v19, s39
@@ -232130,6 +232131,7 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; GFX9-NEXT: v_mov_b32_e32 v29, s49
; GFX9-NEXT: v_mov_b32_e32 v30, s50
; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
@@ -232244,7 +232246,6 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; GFX11-NEXT: s_branch .LBB111_5
; GFX11-NEXT: .LBB111_4:
; GFX11-NEXT: v_dual_mov_b32 v16, s36 :: v_dual_mov_b32 v17, s37
-; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v18, s38 :: v_dual_mov_b32 v19, s39
; GFX11-NEXT: v_dual_mov_b32 v20, s40 :: v_dual_mov_b32 v21, s41
; GFX11-NEXT: v_dual_mov_b32 v22, s42 :: v_dual_mov_b32 v23, s43
@@ -232252,6 +232253,7 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; GFX11-NEXT: v_dual_mov_b32 v26, s46 :: v_dual_mov_b32 v27, s47
; GFX11-NEXT: v_dual_mov_b32 v28, s48 :: v_dual_mov_b32 v29, s49
; GFX11-NEXT: v_dual_mov_b32 v30, s50 :: v_dual_mov_b32 v31, s51
+; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index b3a0edef24ed4..076dca8504fea 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -75360,19 +75360,19 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v47
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v41
; SI-NEXT: v_mov_b32_e32 v29, v20
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v0
; SI-NEXT: v_lshr_b64 v[2:3], v[34:35], 16
-; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
-; SI-NEXT: v_mov_b32_e32 v31, v2
; SI-NEXT: v_mov_b32_e32 v30, v1
+; SI-NEXT: v_mov_b32_e32 v31, v2
; SI-NEXT: v_lshr_b64 v[1:2], v[60:61], 16
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
; SI-NEXT: v_lshr_b64 v[9:10], v[0:1], 16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v2
@@ -75381,6 +75381,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: v_lshr_b64 v[57:58], v[48:49], 16
; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v12
+; SI-NEXT: v_mov_b32_e32 v61, v49
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
@@ -75399,18 +75400,19 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; SI-NEXT: v_mov_b32_e32 v6, v43
; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v28
; SI-NEXT: v_mov_b32_e32 v16, v12
-; SI-NEXT: v_mov_b32_e32 v61, v49
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshr_b64 v[4:5], v[23:24], 16
+; SI-NEXT: v_mov_b32_e32 v23, v18
; SI-NEXT: v_mov_b32_e32 v60, v48
; SI-NEXT: v_mov_b32_e32 v49, v39
; SI-NEXT: v_mov_b32_e32 v48, v38
; SI-NEXT: v_mov_b32_e32 v39, v37
; SI-NEXT: v_mov_b32_e32 v38, v36
; SI-NEXT: v_lshr_b64 v[36:37], v[30:31], 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshr_b64 v[4:5], v[23:24], 16
; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16
; SI-NEXT: v_lshr_b64 v[12:13], v[26:27], 16
+; SI-NEXT: v_mov_b32_e32 v37, v39
; SI-NEXT: v_mov_b32_e32 v30, v40
; SI-NEXT: v_mov_b32_e32 v40, v17
; SI-NEXT: v_mov_b32_e32 v5, v32
@@ -75424,14 +75426,13 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v2, v51
; SI-NEXT: v_mov_b32_e32 v24, v19
-; SI-NEXT: v_mov_b32_e32 v23, v18
; SI-NEXT: v_lshr_b64 v[19:20], v[50:51], 16
; SI-NEXT: v_lshr_b64 v[50:51], v[58:59], 16
; SI-NEXT: v_lshr_b64 v[51:52], v[14:15], 16
; SI-NEXT: v_lshr_b64 v[13:14], v[62:63], 16
-; SI-NEXT: v_mov_b32_e32 v17, v53
; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v17, v53
; SI-NEXT: v_mov_b32_e32 v18, v54
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v14, v55
@@ -75467,18 +75468,17 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshr_b64 v[2:3], v[23:24], 16
-; SI-NEXT: v_mov_b32_e32 v24, v36
-; SI-NEXT: v_mov_b32_e32 v36, v38
-; SI-NEXT: v_mov_b32_e32 v37, v39
-; SI-NEXT: v_mov_b32_e32 v38, v48
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v39, v49
-; SI-NEXT: v_mov_b32_e32 v48, v60
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v2, v62
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v24, v36
+; SI-NEXT: v_mov_b32_e32 v36, v38
+; SI-NEXT: v_mov_b32_e32 v38, v48
+; SI-NEXT: v_mov_b32_e32 v39, v49
+; SI-NEXT: v_mov_b32_e32 v48, v60
; SI-NEXT: v_mov_b32_e32 v49, v61
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index 0f285bb2020bf..718a24f545202 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -11944,9 +11944,8 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v5, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
index 7e9f825e298c7..40c960343fafe 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
@@ -55,10 +55,10 @@ define amdgpu_kernel void @bitcast_i8ptr_v16i8ptr(ptr addrspace(1) %out, ptr add
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
index 2ff4accf2719f..8e518ea411cf6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
@@ -54,9 +54,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr,
; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, s1
; GISEL-GFX10-NEXT: v_mov_b32_e32 v2, s2
; GISEL-GFX10-NEXT: v_mov_b32_e32 v3, s3
-; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-GFX10-NEXT: s_mov_b32 s4, use at abs32@lo
; GISEL-GFX10-NEXT: s_mov_b32 s5, use at abs32@hi
+; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51]
; GISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-GFX10-NEXT: s_endpgm
@@ -85,9 +85,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr,
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v1, s1
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v2, s2
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v3, s3
-; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; DAGISEL-GFX10-NEXT: s_mov_b32 s5, use at abs32@hi
; DAGISEL-GFX10-NEXT: s_mov_b32 s4, use at abs32@lo
+; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; DAGISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51]
; DAGISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; DAGISEL-GFX10-NEXT: s_endpgm
@@ -215,9 +215,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24
; GISEL-GFX10-NEXT: v_mov_b32_e32 v29, v37
; GISEL-GFX10-NEXT: v_mov_b32_e32 v30, v38
; GISEL-GFX10-NEXT: v_mov_b32_e32 v31, v39
-; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-GFX10-NEXT: s_mov_b32 s24, use at abs32@lo
; GISEL-GFX10-NEXT: s_mov_b32 s25, use at abs32@hi
+; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51]
; GISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[24:25]
; GISEL-GFX10-NEXT: s_endpgm
@@ -341,9 +341,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v29, v34
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v30, v33
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v31, v32
-; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; DAGISEL-GFX10-NEXT: s_mov_b32 s25, use at abs32@hi
; DAGISEL-GFX10-NEXT: s_mov_b32 s24, use at abs32@lo
+; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; DAGISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51]
; DAGISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[24:25]
; DAGISEL-GFX10-NEXT: s_endpgm
@@ -370,9 +370,9 @@ define amdgpu_cs_chain void @alloca_and_call() #0 {
; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 42
; GISEL-GFX10-NEXT: s_mov_b32 s33, s32
-; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-GFX10-NEXT: s_mov_b32 s4, use at abs32@lo
; GISEL-GFX10-NEXT: s_mov_b32 s5, use at abs32@hi
+; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-GFX10-NEXT: buffer_store_dword v0, off, s[48:51], s33
; GISEL-GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
; GISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51]
@@ -398,9 +398,9 @@ define amdgpu_cs_chain void @alloca_and_call() #0 {
; DAGISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v0, 42
; DAGISEL-GFX10-NEXT: s_mov_b32 s33, s32
-; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; DAGISEL-GFX10-NEXT: s_mov_b32 s5, use at abs32@hi
; DAGISEL-GFX10-NEXT: s_mov_b32 s4, use at abs32@lo
+; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49]
; DAGISEL-GFX10-NEXT: buffer_store_dword v0, off, s[48:51], s33
; DAGISEL-GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
; DAGISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51]
@@ -449,10 +449,10 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) #0 {
; GISEL-GFX10-NEXT: ;;#ASMSTART
; GISEL-GFX10-NEXT: s_nop
; GISEL-GFX10-NEXT: ;;#ASMEND
-; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; GISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3
-; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
+; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; GISEL-GFX10-NEXT: s_mov_b32 s0, s3
+; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
; GISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
; GISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
; GISEL-GFX10-NEXT: s_setpc_b64 s[4:5]
@@ -491,10 +491,10 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) #0 {
; DAGISEL-GFX10-NEXT: ;;#ASMSTART
; DAGISEL-GFX10-NEXT: s_nop
; DAGISEL-GFX10-NEXT: ;;#ASMEND
-; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3
-; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
+; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; DAGISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
+; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
; DAGISEL-GFX10-NEXT: s_mov_b32 s0, s3
; DAGISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
; DAGISEL-GFX10-NEXT: s_setpc_b64 s[4:5]
@@ -534,10 +534,10 @@ define amdgpu_cs void @cs_to_chain_nonuniform(<3 x i32> %a, <3 x i32> %b) #0 {
; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-GFX10-NEXT: s_bitset0_b32 s103, 21
; GISEL-GFX10-NEXT: s_add_u32 s100, s100, s0
-; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; GISEL-GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
+; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; GISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
+; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
; GISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
; GISEL-GFX10-NEXT: s_setpc_b64 s[4:5]
;
@@ -570,10 +570,10 @@ define amdgpu_cs void @cs_to_chain_nonuniform(<3 x i32> %a, <3 x i32> %b) #0 {
; DAGISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
; DAGISEL-GFX10-NEXT: s_bitset0_b32 s103, 21
; DAGISEL-GFX10-NEXT: s_add_u32 s100, s100, s0
-; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; DAGISEL-GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
+; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; DAGISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
+; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
; DAGISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
; DAGISEL-GFX10-NEXT: s_setpc_b64 s[4:5]
call void(ptr, i32, <3 x i32>, <3 x i32>, i32, ...) @llvm.amdgcn.cs.chain.v3i32(ptr @chain_callee, i32 -1, <3 x i32> inreg %a, <3 x i32> %b, i32 0)
@@ -940,14 +940,15 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_dont_realign_stack(i32 %idx) #0 {
; GISEL-GFX11-NEXT: s_mov_b32 s2, 3
; GISEL-GFX11-NEXT: s_mov_b32 s1, 2
; GISEL-GFX11-NEXT: s_mov_b32 s0, 1
-; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v8
+; GISEL-GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v0, 4, v8
; GISEL-GFX11-NEXT: s_add_i32 s33, s32, 31
-; GISEL-GFX11-NEXT: s_mov_b32 s34, s32
+; GISEL-GFX11-NEXT: v_mov_b32_e32 v2, s2
; GISEL-GFX11-NEXT: s_and_not1_b32 s33, s33, 31
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GISEL-GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_add_nc_u32 v4, s33, v0
+; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX11-NEXT: s_mov_b32 s34, s32
; GISEL-GFX11-NEXT: s_addk_i32 s32, 0xc0
-; GISEL-GFX11-NEXT: v_add_nc_u32_e32 v4, s33, v0
-; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GISEL-GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX11-NEXT: scratch_store_b128 v4, v[0:3], off dlc
; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX11-NEXT: s_endpgm
@@ -1029,9 +1030,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_realign_stack_chain_call(i32 %idx,
; GISEL-GFX11-NEXT: s_mov_b32 s6, 3
; GISEL-GFX11-NEXT: s_mov_b32 s5, 2
; GISEL-GFX11-NEXT: s_mov_b32 s4, 1
-; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v4, 4, v8
+; GISEL-GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_lshlrev_b32 v4, 4, v8
; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GISEL-GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GISEL-GFX11-NEXT: v_mov_b32_e32 v2, s6
; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GISEL-GFX11-NEXT: v_add_nc_u32_e32 v4, s33, v4
; GISEL-GFX11-NEXT: s_addk_i32 s32, 0xc0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
index a0b70444be51b..d20277a8da6c3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
@@ -62,10 +62,10 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %a, <3 x i32> %b) #0
; GISEL-GFX10-NEXT: ;;#ASMSTART
; GISEL-GFX10-NEXT: s_nop
; GISEL-GFX10-NEXT: ;;#ASMEND
-; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; GISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3
-; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
+; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; GISEL-GFX10-NEXT: s_mov_b32 s0, s3
+; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
; GISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
; GISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
; GISEL-GFX10-NEXT: s_setpc_b64 s[4:5]
@@ -104,10 +104,10 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %a, <3 x i32> %b) #0
; DAGISEL-GFX10-NEXT: ;;#ASMSTART
; DAGISEL-GFX10-NEXT: s_nop
; DAGISEL-GFX10-NEXT: ;;#ASMEND
-; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3
-; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
+; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0
; DAGISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103]
+; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101]
; DAGISEL-GFX10-NEXT: s_mov_b32 s0, s3
; DAGISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1
; DAGISEL-GFX10-NEXT: s_setpc_b64 s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/and.ll b/llvm/test/CodeGen/AMDGPU/and.ll
index fe9ec8e6ef52a..25124c88d490c 100644
--- a/llvm/test/CodeGen/AMDGPU/and.ll
+++ b/llvm/test/CodeGen/AMDGPU/and.ll
@@ -651,8 +651,8 @@ define amdgpu_kernel void @s_and_multi_use_constant_i64(ptr addrspace(1) %out, i
; GFX6-NEXT: s_mov_b32 s0, 0x80000
; GFX6-NEXT: s_movk_i32 s1, 0x80
; GFX6-NEXT: s_and_b64 s[2:3], s[2:3], s[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
@@ -674,8 +674,8 @@ define amdgpu_kernel void @s_and_multi_use_constant_i64(ptr addrspace(1) %out, i
; GFX8-NEXT: s_mov_b32 s0, 0x80000
; GFX8-NEXT: s_movk_i32 s1, 0x80
; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -738,10 +738,10 @@ define amdgpu_kernel void @s_and_multi_use_inline_imm_i64(ptr addrspace(1) %out,
; GFX6-NEXT: s_and_b32 s8, s7, 62
; GFX6-NEXT: s_add_u32 s6, s6, s4
; GFX6-NEXT: s_addc_u32 s7, 0, s5
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: s_add_u32 s4, s8, s4
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: s_addc_u32 s5, 0, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4
@@ -765,10 +765,10 @@ define amdgpu_kernel void @s_and_multi_use_inline_imm_i64(ptr addrspace(1) %out,
; GFX8-NEXT: s_and_b32 s8, s7, 62
; GFX8-NEXT: s_add_u32 s6, s6, s4
; GFX8-NEXT: s_addc_u32 s7, 0, s5
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_add_u32 s4, s8, s4
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_addc_u32 s5, 0, s5
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s4
diff --git a/llvm/test/CodeGen/AMDGPU/andorn2.ll b/llvm/test/CodeGen/AMDGPU/andorn2.ll
index c9ad669ad5b20..1ddbbd8c9407f 100644
--- a/llvm/test/CodeGen/AMDGPU/andorn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/andorn2.ll
@@ -130,8 +130,9 @@ define amdgpu_kernel void @scalar_andn2_i64_one_use(ptr addrspace(1) %r0, i64 %a
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[4:5]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -266,8 +267,9 @@ define amdgpu_kernel void @scalar_orn2_i64_one_use(ptr addrspace(1) %r0, i64 %a,
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_or_not1_b64 s[2:3], s[2:3], s[4:5]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -827,9 +829,9 @@ define amdgpu_kernel void @vector_andn2_v2i32_s_v_one_use(ptr addrspace(1) %r0,
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_bfi_b32 v1, v1, 0, s3
; GFX8-NEXT: v_bfi_b32 v0, v0, 0, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -896,9 +898,9 @@ define amdgpu_kernel void @vector_andn2_v2i32_v_s_one_use(ptr addrspace(1) %r0,
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_bfi_b32 v1, s3, 0, v1
; GFX8-NEXT: v_bfi_b32 v0, s2, 0, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -970,8 +972,8 @@ define amdgpu_kernel void @vector_andn2_v2i32_s_s_one_use(ptr addrspace(1) %r0,
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm
@@ -995,8 +997,9 @@ define amdgpu_kernel void @vector_andn2_v2i32_s_s_one_use(ptr addrspace(1) %r0,
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX12-NEXT: s_endpgm
entry:
@@ -1264,9 +1267,9 @@ define amdgpu_kernel void @vector_orn2_v2i32_s_v_one_use(ptr addrspace(1) %r0, <
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_bfi_b32 v1, v1, s3, -1
; GFX8-NEXT: v_bfi_b32 v0, v0, s2, -1
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -1333,9 +1336,9 @@ define amdgpu_kernel void @vector_orn2_v2i32_v_s_one_use(ptr addrspace(1) %r0, <
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_bfi_b32 v1, s3, v1, -1
; GFX8-NEXT: v_bfi_b32 v0, s2, v0, -1
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -1407,8 +1410,8 @@ define amdgpu_kernel void @vector_orn2_v2i32_s_s_one_use(ptr addrspace(1) %r0, <
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_orn2_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm
@@ -1432,8 +1435,9 @@ define amdgpu_kernel void @vector_orn2_v2i32_s_s_one_use(ptr addrspace(1) %r0, <
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_or_not1_b64 s[0:1], s[0:1], s[2:3]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX12-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
index aa161a8093532..7d3d2c291a612 100644
--- a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
@@ -66,80 +66,80 @@ define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(ptr addrspace(
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 15
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 14
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 8
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 11
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 10
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 4
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 6
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 1
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 3
; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s10
; GFX8-NEXT: v_mov_b32_e32 v1, s11
-; GFX8-NEXT: s_add_u32 s4, s10, 3
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s10, 9
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NEXT: s_add_u32 s4, s10, 2
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NEXT: s_add_u32 s0, s10, 5
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s1
-; GFX8-NEXT: s_add_u32 s0, s10, 5
-; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s1, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: s_add_u32 s0, s10, 12
-; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: s_addc_u32 s1, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NEXT: s_add_u32 s0, s10, 7
-; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NEXT: s_addc_u32 s1, s11, 0
+; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s6
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 12548e219125e..75699d12c3669 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -2758,12 +2758,12 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB5_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s6
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 s11, 0xf000
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 s10, -1
; GFX7LESS_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 s8, s2
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 s9, s3
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s6
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s7
; GFX7LESS_ITERATIVE-NEXT: buffer_atomic_add_x2 v[3:4], off, s[8:11], 0 glc
; GFX7LESS_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
@@ -2811,12 +2811,12 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB5_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s6
; GFX8_ITERATIVE-NEXT: s_mov_b32 s11, 0xf000
; GFX8_ITERATIVE-NEXT: s_mov_b32 s10, -1
; GFX8_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_ITERATIVE-NEXT: s_mov_b32 s8, s2
; GFX8_ITERATIVE-NEXT: s_mov_b32 s9, s3
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s6
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s7
; GFX8_ITERATIVE-NEXT: buffer_atomic_add_x2 v[3:4], off, s[8:11], 0 glc
; GFX8_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
@@ -2863,12 +2863,12 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB5_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s6
; GFX9_ITERATIVE-NEXT: s_mov_b32 s11, 0xf000
; GFX9_ITERATIVE-NEXT: s_mov_b32 s10, -1
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_ITERATIVE-NEXT: s_mov_b32 s8, s2
; GFX9_ITERATIVE-NEXT: s_mov_b32 s9, s3
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s6
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s7
; GFX9_ITERATIVE-NEXT: buffer_atomic_add_x2 v[3:4], off, s[8:11], 0 glc
; GFX9_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
@@ -3283,12 +3283,12 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX8_DPP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8_DPP-NEXT: s_cbranch_execz .LBB5_2
; GFX8_DPP-NEXT: ; %bb.1:
-; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s6
; GFX8_DPP-NEXT: s_mov_b32 s11, 0xf000
; GFX8_DPP-NEXT: s_mov_b32 s10, -1
; GFX8_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX8_DPP-NEXT: s_mov_b32 s8, s2
; GFX8_DPP-NEXT: s_mov_b32 s9, s3
+; GFX8_DPP-NEXT: v_mov_b32_e32 v6, s6
; GFX8_DPP-NEXT: v_mov_b32_e32 v7, s7
; GFX8_DPP-NEXT: buffer_atomic_add_x2 v[6:7], off, s[8:11], 0 glc
; GFX8_DPP-NEXT: s_waitcnt vmcnt(0)
@@ -3366,12 +3366,12 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX9_DPP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9_DPP-NEXT: s_cbranch_execz .LBB5_2
; GFX9_DPP-NEXT: ; %bb.1:
-; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s6
; GFX9_DPP-NEXT: s_mov_b32 s11, 0xf000
; GFX9_DPP-NEXT: s_mov_b32 s10, -1
; GFX9_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX9_DPP-NEXT: s_mov_b32 s8, s2
; GFX9_DPP-NEXT: s_mov_b32 s9, s3
+; GFX9_DPP-NEXT: v_mov_b32_e32 v6, s6
; GFX9_DPP-NEXT: v_mov_b32_e32 v7, s7
; GFX9_DPP-NEXT: buffer_atomic_add_x2 v[6:7], off, s[8:11], 0 glc
; GFX9_DPP-NEXT: s_waitcnt vmcnt(0)
@@ -4352,8 +4352,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: v_mov_b32_e32 v4, v0
; GFX1064-NEXT: v_subrev_nc_u32_e32 v3, s12, v4
-; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_mov_b32_e32 v1, v4
+; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl1_inv
@@ -4400,8 +4400,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1032-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1032-NEXT: v_mov_b32_e32 v4, v0
; GFX1032-NEXT: v_subrev_nc_u32_e32 v3, s10, v4
-; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_mov_b32_e32 v1, v4
+; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl1_inv
@@ -4451,9 +4451,9 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-NEXT: v_mov_b32_e32 v4, v0
; GFX1164-NEXT: v_subrev_nc_u32_e32 v3, s12, v4
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164-NEXT: v_mov_b32_e32 v0, v3
; GFX1164-NEXT: v_mov_b32_e32 v1, v4
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-NEXT: v_mov_b32_e32 v0, v3
; GFX1164-NEXT: buffer_atomic_cmpswap_b32 v[0:1], off, s[4:7], 0 glc
; GFX1164-NEXT: s_waitcnt vmcnt(0)
; GFX1164-NEXT: buffer_gl1_inv
@@ -4505,7 +4505,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1132-NEXT: v_mov_b32_e32 v4, v0
; GFX1132-NEXT: v_subrev_nc_u32_e32 v3, s10, v4
; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX1132-NEXT: v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v0, v3
; GFX1132-NEXT: buffer_atomic_cmpswap_b32 v[0:1], off, s[4:7], 0 glc
; GFX1132-NEXT: s_waitcnt vmcnt(0)
; GFX1132-NEXT: buffer_gl1_inv
@@ -4857,8 +4857,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: v_mov_b32_e32 v4, v0
; GFX1064-NEXT: v_subrev_nc_u32_e32 v3, s13, v4
-; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: v_mov_b32_e32 v1, v4
+; GFX1064-NEXT: v_mov_b32_e32 v0, v3
; GFX1064-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl1_inv
@@ -4907,8 +4907,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1032-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1032-NEXT: v_mov_b32_e32 v4, v0
; GFX1032-NEXT: v_subrev_nc_u32_e32 v3, s11, v4
-; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: v_mov_b32_e32 v1, v4
+; GFX1032-NEXT: v_mov_b32_e32 v0, v3
; GFX1032-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl1_inv
@@ -4960,9 +4960,9 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-NEXT: v_mov_b32_e32 v4, v0
; GFX1164-NEXT: v_subrev_nc_u32_e32 v3, s13, v4
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164-NEXT: v_mov_b32_e32 v0, v3
; GFX1164-NEXT: v_mov_b32_e32 v1, v4
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-NEXT: v_mov_b32_e32 v0, v3
; GFX1164-NEXT: buffer_atomic_cmpswap_b32 v[0:1], off, s[4:7], 0 glc
; GFX1164-NEXT: s_waitcnt vmcnt(0)
; GFX1164-NEXT: buffer_gl1_inv
@@ -5016,7 +5016,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1132-NEXT: v_mov_b32_e32 v4, v0
; GFX1132-NEXT: v_subrev_nc_u32_e32 v3, s11, v4
; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX1132-NEXT: v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v0, v3
; GFX1132-NEXT: buffer_atomic_cmpswap_b32 v[0:1], off, s[4:7], 0 glc
; GFX1132-NEXT: s_waitcnt vmcnt(0)
; GFX1132-NEXT: buffer_gl1_inv
@@ -5416,8 +5416,8 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1064_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, v0
; GFX1064_ITERATIVE-NEXT: v_subrev_nc_u32_e32 v3, s12, v4
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, v3
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v1, v4
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, v3
; GFX1064_ITERATIVE-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; GFX1064_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl1_inv
@@ -5474,8 +5474,8 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1032_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, v0
; GFX1032_ITERATIVE-NEXT: v_subrev_nc_u32_e32 v3, s8, v4
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, v3
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v1, v4
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, v3
; GFX1032_ITERATIVE-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; GFX1032_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl1_inv
@@ -5538,9 +5538,9 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, v0
; GFX1164_ITERATIVE-NEXT: v_subrev_nc_u32_e32 v3, s12, v4
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v0, v3
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v1, v4
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v0, v3
; GFX1164_ITERATIVE-NEXT: buffer_atomic_cmpswap_b32 v[0:1], off, s[4:7], 0 glc
; GFX1164_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1164_ITERATIVE-NEXT: buffer_gl1_inv
@@ -5604,7 +5604,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1132_ITERATIVE-NEXT: v_mov_b32_e32 v4, v0
; GFX1132_ITERATIVE-NEXT: v_subrev_nc_u32_e32 v3, s8, v4
; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v0, v3
; GFX1132_ITERATIVE-NEXT: buffer_atomic_cmpswap_b32 v[0:1], off, s[4:7], 0 glc
; GFX1132_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1132_ITERATIVE-NEXT: buffer_gl1_inv
@@ -6469,8 +6469,8 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX7LESS-NEXT: s_mov_b32 s5, s3
; GFX7LESS-NEXT: .LBB9_2: ; %atomicrmw.start
; GFX7LESS-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX7LESS-NEXT: v_mov_b32_e32 v8, v1
; GFX7LESS-NEXT: v_mov_b32_e32 v7, v0
+; GFX7LESS-NEXT: v_mov_b32_e32 v8, v1
; GFX7LESS-NEXT: v_subrev_i32_e32 v5, vcc, s12, v7
; GFX7LESS-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v8, vcc
; GFX7LESS-NEXT: s_waitcnt expcnt(0)
@@ -6528,8 +6528,8 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX8-NEXT: s_mov_b32 s5, s3
; GFX8-NEXT: .LBB9_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_mov_b32_e32 v7, v0
+; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s12, v7
; GFX8-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v8, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, v5
@@ -6585,8 +6585,8 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: .LBB9_2: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
+; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s12, v7
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v8, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, v5
@@ -6642,14 +6642,14 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1064-NEXT: s_mov_b32 s5, s3
; GFX1064-NEXT: .LBB9_2: ; %atomicrmw.start
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1064-NEXT: v_mov_b32_e32 v8, v1
; GFX1064-NEXT: v_mov_b32_e32 v7, v0
+; GFX1064-NEXT: v_mov_b32_e32 v8, v1
; GFX1064-NEXT: v_sub_co_u32 v5, vcc, v7, s12
; GFX1064-NEXT: v_subrev_co_ci_u32_e32 v6, vcc, 0, v8, vcc
-; GFX1064-NEXT: v_mov_b32_e32 v0, v5
; GFX1064-NEXT: v_mov_b32_e32 v2, v7
-; GFX1064-NEXT: v_mov_b32_e32 v1, v6
+; GFX1064-NEXT: v_mov_b32_e32 v0, v5
; GFX1064-NEXT: v_mov_b32_e32 v3, v8
+; GFX1064-NEXT: v_mov_b32_e32 v1, v6
; GFX1064-NEXT: buffer_atomic_cmpswap_x2 v[0:3], off, s[4:7], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl1_inv
@@ -6698,14 +6698,14 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1032-NEXT: s_mov_b32 s5, s3
; GFX1032-NEXT: .LBB9_2: ; %atomicrmw.start
; GFX1032-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1032-NEXT: v_mov_b32_e32 v8, v1
; GFX1032-NEXT: v_mov_b32_e32 v7, v0
+; GFX1032-NEXT: v_mov_b32_e32 v8, v1
; GFX1032-NEXT: v_sub_co_u32 v5, vcc_lo, v7, s10
; GFX1032-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v8, vcc_lo
-; GFX1032-NEXT: v_mov_b32_e32 v0, v5
; GFX1032-NEXT: v_mov_b32_e32 v2, v7
-; GFX1032-NEXT: v_mov_b32_e32 v1, v6
+; GFX1032-NEXT: v_mov_b32_e32 v0, v5
; GFX1032-NEXT: v_mov_b32_e32 v3, v8
+; GFX1032-NEXT: v_mov_b32_e32 v1, v6
; GFX1032-NEXT: buffer_atomic_cmpswap_x2 v[0:3], off, s[4:7], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl1_inv
@@ -6756,16 +6756,16 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1164-NEXT: s_mov_b32 s5, s3
; GFX1164-NEXT: .LBB9_2: ; %atomicrmw.start
; GFX1164-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1164-NEXT: v_mov_b32_e32 v8, v1
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-NEXT: v_mov_b32_e32 v7, v0
+; GFX1164-NEXT: v_mov_b32_e32 v8, v1
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-NEXT: v_sub_co_u32 v5, vcc, v7, s12
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-NEXT: v_subrev_co_ci_u32_e64 v6, null, 0, v8, vcc
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1164-NEXT: v_mov_b32_e32 v0, v5
; GFX1164-NEXT: v_mov_b32_e32 v2, v7
; GFX1164-NEXT: v_mov_b32_e32 v3, v8
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1164-NEXT: v_mov_b32_e32 v1, v6
; GFX1164-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1164-NEXT: s_waitcnt vmcnt(0)
@@ -6822,12 +6822,10 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
; GFX1132-NEXT: v_sub_co_u32 v5, vcc_lo, v7, s10
-; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1132-NEXT: v_subrev_co_ci_u32_e64 v6, null, 0, v8, vcc_lo
-; GFX1132-NEXT: v_mov_b32_e32 v0, v5
; GFX1132-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
-; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-NEXT: v_mov_b32_e32 v1, v6
+; GFX1132-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
; GFX1132-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1132-NEXT: s_waitcnt vmcnt(0)
; GFX1132-NEXT: buffer_gl1_inv
@@ -7042,9 +7040,9 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX7LESS-NEXT: s_mul_i32 s6, s8, s6
; GFX7LESS-NEXT: v_mov_b32_e32 v6, s6
; GFX7LESS-NEXT: v_add_i32_e32 v5, vcc, s7, v0
+; GFX7LESS-NEXT: s_mov_b64 s[12:13], 0
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s4
-; GFX7LESS-NEXT: s_mov_b64 s[12:13], 0
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s5
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
; GFX7LESS-NEXT: s_mov_b32 s6, -1
@@ -7052,8 +7050,8 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX7LESS-NEXT: s_mov_b32 s5, s3
; GFX7LESS-NEXT: .LBB10_2: ; %atomicrmw.start
; GFX7LESS-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX7LESS-NEXT: v_mov_b32_e32 v10, v1
; GFX7LESS-NEXT: v_mov_b32_e32 v9, v0
+; GFX7LESS-NEXT: v_mov_b32_e32 v10, v1
; GFX7LESS-NEXT: v_sub_i32_e32 v7, vcc, v9, v6
; GFX7LESS-NEXT: v_subb_u32_e32 v8, vcc, v10, v5, vcc
; GFX7LESS-NEXT: s_waitcnt expcnt(0)
@@ -7116,8 +7114,8 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX8-NEXT: s_mov_b32 s5, s3
; GFX8-NEXT: .LBB10_2: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT: v_mov_b32_e32 v10, v1
; GFX8-NEXT: v_mov_b32_e32 v9, v0
+; GFX8-NEXT: v_mov_b32_e32 v10, v1
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, v9, v4
; GFX8-NEXT: v_subb_u32_e32 v8, vcc, v10, v5, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, v7
@@ -7167,10 +7165,10 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX9-NEXT: s_mul_i32 s7, s9, s6
; GFX9-NEXT: s_mul_hi_u32 s12, s8, s6
; GFX9-NEXT: s_add_i32 s7, s12, s7
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_mul_i32 s14, s8, s6
; GFX9-NEXT: s_mov_b64 s[12:13], 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v5, s7
; GFX9-NEXT: s_mov_b32 s7, 0xf000
@@ -7179,8 +7177,8 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: .LBB10_2: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v0
+; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s14, v8
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v9, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, v6
@@ -7241,14 +7239,14 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1064-NEXT: s_mov_b32 s5, s3
; GFX1064-NEXT: .LBB10_2: ; %atomicrmw.start
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1064-NEXT: v_mov_b32_e32 v8, v1
; GFX1064-NEXT: v_mov_b32_e32 v7, v0
+; GFX1064-NEXT: v_mov_b32_e32 v8, v1
; GFX1064-NEXT: v_sub_co_u32 v5, vcc, v7, s14
; GFX1064-NEXT: v_subrev_co_ci_u32_e32 v6, vcc, s15, v8, vcc
-; GFX1064-NEXT: v_mov_b32_e32 v0, v5
; GFX1064-NEXT: v_mov_b32_e32 v2, v7
-; GFX1064-NEXT: v_mov_b32_e32 v1, v6
+; GFX1064-NEXT: v_mov_b32_e32 v0, v5
; GFX1064-NEXT: v_mov_b32_e32 v3, v8
+; GFX1064-NEXT: v_mov_b32_e32 v1, v6
; GFX1064-NEXT: buffer_atomic_cmpswap_x2 v[0:3], off, s[4:7], 0 glc
; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: buffer_gl1_inv
@@ -7302,14 +7300,14 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1032-NEXT: s_mov_b32 s5, s3
; GFX1032-NEXT: .LBB10_2: ; %atomicrmw.start
; GFX1032-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1032-NEXT: v_mov_b32_e32 v8, v1
; GFX1032-NEXT: v_mov_b32_e32 v7, v0
+; GFX1032-NEXT: v_mov_b32_e32 v8, v1
; GFX1032-NEXT: v_sub_co_u32 v5, vcc_lo, v7, s12
; GFX1032-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s13, v8, vcc_lo
-; GFX1032-NEXT: v_mov_b32_e32 v0, v5
; GFX1032-NEXT: v_mov_b32_e32 v2, v7
-; GFX1032-NEXT: v_mov_b32_e32 v1, v6
+; GFX1032-NEXT: v_mov_b32_e32 v0, v5
; GFX1032-NEXT: v_mov_b32_e32 v3, v8
+; GFX1032-NEXT: v_mov_b32_e32 v1, v6
; GFX1032-NEXT: buffer_atomic_cmpswap_x2 v[0:3], off, s[4:7], 0 glc
; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: buffer_gl1_inv
@@ -7365,16 +7363,16 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1164-NEXT: s_mov_b32 s5, s3
; GFX1164-NEXT: .LBB10_2: ; %atomicrmw.start
; GFX1164-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1164-NEXT: v_mov_b32_e32 v8, v1
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-NEXT: v_mov_b32_e32 v7, v0
+; GFX1164-NEXT: v_mov_b32_e32 v8, v1
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-NEXT: v_sub_co_u32 v5, vcc, v7, s14
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-NEXT: v_subrev_co_ci_u32_e64 v6, null, s15, v8, vcc
+; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1164-NEXT: v_mov_b32_e32 v0, v5
; GFX1164-NEXT: v_mov_b32_e32 v2, v7
; GFX1164-NEXT: v_mov_b32_e32 v3, v8
-; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1164-NEXT: v_mov_b32_e32 v1, v6
; GFX1164-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1164-NEXT: s_waitcnt vmcnt(0)
@@ -7437,12 +7435,10 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
; GFX1132-NEXT: v_sub_co_u32 v5, vcc_lo, v7, s12
-; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1132-NEXT: v_subrev_co_ci_u32_e64 v6, null, s13, v8, vcc_lo
-; GFX1132-NEXT: v_mov_b32_e32 v0, v5
; GFX1132-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
-; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132-NEXT: v_mov_b32_e32 v1, v6
+; GFX1132-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
; GFX1132-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1132-NEXT: s_waitcnt vmcnt(0)
; GFX1132-NEXT: buffer_gl1_inv
@@ -7693,8 +7689,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 s5, s3
; GFX7LESS_ITERATIVE-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX7LESS_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v10, v1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v9, v0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v10, v1
; GFX7LESS_ITERATIVE-NEXT: v_subrev_i32_e32 v7, vcc, s8, v9
; GFX7LESS_ITERATIVE-NEXT: v_subb_u32_e32 v8, vcc, v10, v6, vcc
; GFX7LESS_ITERATIVE-NEXT: s_waitcnt expcnt(0)
@@ -7767,8 +7763,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX8_ITERATIVE-NEXT: s_mov_b32 s5, s3
; GFX8_ITERATIVE-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX8_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v10, v1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v9, v0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v10, v1
; GFX8_ITERATIVE-NEXT: v_subrev_u32_e32 v7, vcc, s8, v9
; GFX8_ITERATIVE-NEXT: v_subb_u32_e32 v8, vcc, v10, v6, vcc
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, v7
@@ -7839,8 +7835,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX9_ITERATIVE-NEXT: s_mov_b32 s5, s3
; GFX9_ITERATIVE-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX9_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v10, v1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v9, v0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v10, v1
; GFX9_ITERATIVE-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v9
; GFX9_ITERATIVE-NEXT: v_subb_co_u32_e32 v8, vcc, v10, v6, vcc
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, v7
@@ -7909,14 +7905,14 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1064_ITERATIVE-NEXT: s_mov_b32 s5, s3
; GFX1064_ITERATIVE-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX1064_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v9, v1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v8, v0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v9, v1
; GFX1064_ITERATIVE-NEXT: v_sub_co_u32 v6, vcc, v8, s8
; GFX1064_ITERATIVE-NEXT: v_subrev_co_ci_u32_e32 v7, vcc, s9, v9, vcc
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v2, v8
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, v9
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7
; GFX1064_ITERATIVE-NEXT: buffer_atomic_cmpswap_x2 v[0:3], off, s[4:7], 0 glc
; GFX1064_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl1_inv
@@ -7978,14 +7974,14 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1032_ITERATIVE-NEXT: s_mov_b32 s5, s3
; GFX1032_ITERATIVE-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX1032_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v9, v1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v8, v0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v9, v1
; GFX1032_ITERATIVE-NEXT: v_sub_co_u32 v6, vcc_lo, v8, s8
; GFX1032_ITERATIVE-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s9, v9, vcc_lo
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v2, v8
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, v9
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7
; GFX1032_ITERATIVE-NEXT: buffer_atomic_cmpswap_x2 v[0:3], off, s[4:7], 0 glc
; GFX1032_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl1_inv
@@ -8053,16 +8049,16 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_ITERATIVE-NEXT: s_mov_b32 s5, s3
; GFX1164_ITERATIVE-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX1164_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v9, v1
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v8, v0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v9, v1
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_ITERATIVE-NEXT: v_sub_co_u32 v6, vcc, v8, s8
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_ITERATIVE-NEXT: v_subrev_co_ci_u32_e64 v7, null, s9, v9, vcc
+; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, v8
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, v9
-; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7
; GFX1164_ITERATIVE-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1164_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
@@ -8133,12 +8129,10 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX1132_ITERATIVE-NEXT: v_sub_co_u32 v6, vcc_lo, v8, s8
-; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1132_ITERATIVE-NEXT: v_subrev_co_ci_u32_e64 v7, null, s9, v9, vcc_lo
-; GFX1132_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6
; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
-; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1132_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7
+; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
; GFX1132_ITERATIVE-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc
; GFX1132_ITERATIVE-NEXT: s_waitcnt vmcnt(0)
; GFX1132_ITERATIVE-NEXT: buffer_gl1_inv
@@ -8380,8 +8374,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX8_DPP-NEXT: v_mov_b32_e32 v0, s11
; GFX8_DPP-NEXT: .LBB11_2: ; %atomicrmw.start
; GFX8_DPP-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8_DPP-NEXT: v_mov_b32_e32 v11, v7
; GFX8_DPP-NEXT: v_mov_b32_e32 v10, v6
+; GFX8_DPP-NEXT: v_mov_b32_e32 v11, v7
; GFX8_DPP-NEXT: v_subrev_u32_e32 v8, vcc, s10, v10
; GFX8_DPP-NEXT: v_subb_u32_e32 v9, vcc, v11, v0, vcc
; GFX8_DPP-NEXT: v_mov_b32_e32 v6, v8
@@ -8483,13 +8477,12 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX9_DPP-NEXT: v_mov_b32_e32 v0, s11
; GFX9_DPP-NEXT: .LBB11_2: ; %atomicrmw.start
; GFX9_DPP-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9_DPP-NEXT: v_mov_b32_e32 v11, v7
; GFX9_DPP-NEXT: v_mov_b32_e32 v10, v6
+; GFX9_DPP-NEXT: v_mov_b32_e32 v11, v7
; GFX9_DPP-NEXT: v_subrev_co_u32_e32 v8, vcc, s10, v10
; GFX9_DPP-NEXT: v_subb_co_u32_e32 v9, vcc, v11, v0, vcc
-; GFX9_DPP-NEXT: v_mov_b32_e32 v7, v9
; GFX9_DPP-NEXT: v_swap_b32 v6, v8
-; GFX9_DPP-NEXT: v_mov_b32_e32 v9, v11
+; GFX9_DPP-NEXT: v_swap_b32 v7, v9
; GFX9_DPP-NEXT: buffer_atomic_cmpswap_x2 v[6:9], off, s[4:7], 0 glc
; GFX9_DPP-NEXT: s_waitcnt vmcnt(0)
; GFX9_DPP-NEXT: buffer_wbinvl1_vol
@@ -8604,13 +8597,12 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1064_DPP-NEXT: s_mov_b32 s5, s3
; GFX1064_DPP-NEXT: .LBB11_2: ; %atomicrmw.start
; GFX1064_DPP-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v13, v9
; GFX1064_DPP-NEXT: v_mov_b32_e32 v12, v8
+; GFX1064_DPP-NEXT: v_mov_b32_e32 v13, v9
; GFX1064_DPP-NEXT: v_sub_co_u32 v10, vcc, v12, s8
; GFX1064_DPP-NEXT: v_subrev_co_ci_u32_e32 v11, vcc, s9, v13, vcc
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v9, v11
; GFX1064_DPP-NEXT: v_swap_b32 v8, v10
-; GFX1064_DPP-NEXT: v_mov_b32_e32 v11, v13
+; GFX1064_DPP-NEXT: v_swap_b32 v9, v11
; GFX1064_DPP-NEXT: buffer_atomic_cmpswap_x2 v[8:11], off, s[4:7], 0 glc
; GFX1064_DPP-NEXT: s_waitcnt vmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl1_inv
@@ -8706,13 +8698,12 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1032_DPP-NEXT: s_mov_b32 s5, s3
; GFX1032_DPP-NEXT: .LBB11_2: ; %atomicrmw.start
; GFX1032_DPP-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v14, v10
; GFX1032_DPP-NEXT: v_mov_b32_e32 v13, v9
+; GFX1032_DPP-NEXT: v_mov_b32_e32 v14, v10
; GFX1032_DPP-NEXT: v_sub_co_u32 v11, vcc_lo, v13, s8
; GFX1032_DPP-NEXT: v_subrev_co_ci_u32_e32 v12, vcc_lo, s9, v14, vcc_lo
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v10, v12
; GFX1032_DPP-NEXT: v_swap_b32 v9, v11
-; GFX1032_DPP-NEXT: v_mov_b32_e32 v12, v14
+; GFX1032_DPP-NEXT: v_swap_b32 v10, v12
; GFX1032_DPP-NEXT: buffer_atomic_cmpswap_x2 v[9:12], off, s[4:7], 0 glc
; GFX1032_DPP-NEXT: s_waitcnt vmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl1_inv
@@ -8834,17 +8825,16 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: s_mov_b32 s5, s3
; GFX1164_DPP-NEXT: .LBB11_2: ; %atomicrmw.start
; GFX1164_DPP-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v13, v9
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v12, v8
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1164_DPP-NEXT: v_mov_b32_e32 v13, v9
; GFX1164_DPP-NEXT: v_sub_co_u32 v10, vcc, v12, s8
; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_subrev_co_ci_u32_e64 v11, null, s9, v13, vcc
-; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v9, v11
; GFX1164_DPP-NEXT: v_swap_b32 v8, v10
-; GFX1164_DPP-NEXT: v_mov_b32_e32 v11, v13
+; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164_DPP-NEXT: v_swap_b32 v9, v11
; GFX1164_DPP-NEXT: buffer_atomic_cmpswap_b64 v[8:11], off, s[4:7], 0 glc
; GFX1164_DPP-NEXT: s_waitcnt vmcnt(0)
; GFX1164_DPP-NEXT: buffer_gl1_inv
@@ -8948,12 +8938,11 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132_DPP-NEXT: v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v12, v8
; GFX1132_DPP-NEXT: v_sub_co_u32 v10, vcc_lo, v12, s8
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1132_DPP-NEXT: v_subrev_co_ci_u32_e64 v11, null, s9, v13, vcc_lo
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v9, v11
-; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1132_DPP-NEXT: v_swap_b32 v8, v10
-; GFX1132_DPP-NEXT: v_mov_b32_e32 v11, v13
+; GFX1132_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132_DPP-NEXT: v_swap_b32 v9, v11
; GFX1132_DPP-NEXT: buffer_atomic_cmpswap_b64 v[8:11], off, s[4:7], 0 glc
; GFX1132_DPP-NEXT: s_waitcnt vmcnt(0)
; GFX1132_DPP-NEXT: buffer_gl1_inv
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 2c6d1ee4d24b2..5dcb7908dca19 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -2405,8 +2405,8 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB6_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_add_rtn_u64 v[3:4], v0, v[3:4]
@@ -2453,8 +2453,8 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB6_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_add_rtn_u64 v[3:4], v0, v[3:4]
@@ -2501,8 +2501,8 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB6_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_add_rtn_u64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -2547,8 +2547,8 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB6_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_add_rtn_u64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -2593,8 +2593,8 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB6_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_add_rtn_u64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -2645,8 +2645,8 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB6_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_add_rtn_u64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -3457,8 +3457,8 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB7_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v1, s1
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_add_u64 v2, v[0:1]
@@ -3489,8 +3489,8 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB7_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v1, s1
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_add_u64 v2, v[0:1]
@@ -3521,8 +3521,8 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB7_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v1, s1
; GFX9_ITERATIVE-NEXT: ds_add_u64 v2, v[0:1]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -3552,8 +3552,8 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB7_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v1, s1
; GFX1064_ITERATIVE-NEXT: ds_add_u64 v2, v[0:1]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -3583,8 +3583,8 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB7_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v1, s1
; GFX1032_ITERATIVE-NEXT: ds_add_u64 v2, v[0:1]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -3619,8 +3619,8 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB7_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v1, s1
; GFX1164_ITERATIVE-NEXT: ds_add_u64 v2, v[0:1]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -3653,8 +3653,8 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1132_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1132_ITERATIVE-NEXT: s_cbranch_execz .LBB7_4
; GFX1132_ITERATIVE-NEXT: ; %bb.3:
-; GFX1132_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1132_ITERATIVE-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX1132_ITERATIVE-NEXT: v_mov_b32_e32 v0, s0
; GFX1132_ITERATIVE-NEXT: ds_add_u64 v2, v[0:1]
; GFX1132_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_ITERATIVE-NEXT: buffer_gl0_inv
@@ -6552,8 +6552,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB14_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_sub_rtn_u64 v[3:4], v0, v[3:4]
@@ -6600,8 +6600,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB14_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_sub_rtn_u64 v[3:4], v0, v[3:4]
@@ -6648,8 +6648,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB14_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_sub_rtn_u64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -6694,8 +6694,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB14_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_sub_rtn_u64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -6740,8 +6740,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB14_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_sub_rtn_u64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -6792,8 +6792,8 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB14_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_sub_rtn_u64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -8342,8 +8342,8 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB16_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_and_rtn_b64 v[3:4], v0, v[3:4]
@@ -8388,8 +8388,8 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB16_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_and_rtn_b64 v[3:4], v0, v[3:4]
@@ -8434,8 +8434,8 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB16_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_and_rtn_b64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -8478,8 +8478,8 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB16_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_and_rtn_b64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -8523,8 +8523,8 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB16_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_and_rtn_b64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -8573,8 +8573,8 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB16_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_and_rtn_b64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -9952,8 +9952,8 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB18_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_or_rtn_b64 v[3:4], v0, v[3:4]
@@ -9998,8 +9998,8 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB18_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_or_rtn_b64 v[3:4], v0, v[3:4]
@@ -10044,8 +10044,8 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB18_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_or_rtn_b64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -10088,8 +10088,8 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB18_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_or_rtn_b64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -10133,8 +10133,8 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB18_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_or_rtn_b64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -10183,8 +10183,8 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB18_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_or_rtn_b64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -11562,8 +11562,8 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB20_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_xor_rtn_b64 v[3:4], v0, v[3:4]
@@ -11608,8 +11608,8 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB20_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_xor_rtn_b64 v[3:4], v0, v[3:4]
@@ -11654,8 +11654,8 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB20_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_xor_rtn_b64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -11698,8 +11698,8 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB20_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_xor_rtn_b64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -11743,8 +11743,8 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB20_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_xor_rtn_b64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -11793,8 +11793,8 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB20_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_xor_rtn_b64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -13479,8 +13479,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB23_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_max_rtn_i64 v[3:4], v0, v[3:4]
@@ -13534,8 +13534,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB23_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_max_rtn_i64 v[3:4], v0, v[3:4]
@@ -13589,8 +13589,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB23_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_max_rtn_i64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -13640,8 +13640,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB23_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_max_rtn_i64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -13690,8 +13690,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB23_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_max_rtn_i64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -13747,8 +13747,8 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB23_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_max_rtn_i64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -15684,8 +15684,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB26_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_min_rtn_i64 v[3:4], v0, v[3:4]
@@ -15739,8 +15739,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB26_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_min_rtn_i64 v[3:4], v0, v[3:4]
@@ -15794,8 +15794,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB26_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_min_rtn_i64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -15845,8 +15845,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB26_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_min_rtn_i64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -15895,8 +15895,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB26_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_min_rtn_i64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -15952,8 +15952,8 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB26_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_min_rtn_i64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -17883,8 +17883,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB29_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_max_rtn_u64 v[3:4], v0, v[3:4]
@@ -17937,8 +17937,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB29_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_max_rtn_u64 v[3:4], v0, v[3:4]
@@ -17991,8 +17991,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB29_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_max_rtn_u64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -18041,8 +18041,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB29_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_max_rtn_u64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -18090,8 +18090,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB29_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_max_rtn_u64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -18146,8 +18146,8 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB29_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_max_rtn_u64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -20071,8 +20071,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX7LESS_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX7LESS_ITERATIVE-NEXT: s_cbranch_execz .LBB32_4
; GFX7LESS_ITERATIVE-NEXT: ; %bb.3:
-; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX7LESS_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX7LESS_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX7LESS_ITERATIVE-NEXT: ds_min_rtn_u64 v[3:4], v0, v[3:4]
@@ -20125,8 +20125,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX8_ITERATIVE-NEXT: s_cbranch_execz .LBB32_4
; GFX8_ITERATIVE-NEXT: ; %bb.3:
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, -1
; GFX8_ITERATIVE-NEXT: ds_min_rtn_u64 v[3:4], v0, v[3:4]
@@ -20179,8 +20179,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX9_ITERATIVE-NEXT: s_cbranch_execz .LBB32_4
; GFX9_ITERATIVE-NEXT: ; %bb.3:
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX9_ITERATIVE-NEXT: ds_min_rtn_u64 v[3:4], v0, v[3:4]
; GFX9_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -20229,8 +20229,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_cbranch_execz .LBB32_4
; GFX1064_ITERATIVE-NEXT: ; %bb.3:
-; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1064_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1064_ITERATIVE-NEXT: ds_min_rtn_u64 v[3:4], v0, v[3:4]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -20278,8 +20278,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_cbranch_execz .LBB32_4
; GFX1032_ITERATIVE-NEXT: ; %bb.3:
-; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v0, 0
+; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v4, s1
; GFX1032_ITERATIVE-NEXT: v_mov_b32_e32 v3, s0
; GFX1032_ITERATIVE-NEXT: ds_min_rtn_u64 v[3:4], v0, v[3:4]
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
@@ -20334,8 +20334,8 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
; GFX1164_ITERATIVE-NEXT: s_cbranch_execz .LBB32_4
; GFX1164_ITERATIVE-NEXT: ; %bb.3:
-; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v4, 0
+; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, s1
; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, s0
; GFX1164_ITERATIVE-NEXT: ds_min_rtn_u64 v[2:3], v4, v[2:3]
; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
index 3286aac1fa9b2..ccc1aa2e6f86f 100644
--- a/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
@@ -116,8 +116,8 @@ define amdgpu_kernel void @flat_atomic_usub_cond_rtn_u32(ptr %addr, i32 %in, ptr
; GFX9-SDAG-NEXT: v_subrev_u32_e32 v0, s6, v1
; GFX9-SDAG-NEXT: s_addc_u32 s9, s1, 0
; GFX9-SDAG-NEXT: v_cmp_le_u32_e32 vcc, s6, v1
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s8
; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s8
; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, s9
; GFX9-SDAG-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] glc
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -172,8 +172,8 @@ define amdgpu_kernel void @flat_atomic_usub_cond_rtn_u32(ptr %addr, i32 %in, ptr
; GFX9-GISEL-NEXT: v_subrev_u32_e32 v0, s6, v1
; GFX9-GISEL-NEXT: s_addc_u32 s9, s1, 0
; GFX9-GISEL-NEXT: v_cmp_le_u32_e32 vcc, s6, v1
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX9-GISEL-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] glc
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll b/llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
index 9c379996385ce..94595b305f037 100644
--- a/llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
@@ -111,15 +111,15 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
; CHECK-NEXT: s_cbranch_vccz .LBB0_5
; CHECK-NEXT: ; %bb.8: ; %.preheader1856.preheader.i.i.i3325
; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
-; CHECK-NEXT: v_accvgpr_write_b32 a2, v28
; CHECK-NEXT: s_mov_b64 s[24:25], 0
+; CHECK-NEXT: v_accvgpr_write_b32 a2, v28
; CHECK-NEXT: v_accvgpr_write_b32 a3, v29
; CHECK-NEXT: s_mov_b64 s[6:7], 0
; CHECK-NEXT: s_branch .LBB0_5
; CHECK-NEXT: .LBB0_9: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: v_mov_b64_e32 v[24:25], s[12:13]
-; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
; CHECK-NEXT: s_mov_b64 s[22:23], 0
+; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
; CHECK-NEXT: v_accvgpr_write_b32 a1, v25
; CHECK-NEXT: s_mov_b64 s[6:7], s[20:21]
; CHECK-NEXT: s_branch .LBB0_15
@@ -134,23 +134,22 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
; CHECK-NEXT: ; %bb.12: ; %._crit_edge2105.i.i.i2330.loopexit
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: v_cmp_nlg_f64_e64 s[6:7], 0, v[26:27]
-; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
; CHECK-NEXT: v_cndmask_b32_e64 v23, v23, 0, s[14:15]
+; CHECK-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[14:15]
; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, s[6:7]
; CHECK-NEXT: v_mov_b32_e32 v27, v26
; CHECK-NEXT: s_and_b64 s[6:7], exec, s[14:15]
-; CHECK-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[14:15]
; CHECK-NEXT: global_store_dwordx2 v0, v[26:27], s[8:9]
; CHECK-NEXT: s_cselect_b32 s23, s23, 0
; CHECK-NEXT: s_cselect_b32 s22, s22, 0
; CHECK-NEXT: s_mov_b64 s[6:7], -1
; CHECK-NEXT: s_branch .LBB0_14
; CHECK-NEXT: .LBB0_13: ; in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
; CHECK-NEXT: s_mov_b64 s[6:7], 0
; CHECK-NEXT: v_mov_b64_e32 v[22:23], 0
; CHECK-NEXT: .LBB0_14: ; %Flow6
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
; CHECK-NEXT: v_accvgpr_write_b32 a1, v25
; CHECK-NEXT: .LBB0_15: ; %Flow6
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/bfi_int.ll b/llvm/test/CodeGen/AMDGPU/bfi_int.ll
index 013523f07682c..8714ae5bdc9b4 100644
--- a/llvm/test/CodeGen/AMDGPU/bfi_int.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfi_int.ll
@@ -815,8 +815,8 @@ define amdgpu_ps <2 x float> @s_s_v_bitselect_i64_pat_0(i64 inreg %a, i64 inreg
; GFX10-GISEL-NEXT: s_not_b64 s[4:5], s[0:1]
; GFX10-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s0
; GFX10-GISEL-NEXT: v_and_or_b32 v1, v3, v1, v5
; GFX10-GISEL-NEXT: v_and_or_b32 v0, v2, v0, v4
@@ -1346,8 +1346,8 @@ define amdgpu_ps <2 x float> @s_v_s_bfi_sha256_ma_i64(i64 inreg %x, i64 %y, i64
; GFX10-GISEL-NEXT: s_or_b64 s[4:5], s[0:1], s[2:3]
; GFX10-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s0
; GFX10-GISEL-NEXT: v_and_or_b32 v1, v1, v3, v5
; GFX10-GISEL-NEXT: v_and_or_b32 v0, v0, v2, v4
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
index d9f6688833ec8..b901ea8eafa84 100644
--- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
@@ -54,8 +54,8 @@ define amdgpu_kernel void @s_brev_i16(ptr addrspace(1) noalias %out, i16 %val) #
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: s_brev_b32 s2, s2
; GISEL-NEXT: s_lshr_b32 s2, s2, 16
-; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: flat_store_short v[0:1], v2
; GISEL-NEXT: s_endpgm
@@ -150,13 +150,13 @@ define amdgpu_kernel void @v_brev_i16(ptr addrspace(1) noalias %out, ptr addrspa
; GISEL-NEXT: v_mov_b32_e32 v0, s2
; GISEL-NEXT: v_mov_b32_e32 v1, s3
; GISEL-NEXT: flat_load_ushort v0, v[0:1]
+; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: s_waitcnt vmcnt(0)
; GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GISEL-NEXT: s_brev_b32 s2, s2
; GISEL-NEXT: s_lshr_b32 s2, s2, 16
-; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: flat_store_short v[0:1], v2
; GISEL-NEXT: s_endpgm
;
@@ -241,8 +241,8 @@ define amdgpu_kernel void @s_brev_i32(ptr addrspace(1) noalias %out, i32 %val) #
; GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: s_brev_b32 s2, s2
-; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: flat_store_dword v[0:1], v2
; GISEL-NEXT: s_endpgm
@@ -324,10 +324,10 @@ define amdgpu_kernel void @v_brev_i32(ptr addrspace(1) noalias %out, ptr addrspa
; GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GISEL-NEXT: flat_load_dword v0, v[0:1]
+; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: s_waitcnt vmcnt(0)
; GISEL-NEXT: v_bfrev_b32_e32 v2, v0
; GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: flat_store_dword v[0:1], v2
; GISEL-NEXT: s_endpgm
;
@@ -402,8 +402,8 @@ define amdgpu_kernel void @s_brev_v2i32(ptr addrspace(1) noalias %out, <2 x i32>
; GISEL-NEXT: s_brev_b32 s2, s2
; GISEL-NEXT: s_brev_b32 s3, s3
; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: v_mov_b32_e32 v3, s1
; GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-NEXT: v_mov_b32_e32 v3, s1
; GISEL-NEXT: v_mov_b32_e32 v2, s0
; GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-NEXT: s_endpgm
@@ -566,8 +566,8 @@ define amdgpu_kernel void @s_brev_i64(ptr addrspace(1) noalias %out, i64 %val) #
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: s_brev_b64 s[2:3], s[2:3]
; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: v_mov_b32_e32 v3, s1
; GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-NEXT: v_mov_b32_e32 v3, s1
; GISEL-NEXT: v_mov_b32_e32 v2, s0
; GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-NEXT: s_endpgm
@@ -733,10 +733,10 @@ define amdgpu_kernel void @s_brev_v2i64(ptr addrspace(1) noalias %out, <2 x i64>
; GISEL-NEXT: s_brev_b64 s[0:1], s[0:1]
; GISEL-NEXT: s_brev_b64 s[2:3], s[2:3]
; GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-NEXT: v_mov_b32_e32 v4, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: v_mov_b32_e32 v2, s2
; GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GISEL-NEXT: v_mov_b32_e32 v4, s4
; GISEL-NEXT: v_mov_b32_e32 v5, s5
; GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GISEL-NEXT: s_endpgm
@@ -829,9 +829,9 @@ define amdgpu_kernel void @v_brev_v2i64(ptr addrspace(1) noalias %out, ptr addrs
; GISEL-NEXT: s_waitcnt vmcnt(0)
; GISEL-NEXT: v_bfrev_b32_e32 v5, v0
; GISEL-NEXT: v_bfrev_b32_e32 v4, v1
-; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_bfrev_b32_e32 v7, v2
; GISEL-NEXT: v_bfrev_b32_e32 v6, v3
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll b/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
index dda8f1e343a2c..87be714a54730 100644
--- a/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
+++ b/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
@@ -29,11 +29,11 @@ define amdgpu_kernel void @blender_no_live_segment_at_def_error(<4 x float> %ext
; CHECK-NEXT: s_mov_b32 s15, 0
; CHECK-NEXT: s_branch .LBB0_6
; CHECK-NEXT: .LBB0_4:
+; CHECK-NEXT: s_mov_b32 s13, s12
; CHECK-NEXT: s_mov_b32 s14, s12
; CHECK-NEXT: s_mov_b32 s15, s12
-; CHECK-NEXT: s_mov_b32 s13, s12
-; CHECK-NEXT: s_mov_b64 s[50:51], s[14:15]
; CHECK-NEXT: s_mov_b64 s[48:49], s[12:13]
+; CHECK-NEXT: s_mov_b64 s[50:51], s[14:15]
; CHECK-NEXT: s_branch .LBB0_8
; CHECK-NEXT: .LBB0_5: ; %if.then263.i.i
; CHECK-NEXT: v_cmp_lt_f32_e64 s17, s53, 0
@@ -82,8 +82,8 @@ define amdgpu_kernel void @blender_no_live_segment_at_def_error(<4 x float> %ext
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0
; CHECK-NEXT: .LBB0_9: ; %kernel_direct_lighting.exit
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x20
-; CHECK-NEXT: v_mov_b32_e32 v0, s48
; CHECK-NEXT: v_mov_b32_e32 v4, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, s48
; CHECK-NEXT: v_mov_b32_e32 v1, s49
; CHECK-NEXT: v_mov_b32_e32 v2, s50
; CHECK-NEXT: v_mov_b32_e32 v3, s51
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index 05d2195de63d6..59bf43637f504 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -66,8 +66,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_fine_g
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -567,8 +567,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX908-NEXT: ; Child Loop BB2_4 Depth 2
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_add_f32_e32 v7, v8, v5
-; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: v_mov_b32_e32 v7, v8
; GFX908-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -623,8 +623,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX8-NEXT: ; Child Loop BB2_4 Depth 2
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_f32_e32 v7, v8, v5
-; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: v_mov_b32_e32 v7, v8
; GFX8-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -678,8 +678,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX7-NEXT: ; Child Loop BB2_4 Depth 2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f32_e32 v7, v8, v5
-; GFX7-NEXT: v_mov_b32_e32 v6, v7
; GFX7-NEXT: s_mov_b64 s[12:13], exec
+; GFX7-NEXT: v_mov_b32_e32 v6, v7
; GFX7-NEXT: v_mov_b32_e32 v7, v8
; GFX7-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX7-NEXT: ; => This Inner Loop Header: Depth=2
@@ -735,8 +735,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX6-NEXT: ; Child Loop BB2_4 Depth 2
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: v_add_f32_e32 v7, v8, v5
-; GFX6-NEXT: v_mov_b32_e32 v6, v7
; GFX6-NEXT: s_mov_b64 s[12:13], exec
+; GFX6-NEXT: v_mov_b32_e32 v6, v7
; GFX6-NEXT: v_mov_b32_e32 v7, v8
; GFX6-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX6-NEXT: ; => This Inner Loop Header: Depth=2
@@ -822,8 +822,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_fine_g
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -1206,7 +1206,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset(ptr addrspace(7)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1234,8 +1234,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset(ptr addrspace(7)
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -1424,7 +1424,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_remote
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1452,8 +1452,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_remote
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -1642,7 +1642,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_remote
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1670,8 +1670,8 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_remote
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -1841,10 +1841,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -1881,10 +1881,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX11-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1912,11 +1912,11 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX10-NEXT: v_mov_b32_e32 v2, v8
+; GFX10-NEXT: v_mov_b32_e32 v3, v9
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v0, v6
; GFX10-NEXT: v_mov_b32_e32 v1, v7
-; GFX10-NEXT: v_mov_b32_e32 v2, v8
-; GFX10-NEXT: v_mov_b32_e32 v3, v9
; GFX10-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -1953,10 +1953,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v6
-; GFX908-NEXT: v_mov_b32_e32 v1, v7
; GFX908-NEXT: v_mov_b32_e32 v2, v8
; GFX908-NEXT: v_mov_b32_e32 v3, v9
+; GFX908-NEXT: v_mov_b32_e32 v0, v6
+; GFX908-NEXT: v_mov_b32_e32 v1, v7
; GFX908-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
@@ -1983,10 +1983,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v6
-; GFX8-NEXT: v_mov_b32_e32 v1, v7
; GFX8-NEXT: v_mov_b32_e32 v2, v8
; GFX8-NEXT: v_mov_b32_e32 v3, v9
+; GFX8-NEXT: v_mov_b32_e32 v0, v6
+; GFX8-NEXT: v_mov_b32_e32 v1, v7
; GFX8-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -2013,9 +2013,9 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v0, v6
; GFX7-NEXT: v_mov_b32_e32 v1, v7
-; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v3, v9
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -2045,9 +2045,9 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v0, v6
; GFX6-NEXT: v_mov_b32_e32 v1, v7
-; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v3, v9
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -2333,13 +2333,13 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: ; Child Loop BB10_4 Depth 2
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[11:12], v[13:14], v[5:6]
+; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX12-NEXT: s_mov_b32 s5, exec_lo
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s6, s5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
-; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX12-NEXT: .LBB10_4: ; Parent Loop BB10_3 Depth=1
; GFX12-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-NEXT: v_readfirstlane_b32 s0, v9
@@ -2428,12 +2428,12 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX11-NEXT: ; Child Loop BB10_4 Depth 2
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_f64 v[11:12], v[13:14], v[5:6]
+; GFX11-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX11-NEXT: s_mov_b32 s5, exec_lo
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_mov_b32 s6, s5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
-; GFX11-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
; GFX11-NEXT: .LBB10_4: ; Parent Loop BB10_3 Depth=1
; GFX11-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-NEXT: v_readfirstlane_b32 s0, v9
@@ -2491,13 +2491,13 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: ; Child Loop BB10_4 Depth 2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_f64 v[11:12], v[13:14], v[5:6]
+; GFX10-NEXT: v_mov_b32_e32 v2, v13
+; GFX10-NEXT: v_mov_b32_e32 v3, v14
; GFX10-NEXT: s_mov_b32 s9, exec_lo
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s10, s9
; GFX10-NEXT: v_mov_b32_e32 v0, v11
; GFX10-NEXT: v_mov_b32_e32 v1, v12
-; GFX10-NEXT: v_mov_b32_e32 v2, v13
-; GFX10-NEXT: v_mov_b32_e32 v3, v14
; GFX10-NEXT: .LBB10_4: ; Parent Loop BB10_3 Depth=1
; GFX10-NEXT: ; => This Inner Loop Header: Depth=2
; GFX10-NEXT: v_readfirstlane_b32 s4, v9
@@ -2587,10 +2587,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_add_f64 v[11:12], v[13:14], v[5:6]
; GFX908-NEXT: s_mov_b64 s[12:13], exec
-; GFX908-NEXT: v_mov_b32_e32 v0, v11
-; GFX908-NEXT: v_mov_b32_e32 v1, v12
; GFX908-NEXT: v_mov_b32_e32 v2, v13
; GFX908-NEXT: v_mov_b32_e32 v3, v14
+; GFX908-NEXT: v_mov_b32_e32 v0, v11
+; GFX908-NEXT: v_mov_b32_e32 v1, v12
; GFX908-NEXT: .LBB10_4: ; Parent Loop BB10_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
; GFX908-NEXT: v_readfirstlane_b32 s8, v9
@@ -2649,10 +2649,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_f64 v[11:12], v[13:14], v[5:6]
; GFX8-NEXT: s_mov_b64 s[12:13], exec
-; GFX8-NEXT: v_mov_b32_e32 v0, v11
-; GFX8-NEXT: v_mov_b32_e32 v1, v12
; GFX8-NEXT: v_mov_b32_e32 v2, v13
; GFX8-NEXT: v_mov_b32_e32 v3, v14
+; GFX8-NEXT: v_mov_b32_e32 v0, v11
+; GFX8-NEXT: v_mov_b32_e32 v1, v12
; GFX8-NEXT: .LBB10_4: ; Parent Loop BB10_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
; GFX8-NEXT: v_readfirstlane_b32 s8, v9
@@ -2828,10 +2828,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -2868,10 +2868,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX11-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -2899,11 +2899,11 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX10-NEXT: v_mov_b32_e32 v2, v8
+; GFX10-NEXT: v_mov_b32_e32 v3, v9
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v0, v6
; GFX10-NEXT: v_mov_b32_e32 v1, v7
-; GFX10-NEXT: v_mov_b32_e32 v2, v8
-; GFX10-NEXT: v_mov_b32_e32 v3, v9
; GFX10-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -2958,10 +2958,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v6
-; GFX908-NEXT: v_mov_b32_e32 v1, v7
; GFX908-NEXT: v_mov_b32_e32 v2, v8
; GFX908-NEXT: v_mov_b32_e32 v3, v9
+; GFX908-NEXT: v_mov_b32_e32 v0, v6
+; GFX908-NEXT: v_mov_b32_e32 v1, v7
; GFX908-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
@@ -2988,10 +2988,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v6
-; GFX8-NEXT: v_mov_b32_e32 v1, v7
; GFX8-NEXT: v_mov_b32_e32 v2, v8
; GFX8-NEXT: v_mov_b32_e32 v3, v9
+; GFX8-NEXT: v_mov_b32_e32 v0, v6
+; GFX8-NEXT: v_mov_b32_e32 v1, v7
; GFX8-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -3018,9 +3018,9 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v0, v6
; GFX7-NEXT: v_mov_b32_e32 v1, v7
-; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v3, v9
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -3050,9 +3050,9 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v0, v6
; GFX6-NEXT: v_mov_b32_e32 v1, v7
-; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v3, v9
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -3089,10 +3089,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[6:7], v[8:9], v[4:5]
+; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX12-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -3129,10 +3129,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX11-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GFX11-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v10, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -3160,11 +3160,11 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX10-NEXT: v_mov_b32_e32 v2, v8
+; GFX10-NEXT: v_mov_b32_e32 v3, v9
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v0, v6
; GFX10-NEXT: v_mov_b32_e32 v1, v7
-; GFX10-NEXT: v_mov_b32_e32 v2, v8
-; GFX10-NEXT: v_mov_b32_e32 v3, v9
; GFX10-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -3201,10 +3201,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v6
-; GFX908-NEXT: v_mov_b32_e32 v1, v7
; GFX908-NEXT: v_mov_b32_e32 v2, v8
; GFX908-NEXT: v_mov_b32_e32 v3, v9
+; GFX908-NEXT: v_mov_b32_e32 v0, v6
+; GFX908-NEXT: v_mov_b32_e32 v1, v7
; GFX908-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
@@ -3231,10 +3231,10 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v6
-; GFX8-NEXT: v_mov_b32_e32 v1, v7
; GFX8-NEXT: v_mov_b32_e32 v2, v8
; GFX8-NEXT: v_mov_b32_e32 v3, v9
+; GFX8-NEXT: v_mov_b32_e32 v0, v6
+; GFX8-NEXT: v_mov_b32_e32 v1, v7
; GFX8-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -3261,9 +3261,9 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v0, v6
; GFX7-NEXT: v_mov_b32_e32 v1, v7
-; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v3, v9
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen offset:2048 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -3293,9 +3293,9 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v0, v6
; GFX6-NEXT: v_mov_b32_e32 v1, v7
-; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v3, v9
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v10, s[16:19], 0 offen glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -4717,8 +4717,8 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX908-NEXT: v_add_f16_e32 v6, v6, v5
; GFX908-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX908-NEXT: v_and_or_b32 v6, v7, v11, v6
-; GFX908-NEXT: v_mov_b32_e32 v9, v7
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v9, v7
; GFX908-NEXT: v_mov_b32_e32 v8, v6
; GFX908-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -4784,8 +4784,8 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX8-NEXT: v_and_b32_e32 v8, v7, v11
; GFX8-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX8-NEXT: v_mov_b32_e32 v9, v7
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v9, v7
; GFX8-NEXT: v_mov_b32_e32 v8, v6
; GFX8-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -6046,8 +6046,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v7, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-TRUE16-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6136,8 +6135,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-FAKE16-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6296,8 +6294,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-TRUE16-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6381,8 +6378,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-FAKE16-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6602,8 +6598,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX908-NEXT: v_cndmask_b32_e32 v4, v5, v11, vcc
; GFX908-NEXT: v_lshlrev_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX908-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -6676,8 +6672,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX8-NEXT: v_lshlrev_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
-; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -6746,8 +6742,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX7-NEXT: v_lshlrev_b32_e32 v4, v8, v4
; GFX7-NEXT: v_and_b32_e32 v6, v5, v10
; GFX7-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: s_mov_b64 s[12:13], exec
+; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_mov_b32_e32 v6, v4
; GFX7-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX7-NEXT: ; => This Inner Loop Header: Depth=2
@@ -6817,8 +6813,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_and_b32_e32 v6, v5, v10
; GFX6-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: s_mov_b64 s[12:13], exec
+; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: v_mov_b32_e32 v6, v4
; GFX6-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1
; GFX6-NEXT: ; => This Inner Loop Header: Depth=2
@@ -6901,7 +6897,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, v5, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -6936,7 +6932,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, v5, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -6970,8 +6966,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_add_f16 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -7519,8 +7515,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX11-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v7
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v7 :: v_dual_mov_b32 v7, v8
; GFX11-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7596,8 +7591,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX11-FAKE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FAKE16-NEXT: s_mov_b32 s6, s5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v7
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, v7 :: v_dual_mov_b32 v7, v8
; GFX11-FAKE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7773,8 +7767,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX908-NEXT: ; =>This Loop Header: Depth=1
; GFX908-NEXT: ; Child Loop BB21_6 Depth 2
; GFX908-NEXT: v_pk_add_f16 v7, v8, v5
-; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: v_mov_b32_e32 v7, v8
; GFX908-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -7849,8 +7843,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX8-NEXT: v_add_f16_sdwa v6, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_add_f16_e32 v7, v8, v5
; GFX8-NEXT: v_or_b32_e32 v7, v7, v6
-; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: v_mov_b32_e32 v7, v8
; GFX8-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -8102,7 +8096,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset(ptr addrsp
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, v5, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -8137,7 +8131,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset(ptr addrsp
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, v5, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -8171,8 +8165,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset(ptr addrsp
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_add_f16 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -8716,7 +8710,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, v5, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -8751,7 +8745,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no
; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, v5, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -8785,8 +8779,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_add_f16 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -9394,7 +9388,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -9451,7 +9445,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -9501,8 +9495,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
+; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v4, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -10421,8 +10415,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB28_6: ; Parent Loop BB28_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -10518,8 +10511,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x7060302
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-FAKE16-NEXT: .LBB28_6: ; Parent Loop BB28_5 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -10795,8 +10787,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX908-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX908-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc
; GFX908-NEXT: v_perm_b32 v6, v6, v5, s15
-; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: .LBB28_6: ; Parent Loop BB28_5 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -10888,8 +10880,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v6, v6, v5, 16
-; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: .LBB28_6: ; Parent Loop BB28_5 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -10970,13 +10962,13 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX7-NEXT: v_add_f32_e32 v8, v8, v10
-; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX7-NEXT: v_add_f32_e32 v5, v5, v9
; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX7-NEXT: v_alignbit_b32 v6, v7, v6, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX7-NEXT: v_alignbit_b32 v5, v8, v5, 16
-; GFX7-NEXT: v_mov_b32_e32 v8, v6
+; GFX7-NEXT: v_alignbit_b32 v6, v7, v6, 16
; GFX7-NEXT: s_mov_b64 s[12:13], exec
+; GFX7-NEXT: v_mov_b32_e32 v8, v6
; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: .LBB28_6: ; Parent Loop BB28_5 Depth=1
; GFX7-NEXT: ; => This Inner Loop Header: Depth=2
@@ -11068,8 +11060,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v7
; GFX6-NEXT: v_alignbit_b32 v5, v6, v5, 16
-; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: s_mov_b64 s[12:13], exec
+; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: v_mov_b32_e32 v6, v4
; GFX6-NEXT: .LBB28_6: ; Parent Loop BB28_5 Depth=1
; GFX6-NEXT: ; => This Inner Loop Header: Depth=2
@@ -11212,7 +11204,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset(ptr add
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -11269,7 +11261,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset(ptr add
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -11319,8 +11311,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset(ptr add
; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
+; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v4, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -12148,7 +12140,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -12205,7 +12197,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -12255,8 +12247,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
+; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v4, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -13497,8 +13489,8 @@ define float @buffer_fat_ptr_system_atomic_fadd_ret_f32__offset__amdgpu_no_fine_
; GFX10-NEXT: v_mov_b32_e32 v5, v0
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_f32_e32 v4, v5, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index 29bde07836045..eec2dc25cc61e 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -591,8 +591,8 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f32_e32 v5, v7, v7
; GFX908-NEXT: v_max_f32_e32 v6, v5, v8
-; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -649,8 +649,8 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v7
; GFX8-NEXT: v_max_f32_e32 v6, v5, v8
-; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -798,7 +798,7 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__amdgpu_no_remote
; GFX11-NEXT: v_max_f32_e32 v0, v5, v5
; GFX11-NEXT: v_max_f32_e32 v4, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -828,8 +828,8 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__amdgpu_no_remote
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_max_f32_e32 v0, v5, v5
; GFX10-NEXT: v_max_f32_e32 v4, v0, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -1184,9 +1184,8 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1227,9 +1226,8 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1568,10 +1566,10 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s6, s5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_num_f64_e32 v[11:12], v[0:1], v[5:6]
-; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
+; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX12-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-NEXT: v_readfirstlane_b32 s0, v9
@@ -1664,10 +1662,10 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX11-NEXT: s_mov_b32 s5, exec_lo
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_mov_b32 s6, s5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f64 v[11:12], v[0:1], v[5:6]
-; GFX11-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX11-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
+; GFX11-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX11-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX11-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-NEXT: v_readfirstlane_b32 s0, v9
@@ -1787,10 +1785,10 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX908-NEXT: v_max_f64 v[0:1], v[13:14], v[13:14]
; GFX908-NEXT: s_mov_b64 s[12:13], exec
; GFX908-NEXT: v_max_f64 v[11:12], v[0:1], v[5:6]
-; GFX908-NEXT: v_mov_b32_e32 v0, v11
-; GFX908-NEXT: v_mov_b32_e32 v1, v12
; GFX908-NEXT: v_mov_b32_e32 v2, v13
; GFX908-NEXT: v_mov_b32_e32 v3, v14
+; GFX908-NEXT: v_mov_b32_e32 v0, v11
+; GFX908-NEXT: v_mov_b32_e32 v1, v12
; GFX908-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
; GFX908-NEXT: v_readfirstlane_b32 s8, v9
@@ -1851,10 +1849,10 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX8-NEXT: v_max_f64 v[0:1], v[13:14], v[13:14]
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_max_f64 v[11:12], v[0:1], v[5:6]
-; GFX8-NEXT: v_mov_b32_e32 v0, v11
-; GFX8-NEXT: v_mov_b32_e32 v1, v12
; GFX8-NEXT: v_mov_b32_e32 v2, v13
; GFX8-NEXT: v_mov_b32_e32 v3, v14
+; GFX8-NEXT: v_mov_b32_e32 v0, v11
+; GFX8-NEXT: v_mov_b32_e32 v1, v12
; GFX8-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
; GFX8-NEXT: v_readfirstlane_b32 s8, v9
@@ -1962,9 +1960,8 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2005,9 +2002,8 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_remot
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2228,9 +2224,8 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2271,9 +2266,8 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3429,8 +3423,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3649,8 +3642,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3855,8 +3847,8 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX908-NEXT: v_max_f16_e32 v4, v4, v10
; GFX908-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX908-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -3924,8 +3916,8 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
-; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5190,8 +5182,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v7, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-TRUE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5280,8 +5271,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-FAKE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5440,8 +5430,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-TRUE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5525,8 +5514,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-FAKE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5746,8 +5734,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX908-NEXT: v_cndmask_b32_e32 v4, v5, v11, vcc
; GFX908-NEXT: v_lshlrev_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX908-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5820,8 +5808,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX8-NEXT: v_lshlrev_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
-; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5891,8 +5879,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX7-NEXT: v_lshlrev_b32_e32 v4, v8, v4
; GFX7-NEXT: v_and_b32_e32 v6, v5, v10
; GFX7-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: s_mov_b64 s[12:13], exec
+; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_mov_b32_e32 v6, v4
; GFX7-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX7-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5963,8 +5951,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_and_b32_e32 v6, v5, v10
; GFX6-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: s_mov_b64 s[12:13], exec
+; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: v_mov_b32_e32 v6, v4
; GFX6-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX6-NEXT: ; => This Inner Loop Header: Depth=2
@@ -6028,7 +6016,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v0, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v4, v0, v2
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
@@ -6068,7 +6056,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v0, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v4, v0, v2
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
@@ -6135,7 +6123,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v5, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v0, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -6172,7 +6160,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v5, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pk_max_f16 v4, v0, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -6207,8 +6195,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_max_f16 v0, v5, v5
; GFX10-NEXT: v_pk_max_f16 v4, v0, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -6873,8 +6861,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v6, v5, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-TRUE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6963,8 +6950,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: s_mov_b32 s6, s5
; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v6, v5, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-FAKE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7121,8 +7107,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX11-TRUE16-NEXT: s_mov_b32 s6, s5
; GFX11-TRUE16-NEXT: v_pk_max_f16 v6, v5, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7201,8 +7186,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX11-FAKE16-NEXT: s_mov_b32 s6, s5
; GFX11-FAKE16-NEXT: v_pk_max_f16 v6, v5, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-FAKE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7431,8 +7415,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX908-NEXT: ; Child Loop BB18_6 Depth 2
; GFX908-NEXT: v_pk_max_f16 v5, v7, v7
; GFX908-NEXT: v_pk_max_f16 v6, v5, v8
-; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -7511,8 +7495,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX8-NEXT: v_max_f16_sdwa v5, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_max_f16_e32 v6, v6, v9
; GFX8-NEXT: v_or_b32_e32 v6, v6, v5
-; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -7769,7 +7753,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
@@ -7828,7 +7812,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
@@ -7930,7 +7914,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -7987,7 +7971,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -8037,8 +8021,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
+; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v4, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -8935,8 +8919,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9042,8 +9025,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x7060302
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-FAKE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9233,8 +9215,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9330,8 +9311,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x7060302
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-FAKE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9607,8 +9587,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX908-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX908-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc
; GFX908-NEXT: v_perm_b32 v6, v6, v5, s15
-; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -9700,8 +9680,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v6, v6, v5, 16
-; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -9782,13 +9762,13 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v7
; GFX7-NEXT: v_max_f32_e32 v5, v5, v9
; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX7-NEXT: v_max_f32_e32 v8, v8, v10
-; GFX7-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX7-NEXT: v_alignbit_b32 v5, v5, v8, 16
-; GFX7-NEXT: v_mov_b32_e32 v8, v6
+; GFX7-NEXT: v_alignbit_b32 v6, v6, v7, 16
; GFX7-NEXT: s_mov_b64 s[12:13], exec
+; GFX7-NEXT: v_mov_b32_e32 v8, v6
; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX7-NEXT: ; => This Inner Loop Header: Depth=2
@@ -9876,13 +9856,13 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX6-NEXT: v_mul_f32_e32 v7, 1.0, v4
; GFX6-NEXT: v_max_f32_e32 v6, v6, v9
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX6-NEXT: v_max_f32_e32 v4, v4, v10
-; GFX6-NEXT: v_alignbit_b32 v5, v5, v7, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_alignbit_b32 v4, v6, v4, 16
-; GFX6-NEXT: v_mov_b32_e32 v7, v5
+; GFX6-NEXT: v_alignbit_b32 v5, v5, v7, 16
; GFX6-NEXT: s_mov_b64 s[12:13], exec
+; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: v_mov_b32_e32 v6, v4
; GFX6-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX6-NEXT: ; => This Inner Loop Header: Depth=2
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index d0d8327947e0f..5ed7f52fcb000 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -591,8 +591,8 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_max_f32_e32 v5, v7, v7
; GFX908-NEXT: v_min_f32_e32 v6, v5, v8
-; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -649,8 +649,8 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mul_f32_e32 v5, 1.0, v7
; GFX8-NEXT: v_min_f32_e32 v6, v5, v8
-; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -798,7 +798,7 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__amdgpu_no_remote
; GFX11-NEXT: v_max_f32_e32 v0, v5, v5
; GFX11-NEXT: v_min_f32_e32 v4, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -828,8 +828,8 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__amdgpu_no_remote
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_max_f32_e32 v0, v5, v5
; GFX10-NEXT: v_min_f32_e32 v4, v0, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -1184,9 +1184,8 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1227,9 +1226,8 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1568,10 +1566,10 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s6, s5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_min_num_f64_e32 v[11:12], v[0:1], v[5:6]
-; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
+; GFX12-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX12-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX12-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-NEXT: v_readfirstlane_b32 s0, v9
@@ -1664,10 +1662,10 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX11-NEXT: s_mov_b32 s5, exec_lo
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_mov_b32 s6, s5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_min_f64 v[11:12], v[0:1], v[5:6]
-; GFX11-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX11-NEXT: v_dual_mov_b32 v2, v13 :: v_dual_mov_b32 v3, v14
+; GFX11-NEXT: v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v1, v12
; GFX11-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX11-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-NEXT: v_readfirstlane_b32 s0, v9
@@ -1787,10 +1785,10 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX908-NEXT: v_max_f64 v[0:1], v[13:14], v[13:14]
; GFX908-NEXT: s_mov_b64 s[12:13], exec
; GFX908-NEXT: v_min_f64 v[11:12], v[0:1], v[5:6]
-; GFX908-NEXT: v_mov_b32_e32 v0, v11
-; GFX908-NEXT: v_mov_b32_e32 v1, v12
; GFX908-NEXT: v_mov_b32_e32 v2, v13
; GFX908-NEXT: v_mov_b32_e32 v3, v14
+; GFX908-NEXT: v_mov_b32_e32 v0, v11
+; GFX908-NEXT: v_mov_b32_e32 v1, v12
; GFX908-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
; GFX908-NEXT: v_readfirstlane_b32 s8, v9
@@ -1851,10 +1849,10 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX8-NEXT: v_max_f64 v[0:1], v[13:14], v[13:14]
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_min_f64 v[11:12], v[0:1], v[5:6]
-; GFX8-NEXT: v_mov_b32_e32 v0, v11
-; GFX8-NEXT: v_mov_b32_e32 v1, v12
; GFX8-NEXT: v_mov_b32_e32 v2, v13
; GFX8-NEXT: v_mov_b32_e32 v3, v14
+; GFX8-NEXT: v_mov_b32_e32 v0, v11
+; GFX8-NEXT: v_mov_b32_e32 v1, v12
; GFX8-NEXT: .LBB7_4: ; Parent Loop BB7_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
; GFX8-NEXT: v_readfirstlane_b32 s8, v9
@@ -1962,9 +1960,8 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2005,9 +2002,8 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_remot
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2228,9 +2224,8 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[0:1], v[6:7]
-; GFX12-NEXT: v_mov_b32_e32 v0, v2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX12-NEXT: v_mov_b32_e32 v2, v4
; GFX12-NEXT: v_mov_b32_e32 v3, v5
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], null offen offset:2048 th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2271,9 +2266,8 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
+; GFX11-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v2, v4
; GFX11-NEXT: v_mov_b32_e32 v3, v5
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v8, s[0:3], 0 offen offset:2048 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3429,8 +3423,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3649,8 +3642,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-FAKE16-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3855,8 +3847,8 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX908-NEXT: v_min_f16_e32 v4, v4, v10
; GFX908-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX908-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -3924,8 +3916,8 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
-; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5190,8 +5182,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v7, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-TRUE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5280,8 +5271,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX12-FAKE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5440,8 +5430,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-TRUE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5525,8 +5514,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, v6, v9, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX11-FAKE16-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -5746,8 +5734,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX908-NEXT: v_cndmask_b32_e32 v4, v5, v11, vcc
; GFX908-NEXT: v_lshlrev_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX908-NEXT: v_and_or_b32 v5, v6, v9, v4
-; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v4, v5
; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5820,8 +5808,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX8-NEXT: v_lshlrev_b32_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
-; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5891,8 +5879,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX7-NEXT: v_lshlrev_b32_e32 v4, v8, v4
; GFX7-NEXT: v_and_b32_e32 v6, v5, v10
; GFX7-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: s_mov_b64 s[12:13], exec
+; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_mov_b32_e32 v6, v4
; GFX7-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX7-NEXT: ; => This Inner Loop Header: Depth=2
@@ -5963,8 +5951,8 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_and_b32_e32 v6, v5, v10
; GFX6-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: s_mov_b64 s[12:13], exec
+; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: v_mov_b32_e32 v6, v4
; GFX6-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1
; GFX6-NEXT: ; => This Inner Loop Header: Depth=2
@@ -6028,7 +6016,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX12-TRUE16-NEXT: v_pk_max_num_f16 v0, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v4, v0, v2
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
@@ -6068,7 +6056,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX12-FAKE16-NEXT: v_pk_max_num_f16 v0, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v4, v0, v2
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
@@ -6135,7 +6123,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v5, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v0, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -6172,7 +6160,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX11-FAKE16-NEXT: v_pk_max_f16 v0, v5, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_pk_min_f16 v4, v0, v2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -6207,8 +6195,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_max_f16 v0, v5, v5
; GFX10-NEXT: v_pk_min_f16 v4, v0, v2
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -6873,8 +6861,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
; GFX12-TRUE16-NEXT: v_pk_min_num_f16 v6, v5, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-TRUE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -6963,8 +6950,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-FAKE16-NEXT: s_mov_b32 s6, s5
; GFX12-FAKE16-NEXT: v_pk_min_num_f16 v6, v5, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-FAKE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7121,8 +7107,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX11-TRUE16-NEXT: s_mov_b32 s6, s5
; GFX11-TRUE16-NEXT: v_pk_min_f16 v6, v5, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7201,8 +7186,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX11-FAKE16-NEXT: s_mov_b32 s6, s5
; GFX11-FAKE16-NEXT: v_pk_min_f16 v6, v5, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-FAKE16-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -7431,8 +7415,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX908-NEXT: ; Child Loop BB18_6 Depth 2
; GFX908-NEXT: v_pk_max_f16 v5, v7, v7
; GFX908-NEXT: v_pk_min_f16 v6, v5, v8
-; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -7511,8 +7495,8 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX8-NEXT: v_min_f16_sdwa v5, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_min_f16_e32 v6, v6, v9
; GFX8-NEXT: v_or_b32_e32 v6, v6, v5
-; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: .LBB18_6: ; Parent Loop BB18_5 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -7769,7 +7753,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
@@ -7828,7 +7812,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
@@ -7930,7 +7914,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_gl1_inv
@@ -7987,7 +7971,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_gl1_inv
@@ -8037,8 +8021,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX10-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
-; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v1, v6
+; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: buffer_atomic_cmpswap v[0:1], v4, s[16:19], 0 offen offset:1024 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_gl1_inv
@@ -8935,8 +8919,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX12-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9042,8 +9025,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x7060302
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-FAKE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX12-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9233,8 +9215,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9330,8 +9311,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x7060302
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v6
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v7
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-FAKE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-FAKE16-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -9607,8 +9587,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX908-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX908-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc
; GFX908-NEXT: v_perm_b32 v6, v6, v5, s15
-; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: s_mov_b64 s[12:13], exec
+; GFX908-NEXT: v_mov_b32_e32 v5, v6
; GFX908-NEXT: v_mov_b32_e32 v6, v7
; GFX908-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
@@ -9700,8 +9680,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_alignbit_b32 v6, v6, v5, 16
-; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: s_mov_b64 s[12:13], exec
+; GFX8-NEXT: v_mov_b32_e32 v5, v6
; GFX8-NEXT: v_mov_b32_e32 v6, v7
; GFX8-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
@@ -9782,13 +9762,13 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v7
; GFX7-NEXT: v_min_f32_e32 v5, v5, v9
; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX7-NEXT: v_min_f32_e32 v8, v8, v10
-; GFX7-NEXT: v_alignbit_b32 v6, v6, v7, 16
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX7-NEXT: v_alignbit_b32 v5, v5, v8, 16
-; GFX7-NEXT: v_mov_b32_e32 v8, v6
+; GFX7-NEXT: v_alignbit_b32 v6, v6, v7, 16
; GFX7-NEXT: s_mov_b64 s[12:13], exec
+; GFX7-NEXT: v_mov_b32_e32 v8, v6
; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX7-NEXT: ; => This Inner Loop Header: Depth=2
@@ -9876,13 +9856,13 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX6-NEXT: v_mul_f32_e32 v7, 1.0, v4
; GFX6-NEXT: v_min_f32_e32 v6, v6, v9
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX6-NEXT: v_min_f32_e32 v4, v4, v10
-; GFX6-NEXT: v_alignbit_b32 v5, v5, v7, 16
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_alignbit_b32 v4, v6, v4, 16
-; GFX6-NEXT: v_mov_b32_e32 v7, v5
+; GFX6-NEXT: v_alignbit_b32 v5, v5, v7, 16
; GFX6-NEXT: s_mov_b64 s[12:13], exec
+; GFX6-NEXT: v_mov_b32_e32 v7, v5
; GFX6-NEXT: v_mov_b32_e32 v6, v4
; GFX6-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX6-NEXT: ; => This Inner Loop Header: Depth=2
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
index 2414290ccd62d..37af5aba9810f 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
@@ -39,7 +39,7 @@ define i32 @buffer_fat_ptr_agent_atomic_usub_cond_ret_u32__offset__amdgpu_no_fin
; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v2
; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -138,7 +138,7 @@ define i32 @buffer_fat_ptr_agent_atomic_usub_cond_ret_u32__offset__amdgpu_no_rem
; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v2
; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -188,7 +188,7 @@ define i32 @buffer_fat_ptr_agent_atomic_usub_cond_ret_u32__offset__amdgpu_no_fin
; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v2
; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -243,7 +243,7 @@ define i32 @buffer_fat_ptr_system_atomic_usub_cond_ret_u32__offset__amdgpu_no_fi
; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v2
; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX11-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v3, s[0:3], 0 offen offset:1024 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll b/llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
index 96b71cf85c8b2..bfd0c405fe1a6 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
@@ -11,10 +11,10 @@ define amdgpu_kernel void @buffer_ptr_vector_ops(ptr addrspace(1) %somewhere) {
; GISEL-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-NEXT: v_mov_b32_e32 v4, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: v_mov_b32_e32 v2, s2
; GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GISEL-NEXT: v_mov_b32_e32 v4, s4
; GISEL-NEXT: v_mov_b32_e32 v5, s5
; GISEL-NEXT: v_mov_b32_e32 v6, s6
; GISEL-NEXT: v_mov_b32_e32 v7, s7
@@ -68,9 +68,9 @@ define amdgpu_kernel void @buffer_structs(%fat_buffer_struct %arg, ptr addrspace
; GISEL-NEXT: s_ashr_i32 s7, s6, 31
; GISEL-NEXT: s_lshl_b64 s[4:5], s[6:7], 5
; GISEL-NEXT: s_add_u32 s4, s8, s4
-; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v4, s6
; GISEL-NEXT: s_addc_u32 s5, s9, s5
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: v_mov_b32_e32 v2, s2
; GISEL-NEXT: v_mov_b32_e32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.ll b/llvm/test/CodeGen/AMDGPU/build_vector.ll
index 37f4094806637..62599aa9d7d08 100644
--- a/llvm/test/CodeGen/AMDGPU/build_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/build_vector.ll
@@ -274,9 +274,9 @@ define amdgpu_kernel void @build_v2i32_from_v4i16_shuffle(ptr addrspace(1) %out,
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_lshl_b32 s3, s3, 16
; GFX8-NEXT: s_lshl_b32 s2, s2, 16
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
index 9a6dbcd30e2ea..85cadf9d06827 100644
--- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
@@ -71,11 +71,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i1 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i1 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1
; VI-NEXT: s_mov_b32 s32, 0
@@ -90,11 +90,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i1 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i1 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1
; CI-NEXT: s_mov_b32 s32, 0
@@ -109,11 +109,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i1 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i1 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1
; SDAG-NEXT: s_mov_b32 s32, 0
@@ -156,11 +156,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i1 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i1 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 1
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -182,11 +182,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: v_bfe_i32 v0, v0, 0, 1
@@ -205,11 +205,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: v_bfe_i32 v0, v0, 0, 1
@@ -228,11 +228,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: v_bfe_i32 v0, v0, 0, 1
@@ -290,11 +290,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-NEXT: s_bfe_i32 s8, s0, 0x10000
; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-NEXT: s_endpgm
@@ -317,11 +317,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: v_and_b32_e32 v0, 1, v0
@@ -340,11 +340,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: v_and_b32_e32 v0, 1, v0
@@ -363,11 +363,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: v_and_b32_e32 v0, 1, v0
@@ -425,11 +425,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-NEXT: s_and_b32 s8, s0, 1
; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-NEXT: s_endpgm
@@ -447,11 +447,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i8 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i8 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0x7b
; VI-NEXT: s_mov_b32 s32, 0
@@ -466,11 +466,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i8 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i8 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0x7b
; CI-NEXT: s_mov_b32 s32, 0
@@ -485,11 +485,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i8 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i8 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0x7b
; SDAG-NEXT: s_mov_b32 s32, 0
@@ -543,11 +543,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i8 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i8 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7b
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -570,11 +570,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -592,11 +592,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -614,11 +614,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -670,10 +670,10 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -696,11 +696,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -718,11 +718,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -740,11 +740,11 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -796,10 +796,10 @@ define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -818,11 +818,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0x7b
; VI-NEXT: s_mov_b32 s32, 0
@@ -837,11 +837,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0x7b
; CI-NEXT: s_mov_b32 s32, 0
@@ -856,11 +856,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0x7b
; SDAG-NEXT: s_mov_b32 s32, 0
@@ -914,11 +914,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i16 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i16 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7b
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -940,11 +940,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -962,11 +962,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -984,11 +984,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1040,10 +1040,10 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1066,11 +1066,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1088,11 +1088,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1110,11 +1110,11 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1166,10 +1166,10 @@ define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1188,11 +1188,11 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_mov_b32 s32, 0
@@ -1207,11 +1207,11 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_mov_b32 s32, 0
@@ -1226,11 +1226,11 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 42
; SDAG-NEXT: s_mov_b32 s32, 0
@@ -1273,11 +1273,11 @@ define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i32 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 42
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1295,11 +1295,11 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_i64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_i64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0x7b
; VI-NEXT: v_mov_b32_e32 v1, 0
@@ -1315,11 +1315,11 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_i64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_i64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0x7b
; CI-NEXT: v_mov_b32_e32 v1, 0
@@ -1335,11 +1335,11 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_i64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_i64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0x7b
; SDAG-NEXT: v_mov_b32_e32 v1, 0
@@ -1384,12 +1384,12 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_i64 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_i64 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7b
; GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1412,10 +1412,10 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2i64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1434,10 +1434,10 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2i64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1456,10 +1456,10 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
; SDAG-NEXT: s_mov_b32 s2, -1
; SDAG-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2i64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2i64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1536,11 +1536,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2i64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1
; VI-NEXT: v_mov_b32_e32 v1, 2
@@ -1558,11 +1558,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2i64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1
; CI-NEXT: v_mov_b32_e32 v1, 2
@@ -1580,11 +1580,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2i64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2i64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1
; SDAG-NEXT: v_mov_b32_e32 v1, 2
@@ -1634,7 +1634,6 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2i64 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2i64 at rel32@hi+12
@@ -1642,6 +1641,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; GISEL-NEXT: v_mov_b32_e32 v1, 2
; GISEL-NEXT: v_mov_b32_e32 v2, 3
; GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1664,10 +1664,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3i64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v4, 1
; VI-NEXT: v_mov_b32_e32 v5, 2
@@ -1688,10 +1688,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3i64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v4, 1
; CI-NEXT: v_mov_b32_e32 v5, 2
@@ -1712,10 +1712,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
; SDAG-NEXT: s_mov_b32 s2, -1
; SDAG-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3i64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3i64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v4, 1
; SDAG-NEXT: v_mov_b32_e32 v5, 2
@@ -1806,10 +1806,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v4i64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v4, 1
; VI-NEXT: v_mov_b32_e32 v5, 2
@@ -1832,10 +1832,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v4i64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v4, 1
; CI-NEXT: v_mov_b32_e32 v5, 2
@@ -1858,10 +1858,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
; SDAG-NEXT: s_mov_b32 s2, -1
; SDAG-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v4i64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v4i64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v4, 1
; SDAG-NEXT: v_mov_b32_e32 v5, 2
@@ -1931,9 +1931,9 @@ define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: v_mov_b32_e32 v2, s2
; GISEL-NEXT: v_mov_b32_e32 v3, s3
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: v_mov_b32_e32 v6, 3
; GISEL-NEXT: v_mov_b32_e32 v7, 4
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -1953,11 +1953,11 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_f16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_f16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0x4400
; VI-NEXT: s_mov_b32 s32, 0
@@ -1972,11 +1972,11 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_f16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_f16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0x4400
; CI-NEXT: s_mov_b32 s32, 0
@@ -1991,11 +1991,11 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_f16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_f16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0x4400
; SDAG-NEXT: s_mov_b32 s32, 0
@@ -2049,11 +2049,11 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_f16 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_f16 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0x4400
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2071,11 +2071,11 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_f32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_f32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 4.0
; VI-NEXT: s_mov_b32 s32, 0
@@ -2090,11 +2090,11 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_f32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_f32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 4.0
; CI-NEXT: s_mov_b32 s32, 0
@@ -2109,11 +2109,11 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_f32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_f32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 4.0
; SDAG-NEXT: s_mov_b32 s32, 0
@@ -2156,11 +2156,11 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_f32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_f32 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 4.0
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2178,11 +2178,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2f32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2f32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1.0
; VI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2198,11 +2198,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2f32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2f32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1.0
; CI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2218,11 +2218,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2f32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2f32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1.0
; SDAG-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2267,12 +2267,12 @@ define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2f32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2f32 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 1.0
; GISEL-NEXT: v_mov_b32_e32 v1, 2.0
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2290,11 +2290,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3f32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1.0
; VI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2311,11 +2311,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3f32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1.0
; CI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2332,11 +2332,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3f32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3f32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1.0
; SDAG-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2384,13 +2384,13 @@ define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3f32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3f32 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 1.0
; GISEL-NEXT: v_mov_b32_e32 v1, 2.0
; GISEL-NEXT: v_mov_b32_e32 v2, 4.0
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2408,11 +2408,11 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v5f32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v5f32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1.0
; VI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2431,11 +2431,11 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v5f32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v5f32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1.0
; CI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2454,11 +2454,11 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v5f32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v5f32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1.0
; SDAG-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2511,7 +2511,6 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v5f32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v5f32 at rel32@hi+12
@@ -2520,6 +2519,7 @@ define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
; GISEL-NEXT: v_mov_b32_e32 v2, 4.0
; GISEL-NEXT: v_mov_b32_e32 v3, -1.0
; GISEL-NEXT: v_mov_b32_e32 v4, 0.5
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2537,11 +2537,11 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_f64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_f64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0x40100000
@@ -2557,11 +2557,11 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_f64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_f64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, 0x40100000
@@ -2577,11 +2577,11 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_f64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_f64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0
; SDAG-NEXT: v_mov_b32_e32 v1, 0x40100000
@@ -2626,12 +2626,12 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_f64 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_f64 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0
; GISEL-NEXT: v_mov_b32_e32 v1, 0x40100000
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2649,11 +2649,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2f64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2f64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2671,11 +2671,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2f64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2f64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2693,11 +2693,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2f64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2f64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0
; SDAG-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2747,7 +2747,6 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2f64 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2f64 at rel32@hi+12
@@ -2755,6 +2754,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {
; GISEL-NEXT: v_mov_b32_e32 v1, 2.0
; GISEL-NEXT: v_mov_b32_e32 v2, 0
; GISEL-NEXT: v_mov_b32_e32 v3, 0x40100000
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2772,11 +2772,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3f64 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f64 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2796,11 +2796,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3f64 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f64 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2820,11 +2820,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3f64 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3f64 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0
; SDAG-NEXT: v_mov_b32_e32 v1, 2.0
@@ -2879,7 +2879,6 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3f64 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3f64 at rel32@hi+12
@@ -2889,6 +2888,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; GISEL-NEXT: v_mov_b32_e32 v3, 0x40100000
; GISEL-NEXT: v_mov_b32_e32 v4, 0
; GISEL-NEXT: v_mov_b32_e32 v5, 0x40200000
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2909,11 +2909,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2i16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2930,11 +2930,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: buffer_load_dword v0, off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2i16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2951,11 +2951,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
; SDAG-NEXT: s_mov_b32 s2, -1
; SDAG-NEXT: buffer_load_dword v0, off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2i16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2i16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -2996,16 +2996,16 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
; GISEL: ; %bb.0:
; GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GISEL-NEXT: s_mov_b32 s38, -1
; GISEL-NEXT: s_load_dword s8, s[0:1], 0x0
+; GISEL-NEXT: s_mov_b32 s38, -1
; GISEL-NEXT: s_mov_b32 s39, 0xe00000
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2i16 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2i16 at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s8
@@ -3030,10 +3030,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3051,10 +3051,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3074,10 +3074,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; SDAG-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3124,13 +3124,13 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; GISEL-NEXT: s_mov_b32 s39, 0xe00000
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
+; GISEL-NEXT: s_getpc_b64 s[4:5]
+; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GISEL-NEXT: s_getpc_b64 s[4:5]
-; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
-; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3153,10 +3153,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3174,10 +3174,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3197,10 +3197,10 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
; SDAG-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3247,13 +3247,13 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
; GISEL-NEXT: s_mov_b32 s39, 0xe00000
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
+; GISEL-NEXT: s_getpc_b64 s[4:5]
+; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GISEL-NEXT: s_getpc_b64 s[4:5]
-; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
-; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3272,11 +3272,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0x20001
; VI-NEXT: v_mov_b32_e32 v1, 3
@@ -3292,11 +3292,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0x20001
; CI-NEXT: v_mov_b32_e32 v1, 3
@@ -3312,11 +3312,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0x20001
; SDAG-NEXT: v_mov_b32_e32 v1, 3
@@ -3361,12 +3361,12 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3i16 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3i16 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0x20001
; GISEL-NEXT: v_mov_b32_e32 v1, 3
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3384,11 +3384,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0x40003c00
; VI-NEXT: v_mov_b32_e32 v1, 0x4400
@@ -3404,11 +3404,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0x40003c00
; CI-NEXT: v_mov_b32_e32 v1, 0x4400
@@ -3424,11 +3424,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0x40003c00
; SDAG-NEXT: v_mov_b32_e32 v1, 0x4400
@@ -3474,12 +3474,12 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3f16 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3f16 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0x40003c00
; GISEL-NEXT: v_mov_b32_e32 v1, 0x4400
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3501,10 +3501,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3522,10 +3522,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3543,10 +3543,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
; SDAG-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3593,13 +3593,13 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
; GISEL-NEXT: s_mov_b32 s39, 0xe00000
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
+; GISEL-NEXT: s_getpc_b64 s[4:5]
+; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GISEL-NEXT: s_getpc_b64 s[4:5]
-; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
-; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3618,11 +3618,11 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 0x20001
; VI-NEXT: v_mov_b32_e32 v1, 0x40003
@@ -3638,11 +3638,11 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 0x20001
; CI-NEXT: v_mov_b32_e32 v1, 0x40003
@@ -3658,11 +3658,11 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 0x20001
; SDAG-NEXT: v_mov_b32_e32 v1, 0x40003
@@ -3708,12 +3708,12 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v4i16 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v4i16 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 0x20001
; GISEL-NEXT: v_mov_b32_e32 v1, 0x40003
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3734,11 +3734,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2f16 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2f16 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3755,11 +3755,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: buffer_load_dword v0, off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2f16 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2f16 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3776,11 +3776,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
; SDAG-NEXT: s_mov_b32 s2, -1
; SDAG-NEXT: buffer_load_dword v0, off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2f16 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2f16 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3821,16 +3821,16 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
; GISEL: ; %bb.0:
; GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GISEL-NEXT: s_mov_b32 s38, -1
; GISEL-NEXT: s_load_dword s8, s[0:1], 0x0
+; GISEL-NEXT: s_mov_b32 s38, -1
; GISEL-NEXT: s_mov_b32 s39, 0xe00000
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2f16 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2f16 at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s8
@@ -3855,10 +3855,10 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3876,10 +3876,10 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3897,10 +3897,10 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
; SDAG-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3947,13 +3947,13 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
; GISEL-NEXT: s_mov_b32 s39, 0xe00000
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
+; GISEL-NEXT: s_getpc_b64 s[4:5]
+; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s1
; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GISEL-NEXT: s_getpc_b64 s[4:5]
-; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
-; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -3972,11 +3972,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1
; VI-NEXT: v_mov_b32_e32 v1, 2
@@ -3992,11 +3992,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1
; CI-NEXT: v_mov_b32_e32 v1, 2
@@ -4012,11 +4012,11 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1
; SDAG-NEXT: v_mov_b32_e32 v1, 2
@@ -4061,12 +4061,12 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v2i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v2i32 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 1
; GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4084,11 +4084,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 3
; VI-NEXT: v_mov_b32_e32 v1, 4
@@ -4105,11 +4105,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 3
; CI-NEXT: v_mov_b32_e32 v1, 4
@@ -4126,11 +4126,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 3
; SDAG-NEXT: v_mov_b32_e32 v1, 4
@@ -4178,13 +4178,13 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 3
; GISEL-NEXT: v_mov_b32_e32 v1, 4
; GISEL-NEXT: v_mov_b32_e32 v2, 5
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4202,11 +4202,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s5
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v3i32_i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32_i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 3
; VI-NEXT: v_mov_b32_e32 v1, 4
@@ -4224,11 +4224,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s5
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v3i32_i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32_i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 3
; CI-NEXT: v_mov_b32_e32 v1, 4
@@ -4246,11 +4246,11 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s5
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v3i32_i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32_i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 3
; SDAG-NEXT: v_mov_b32_e32 v1, 4
@@ -4300,7 +4300,6 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s5
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v3i32_i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v3i32_i32 at rel32@hi+12
@@ -4308,6 +4307,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GISEL-NEXT: v_mov_b32_e32 v1, 4
; GISEL-NEXT: v_mov_b32_e32 v2, 5
; GISEL-NEXT: v_mov_b32_e32 v3, 6
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4329,10 +4329,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v4i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4350,10 +4350,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v4i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4371,10 +4371,10 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
; SDAG-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v4i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v4i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4448,11 +4448,11 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v4i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1
; VI-NEXT: v_mov_b32_e32 v1, 2
@@ -4470,11 +4470,11 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v4i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v4i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1
; CI-NEXT: v_mov_b32_e32 v1, 2
@@ -4492,11 +4492,11 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v4i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v4i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1
; SDAG-NEXT: v_mov_b32_e32 v1, 2
@@ -4546,7 +4546,6 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v4i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v4i32 at rel32@hi+12
@@ -4554,6 +4553,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
; GISEL-NEXT: v_mov_b32_e32 v1, 2
; GISEL-NEXT: v_mov_b32_e32 v2, 3
; GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4571,11 +4571,11 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v5i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v5i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1
; VI-NEXT: v_mov_b32_e32 v1, 2
@@ -4594,11 +4594,11 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v5i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v5i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1
; CI-NEXT: v_mov_b32_e32 v1, 2
@@ -4617,11 +4617,11 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v5i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v5i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1
; SDAG-NEXT: v_mov_b32_e32 v1, 2
@@ -4674,7 +4674,6 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v5i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v5i32 at rel32@hi+12
@@ -4683,6 +4682,7 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; GISEL-NEXT: v_mov_b32_e32 v2, 3
; GISEL-NEXT: v_mov_b32_e32 v3, 4
; GISEL-NEXT: v_mov_b32_e32 v4, 5
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4707,10 +4707,10 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4731,10 +4731,10 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4755,10 +4755,10 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; SDAG-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; SDAG-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -4814,10 +4814,10 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
; GISEL-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0x0
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_mov_b32_e32 v1, s9
@@ -4846,11 +4846,11 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: v_mov_b32_e32 v0, 1
; VI-NEXT: v_mov_b32_e32 v1, 2
@@ -4872,11 +4872,11 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: v_mov_b32_e32 v0, 1
; CI-NEXT: v_mov_b32_e32 v1, 2
@@ -4898,11 +4898,11 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: v_mov_b32_e32 v0, 1
; SDAG-NEXT: v_mov_b32_e32 v1, 2
@@ -4962,7 +4962,6 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v8i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v8i32 at rel32@hi+12
@@ -4974,6 +4973,7 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; GISEL-NEXT: v_mov_b32_e32 v5, 6
; GISEL-NEXT: v_mov_b32_e32 v6, 7
; GISEL-NEXT: v_mov_b32_e32 v7, 8
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5000,10 +5000,10 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; VI-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
; VI-NEXT: buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v16i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v16i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5026,10 +5026,10 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; CI-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
; CI-NEXT: buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v16i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v16i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5052,10 +5052,10 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; SDAG-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 offset:32
; SDAG-NEXT: buffer_load_dwordx4 v[12:15], off, s[0:3], 0 offset:48
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v16i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v16i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5115,10 +5115,10 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; GISEL-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x0
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v16i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v16i32 at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_mov_b32_e32 v1, s9
@@ -5167,12 +5167,12 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; VI-NEXT: s_mov_b32 s39, 0xe80000
; VI-NEXT: s_add_u32 s36, s36, s3
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_getpc_b64 s[8:9]
; VI-NEXT: s_add_u32 s8, s8, external_void_func_v32i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s9, s9, external_void_func_v32i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_waitcnt vmcnt(6)
; VI-NEXT: buffer_store_dword v31, off, s[36:39], s32
@@ -5199,12 +5199,12 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; CI-NEXT: s_mov_b32 s39, 0xe8f000
; CI-NEXT: s_add_u32 s36, s36, s3
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_getpc_b64 s[8:9]
; CI-NEXT: s_add_u32 s8, s8, external_void_func_v32i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s9, s9, external_void_func_v32i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_waitcnt vmcnt(6)
; CI-NEXT: buffer_store_dword v31, off, s[36:39], s32
@@ -5231,12 +5231,12 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; SDAG-NEXT: s_mov_b32 s39, 0xe00000
; SDAG-NEXT: s_add_u32 s36, s36, s3
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_getpc_b64 s[8:9]
; SDAG-NEXT: s_add_u32 s8, s8, external_void_func_v32i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s9, s9, external_void_func_v32i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_waitcnt vmcnt(6)
; SDAG-NEXT: buffer_store_dword v31, off, s[36:39], s32
@@ -5309,11 +5309,10 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; GISEL-NEXT: s_load_dwordx16 s[36:51], s[0:1], 0x0
; GISEL-NEXT: s_mov_b32 s55, 0xe00000
; GISEL-NEXT: s_add_u32 s52, s52, s3
-; GISEL-NEXT: s_addc_u32 s53, s53, 0
; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_addc_u32 s53, s53, 0
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s23
-; GISEL-NEXT: s_mov_b64 s[0:1], s[52:53]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v32i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v32i32 at rel32@hi+12
@@ -5338,6 +5337,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; GISEL-NEXT: v_mov_b32_e32 v17, s9
; GISEL-NEXT: v_mov_b32_e32 v18, s10
; GISEL-NEXT: v_mov_b32_e32 v19, s11
+; GISEL-NEXT: s_mov_b64 s[0:1], s[52:53]
; GISEL-NEXT: s_mov_b64 s[2:3], s[54:55]
; GISEL-NEXT: v_mov_b32_e32 v20, s12
; GISEL-NEXT: v_mov_b32_e32 v21, s13
@@ -5380,12 +5380,12 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; VI-NEXT: buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
; VI-NEXT: buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
; VI-NEXT: buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v32i32_i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v32i32_i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_waitcnt vmcnt(8)
; VI-NEXT: buffer_store_dword v32, off, s[36:39], s32 offset:4
@@ -5415,12 +5415,12 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; CI-NEXT: buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
; CI-NEXT: buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
; CI-NEXT: buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v32i32_i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v32i32_i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_waitcnt vmcnt(8)
; CI-NEXT: buffer_store_dword v32, off, s[36:39], s32 offset:4
@@ -5450,12 +5450,12 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; SDAG-NEXT: buffer_load_dwordx4 v[16:19], off, s[4:7], 0 offset:64
; SDAG-NEXT: buffer_load_dwordx4 v[20:23], off, s[4:7], 0 offset:80
; SDAG-NEXT: buffer_load_dwordx4 v[24:27], off, s[4:7], 0 offset:96
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v32i32_i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v32i32_i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_waitcnt vmcnt(8)
; SDAG-NEXT: buffer_store_dword v32, off, s[36:39], s32 offset:4
@@ -5542,11 +5542,10 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GISEL-NEXT: s_addc_u32 s53, s53, 0
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-NEXT: ; kill: killed $sgpr0_sgpr1
-; GISEL-NEXT: ; kill: killed $sgpr0_sgpr1
; GISEL-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:4
; GISEL-NEXT: v_mov_b32_e32 v0, s23
-; GISEL-NEXT: s_mov_b64 s[0:1], s[52:53]
+; GISEL-NEXT: ; kill: killed $sgpr0_sgpr1
+; GISEL-NEXT: ; kill: killed $sgpr0_sgpr1
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v32i32_i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v32i32_i32 at rel32@hi+12
@@ -5571,6 +5570,7 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GISEL-NEXT: v_mov_b32_e32 v17, s9
; GISEL-NEXT: v_mov_b32_e32 v18, s10
; GISEL-NEXT: v_mov_b32_e32 v19, s11
+; GISEL-NEXT: s_mov_b64 s[0:1], s[52:53]
; GISEL-NEXT: s_mov_b64 s[2:3], s[54:55]
; GISEL-NEXT: v_mov_b32_e32 v20, s12
; GISEL-NEXT: v_mov_b32_e32 v21, s13
@@ -5599,14 +5599,14 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
; VI-NEXT: s_mov_b32 s49, SCRATCH_RSRC_DWORD1
; VI-NEXT: s_mov_b32 s50, -1
; VI-NEXT: s_mov_b32 s51, 0xe80000
-; VI-NEXT: s_add_u32 s48, s48, s5
; VI-NEXT: s_load_dwordx2 s[36:37], s[2:3], 0x24
+; VI-NEXT: s_add_u32 s48, s48, s5
; VI-NEXT: s_addc_u32 s49, s49, 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[48:49]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_i32_func_i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_i32_func_i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[48:49]
; VI-NEXT: s_mov_b64 s[2:3], s[50:51]
; VI-NEXT: v_mov_b32_e32 v0, 42
; VI-NEXT: s_mov_b32 s32, 0
@@ -5623,14 +5623,14 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
; CI-NEXT: s_mov_b32 s49, SCRATCH_RSRC_DWORD1
; CI-NEXT: s_mov_b32 s50, -1
; CI-NEXT: s_mov_b32 s51, 0xe8f000
-; CI-NEXT: s_add_u32 s48, s48, s5
; CI-NEXT: s_load_dwordx2 s[36:37], s[2:3], 0x9
+; CI-NEXT: s_add_u32 s48, s48, s5
; CI-NEXT: s_addc_u32 s49, s49, 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[48:49]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_i32_func_i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_i32_func_i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[48:49]
; CI-NEXT: s_mov_b64 s[2:3], s[50:51]
; CI-NEXT: v_mov_b32_e32 v0, 42
; CI-NEXT: s_mov_b32 s32, 0
@@ -5647,14 +5647,14 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
; SDAG-NEXT: s_mov_b32 s49, SCRATCH_RSRC_DWORD1
; SDAG-NEXT: s_mov_b32 s50, -1
; SDAG-NEXT: s_mov_b32 s51, 0xe00000
-; SDAG-NEXT: s_add_u32 s48, s48, s5
; SDAG-NEXT: s_load_dwordx2 s[36:37], s[2:3], 0x24
+; SDAG-NEXT: s_add_u32 s48, s48, s5
; SDAG-NEXT: s_addc_u32 s49, s49, 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[48:49]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_i32_func_i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_i32_func_i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[48:49]
; SDAG-NEXT: s_mov_b64 s[2:3], s[50:51]
; SDAG-NEXT: v_mov_b32_e32 v0, 42
; SDAG-NEXT: s_mov_b32 s32, 0
@@ -5708,15 +5708,15 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1)
; GISEL-NEXT: s_mov_b32 s49, SCRATCH_RSRC_DWORD1
; GISEL-NEXT: s_mov_b32 s50, -1
; GISEL-NEXT: s_mov_b32 s51, 0xe00000
-; GISEL-NEXT: s_add_u32 s48, s48, s5
; GISEL-NEXT: s_load_dwordx2 s[36:37], s[2:3], 0x24
+; GISEL-NEXT: s_add_u32 s48, s48, s5
; GISEL-NEXT: s_addc_u32 s49, s49, 0
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_i32_func_i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_i32_func_i32 at rel32@hi+12
; GISEL-NEXT: v_mov_b32_e32 v0, 42
+; GISEL-NEXT: s_mov_b64 s[0:1], s[48:49]
; GISEL-NEXT: s_mov_b64 s[2:3], s[50:51]
; GISEL-NEXT: s_mov_b32 s32, 0
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5746,10 +5746,10 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
; VI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:4
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_struct_i8_i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_struct_i8_i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5770,10 +5770,10 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; CI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
; CI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:4
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_struct_i8_i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_struct_i8_i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5794,10 +5794,10 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; SDAG-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
; SDAG-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:4
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_struct_i8_i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_struct_i8_i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -5870,10 +5870,10 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GISEL-NEXT: s_add_u32 s36, s36, s3
; GISEL-NEXT: s_addc_u32 s37, s37, 0
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[8:9]
; GISEL-NEXT: s_add_u32 s8, s8, external_void_func_struct_i8_i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s9, s9, external_void_func_struct_i8_i32 at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s4
@@ -5902,12 +5902,12 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
; VI-NEXT: buffer_store_dword v0, off, s[36:39], 0 offset:4
; VI-NEXT: buffer_load_dword v0, off, s[36:39], 0 offset:4
; VI-NEXT: buffer_load_dword v1, off, s[36:39], 0
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_movk_i32 s32, 0x400
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_byval_struct_i8_i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_byval_struct_i8_i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: buffer_store_dword v0, off, s[36:39], s32 offset:4
@@ -5930,12 +5930,12 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
; CI-NEXT: buffer_store_dword v0, off, s[36:39], 0 offset:4
; CI-NEXT: buffer_load_dword v0, off, s[36:39], 0 offset:4
; CI-NEXT: buffer_load_dword v1, off, s[36:39], 0
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_movk_i32 s32, 0x400
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_byval_struct_i8_i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_byval_struct_i8_i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: buffer_store_dword v0, off, s[36:39], s32 offset:4
@@ -5959,12 +5959,12 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
; SDAG-NEXT: buffer_load_dword v0, off, s[36:39], 0 offset:4
; SDAG-NEXT: s_nop 0
; SDAG-NEXT: buffer_load_dword v1, off, s[36:39], 0
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_movk_i32 s32, 0x400
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_byval_struct_i8_i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_byval_struct_i8_i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_waitcnt vmcnt(1)
; SDAG-NEXT: buffer_store_dword v0, off, s[36:39], s32 offset:4
@@ -6048,12 +6048,12 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
; GISEL-NEXT: buffer_load_dword v0, off, s[36:39], 0
; GISEL-NEXT: s_nop 0
; GISEL-NEXT: buffer_load_dword v1, off, s[36:39], 0 offset:4
-; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_movk_i32 s32, 0x400
+; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_byval_struct_i8_i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_byval_struct_i8_i32 at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_waitcnt vmcnt(1)
; GISEL-NEXT: buffer_store_dword v0, off, s[36:39], s32
@@ -6087,10 +6087,10 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
; VI-NEXT: buffer_load_dword v1, off, s[36:39], 0
; VI-NEXT: s_movk_i32 s32, 0x800
; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: buffer_store_dword v0, off, s[36:39], s32 offset:4
@@ -6125,10 +6125,10 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
; CI-NEXT: buffer_load_dword v1, off, s[36:39], 0
; CI-NEXT: s_movk_i32 s32, 0x800
; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: buffer_store_dword v0, off, s[36:39], s32 offset:4
@@ -6164,10 +6164,10 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
; SDAG-NEXT: buffer_load_dword v1, off, s[36:39], 0
; SDAG-NEXT: s_movk_i32 s32, 0x800
; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_waitcnt vmcnt(1)
; SDAG-NEXT: buffer_store_dword v0, off, s[36:39], s32 offset:4
@@ -6301,10 +6301,10 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
; GISEL-NEXT: buffer_load_dword v1, off, s[36:39], 0 offset:4
; GISEL-NEXT: s_movk_i32 s32, 0x800
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at rel32@hi+12
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_waitcnt vmcnt(1)
; GISEL-NEXT: buffer_store_dword v0, off, s[36:39], s32
@@ -6354,10 +6354,10 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_addc_u32 s37, s37, 0
-; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_v16i8 at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, external_void_func_v16i8 at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[0:1], s[36:37]
; VI-NEXT: s_mov_b64 s[2:3], s[38:39]
; VI-NEXT: s_mov_b32 s32, 0
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -6396,10 +6396,10 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_addc_u32 s37, s37, 0
-; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_v16i8 at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, external_void_func_v16i8 at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[0:1], s[36:37]
; CI-NEXT: s_mov_b64 s[2:3], s[38:39]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -6438,10 +6438,10 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; SDAG-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
; SDAG-NEXT: s_addc_u32 s37, s37, 0
-; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, external_void_func_v16i8 at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, external_void_func_v16i8 at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; SDAG-NEXT: s_mov_b32 s32, 0
; SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -6563,26 +6563,26 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
; GISEL-NEXT: s_lshr_b32 s17, s3, 8
; GISEL-NEXT: s_lshr_b32 s18, s3, 16
; GISEL-NEXT: s_lshr_b32 s19, s3, 24
-; GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-NEXT: v_mov_b32_e32 v4, s1
-; GISEL-NEXT: v_mov_b32_e32 v8, s2
-; GISEL-NEXT: v_mov_b32_e32 v12, s3
-; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, external_void_func_v16i8 at rel32@lo+4
; GISEL-NEXT: s_addc_u32 s5, s5, external_void_func_v16i8 at rel32@hi+12
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: v_mov_b32_e32 v1, s8
; GISEL-NEXT: v_mov_b32_e32 v2, s9
; GISEL-NEXT: v_mov_b32_e32 v3, s10
+; GISEL-NEXT: v_mov_b32_e32 v4, s1
; GISEL-NEXT: v_mov_b32_e32 v5, s11
; GISEL-NEXT: v_mov_b32_e32 v6, s12
; GISEL-NEXT: v_mov_b32_e32 v7, s13
+; GISEL-NEXT: v_mov_b32_e32 v8, s2
; GISEL-NEXT: v_mov_b32_e32 v9, s14
; GISEL-NEXT: v_mov_b32_e32 v10, s15
; GISEL-NEXT: v_mov_b32_e32 v11, s16
+; GISEL-NEXT: v_mov_b32_e32 v12, s3
; GISEL-NEXT: v_mov_b32_e32 v13, s17
; GISEL-NEXT: v_mov_b32_e32 v14, s18
; GISEL-NEXT: v_mov_b32_e32 v15, s19
+; GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GISEL-NEXT: s_endpgm
@@ -6611,12 +6611,12 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:4
; VI-NEXT: v_mov_b32_e32 v0, s5
-; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; VI-NEXT: s_mov_b64 s[0:1], s[52:53]
; VI-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:8
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, stack_passed_f64_arg at rel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, stack_passed_f64_arg at rel32@hi+12
+; VI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; VI-NEXT: s_mov_b64 s[0:1], s[52:53]
; VI-NEXT: s_mov_b64 s[2:3], s[54:55]
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
@@ -6670,12 +6670,12 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:4
; CI-NEXT: v_mov_b32_e32 v0, s5
-; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
-; CI-NEXT: s_mov_b64 s[0:1], s[52:53]
; CI-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:8
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, stack_passed_f64_arg at rel32@lo+4
; CI-NEXT: s_addc_u32 s5, s5, stack_passed_f64_arg at rel32@hi+12
+; CI-NEXT: s_mov_b64 s[6:7], s[0:1]
+; CI-NEXT: s_mov_b64 s[0:1], s[52:53]
; CI-NEXT: s_mov_b64 s[2:3], s[54:55]
; CI-NEXT: v_mov_b32_e32 v0, s36
; CI-NEXT: v_mov_b32_e32 v1, s37
@@ -6729,12 +6729,12 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
; SDAG-NEXT: v_mov_b32_e32 v0, s4
; SDAG-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:4
; SDAG-NEXT: v_mov_b32_e32 v0, s5
-; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
-; SDAG-NEXT: s_mov_b64 s[0:1], s[52:53]
; SDAG-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:8
; SDAG-NEXT: s_getpc_b64 s[4:5]
; SDAG-NEXT: s_add_u32 s4, s4, stack_passed_f64_arg at rel32@lo+4
; SDAG-NEXT: s_addc_u32 s5, s5, stack_passed_f64_arg at rel32@hi+12
+; SDAG-NEXT: s_mov_b64 s[6:7], s[0:1]
+; SDAG-NEXT: s_mov_b64 s[0:1], s[52:53]
; SDAG-NEXT: s_mov_b64 s[2:3], s[54:55]
; SDAG-NEXT: v_mov_b32_e32 v0, s36
; SDAG-NEXT: v_mov_b32_e32 v1, s37
@@ -6884,7 +6884,6 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:4
; GISEL-NEXT: v_mov_b32_e32 v0, s1
-; GISEL-NEXT: s_mov_b64 s[0:1], s[52:53]
; GISEL-NEXT: buffer_store_dword v0, off, s[52:55], s32 offset:8
; GISEL-NEXT: s_getpc_b64 s[4:5]
; GISEL-NEXT: s_add_u32 s4, s4, stack_passed_f64_arg at rel32@lo+4
@@ -6909,6 +6908,7 @@ define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val
; GISEL-NEXT: v_mov_b32_e32 v17, s9
; GISEL-NEXT: v_mov_b32_e32 v18, s10
; GISEL-NEXT: v_mov_b32_e32 v19, s11
+; GISEL-NEXT: s_mov_b64 s[0:1], s[52:53]
; GISEL-NEXT: s_mov_b64 s[2:3], s[54:55]
; GISEL-NEXT: v_mov_b32_e32 v20, s12
; GISEL-NEXT: v_mov_b32_e32 v21, s13
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 2beecd9a64afb..411468e07e131 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -210,14 +210,14 @@ define amdgpu_kernel void @call_coldcc() #0 {
; SI-NEXT: s_addc_u32 s5, s5, coldcc at gotpcrel32@hi+12
; SI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; SI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; SI-NEXT: s_mov_b32 s14, s10
-; SI-NEXT: s_mov_b64 s[10:11], s[6:7]
; SI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: s_mov_b32 s14, s10
+; SI-NEXT: s_mov_b64 s[10:11], s[6:7]
+; SI-NEXT: v_or_b32_e32 v31, v0, v2
; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_mov_b64 s[0:1], s[20:21]
-; SI-NEXT: v_or_b32_e32 v31, v0, v2
; SI-NEXT: s_mov_b64 s[2:3], s[22:23]
; SI-NEXT: v_mov_b32_e32 v0, 1.0
; SI-NEXT: s_mov_b32 s32, 0
@@ -245,14 +245,14 @@ define amdgpu_kernel void @call_coldcc() #0 {
; VI-NEXT: s_addc_u32 s5, s5, coldcc at gotpcrel32@hi+12
; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; VI-NEXT: s_mov_b32 s14, s10
-; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: s_mov_b32 s14, s10
+; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
+; VI-NEXT: v_or_b32_e32 v31, v0, v2
; VI-NEXT: s_mov_b64 s[4:5], s[0:1]
; VI-NEXT: s_mov_b64 s[6:7], s[2:3]
; VI-NEXT: s_mov_b64 s[0:1], s[88:89]
-; VI-NEXT: v_or_b32_e32 v31, v0, v2
; VI-NEXT: s_mov_b64 s[2:3], s[90:91]
; VI-NEXT: v_mov_b32_e32 v0, 1.0
; VI-NEXT: s_mov_b32 s32, 0
@@ -322,14 +322,14 @@ define amdgpu_kernel void @call_fastcc() #0 {
; SI-NEXT: s_addc_u32 s5, s5, fastcc at gotpcrel32@hi+12
; SI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; SI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; SI-NEXT: s_mov_b32 s14, s10
-; SI-NEXT: s_mov_b64 s[10:11], s[6:7]
; SI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: s_mov_b32 s14, s10
+; SI-NEXT: s_mov_b64 s[10:11], s[6:7]
+; SI-NEXT: v_or_b32_e32 v31, v0, v2
; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_mov_b64 s[0:1], s[20:21]
-; SI-NEXT: v_or_b32_e32 v31, v0, v2
; SI-NEXT: s_mov_b64 s[2:3], s[22:23]
; SI-NEXT: v_mov_b32_e32 v0, 1.0
; SI-NEXT: s_mov_b32 s32, 0
@@ -357,14 +357,14 @@ define amdgpu_kernel void @call_fastcc() #0 {
; VI-NEXT: s_addc_u32 s5, s5, fastcc at gotpcrel32@hi+12
; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; VI-NEXT: s_mov_b32 s14, s10
-; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: s_mov_b32 s14, s10
+; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
+; VI-NEXT: v_or_b32_e32 v31, v0, v2
; VI-NEXT: s_mov_b64 s[4:5], s[0:1]
; VI-NEXT: s_mov_b64 s[6:7], s[2:3]
; VI-NEXT: s_mov_b64 s[0:1], s[88:89]
-; VI-NEXT: v_or_b32_e32 v31, v0, v2
; VI-NEXT: s_mov_b64 s[2:3], s[90:91]
; VI-NEXT: v_mov_b32_e32 v0, 1.0
; VI-NEXT: s_mov_b32 s32, 0
diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
index 48f0ef41db527..a6d6abe6493c1 100644
--- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
@@ -107,8 +107,9 @@ define amdgpu_kernel void @sadd64rr(ptr addrspace(1) %out, i64 %a, i64 %b) {
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_add_u32 s2, s2, s4
; GFX11-NEXT: s_addc_u32 s3, s3, s5
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -252,8 +253,9 @@ define amdgpu_kernel void @sadd64ri(ptr addrspace(1) %out, i64 %a) {
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_add_u32 s2, s2, 0x56789876
; GFX11-NEXT: s_addc_u32 s3, s3, 0x1234
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -1404,8 +1406,9 @@ define amdgpu_kernel void @ssub64rr(ptr addrspace(1) %out, i64 %a, i64 %b) {
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_sub_u32 s2, s2, s4
; GFX11-NEXT: s_subb_u32 s3, s3, s5
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -1549,8 +1552,9 @@ define amdgpu_kernel void @ssub64ri(ptr addrspace(1) %out, i64 %a) {
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_sub_u32 s2, 0x56789876, s2
; GFX11-NEXT: s_subb_u32 s3, 0x1234, s3
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -3071,8 +3075,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX9-NEXT: s_cmp_ge_u32 s2, s6
; GFX9-NEXT: s_cselect_b32 s8, s4, s3
; GFX9-NEXT: .LBB16_5: ; %.split
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm
@@ -3228,8 +3232,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1010-NEXT: s_mov_b32 s5, 0
; GFX1010-NEXT: s_cselect_b32 s4, s4, s3
; GFX1010-NEXT: .LBB16_5: ; %.split
-; GFX1010-NEXT: v_mov_b32_e32 v0, s4
; GFX1010-NEXT: v_mov_b32_e32 v2, 0
+; GFX1010-NEXT: v_mov_b32_e32 v0, s4
; GFX1010-NEXT: v_mov_b32_e32 v1, s5
; GFX1010-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1010-NEXT: s_endpgm
@@ -3385,8 +3389,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1030W32-NEXT: s_cmp_ge_u32 s2, s4
; GFX1030W32-NEXT: s_cselect_b32 s6, s5, s3
; GFX1030W32-NEXT: .LBB16_5: ; %.split
-; GFX1030W32-NEXT: v_mov_b32_e32 v0, s6
; GFX1030W32-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030W32-NEXT: v_mov_b32_e32 v0, s6
; GFX1030W32-NEXT: v_mov_b32_e32 v1, s7
; GFX1030W32-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1030W32-NEXT: s_endpgm
@@ -3542,8 +3546,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1030W64-NEXT: s_cmp_ge_u32 s2, s4
; GFX1030W64-NEXT: s_cselect_b32 s6, s5, s3
; GFX1030W64-NEXT: .LBB16_5: ; %.split
-; GFX1030W64-NEXT: v_mov_b32_e32 v0, s6
; GFX1030W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX1030W64-NEXT: v_mov_b32_e32 v0, s6
; GFX1030W64-NEXT: v_mov_b32_e32 v1, s7
; GFX1030W64-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1030W64-NEXT: s_endpgm
@@ -3715,9 +3719,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX11-NEXT: s_cmp_ge_u32 s2, s4
; GFX11-NEXT: s_cselect_b32 s6, s5, s3
; GFX11-NEXT: .LBB16_5: ; %.split
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b32_e32 v0, s6
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s7
+; GFX11-NEXT: v_mov_b32_e32 v0, s6
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/cluster_stores.ll b/llvm/test/CodeGen/AMDGPU/cluster_stores.ll
index da5e73199a223..cb3e4ea36089d 100644
--- a/llvm/test/CodeGen/AMDGPU/cluster_stores.ll
+++ b/llvm/test/CodeGen/AMDGPU/cluster_stores.ll
@@ -54,13 +54,13 @@ define amdgpu_kernel void @cluster_load_cluster_store(ptr noalias %lb, ptr noali
; GFX10-NEXT: s_add_u32 s4, s0, 8
; GFX10-NEXT: s_addc_u32 s5, s1, 0
; GFX10-NEXT: s_add_u32 s6, s0, 16
-; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_addc_u32 s7, s1, 0
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_add_u32 s0, s0, 24
; GFX10-NEXT: v_mov_b32_e32 v2, s4
-; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v3, s5
+; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, s6
; GFX10-NEXT: v_mov_b32_e32 v5, s7
; GFX10-NEXT: v_mov_b32_e32 v7, s1
@@ -72,11 +72,11 @@ define amdgpu_kernel void @cluster_load_cluster_store(ptr noalias %lb, ptr noali
; GFX10-NEXT: flat_load_dword v11, v[6:7]
; GFX10-NEXT: s_add_u32 s0, s2, 8
; GFX10-NEXT: s_addc_u32 s1, s3, 0
-; GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: s_add_u32 s0, s2, 16
; GFX10-NEXT: s_addc_u32 s1, s3, 0
+; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: s_add_u32 s2, s2, 24
; GFX10-NEXT: s_addc_u32 s3, s3, 0
@@ -179,11 +179,11 @@ define amdgpu_kernel void @cluster_load_valu_cluster_store(ptr noalias %lb, ptr
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_u32 s4, s0, 8
; GFX10-NEXT: s_addc_u32 s5, s1, 0
-; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_add_u32 s6, s0, 16
+; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: v_mov_b32_e32 v3, s5
-; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: s_addc_u32 s7, s1, 0
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: s_add_u32 s0, s0, 24
; GFX10-NEXT: s_addc_u32 s1, s1, 0
@@ -199,18 +199,18 @@ define amdgpu_kernel void @cluster_load_valu_cluster_store(ptr noalias %lb, ptr
; GFX10-NEXT: s_add_u32 s0, s2, 8
; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_add_u32 s4, s2, 16
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: s_addc_u32 s5, s3, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-NEXT: v_mov_b32_e32 v1, s3
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_add_u32 s0, s2, 24
-; GFX10-NEXT: v_mov_b32_e32 v1, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s4
-; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: s_addc_u32 s1, s3, 0
+; GFX10-NEXT: v_mov_b32_e32 v7, s1
; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v6
-; GFX10-NEXT: v_mov_b32_e32 v7, s1
; GFX10-NEXT: v_mov_b32_e32 v6, s0
; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
; GFX10-NEXT: flat_store_dword v[0:1], v8
diff --git a/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll b/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
index 0d0fae932ed98..862385e565c77 100644
--- a/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+++ b/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
@@ -228,8 +228,8 @@ define void @private_alloca_to_flat(ptr %ptr) {
; GISEL-ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-ASM-NEXT: s_mov_b64 s[4:5], src_private_base
; GISEL-ASM-NEXT: s_lshr_b32 s4, s32, 6
-; GISEL-ASM-NEXT: v_mov_b32_e32 v0, s4
; GISEL-ASM-NEXT: v_mov_b32_e32 v2, 7
+; GISEL-ASM-NEXT: v_mov_b32_e32 v0, s4
; GISEL-ASM-NEXT: v_mov_b32_e32 v1, s5
; GISEL-ASM-NEXT: flat_store_dword v[0:1], v2
; GISEL-ASM-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index c554e26a43965..6bd189ec99e4c 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -1181,10 +1181,13 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 {
; GCN-O0-NEXT: s_mov_b32 s8, 0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7
; GCN-O0-NEXT: s_mov_b32 s5, s8
-; GCN-O0-NEXT: s_waitcnt expcnt(1)
+; GCN-O0-NEXT: s_waitcnt expcnt(4)
; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
+; GCN-O0-NEXT: s_waitcnt expcnt(3)
; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
+; GCN-O0-NEXT: s_waitcnt expcnt(2)
; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: s_waitcnt expcnt(1)
; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir b/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
index 46a72c032827c..004830397c98b 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
+++ b/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
@@ -15,7 +15,7 @@ body: |
; CHECK-LABEL: name: overlapping_copy_kill_undef_reg_after_copy
; CHECK: liveins: $sgpr30_sgpr31, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; CHECK-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr6_sgpr7, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
; CHECK-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $sgpr10_sgpr11, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
@@ -37,7 +37,7 @@ body: |
; CHECK-LABEL: name: nonoverlapping_copy_kill
; CHECK: liveins: $sgpr30_sgpr31, $sgpr4_sgpr5_sgpr6
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6, implicit-def $sgpr0_sgpr1_sgpr2
+ ; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6
; CHECK-NEXT: $sgpr2 = S_MOV_B32 $sgpr6, implicit killed $sgpr4_sgpr5_sgpr6
; CHECK-NEXT: renamable $sgpr1 = S_ADD_I32 0, $sgpr1, implicit-def $scc
; CHECK-NEXT: S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir b/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
index 5efeb8d40afbb..5286c6d34cf44 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
+++ b/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
@@ -15,7 +15,7 @@ body: |
; CHECK-LABEL: name: overlapping_copy_kill_undef_reg_after_copy
; CHECK: liveins: $sgpr30_sgpr31, $vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $vgpr1_vgpr2_vgpr3
; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr1_vgpr2_vgpr3
; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr1_vgpr2_vgpr3
; CHECK-NEXT: renamable $vgpr1 = nofpexcept V_MUL_F32_e32 0, $vgpr1, implicit $mode, implicit $exec
@@ -36,7 +36,7 @@ body: |
; CHECK-LABEL: name: overlapping_copy_kill_undef_reg_after_copy_1
; CHECK: liveins: $sgpr30_sgpr31, $vgpr2_vgpr3_vgpr4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr2_vgpr3_vgpr4
+ ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3_vgpr4
; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3_vgpr4
; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr2_vgpr3_vgpr4
; CHECK-NEXT: renamable $vgpr1 = nofpexcept V_MUL_F32_e32 0, $vgpr1, implicit $mode, implicit $exec
@@ -57,7 +57,7 @@ body: |
; CHECK-LABEL: name: nonoverlapping_copy_kill
; CHECK: liveins: $sgpr30_sgpr31, $vgpr3_vgpr4_vgpr5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr3_vgpr4_vgpr5
+ ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr3_vgpr4_vgpr5
; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr3_vgpr4_vgpr5
; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit killed $vgpr3_vgpr4_vgpr5
; CHECK-NEXT: renamable $vgpr1 = nofpexcept V_MUL_F32_e32 0, $vgpr1, implicit $mode, implicit $exec
@@ -78,7 +78,7 @@ body: |
; CHECK-LABEL: name: overlapping_copy_kill_half_s128
; CHECK: liveins: $sgpr30_sgpr31, $vgpr2_vgpr3_vgpr4_vgpr5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr2_vgpr3_vgpr4_vgpr5
+ ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; CHECK-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
diff --git a/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir b/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
index 9376a4c59c170..06a5cbbcb5238 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
+++ b/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
@@ -14,7 +14,7 @@ body: |
; CHECK-LABEL: name: copy_has_implicit_kill_superreg
; CHECK: renamable $vgpr7_vgpr8_vgpr9_vgpr10 = IMPLICIT_DEF
- ; CHECK-NEXT: $vgpr7 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit-def $vgpr7_vgpr8, implicit $vgpr10_vgpr11
+ ; CHECK-NEXT: $vgpr7 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit $vgpr10_vgpr11
; CHECK-NEXT: $vgpr8 = V_MOV_B32_e32 $vgpr11, implicit $exec, implicit killed $vgpr10_vgpr11, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr7
renamable $vgpr7_vgpr8_vgpr9_vgpr10 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir b/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
index cc976fe13c47c..daeffdd7917dc 100644
--- a/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
+++ b/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
@@ -15,7 +15,7 @@ body: |
; GFX908-LABEL: name: copy_v64_to_v64
; GFX908: liveins: $vgpr2_vgpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr2_vgpr3
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit killed $vgpr2_vgpr3, implicit $exec
;
; GFX90A-LABEL: name: copy_v64_to_v64
@@ -31,8 +31,9 @@ body: |
; GFX10-LABEL: name: copy_v64_to_v64
; GFX10: liveins: $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr2_vgpr3
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit killed $vgpr2_vgpr3, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v64_to_v64
; GFX1250: liveins: $vgpr2_vgpr3
; GFX1250-NEXT: {{ $}}
@@ -49,7 +50,7 @@ body: |
; GFX908-LABEL: name: copy_s64_to_v64
; GFX908: liveins: $sgpr2_sgpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr2_sgpr3
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr3, implicit $exec, implicit killed $sgpr2_sgpr3, implicit $exec
;
; GFX90A-LABEL: name: copy_s64_to_v64
@@ -65,8 +66,9 @@ body: |
; GFX10-LABEL: name: copy_s64_to_v64
; GFX10: liveins: $sgpr2_sgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr2_sgpr3
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr3, implicit $exec, implicit killed $sgpr2_sgpr3, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_s64_to_v64
; GFX1250: liveins: $sgpr2_sgpr3
; GFX1250-NEXT: {{ $}}
@@ -83,30 +85,31 @@ body: |
; GFX908-LABEL: name: copy_a64_to_v64
; GFX908: liveins: $agpr2_agpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr2_agpr3
+ ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr2_agpr3
; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr2_agpr3, implicit $exec
;
; GFX90A-LABEL: name: copy_a64_to_v64
; GFX90A: liveins: $agpr2_agpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr2_agpr3
+ ; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr2_agpr3
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr2_agpr3, implicit $exec
;
; GFX942-LABEL: name: copy_a64_to_v64
; GFX942: liveins: $agpr2_agpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr2_agpr3
+ ; GFX942-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr2_agpr3
; GFX942-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr2_agpr3, implicit $exec
;
; GFX10-LABEL: name: copy_a64_to_v64
; GFX10: liveins: $agpr2_agpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr2_agpr3
+ ; GFX10-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr2_agpr3
; GFX10-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr2_agpr3, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_a64_to_v64
; GFX1250: liveins: $agpr2_agpr3
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $agpr2_agpr3
+ ; GFX1250-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr2_agpr3
; GFX1250-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit killed $agpr2_agpr3, implicit $exec
$vgpr0_vgpr1 = COPY killed $agpr2_agpr3, implicit $exec
...
@@ -120,7 +123,7 @@ body: |
; GFX908-LABEL: name: copy_v128_to_v128_fwd
; GFX908: liveins: $vgpr2_vgpr3_vgpr4_vgpr5
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr2_vgpr3_vgpr4_vgpr5
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5, implicit $exec
@@ -128,26 +131,27 @@ body: |
; GFX90A-LABEL: name: copy_v128_to_v128_fwd
; GFX90A: liveins: $vgpr2_vgpr3_vgpr4_vgpr5
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0_vgpr1 = V_PK_MOV_B32 8, $vgpr2_vgpr3, 12, $vgpr2_vgpr3, 0, 0, 0, 0, 0, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX90A-NEXT: $vgpr0_vgpr1 = V_PK_MOV_B32 8, $vgpr2_vgpr3, 12, $vgpr2_vgpr3, 0, 0, 0, 0, 0, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX90A-NEXT: $vgpr2_vgpr3 = V_PK_MOV_B32 8, $vgpr4_vgpr5, 12, $vgpr4_vgpr5, 0, 0, 0, 0, 0, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5, implicit $exec
;
; GFX942-LABEL: name: copy_v128_to_v128_fwd
; GFX942: liveins: $vgpr2_vgpr3_vgpr4_vgpr5
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr2_vgpr3_vgpr4_vgpr5
+ ; GFX942-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX942-NEXT: $vgpr2_vgpr3 = V_MOV_B64_e32 $vgpr4_vgpr5, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5, implicit $exec
;
; GFX10-LABEL: name: copy_v128_to_v128_fwd
; GFX10: liveins: $vgpr2_vgpr3_vgpr4_vgpr5
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr2_vgpr3_vgpr4_vgpr5
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v128_to_v128_fwd
; GFX1250: liveins: $vgpr2_vgpr3_vgpr4_vgpr5
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr2_vgpr3_vgpr4_vgpr5
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5
; GFX1250-NEXT: $vgpr2_vgpr3 = V_MOV_B64_e32 $vgpr4_vgpr5, implicit $exec, implicit $vgpr2_vgpr3_vgpr4_vgpr5, implicit $exec
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY killed $vgpr2_vgpr3_vgpr4_vgpr5, implicit $exec
...
@@ -161,7 +165,7 @@ body: |
; GFX908-LABEL: name: copy_v128_to_v128_back
; GFX908: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr5 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX908-NEXT: $vgpr5 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
@@ -169,26 +173,27 @@ body: |
; GFX90A-LABEL: name: copy_v128_to_v128_back
; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr4_vgpr5 = V_PK_MOV_B32 8, $vgpr2_vgpr3, 12, $vgpr2_vgpr3, 0, 0, 0, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def $vgpr2_vgpr3_vgpr4_vgpr5
+ ; GFX90A-NEXT: $vgpr4_vgpr5 = V_PK_MOV_B32 8, $vgpr2_vgpr3, 12, $vgpr2_vgpr3, 0, 0, 0, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX90A-NEXT: $vgpr2_vgpr3 = V_PK_MOV_B32 8, $vgpr0_vgpr1, 12, $vgpr0_vgpr1, 0, 0, 0, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
;
; GFX942-LABEL: name: copy_v128_to_v128_back
; GFX942: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr4_vgpr5 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit-def $vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX942-NEXT: $vgpr4_vgpr5 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX942-NEXT: $vgpr2_vgpr3 = V_MOV_B64_e32 $vgpr0_vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
;
; GFX10-LABEL: name: copy_v128_to_v128_back
; GFX10: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr5 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX10-NEXT: $vgpr5 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v128_to_v128_back
; GFX1250: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr4_vgpr5 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit-def $vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX1250-NEXT: $vgpr4_vgpr5 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1250-NEXT: $vgpr2_vgpr3 = V_MOV_B64_e32 $vgpr0_vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
$vgpr2_vgpr3_vgpr4_vgpr5 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
...
@@ -202,34 +207,35 @@ body: |
; GFX908-LABEL: name: copy_v96_to_v96
; GFX908: liveins: $vgpr4_vgpr5_vgpr6
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr4_vgpr5_vgpr6
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6, implicit $exec
;
; GFX90A-LABEL: name: copy_v96_to_v96
; GFX90A: liveins: $vgpr4_vgpr5_vgpr6
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr4_vgpr5_vgpr6
+ ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6, implicit $exec
;
; GFX942-LABEL: name: copy_v96_to_v96
; GFX942: liveins: $vgpr4_vgpr5_vgpr6
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr4_vgpr5_vgpr6
+ ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6, implicit $exec
;
; GFX10-LABEL: name: copy_v96_to_v96
; GFX10: liveins: $vgpr4_vgpr5_vgpr6
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr4_vgpr5_vgpr6
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v96_to_v96
; GFX1250: liveins: $vgpr4_vgpr5_vgpr6
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr4_vgpr5_vgpr6
+ ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6, implicit $exec
$vgpr0_vgpr1_vgpr2 = COPY killed $vgpr4_vgpr5_vgpr6, implicit $exec
@@ -244,7 +250,7 @@ body: |
; GFX908-LABEL: name: copy_v64_to_v64_undef_sub0
; GFX908: liveins: $vgpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr2_vgpr3
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit killed $vgpr2_vgpr3, implicit $exec
;
; GFX90A-LABEL: name: copy_v64_to_v64_undef_sub0
@@ -260,8 +266,9 @@ body: |
; GFX10-LABEL: name: copy_v64_to_v64_undef_sub0
; GFX10: liveins: $vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr2_vgpr3
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit killed $vgpr2_vgpr3, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v64_to_v64_undef_sub0
; GFX1250: liveins: $vgpr3
; GFX1250-NEXT: {{ $}}
@@ -278,7 +285,7 @@ body: |
; GFX908-LABEL: name: copy_v64_to_v64_undef_sub1
; GFX908: liveins: $vgpr2
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr2_vgpr3
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit killed $vgpr2_vgpr3, implicit $exec
;
; GFX90A-LABEL: name: copy_v64_to_v64_undef_sub1
@@ -294,8 +301,9 @@ body: |
; GFX10-LABEL: name: copy_v64_to_v64_undef_sub1
; GFX10: liveins: $vgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr2_vgpr3
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit killed $vgpr2_vgpr3, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v64_to_v64_undef_sub1
; GFX1250: liveins: $vgpr2
; GFX1250-NEXT: {{ $}}
@@ -312,7 +320,7 @@ body: |
; GFX908-LABEL: name: copy_s128_to_v128_killed
; GFX908: liveins: $sgpr4_sgpr5_sgpr6_sgpr7
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr5, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr6, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr7, implicit $exec, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7
@@ -320,26 +328,27 @@ body: |
; GFX90A-LABEL: name: copy_s128_to_v128_killed
; GFX90A: liveins: $sgpr4_sgpr5_sgpr6_sgpr7
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0_vgpr1 = V_PK_MOV_B32 8, $sgpr4_sgpr5, 12, $sgpr4_sgpr5, 0, 0, 0, 0, 0, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX90A-NEXT: $vgpr0_vgpr1 = V_PK_MOV_B32 8, $sgpr4_sgpr5, 12, $sgpr4_sgpr5, 0, 0, 0, 0, 0, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX90A-NEXT: $vgpr2_vgpr3 = V_PK_MOV_B32 8, $sgpr6_sgpr7, 12, $sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7
;
; GFX942-LABEL: name: copy_s128_to_v128_killed
; GFX942: liveins: $sgpr4_sgpr5_sgpr6_sgpr7
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $sgpr4_sgpr5, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX942-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $sgpr4_sgpr5, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX942-NEXT: $vgpr2_vgpr3 = V_MOV_B64_e32 $sgpr6_sgpr7, implicit $exec, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7
;
; GFX10-LABEL: name: copy_s128_to_v128_killed
; GFX10: liveins: $sgpr4_sgpr5_sgpr6_sgpr7
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr5, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr6, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr7, implicit $exec, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7
+ ;
; GFX1250-LABEL: name: copy_s128_to_v128_killed
; GFX1250: liveins: $sgpr4_sgpr5_sgpr6_sgpr7
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $sgpr4_sgpr5, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $sgpr4_sgpr5, implicit $exec, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX1250-NEXT: $vgpr2_vgpr3 = V_MOV_B64_e32 $sgpr6_sgpr7, implicit $exec, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY killed $sgpr4_sgpr5_sgpr6_sgpr7
...
@@ -353,30 +362,31 @@ body: |
; GFX908-LABEL: name: copy_v64_to_v64_unaligned
; GFX908: liveins: $vgpr2_vgpr3
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $vgpr2_vgpr3
+ ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3, implicit $exec
;
; GFX90A-LABEL: name: copy_v64_to_v64_unaligned
; GFX90A: liveins: $vgpr2_vgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $vgpr2_vgpr3
+ ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3, implicit $exec
;
; GFX942-LABEL: name: copy_v64_to_v64_unaligned
; GFX942: liveins: $vgpr2_vgpr3
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $vgpr2_vgpr3
+ ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3, implicit $exec
;
; GFX10-LABEL: name: copy_v64_to_v64_unaligned
; GFX10: liveins: $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $vgpr2_vgpr3
+ ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v64_to_v64_unaligned
; GFX1250: liveins: $vgpr2_vgpr3
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $vgpr2_vgpr3
+ ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr2_vgpr3
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr2_vgpr3, implicit $exec
$vgpr1_vgpr2 = COPY killed $vgpr2_vgpr3, implicit $exec
...
@@ -390,30 +400,31 @@ body: |
; GFX908-LABEL: name: copy_v64_unaligned_to_v64
; GFX908: liveins: $vgpr3_vgpr4
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr3_vgpr4
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr3_vgpr4
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit killed $vgpr3_vgpr4, implicit $exec
;
; GFX90A-LABEL: name: copy_v64_unaligned_to_v64
; GFX90A: liveins: $vgpr3_vgpr4
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr3_vgpr4
+ ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr3_vgpr4
; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit killed $vgpr3_vgpr4, implicit $exec
;
; GFX942-LABEL: name: copy_v64_unaligned_to_v64
; GFX942: liveins: $vgpr3_vgpr4
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr3_vgpr4
+ ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr3_vgpr4
; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit killed $vgpr3_vgpr4, implicit $exec
;
; GFX10-LABEL: name: copy_v64_unaligned_to_v64
; GFX10: liveins: $vgpr3_vgpr4
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr3_vgpr4
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr3_vgpr4
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit killed $vgpr3_vgpr4, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v64_unaligned_to_v64
; GFX1250: liveins: $vgpr3_vgpr4
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr3_vgpr4
+ ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit $vgpr3_vgpr4
; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit killed $vgpr3_vgpr4, implicit $exec
$vgpr0_vgpr1 = COPY killed $vgpr3_vgpr4, implicit $exec
...
@@ -427,7 +438,7 @@ body: |
; GFX908-LABEL: name: copy_v128_to_v128_unaligned
; GFX908: liveins: $vgpr8_vgpr9_vgpr10_vgpr11
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX908-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr11, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10_vgpr11, implicit $exec
@@ -435,7 +446,7 @@ body: |
; GFX90A-LABEL: name: copy_v128_to_v128_unaligned
; GFX90A: liveins: $vgpr8_vgpr9_vgpr10_vgpr11
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX90A-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX90A-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr11, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10_vgpr11, implicit $exec
@@ -443,7 +454,7 @@ body: |
; GFX942-LABEL: name: copy_v128_to_v128_unaligned
; GFX942: liveins: $vgpr8_vgpr9_vgpr10_vgpr11
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX942-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX942-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr11, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10_vgpr11, implicit $exec
@@ -451,14 +462,15 @@ body: |
; GFX10-LABEL: name: copy_v128_to_v128_unaligned
; GFX10: liveins: $vgpr8_vgpr9_vgpr10_vgpr11
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX10-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr11, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10_vgpr11, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v128_to_v128_unaligned
; GFX1250: liveins: $vgpr8_vgpr9_vgpr10_vgpr11
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX1250-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit $vgpr8_vgpr9_vgpr10_vgpr11
; GFX1250-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr11, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10_vgpr11, implicit $exec
@@ -474,7 +486,7 @@ body: |
; GFX908-LABEL: name: copy_v128_unaligned_to_v128
; GFX908: liveins: $vgpr7_vgpr8_vgpr9_vgpr10
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr7_vgpr8_vgpr9_vgpr10
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9_vgpr10, implicit $exec
@@ -482,7 +494,7 @@ body: |
; GFX90A-LABEL: name: copy_v128_unaligned_to_v128
; GFX90A: liveins: $vgpr7_vgpr8_vgpr9_vgpr10
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr7_vgpr8_vgpr9_vgpr10
+ ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX90A-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9_vgpr10, implicit $exec
@@ -490,7 +502,7 @@ body: |
; GFX942-LABEL: name: copy_v128_unaligned_to_v128
; GFX942: liveins: $vgpr7_vgpr8_vgpr9_vgpr10
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr7_vgpr8_vgpr9_vgpr10
+ ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX942-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9_vgpr10, implicit $exec
@@ -498,14 +510,15 @@ body: |
; GFX10-LABEL: name: copy_v128_unaligned_to_v128
; GFX10: liveins: $vgpr7_vgpr8_vgpr9_vgpr10
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr7_vgpr8_vgpr9_vgpr10
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9_vgpr10, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v128_unaligned_to_v128
; GFX1250: liveins: $vgpr7_vgpr8_vgpr9_vgpr10
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr7_vgpr8_vgpr9_vgpr10
+ ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr7_vgpr8_vgpr9_vgpr10
; GFX1250-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9_vgpr10, implicit $exec
@@ -521,30 +534,31 @@ body: |
; GFX908-LABEL: name: copy_s64_to_v64_unaligned
; GFX908: liveins: $sgpr8_sgpr9
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr8_sgpr9
+ ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit killed $sgpr8_sgpr9, implicit $exec
;
; GFX90A-LABEL: name: copy_s64_to_v64_unaligned
; GFX90A: liveins: $sgpr8_sgpr9
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr8_sgpr9
+ ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit killed $sgpr8_sgpr9, implicit $exec
;
; GFX942-LABEL: name: copy_s64_to_v64_unaligned
; GFX942: liveins: $sgpr8_sgpr9
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr8_sgpr9
+ ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit killed $sgpr8_sgpr9, implicit $exec
;
; GFX10-LABEL: name: copy_s64_to_v64_unaligned
; GFX10: liveins: $sgpr8_sgpr9
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr8_sgpr9
+ ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit killed $sgpr8_sgpr9, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_s64_to_v64_unaligned
; GFX1250: liveins: $sgpr8_sgpr9
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr8_sgpr9
+ ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit killed $sgpr8_sgpr9, implicit $exec
$vgpr1_vgpr2 = COPY killed $sgpr8_sgpr9, implicit $exec
...
@@ -558,7 +572,7 @@ body: |
; GFX908-LABEL: name: copy_s128_to_v128_unaligned
; GFX908: liveins: $sgpr8_sgpr9_sgpr10_sgpr11
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $sgpr8_sgpr9_sgpr10_sgpr11
+ ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX908-NEXT: $vgpr4 = V_MOV_B32_e32 $sgpr11, implicit $exec, implicit killed $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
@@ -566,7 +580,7 @@ body: |
; GFX90A-LABEL: name: copy_s128_to_v128_unaligned
; GFX90A: liveins: $sgpr8_sgpr9_sgpr10_sgpr11
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $sgpr8_sgpr9_sgpr10_sgpr11
+ ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX90A-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX90A-NEXT: $vgpr4 = V_MOV_B32_e32 $sgpr11, implicit $exec, implicit killed $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
@@ -574,7 +588,7 @@ body: |
; GFX942-LABEL: name: copy_s128_to_v128_unaligned
; GFX942: liveins: $sgpr8_sgpr9_sgpr10_sgpr11
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $sgpr8_sgpr9_sgpr10_sgpr11
+ ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX942-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX942-NEXT: $vgpr4 = V_MOV_B32_e32 $sgpr11, implicit $exec, implicit killed $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
@@ -582,14 +596,15 @@ body: |
; GFX10-LABEL: name: copy_s128_to_v128_unaligned
; GFX10: liveins: $sgpr8_sgpr9_sgpr10_sgpr11
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $sgpr8_sgpr9_sgpr10_sgpr11
+ ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX10-NEXT: $vgpr4 = V_MOV_B32_e32 $sgpr11, implicit $exec, implicit killed $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_s128_to_v128_unaligned
; GFX1250: liveins: $sgpr8_sgpr9_sgpr10_sgpr11
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4, implicit $sgpr8_sgpr9_sgpr10_sgpr11
+ ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX1250-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
; GFX1250-NEXT: $vgpr4 = V_MOV_B32_e32 $sgpr11, implicit $exec, implicit killed $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
@@ -605,34 +620,35 @@ body: |
; GFX908-LABEL: name: copy_v96_to_v96_unaligned
; GFX908: liveins: $vgpr8_vgpr9_vgpr10
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $vgpr8_vgpr9_vgpr10
+ ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10, implicit $exec
;
; GFX90A-LABEL: name: copy_v96_to_v96_unaligned
; GFX90A: liveins: $vgpr8_vgpr9_vgpr10
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $vgpr8_vgpr9_vgpr10
+ ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX90A-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10, implicit $exec
;
; GFX942-LABEL: name: copy_v96_to_v96_unaligned
; GFX942: liveins: $vgpr8_vgpr9_vgpr10
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $vgpr8_vgpr9_vgpr10
+ ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX942-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10, implicit $exec
;
; GFX10-LABEL: name: copy_v96_to_v96_unaligned
; GFX10: liveins: $vgpr8_vgpr9_vgpr10
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $vgpr8_vgpr9_vgpr10
+ ; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v96_to_v96_unaligned
; GFX1250: liveins: $vgpr8_vgpr9_vgpr10
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $vgpr8_vgpr9_vgpr10
+ ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit $vgpr8_vgpr9_vgpr10
; GFX1250-NEXT: $vgpr3 = V_MOV_B32_e32 $vgpr10, implicit $exec, implicit killed $vgpr8_vgpr9_vgpr10, implicit $exec
$vgpr1_vgpr2_vgpr3 = COPY killed $vgpr8_vgpr9_vgpr10, implicit $exec
@@ -647,34 +663,35 @@ body: |
; GFX908-LABEL: name: copy_v96_unaligned_to_v96
; GFX908: liveins: $vgpr7_vgpr8_vgpr9
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr7_vgpr8_vgpr9
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9, implicit $exec
;
; GFX90A-LABEL: name: copy_v96_unaligned_to_v96
; GFX90A: liveins: $vgpr7_vgpr8_vgpr9
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr7_vgpr8_vgpr9
+ ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9, implicit $exec
;
; GFX942-LABEL: name: copy_v96_unaligned_to_v96
; GFX942: liveins: $vgpr7_vgpr8_vgpr9
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr7_vgpr8_vgpr9
+ ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9, implicit $exec
;
; GFX10-LABEL: name: copy_v96_unaligned_to_v96
; GFX10: liveins: $vgpr7_vgpr8_vgpr9
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr7_vgpr8_vgpr9
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_v96_unaligned_to_v96
; GFX1250: liveins: $vgpr7_vgpr8_vgpr9
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr7_vgpr8_vgpr9
+ ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr7, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr8, implicit $exec, implicit $vgpr7_vgpr8_vgpr9
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr9, implicit $exec, implicit killed $vgpr7_vgpr8_vgpr9, implicit $exec
$vgpr0_vgpr1_vgpr2 = COPY killed $vgpr7_vgpr8_vgpr9, implicit $exec
@@ -689,34 +706,35 @@ body: |
; GFX908-LABEL: name: copy_s96_to_v96
; GFX908: liveins: $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX908-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
;
; GFX90A-LABEL: name: copy_s96_to_v96
; GFX90A: liveins: $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX90A-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
;
; GFX942-LABEL: name: copy_s96_to_v96
; GFX942: liveins: $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
;
; GFX10-LABEL: name: copy_s96_to_v96
; GFX10: liveins: $sgpr0_sgpr1_sgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_s96_to_v96
; GFX1250: liveins: $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
$vgpr0_vgpr1_vgpr2 = COPY killed $sgpr0_sgpr1_sgpr2, implicit $exec
@@ -731,34 +749,35 @@ body: |
; GFX908-LABEL: name: copy_s96_to_v96_unaligned
; GFX908: liveins: $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: {{ $}}
- ; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX908-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
;
; GFX90A-LABEL: name: copy_s96_to_v96_unaligned
; GFX90A: liveins: $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX90A-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
;
; GFX942-LABEL: name: copy_s96_to_v96_unaligned
; GFX942: liveins: $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX942-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
;
; GFX10-LABEL: name: copy_s96_to_v96_unaligned
; GFX10: liveins: $sgpr0_sgpr1_sgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX10-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
+ ;
; GFX1250-LABEL: name: copy_s96_to_v96_unaligned
; GFX1250: liveins: $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX1250-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
$vgpr1_vgpr2_vgpr3 = COPY killed $sgpr0_sgpr1_sgpr2, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index 29ada652d2660..0a18071eb8d77 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -663,8 +663,8 @@ define amdgpu_kernel void @s_ctlz_i64(ptr addrspace(1) noalias %out, [8 x i32],
; GFX10-GISEL-NEXT: s_flbit_i32_b64 s0, s[0:1]
; GFX10-GISEL-NEXT: s_mov_b32 s1, 0
; GFX10-GISEL-NEXT: s_min_u32 s0, s0, 64
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX10-GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
index ed77cf3d0e052..cf2829bec71d9 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
@@ -704,8 +704,8 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i16_with_select(ptr addrspace(1) n
; VI-NEXT: s_add_u32 s4, s2, 1
; VI-NEXT: s_addc_u32 s5, s3, 0
; VI-NEXT: v_mov_b32_e32 v2, s4
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: flat_load_ubyte v3, v[0:1]
@@ -825,13 +825,13 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i32_with_select(ptr addrspace(1) n
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: s_add_u32 s4, s2, 3
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_addc_u32 s5, s3, 0
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: flat_load_ubyte v2, v[2:3]
@@ -987,18 +987,18 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i64_with_select(ptr addrspace(1) n
; VI-NEXT: v_mov_b32_e32 v9, s5
; VI-NEXT: v_mov_b32_e32 v8, s4
; VI-NEXT: s_add_u32 s4, s2, 3
+; VI-NEXT: s_addc_u32 s5, s3, 0
; VI-NEXT: flat_load_ubyte v10, v[0:1]
; VI-NEXT: flat_load_ubyte v11, v[2:3]
; VI-NEXT: flat_load_ubyte v12, v[4:5]
; VI-NEXT: flat_load_ubyte v6, v[6:7]
; VI-NEXT: flat_load_ubyte v7, v[8:9]
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: s_addc_u32 s5, s3, 0
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: v_mov_b32_e32 v2, s4
-; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_load_ubyte v8, v[0:1]
@@ -1233,8 +1233,8 @@ define amdgpu_kernel void @s_ctlz_zero_poison_i64(ptr addrspace(1) noalias %out,
; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_flbit_i32_b64 s0, s[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -2251,13 +2251,13 @@ define amdgpu_kernel void @s_ctlz_zero_poison_i18(ptr addrspace(1) noalias %out,
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b32 s2, s2, 14
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_flbit_i32_b32 s2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_flbit_i32_b32 s2, s2
; VI-NEXT: s_add_u32 s0, s0, 2
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_bfe_u32 s2, s2, 0x20010
+; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
diff --git a/llvm/test/CodeGen/AMDGPU/ctpop64.ll b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
index 9a3dd2c796ad9..6dd0c0fbaf5b6 100644
--- a/llvm/test/CodeGen/AMDGPU/ctpop64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
@@ -477,10 +477,10 @@ define amdgpu_kernel void @ctpop_i64_in_br(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: s_bcnt1_i32_b64 s4, s[6:7]
; SI-NEXT: s_mov_b32 s5, 0
; SI-NEXT: .LBB7_5: ; %endif
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
@@ -510,10 +510,10 @@ define amdgpu_kernel void @ctpop_i64_in_br(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: s_bcnt1_i32_b64 s4, s[6:7]
; VI-NEXT: s_mov_b32 s5, 0
; VI-NEXT: .LBB7_5: ; %endif
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/cttz.ll b/llvm/test/CodeGen/AMDGPU/cttz.ll
index dded2731c2b3e..2fb2140b5bec8 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz.ll
@@ -574,8 +574,8 @@ define amdgpu_kernel void @s_cttz_i64(ptr addrspace(1) noalias %out, [8 x i32],
; GFX10-GISEL-NEXT: s_ff1_i32_b64 s0, s[0:1]
; GFX10-GISEL-NEXT: s_mov_b32 s1, 0
; GFX10-GISEL-NEXT: s_min_u32 s0, s0, 64
-; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX10-GISEL-NEXT: s_endpgm
%cttz = call i64 @llvm.cttz.i64(i64 %val, i1 false)
diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
index bdc791256d978..4612d53b976ba 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
@@ -675,8 +675,8 @@ define amdgpu_kernel void @v_cttz_zero_poison_i16_with_select(ptr addrspace(1) n
; VI-NEXT: s_add_u32 s4, s2, 1
; VI-NEXT: s_addc_u32 s5, s3, 0
; VI-NEXT: v_mov_b32_e32 v2, s4
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: flat_load_ubyte v3, v[0:1]
@@ -790,13 +790,13 @@ define amdgpu_kernel void @v_cttz_zero_poison_i32_with_select(ptr addrspace(1) n
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: s_add_u32 s4, s2, 3
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_addc_u32 s5, s3, 0
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: flat_load_ubyte v2, v[2:3]
@@ -951,9 +951,10 @@ define amdgpu_kernel void @v_cttz_zero_poison_i64_with_select(ptr addrspace(1) n
; VI-NEXT: v_mov_b32_e32 v9, s5
; VI-NEXT: v_mov_b32_e32 v8, s4
; VI-NEXT: s_add_u32 s4, s2, 3
-; VI-NEXT: v_mov_b32_e32 v11, s3
; VI-NEXT: s_addc_u32 s5, s3, 0
+; VI-NEXT: v_mov_b32_e32 v11, s3
; VI-NEXT: v_mov_b32_e32 v10, s2
+; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: flat_load_ubyte v12, v[0:1]
; VI-NEXT: flat_load_ubyte v13, v[2:3]
; VI-NEXT: flat_load_ubyte v4, v[4:5]
@@ -961,7 +962,6 @@ define amdgpu_kernel void @v_cttz_zero_poison_i64_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v6, v[8:9]
; VI-NEXT: flat_load_ubyte v7, v[10:11]
; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v2, s2
@@ -1127,13 +1127,13 @@ define amdgpu_kernel void @v_cttz_i32_sel_eq_neg1(ptr addrspace(1) noalias %out,
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: s_add_u32 s4, s2, 3
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_addc_u32 s5, s3, 0
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: flat_load_ubyte v2, v[2:3]
@@ -1257,13 +1257,13 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_neg1(ptr addrspace(1) noalias %out,
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: s_add_u32 s4, s2, 3
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_addc_u32 s5, s3, 0
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: flat_load_ubyte v2, v[2:3]
@@ -1390,13 +1390,13 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: s_add_u32 s4, s2, 3
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_addc_u32 s5, s3, 0
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s2, 2
; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: flat_load_ubyte v2, v[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
index 014fae010c6fe..c903d5b8428c1 100644
--- a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
+++ b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
@@ -54,9 +54,9 @@ define amdgpu_kernel void @d16_load_same_order_group(ptr %in1, ptr %in2) {
; GFX11-NEXT: v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: flat_load_b32 v0, v[0:1]
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_mov_b32_e32 v3, s1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
@@ -75,9 +75,9 @@ define amdgpu_kernel void @d16_load_same_order_group(ptr %in1, ptr %in2) {
; GFX12-NEXT: v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: flat_load_b32 v0, v[0:1]
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: v_mov_b32_e32 v3, s1
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 1, v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
index 1576f5593a411..7b321141448de 100644
--- a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
+++ b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
@@ -5,8 +5,8 @@ define amdgpu_kernel void @private_load_maybe_divergent(ptr addrspace(4) %k, ptr
; GCN-LABEL: private_load_maybe_divergent:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_i32 s12, s12, s17
-; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]
; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]
; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]
; GCN-NEXT: s_add_u32 s20, s20, s17
; GCN-NEXT: s_addc_u32 s21, s21, 0
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index e3c8eaacf88fe..6d789f3499e20 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -178,9 +178,9 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[15:16]
; GFX9-NEXT: v_or3_b32 v2, v2, v6, v8
; GFX9-NEXT: v_and_b32_e32 v6, 1, v30
-; GFX9-NEXT: v_mov_b32_e32 v16, v7
; GFX9-NEXT: v_or3_b32 v3, v3, 0, v9
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v16, v7
; GFX9-NEXT: v_mov_b32_e32 v15, v6
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB0_3
@@ -1294,16 +1294,16 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc
; GFX9-G-NEXT: v_add_co_u32_e32 v24, vcc, -1, v18
+; GFX9-G-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v19, vcc
; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
; GFX9-G-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v20
-; GFX9-G-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v19, vcc
+; GFX9-G-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v4, vcc
; GFX9-G-NEXT: v_cndmask_b32_e64 v10, v0, v8, s[4:5]
; GFX9-G-NEXT: v_cndmask_b32_e64 v11, v1, v9, s[4:5]
-; GFX9-G-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v4, vcc
-; GFX9-G-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GFX9-G-NEXT: v_mov_b32_e32 v0, s8
; GFX9-G-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v5, vcc
+; GFX9-G-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX9-G-NEXT: v_mov_b32_e32 v9, 0
+; GFX9-G-NEXT: v_mov_b32_e32 v0, s8
; GFX9-G-NEXT: v_mov_b32_e32 v1, s9
; GFX9-G-NEXT: v_mov_b32_e32 v8, 1
; GFX9-G-NEXT: v_mov_b32_e32 v2, s10
@@ -1337,14 +1337,14 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_addc_co_u32_e32 v21, vcc, -1, v21, vcc
; GFX9-G-NEXT: v_addc_co_u32_e32 v22, vcc, -1, v22, vcc
; GFX9-G-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
-; GFX9-G-NEXT: v_lshlrev_b64 v[12:13], 1, v[12:13]
; GFX9-G-NEXT: v_or_b32_e32 v0, v20, v22
; GFX9-G-NEXT: v_or_b32_e32 v1, v21, v23
+; GFX9-G-NEXT: v_lshlrev_b64 v[12:13], 1, v[12:13]
; GFX9-G-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GFX9-G-NEXT: v_or_b32_e32 v12, v12, v8
; GFX9-G-NEXT: v_and_b32_e32 v8, 1, v28
-; GFX9-G-NEXT: v_mov_b32_e32 v0, v8
; GFX9-G-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GFX9-G-NEXT: v_mov_b32_e32 v0, v8
; GFX9-G-NEXT: v_mov_b32_e32 v1, v9
; GFX9-G-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GFX9-G-NEXT: s_cbranch_execnz .LBB0_3
@@ -2382,9 +2382,9 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
; GFX9-NEXT: v_or3_b32 v8, v8, v12, v0
; GFX9-NEXT: v_and_b32_e32 v12, 1, v26
-; GFX9-NEXT: v_mov_b32_e32 v17, v13
; GFX9-NEXT: v_or3_b32 v9, v9, 0, v1
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v17, v13
; GFX9-NEXT: v_mov_b32_e32 v16, v12
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB1_3
@@ -3334,17 +3334,17 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_or_b32_e32 v11, v9, v11
; GFX9-G-NEXT: v_lshlrev_b64 v[8:9], v14, v[0:1]
; GFX9-G-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
-; GFX9-G-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX9-G-NEXT: v_cndmask_b32_e32 v14, 0, v12, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v15, 0, v13, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GFX9-G-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
-; GFX9-G-NEXT: v_mov_b32_e32 v13, s11
; GFX9-G-NEXT: v_cndmask_b32_e32 v8, v8, v2, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v9, v9, v3, vcc
+; GFX9-G-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX9-G-NEXT: v_mov_b32_e32 v11, s9
; GFX9-G-NEXT: v_mov_b32_e32 v10, s8
+; GFX9-G-NEXT: v_mov_b32_e32 v13, s11
; GFX9-G-NEXT: v_mov_b32_e32 v12, s10
; GFX9-G-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-G-NEXT: s_xor_b64 s[12:13], exec, s[8:9]
@@ -3359,24 +3359,24 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_or_b32_e32 v10, v10, v12
; GFX9-G-NEXT: v_or_b32_e32 v11, v11, v13
; GFX9-G-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18
-; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
; GFX9-G-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc
; GFX9-G-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc
; GFX9-G-NEXT: v_add_co_u32_e32 v22, vcc, -1, v4
; GFX9-G-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v5, vcc
-; GFX9-G-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GFX9-G-NEXT: s_mov_b64 s[8:9], 0
; GFX9-G-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
; GFX9-G-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v6, vcc
-; GFX9-G-NEXT: v_mov_b32_e32 v13, s11
; GFX9-G-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[4:5]
; GFX9-G-NEXT: v_cndmask_b32_e64 v3, v3, v1, s[4:5]
; GFX9-G-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v7, vcc
+; GFX9-G-NEXT: s_mov_b64 s[10:11], s[8:9]
; GFX9-G-NEXT: v_mov_b32_e32 v1, 0
; GFX9-G-NEXT: v_mov_b32_e32 v11, s9
; GFX9-G-NEXT: v_mov_b32_e32 v10, s8
; GFX9-G-NEXT: v_mov_b32_e32 v0, 1
+; GFX9-G-NEXT: v_mov_b32_e32 v13, s11
; GFX9-G-NEXT: v_mov_b32_e32 v12, s10
; GFX9-G-NEXT: .LBB1_3: ; %udiv-do-while
; GFX9-G-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3413,8 +3413,8 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX9-G-NEXT: v_or_b32_e32 v8, v8, v0
; GFX9-G-NEXT: v_and_b32_e32 v0, 1, v12
-; GFX9-G-NEXT: v_mov_b32_e32 v11, v1
; GFX9-G-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GFX9-G-NEXT: v_mov_b32_e32 v11, v1
; GFX9-G-NEXT: v_mov_b32_e32 v10, v0
; GFX9-G-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GFX9-G-NEXT: s_cbranch_execnz .LBB1_3
diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
index c013a1d779f36..e0287b2d1b4f5 100644
--- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
@@ -176,10 +176,10 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23]
; SDAG-NEXT: v_or_b32_e32 v0, v0, v10
; SDAG-NEXT: v_and_b32_e32 v10, 1, v38
-; SDAG-NEXT: v_mov_b32_e32 v23, v11
; SDAG-NEXT: v_or_b32_e32 v1, v19, v1
; SDAG-NEXT: v_or_b32_e32 v0, v18, v0
; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; SDAG-NEXT: v_mov_b32_e32 v23, v11
; SDAG-NEXT: v_mov_b32_e32 v22, v10
; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SDAG-NEXT: s_cbranch_execnz .LBB0_3
@@ -363,11 +363,11 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_and_b32_e32 v39, v14, v2
; SDAG-NEXT: v_and_b32_e32 v12, 1, v14
; SDAG-NEXT: v_and_b32_e32 v38, v14, v3
-; SDAG-NEXT: v_mov_b32_e32 v15, v13
; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v16, v39, vcc
; SDAG-NEXT: v_or_b32_e32 v11, v7, v11
; SDAG-NEXT: v_or_b32_e32 v10, v6, v10
; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11]
+; SDAG-NEXT: v_mov_b32_e32 v15, v13
; SDAG-NEXT: v_mov_b32_e32 v14, v12
; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v38, vcc
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
@@ -533,16 +533,16 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cndmask_b32_e32 v22, 0, v22, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc
; GISEL-NEXT: v_add_i32_e32 v32, vcc, -1, v26
+; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v27, vcc
; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v28
-; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v27, vcc
+; GISEL-NEXT: v_addc_u32_e32 v34, vcc, -1, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v18, v0, v16, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v19, v1, v17, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v34, vcc, -1, v10, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_addc_u32_e32 v35, vcc, -1, v11, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v17, 0
+; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_mov_b32_e32 v1, s9
; GISEL-NEXT: v_mov_b32_e32 v16, 1
; GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -576,14 +576,14 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc
; GISEL-NEXT: v_addc_u32_e32 v30, vcc, -1, v30, vcc
; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc
-; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GISEL-NEXT: v_or_b32_e32 v0, v28, v30
; GISEL-NEXT: v_or_b32_e32 v1, v29, v31
+; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_or_b32_e32 v8, v8, v16
; GISEL-NEXT: v_and_b32_e32 v16, 1, v36
-; GISEL-NEXT: v_mov_b32_e32 v0, v16
; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v0, v16
; GISEL-NEXT: v_mov_b32_e32 v1, v17
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execnz .LBB0_3
@@ -723,16 +723,16 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc
; GISEL-NEXT: v_add_i32_e32 v30, vcc, -1, v22
+; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v23, vcc
; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v26
-; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v23, vcc
+; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v4, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, v0, v6, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v11, v1, v7, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v4, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v5, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v7, 0
+; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_mov_b32_e32 v1, s9
; GISEL-NEXT: v_mov_b32_e32 v6, 1
; GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -751,17 +751,17 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v31, v3, vcc
; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v32, v16, vcc
; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v33, v17, vcc
-; GISEL-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
; GISEL-NEXT: v_add_i32_e32 v26, vcc, -1, v26
+; GISEL-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
+; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc
; GISEL-NEXT: v_lshrrev_b32_e32 v6, 31, v13
; GISEL-NEXT: v_ashrrev_i32_e32 v34, 31, v0
-; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc
+; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc
; GISEL-NEXT: v_or_b32_e32 v14, v14, v6
; GISEL-NEXT: v_and_b32_e32 v6, 1, v34
-; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc
+; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc
; GISEL-NEXT: v_or_b32_e32 v13, v1, v11
; GISEL-NEXT: v_mov_b32_e32 v0, v6
-; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc
; GISEL-NEXT: v_mov_b32_e32 v1, v7
; GISEL-NEXT: v_and_b32_e32 v6, v34, v22
; GISEL-NEXT: v_or_b32_e32 v10, v26, v28
@@ -1028,10 +1028,10 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[24:25]
; SDAG-NEXT: v_or_b32_e32 v2, v2, v20
; SDAG-NEXT: v_and_b32_e32 v20, 1, v34
-; SDAG-NEXT: v_mov_b32_e32 v25, v21
; SDAG-NEXT: v_or_b32_e32 v3, v1, v3
; SDAG-NEXT: v_or_b32_e32 v2, v0, v2
; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; SDAG-NEXT: v_mov_b32_e32 v25, v21
; SDAG-NEXT: v_mov_b32_e32 v24, v20
; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SDAG-NEXT: s_cbranch_execnz .LBB2_3
@@ -1196,11 +1196,11 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_or_b32_e32 v22, v9, v25
; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[22:23]
; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v20, v31, vcc
-; SDAG-NEXT: v_mov_b32_e32 v23, v19
; SDAG-NEXT: v_or_b32_e32 v1, v5, v1
; SDAG-NEXT: v_or_b32_e32 v0, v4, v0
; SDAG-NEXT: v_subb_u32_e32 v21, vcc, v21, v30, vcc
; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11]
+; SDAG-NEXT: v_mov_b32_e32 v23, v19
; SDAG-NEXT: v_mov_b32_e32 v22, v18
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
; SDAG-NEXT: s_cbranch_execnz .LBB2_9
@@ -1305,17 +1305,17 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v19, v3, v19
; GISEL-NEXT: v_lshl_b64 v[2:3], v[0:1], v22
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v24
-; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13]
; GISEL-NEXT: v_cndmask_b32_e32 v22, 0, v20, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v23, 0, v21, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24
-; GISEL-NEXT: v_mov_b32_e32 v21, s15
; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
+; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13]
; GISEL-NEXT: v_mov_b32_e32 v19, s13
; GISEL-NEXT: v_mov_b32_e32 v18, s12
+; GISEL-NEXT: v_mov_b32_e32 v21, s15
; GISEL-NEXT: v_mov_b32_e32 v20, s14
; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9]
@@ -1330,24 +1330,24 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v18, v18, v20
; GISEL-NEXT: v_or_b32_e32 v19, v19, v21
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v26
-; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v25, 0, v25, vcc
; GISEL-NEXT: v_add_i32_e32 v30, vcc, -1, v8
; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v9, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v26
; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v10, vcc
-; GISEL-NEXT: v_mov_b32_e32 v21, s11
; GISEL-NEXT: v_cndmask_b32_e64 v16, v16, v0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v17, v17, v1, s[4:5]
; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v11, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v1, 0
; GISEL-NEXT: v_mov_b32_e32 v19, s9
; GISEL-NEXT: v_mov_b32_e32 v18, s8
; GISEL-NEXT: v_mov_b32_e32 v0, 1
+; GISEL-NEXT: v_mov_b32_e32 v21, s11
; GISEL-NEXT: v_mov_b32_e32 v20, s10
; GISEL-NEXT: .LBB2_3: ; %udiv-do-while3
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1384,8 +1384,8 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19]
; GISEL-NEXT: v_or_b32_e32 v2, v2, v0
; GISEL-NEXT: v_and_b32_e32 v0, 1, v20
-; GISEL-NEXT: v_mov_b32_e32 v19, v1
; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v19, v1
; GISEL-NEXT: v_mov_b32_e32 v18, v0
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execnz .LBB2_3
@@ -1477,17 +1477,17 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v23, v1, v9
; GISEL-NEXT: v_lshl_b64 v[8:9], v[4:5], v21
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v20
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v23, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v20
-; GISEL-NEXT: v_mov_b32_e32 v23, s11
; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v6, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v7, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v21, s9
; GISEL-NEXT: v_mov_b32_e32 v20, s8
+; GISEL-NEXT: v_mov_b32_e32 v23, s11
; GISEL-NEXT: v_mov_b32_e32 v22, s10
; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9]
@@ -1502,24 +1502,24 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v10, v10, v20
; GISEL-NEXT: v_or_b32_e32 v11, v11, v21
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v24
-; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v22, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v23, vcc
; GISEL-NEXT: v_add_i32_e32 v26, vcc, -1, v12
; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v13, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v24
; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v14, vcc
-; GISEL-NEXT: v_mov_b32_e32 v23, s11
; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[4:5]
; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v15, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v5, 0
; GISEL-NEXT: v_mov_b32_e32 v21, s9
; GISEL-NEXT: v_mov_b32_e32 v20, s8
; GISEL-NEXT: v_mov_b32_e32 v4, 1
+; GISEL-NEXT: v_mov_b32_e32 v23, s11
; GISEL-NEXT: v_mov_b32_e32 v22, s10
; GISEL-NEXT: .LBB2_9: ; %udiv-do-while
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1534,18 +1534,18 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v28, v10, vcc
; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v29, v11, vcc
; GISEL-NEXT: v_add_i32_e32 v24, vcc, -1, v24
+; GISEL-NEXT: v_addc_u32_e32 v25, vcc, -1, v25, vcc
; GISEL-NEXT: v_lshl_b64 v[6:7], v[0:1], 1
; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
-; GISEL-NEXT: v_addc_u32_e32 v25, vcc, -1, v25, vcc
-; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GISEL-NEXT: v_ashrrev_i32_e32 v30, 31, v4
; GISEL-NEXT: v_addc_u32_e32 v16, vcc, -1, v16, vcc
+; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v1
+; GISEL-NEXT: v_and_b32_e32 v4, 1, v30
+; GISEL-NEXT: v_addc_u32_e32 v17, vcc, -1, v17, vcc
; GISEL-NEXT: v_or_b32_e32 v8, v8, v0
; GISEL-NEXT: v_or_b32_e32 v0, v20, v6
; GISEL-NEXT: v_or_b32_e32 v1, v21, v7
-; GISEL-NEXT: v_and_b32_e32 v4, 1, v30
; GISEL-NEXT: v_mov_b32_e32 v21, v5
-; GISEL-NEXT: v_addc_u32_e32 v17, vcc, -1, v17, vcc
; GISEL-NEXT: v_mov_b32_e32 v20, v4
; GISEL-NEXT: v_and_b32_e32 v4, v30, v12
; GISEL-NEXT: v_or_b32_e32 v6, v24, v16
@@ -1794,10 +1794,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[26:27]
; SDAG-NEXT: v_or_b32_e32 v10, v10, v18
; SDAG-NEXT: v_and_b32_e32 v18, 1, v48
-; SDAG-NEXT: v_mov_b32_e32 v27, v19
; SDAG-NEXT: v_or_b32_e32 v11, v23, v11
; SDAG-NEXT: v_or_b32_e32 v10, v22, v10
; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; SDAG-NEXT: v_mov_b32_e32 v27, v19
; SDAG-NEXT: v_mov_b32_e32 v26, v18
; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SDAG-NEXT: s_cbranch_execnz .LBB4_3
@@ -1980,11 +1980,11 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_and_b32_e32 v22, v22, v36
; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v24, v22
; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v40, vcc
-; SDAG-NEXT: v_mov_b32_e32 v23, v19
; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v26, v55, vcc
; SDAG-NEXT: v_or_b32_e32 v17, v21, v17
; SDAG-NEXT: v_or_b32_e32 v16, v20, v16
; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11]
+; SDAG-NEXT: v_mov_b32_e32 v23, v19
; SDAG-NEXT: v_mov_b32_e32 v22, v18
; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v54, vcc
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
@@ -2195,16 +2195,16 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cndmask_b32_e32 v27, 0, v23, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v28, 0, v24, vcc
; GISEL-NEXT: v_add_i32_e32 v35, vcc, -1, v31
+; GISEL-NEXT: v_addc_u32_e32 v36, vcc, -1, v30, vcc
; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
-; GISEL-NEXT: v_addc_u32_e32 v36, vcc, -1, v30, vcc
+; GISEL-NEXT: v_addc_u32_e32 v37, vcc, -1, v16, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v25, v0, v10, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v26, v1, v11, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v37, vcc, -1, v16, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_addc_u32_e32 v38, vcc, -1, v17, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v24, 0
+; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_mov_b32_e32 v1, s9
; GISEL-NEXT: v_mov_b32_e32 v23, 1
; GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -2238,14 +2238,14 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc
; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
; GISEL-NEXT: v_addc_u32_e32 v34, vcc, -1, v34, vcc
-; GISEL-NEXT: v_lshl_b64 v[21:22], v[21:22], 1
; GISEL-NEXT: v_or_b32_e32 v0, v18, v33
; GISEL-NEXT: v_or_b32_e32 v1, v32, v34
+; GISEL-NEXT: v_lshl_b64 v[21:22], v[21:22], 1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_or_b32_e32 v21, v21, v23
; GISEL-NEXT: v_and_b32_e32 v23, 1, v39
-; GISEL-NEXT: v_mov_b32_e32 v0, v23
; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v0, v23
; GISEL-NEXT: v_mov_b32_e32 v1, v24
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execnz .LBB4_3
@@ -2385,16 +2385,16 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cndmask_b32_e32 v26, 0, v22, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v27, 0, v23, vcc
; GISEL-NEXT: v_add_i32_e32 v48, vcc, -1, v35
+; GISEL-NEXT: v_addc_u32_e32 v49, vcc, -1, v34, vcc
; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v36
-; GISEL-NEXT: v_addc_u32_e32 v49, vcc, -1, v34, vcc
+; GISEL-NEXT: v_addc_u32_e32 v50, vcc, -1, v12, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v24, v0, v6, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v25, v1, v7, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v50, vcc, -1, v12, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_addc_u32_e32 v51, vcc, -1, v13, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v23, 0
+; GISEL-NEXT: v_mov_b32_e32 v0, s8
; GISEL-NEXT: v_mov_b32_e32 v1, s9
; GISEL-NEXT: v_mov_b32_e32 v22, 1
; GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -2432,9 +2432,9 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_and_b32_e32 v52, v24, v13
; GISEL-NEXT: v_sub_i32_e32 v24, vcc, v0, v25
; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v1, v26, vcc
-; GISEL-NEXT: v_mov_b32_e32 v0, v22
; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v2, v27, vcc
; GISEL-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v0, v22
; GISEL-NEXT: v_mov_b32_e32 v1, v23
; GISEL-NEXT: v_subb_u32_e32 v27, vcc, v3, v52, vcc
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
@@ -2658,10 +2658,10 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[28:29]
; SDAG-NEXT: v_or_b32_e32 v16, v16, v20
; SDAG-NEXT: v_and_b32_e32 v20, 1, v38
-; SDAG-NEXT: v_mov_b32_e32 v29, v21
; SDAG-NEXT: v_or_b32_e32 v17, v25, v17
; SDAG-NEXT: v_or_b32_e32 v16, v24, v16
; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; SDAG-NEXT: v_mov_b32_e32 v29, v21
; SDAG-NEXT: v_mov_b32_e32 v28, v20
; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
; SDAG-NEXT: s_cbranch_execnz .LBB5_3
@@ -2825,11 +2825,11 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_and_b32_e32 v51, v28, v14
; SDAG-NEXT: v_and_b32_e32 v22, 1, v28
; SDAG-NEXT: v_and_b32_e32 v50, v28, v15
-; SDAG-NEXT: v_mov_b32_e32 v29, v23
; SDAG-NEXT: v_subb_u32_e32 v30, vcc, v30, v51, vcc
; SDAG-NEXT: v_or_b32_e32 v21, v25, v21
; SDAG-NEXT: v_or_b32_e32 v20, v24, v20
; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11]
+; SDAG-NEXT: v_mov_b32_e32 v29, v23
; SDAG-NEXT: v_mov_b32_e32 v28, v22
; SDAG-NEXT: v_subb_u32_e32 v31, vcc, v31, v50, vcc
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
@@ -2979,12 +2979,12 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v20
-; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13]
; GISEL-NEXT: v_cndmask_b32_e32 v23, v16, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v24, v17, v3, vcc
-; GISEL-NEXT: v_mov_b32_e32 v19, s15
+; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13]
; GISEL-NEXT: v_mov_b32_e32 v17, s13
; GISEL-NEXT: v_mov_b32_e32 v16, s12
+; GISEL-NEXT: v_mov_b32_e32 v19, s15
; GISEL-NEXT: v_mov_b32_e32 v18, s14
; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9]
@@ -2999,24 +2999,24 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v19, v17, v19
; GISEL-NEXT: v_lshr_b64 v[16:17], v[2:3], v20
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v29
-; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v27, 0, v27, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v28, 0, v28, vcc
; GISEL-NEXT: v_add_i32_e32 v33, vcc, -1, v8
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v29
; GISEL-NEXT: v_addc_u32_e32 v34, vcc, -1, v9, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GISEL-NEXT: v_mov_b32_e32 v19, 1
+; GISEL-NEXT: s_mov_b64 s[8:9], 0
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v29
+; GISEL-NEXT: v_addc_u32_e32 v35, vcc, -1, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v25, v16, v0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v26, v17, v1, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v35, vcc, -1, v10, vcc
-; GISEL-NEXT: v_mov_b32_e32 v19, s11
; GISEL-NEXT: v_addc_u32_e32 v36, vcc, -1, v11, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v19, 1
; GISEL-NEXT: v_mov_b32_e32 v20, 0
; GISEL-NEXT: v_mov_b32_e32 v17, s9
; GISEL-NEXT: v_mov_b32_e32 v16, s8
+; GISEL-NEXT: v_mov_b32_e32 v19, s11
; GISEL-NEXT: v_mov_b32_e32 v18, s10
; GISEL-NEXT: .LBB5_3: ; %udiv-do-while3
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3052,9 +3052,9 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_lshl_b64 v[23:24], v[23:24], 1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
; GISEL-NEXT: v_and_b32_e32 v19, 1, v38
-; GISEL-NEXT: v_mov_b32_e32 v16, v19
; GISEL-NEXT: v_or_b32_e32 v23, v23, v37
; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v16, v19
; GISEL-NEXT: v_mov_b32_e32 v17, v20
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execnz .LBB5_3
@@ -3151,12 +3151,12 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_cndmask_b32_e32 v24, v16, v6, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v25, v17, v7, vcc
-; GISEL-NEXT: v_mov_b32_e32 v19, s11
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v17, s9
; GISEL-NEXT: v_mov_b32_e32 v16, s8
+; GISEL-NEXT: v_mov_b32_e32 v19, s11
; GISEL-NEXT: v_mov_b32_e32 v18, s10
; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9]
@@ -3171,24 +3171,24 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v19, v17, v19
; GISEL-NEXT: v_lshr_b64 v[16:17], v[6:7], v28
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v34
-; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v30, 0, v26, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v31, 0, v27, vcc
; GISEL-NEXT: v_add_i32_e32 v38, vcc, -1, v12
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v34
; GISEL-NEXT: v_addc_u32_e32 v39, vcc, -1, v13, vcc
-; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GISEL-NEXT: s_mov_b64 s[8:9], 0
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v34
+; GISEL-NEXT: v_addc_u32_e32 v48, vcc, -1, v14, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v28, v16, v4, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v29, v17, v5, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v48, vcc, -1, v14, vcc
-; GISEL-NEXT: v_mov_b32_e32 v19, s11
; GISEL-NEXT: v_addc_u32_e32 v49, vcc, -1, v15, vcc
+; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v27, 0
; GISEL-NEXT: v_mov_b32_e32 v17, s9
; GISEL-NEXT: v_mov_b32_e32 v16, s8
; GISEL-NEXT: v_mov_b32_e32 v26, 1
+; GISEL-NEXT: v_mov_b32_e32 v19, s11
; GISEL-NEXT: v_mov_b32_e32 v18, s10
; GISEL-NEXT: .LBB5_9: ; %udiv-do-while
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3223,9 +3223,9 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_and_b32_e32 v50, v28, v15
; GISEL-NEXT: v_sub_i32_e32 v28, vcc, v16, v29
; GISEL-NEXT: v_subb_u32_e32 v29, vcc, v17, v30, vcc
-; GISEL-NEXT: v_mov_b32_e32 v16, v26
; GISEL-NEXT: v_subb_u32_e32 v30, vcc, v18, v31, vcc
; GISEL-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v16, v26
; GISEL-NEXT: v_mov_b32_e32 v17, v27
; GISEL-NEXT: v_subb_u32_e32 v31, vcc, v19, v50, vcc
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index 9f1b55ea3b1ef..4e54ad43ff2a9 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -1333,28 +1333,28 @@ define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspac
; CI-NEXT: s_mov_b32 s14, s10
; CI-NEXT: v_lshlrev_b32_e32 v3, 2, v0
; CI-NEXT: s_mov_b32 m0, -1
-; CI-NEXT: s_mov_b32 s12, s8
+; CI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_add_u32 s48, s48, s11
; CI-NEXT: s_mov_b64 s[10:11], s[6:7]
; CI-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x0
; CI-NEXT: s_load_dword s6, s[4:5], 0x2
; CI-NEXT: s_addc_u32 s49, s49, 0
+; CI-NEXT: s_mov_b32 s12, s8
; CI-NEXT: s_add_u32 s8, s4, 12
-; CI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; CI-NEXT: s_mov_b32 s13, s9
+; CI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_add_i32_e32 v40, vcc, s6, v3
; CI-NEXT: ds_read_b32 v41, v40
-; CI-NEXT: s_addc_u32 s9, s5, 0
-; CI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; CI-NEXT: v_or_b32_e32 v0, v0, v1
-; CI-NEXT: s_mov_b64 s[4:5], s[0:1]
-; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
-; CI-NEXT: s_mov_b64 s[0:1], s[48:49]
+; CI-NEXT: s_mov_b32 s13, s9
+; CI-NEXT: s_addc_u32 s9, s5, 0
; CI-NEXT: s_mov_b32 s17, void_func_void at abs32@hi
; CI-NEXT: s_mov_b32 s16, void_func_void at abs32@lo
; CI-NEXT: v_or_b32_e32 v31, v0, v2
+; CI-NEXT: s_mov_b64 s[4:5], s[0:1]
+; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
+; CI-NEXT: s_mov_b64 s[0:1], s[48:49]
; CI-NEXT: s_mov_b64 s[2:3], s[50:51]
; CI-NEXT: s_mov_b32 s32, 0
; CI-NEXT: s_mov_b32 s39, 0xf000
@@ -1373,8 +1373,8 @@ define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspac
; GFX9-NEXT: s_load_dwordx4 s[36:39], s[36:37], 0x0
; GFX9-NEXT: s_mov_b32 s14, s10
; GFX9-NEXT: s_mov_b32 s12, s8
-; GFX9-NEXT: s_mov_b32 s13, s9
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_add_u32 s36, s36, s11
; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
@@ -1382,17 +1382,17 @@ define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspac
; GFX9-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x0
; GFX9-NEXT: s_addc_u32 s37, s37, 0
; GFX9-NEXT: s_add_u32 s8, s4, 12
-; GFX9-NEXT: s_addc_u32 s9, s5, 0
+; GFX9-NEXT: s_mov_b32 s13, s9
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_lshl_add_u32 v41, v0, 2, s6
; GFX9-NEXT: ds_read_b32 v42, v41
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX9-NEXT: s_addc_u32 s9, s5, 0
; GFX9-NEXT: s_mov_b32 s17, void_func_void at abs32@hi
; GFX9-NEXT: s_mov_b32 s16, void_func_void at abs32@lo
; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
+; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
+; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
+; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: v_mov_b32_e32 v40, 0
diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2.ll b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
index b346d5ddb79aa..48d7444401e4a 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_write2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
@@ -1107,8 +1107,8 @@ define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {
; CI-LABEL: store_misaligned64_constant_large_offsets:
; CI: ; %bb.0:
; CI-NEXT: s_mov_b64 s[0:1], 0x7b
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v2, 0
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_write_b64 v2, v[0:1] offset:16384
@@ -1118,8 +1118,8 @@ define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {
; GFX9-LABEL: store_misaligned64_constant_large_offsets:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b64 s[0:1], 0x7b
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: ds_write_b64 v2, v[0:1] offset:16384
; GFX9-NEXT: ds_write_b64 v2, v[0:1] offset:32760
diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll b/llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
index 683887b0a55f3..e2bfb61783711 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
@@ -1024,10 +1024,10 @@ define void @ds_write2_b64_av_av_no_vgprs(ptr addrspace(3) %lds) #0 {
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GCN-NEXT: v_accvgpr_write_b32 a21, v31 ; Reload Reuse
-; GCN-NEXT: v_accvgpr_read_b32 v2, a2
-; GCN-NEXT: v_accvgpr_read_b32 v4, a4
; GCN-NEXT: v_accvgpr_read_b32 v0, a0
+; GCN-NEXT: v_accvgpr_read_b32 v2, a2
; GCN-NEXT: v_accvgpr_read_b32 v3, a3
+; GCN-NEXT: v_accvgpr_read_b32 v4, a4
; GCN-NEXT: v_accvgpr_read_b32 v5, a5
; GCN-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:10 offset1:24
; GCN-NEXT: v_accvgpr_write_b32 a31, v21 ; Reload Reuse
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index 732d112087e49..6e6c463cef0a4 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -123,9 +123,9 @@ define amdgpu_kernel void @double4_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_cmp_eq_u32 s2, 3
; GCN-NEXT: s_cselect_b32 s2, 0x40100a3d, s3
; GCN-NEXT: s_cselect_b32 s3, 0x70a3d70a, s4
-; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v0, s3
; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GCN-NEXT: s_endpgm
@@ -232,9 +232,9 @@ define amdgpu_kernel void @double5_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GCN-NEXT: s_cselect_b32 s2, 0x70a3d70a, s8
-; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s6
+; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GCN-NEXT: s_endpgm
@@ -408,8 +408,8 @@ define amdgpu_kernel void @float2_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_eq_u32 s2, 1
; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[2:3]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: flat_store_dword v[0:1], v2
; GCN-NEXT: s_endpgm
@@ -452,9 +452,9 @@ define amdgpu_kernel void @double2_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_cmp_eq_u32 s2, 1
; GCN-NEXT: s_cselect_b32 s2, s3, 0x3f847ae1
; GCN-NEXT: s_cselect_b32 s3, s4, 0x47ae147b
-; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v0, s3
; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GCN-NEXT: s_endpgm
@@ -754,15 +754,15 @@ define amdgpu_kernel void @double8_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
; GCN-NEXT: s_load_dword s18, s[4:5], 0x2c
-; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: s_mov_b32 s15, 0x40200000
+; GCN-NEXT: s_mov_b32 s1, 0x3ff00000
+; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: s_mov_b32 s13, 0x401c0000
; GCN-NEXT: s_mov_b32 s11, 0x40180000
; GCN-NEXT: s_mov_b32 s9, 0x40140000
; GCN-NEXT: s_mov_b32 s7, 0x40100000
; GCN-NEXT: s_mov_b32 s5, 0x40080000
; GCN-NEXT: s_mov_b32 s3, 2.0
-; GCN-NEXT: s_mov_b32 s1, 0x3ff00000
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s6, s0
@@ -906,6 +906,7 @@ define amdgpu_kernel void @double7_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x24
; GCN-NEXT: s_load_dword s16, s[4:5], 0x2c
+; GCN-NEXT: s_mov_b32 s1, 0x3ff00000
; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: s_mov_b32 s13, 0x401c0000
; GCN-NEXT: s_mov_b32 s11, 0x40180000
@@ -913,7 +914,6 @@ define amdgpu_kernel void @double7_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_mov_b32 s7, 0x40100000
; GCN-NEXT: s_mov_b32 s5, 0x40080000
; GCN-NEXT: s_mov_b32 s3, 2.0
-; GCN-NEXT: s_mov_b32 s1, 0x3ff00000
; GCN-NEXT: s_mov_b32 s2, s0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s6, s0
@@ -1154,6 +1154,7 @@ define amdgpu_kernel void @double15_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GCN-NEXT: s_mov_b32 s37, 0x3ff00000
; GCN-NEXT: s_mov_b32 s36, 0
; GCN-NEXT: s_mov_b32 s65, 0x402e0000
; GCN-NEXT: s_mov_b32 s63, 0x402c0000
@@ -1169,7 +1170,6 @@ define amdgpu_kernel void @double15_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_mov_b32 s43, 0x40100000
; GCN-NEXT: s_mov_b32 s41, 0x40080000
; GCN-NEXT: s_mov_b32 s39, 2.0
-; GCN-NEXT: s_mov_b32 s37, 0x3ff00000
; GCN-NEXT: s_mov_b32 s38, s36
; GCN-NEXT: s_mov_b32 s40, s36
; GCN-NEXT: s_mov_b32 s42, s36
@@ -1416,8 +1416,9 @@ define amdgpu_kernel void @double16_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-NEXT: s_mov_b32 s36, 0
; GCN-NEXT: s_mov_b32 s67, 0x40300000
+; GCN-NEXT: s_mov_b32 s37, 0x3ff00000
+; GCN-NEXT: s_mov_b32 s36, 0
; GCN-NEXT: s_mov_b32 s65, 0x402e0000
; GCN-NEXT: s_mov_b32 s63, 0x402c0000
; GCN-NEXT: s_mov_b32 s61, 0x402a0000
@@ -1432,7 +1433,6 @@ define amdgpu_kernel void @double16_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_mov_b32 s43, 0x40100000
; GCN-NEXT: s_mov_b32 s41, 0x40080000
; GCN-NEXT: s_mov_b32 s39, 2.0
-; GCN-NEXT: s_mov_b32 s37, 0x3ff00000
; GCN-NEXT: s_mov_b32 s38, s36
; GCN-NEXT: s_mov_b32 s40, s36
; GCN-NEXT: s_mov_b32 s42, s36
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
index 7993aa9d8c9d1..bbca95d12c251 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
@@ -408,8 +408,8 @@ define amdgpu_kernel void @dynamic_extract_vector_elt_v2i8(ptr addrspace(1) %out
; SI-NEXT: s_and_b32 s2, s2, 0xffff
; SI-NEXT: s_lshl_b32 s3, s3, 3
; SI-NEXT: s_lshr_b32 s2, s2, s3
-; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: flat_store_byte v[0:1], v2
@@ -427,8 +427,8 @@ define amdgpu_kernel void @dynamic_extract_vector_elt_v2i8(ptr addrspace(1) %out
; VI-NEXT: s_lshl_b32 s2, s2, 3
; VI-NEXT: s_and_b32 s3, s3, 0xffff
; VI-NEXT: s_lshr_b32 s2, s3, s2
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_byte v[0:1], v2
@@ -450,8 +450,8 @@ define amdgpu_kernel void @dynamic_extract_vector_elt_v3i8(ptr addrspace(1) %out
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b32 s2, s2, 3
; SI-NEXT: s_lshr_b32 s2, s3, s2
-; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: flat_store_byte v[0:1], v2
@@ -468,8 +468,8 @@ define amdgpu_kernel void @dynamic_extract_vector_elt_v3i8(ptr addrspace(1) %out
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b32 s2, s2, 3
; VI-NEXT: s_lshr_b32 s2, s3, s2
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_byte v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
index 8717e20ed0184..1b64be326d7d7 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
@@ -220,9 +220,9 @@ define amdgpu_kernel void @s_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat> %in
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s3, s3, 0x7fff7fff
; CI-NEXT: s_and_b32 s2, s2, 0x7fff7fff
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -246,9 +246,9 @@ define amdgpu_kernel void @s_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat> %in
; VI-NEXT: s_lshl_b32 s2, s2, 16
; VI-NEXT: s_or_b32 s3, s4, s3
; VI-NEXT: s_or_b32 s2, s5, s2
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
index dfd1fa6020eab..2209f726f6623 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
@@ -220,9 +220,9 @@ define amdgpu_kernel void @s_fabs_v4f16(ptr addrspace(1) %out, <4 x half> %in) {
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_and_b32 s3, s3, 0x7fff7fff
; CI-NEXT: s_and_b32 s2, s2, 0x7fff7fff
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -236,9 +236,9 @@ define amdgpu_kernel void @s_fabs_v4f16(ptr addrspace(1) %out, <4 x half> %in) {
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s3, s3, 0x7fff7fff
; VI-NEXT: s_and_b32 s2, s2, 0x7fff7fff
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.ll b/llvm/test/CodeGen/AMDGPU/fabs.ll
index f444b57206994..dfa4a72c8a5f3 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.ll
@@ -86,9 +86,9 @@ define amdgpu_kernel void @fabs_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset0_b32 s3, 31
; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
index 52bcaed7ec75a..5259d20664d3f 100644
--- a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
+++ b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
@@ -79,13 +79,13 @@ define amdgpu_kernel void @global_store_2xi16_align2(ptr addrspace(1) %p, ptr ad
; GFX7-ALIGNED-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, 1
; GFX7-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0
; GFX7-ALIGNED-NEXT: s_add_u32 s2, s0, 2
+; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1
; GFX7-ALIGNED-NEXT: s_addc_u32 s3, s1, 0
; GFX7-ALIGNED-NEXT: flat_store_short v[0:1], v2
-; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s2
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, 2
+; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s2
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s3
; GFX7-ALIGNED-NEXT: flat_store_short v[0:1], v2
; GFX7-ALIGNED-NEXT: s_endpgm
@@ -228,23 +228,23 @@ define amdgpu_kernel void @global_store_2xi16_align1(ptr addrspace(1) %p, ptr ad
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, 1
; GFX7-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-ALIGNED-NEXT: s_add_u32 s2, s0, 2
-; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0
; GFX7-ALIGNED-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1
; GFX7-ALIGNED-NEXT: s_add_u32 s4, s0, 1
-; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v2
; GFX7-ALIGNED-NEXT: s_addc_u32 s5, s1, 0
-; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-ALIGNED-NEXT: s_add_u32 s0, s0, 3
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v3, 0
+; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v2
+; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s4
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s5
-; GFX7-ALIGNED-NEXT: s_add_u32 s0, s0, 3
-; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v3
; GFX7-ALIGNED-NEXT: s_addc_u32 s1, s1, 0
+; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v3
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1
; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v3
-; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s2
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, 2
+; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s2
; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s3
; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v2
; GFX7-ALIGNED-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
index d82756506ff73..283af41020043 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
@@ -1383,9 +1383,9 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f32_dyn
; GFX678-SDAG-NEXT: s_mov_b32 s2, 0x7fffff
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s2
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s2
; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX678-SDAG-NEXT: flat_store_dword v[0:1], v2
; GFX678-SDAG-NEXT: s_endpgm
@@ -1393,13 +1393,13 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f32_dyn
; GFX678-GISEL-LABEL: test_no_denormals_fold_canonicalize_denormal0_f32_dynamic:
; GFX678-GISEL: ; %bb.0:
; GFX678-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fffff
; GFX678-GISEL-NEXT: s_add_i32 s12, s12, s17
-; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fffff
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX678-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX678-GISEL-NEXT: s_endpgm
@@ -1512,9 +1512,9 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f32_dyn
; GFX678-SDAG-NEXT: s_mov_b32 s2, 0x7fffff
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s2
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s2
; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX678-SDAG-NEXT: flat_store_dword v[0:1], v2
; GFX678-SDAG-NEXT: s_endpgm
@@ -1522,13 +1522,13 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f32_dyn
; GFX678-GISEL-LABEL: test_no_denormals_fold_canonicalize_denormal0_f32_dynamic_out:
; GFX678-GISEL: ; %bb.0:
; GFX678-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fffff
; GFX678-GISEL-NEXT: s_add_i32 s12, s12, s17
-; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fffff
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX678-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX678-GISEL-NEXT: s_endpgm
@@ -1641,9 +1641,9 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f32_dyn
; GFX678-SDAG-NEXT: s_mov_b32 s2, 0x7fffff
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s2
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-SDAG-NEXT: v_mul_f32_e64 v2, 1.0, s2
; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX678-SDAG-NEXT: flat_store_dword v[0:1], v2
; GFX678-SDAG-NEXT: s_endpgm
@@ -1651,13 +1651,13 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f32_dyn
; GFX678-GISEL-LABEL: test_no_denormals_fold_canonicalize_denormal0_f32_dynamic_in:
; GFX678-GISEL: ; %bb.0:
; GFX678-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fffff
; GFX678-GISEL-NEXT: s_add_i32 s12, s12, s17
-; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fffff
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX678-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX678-GISEL-NEXT: s_endpgm
@@ -2437,13 +2437,13 @@ define amdgpu_kernel void @test_fold_canonicalize_snan0_value_f32(ptr addrspace(
; GFX678-GISEL-LABEL: test_fold_canonicalize_snan0_value_f32:
; GFX678-GISEL: ; %bb.0:
; GFX678-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7f800001
; GFX678-GISEL-NEXT: s_add_i32 s12, s12, s17
-; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7f800001
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX678-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX678-GISEL-NEXT: s_endpgm
@@ -2560,13 +2560,13 @@ define amdgpu_kernel void @test_fold_canonicalize_snan1_value_f32(ptr addrspace(
; GFX678-GISEL-LABEL: test_fold_canonicalize_snan1_value_f32:
; GFX678-GISEL: ; %bb.0:
; GFX678-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fbfffff
; GFX678-GISEL-NEXT: s_add_i32 s12, s12, s17
-; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0x7fbfffff
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX678-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX678-GISEL-NEXT: s_endpgm
@@ -2683,13 +2683,13 @@ define amdgpu_kernel void @test_fold_canonicalize_snan2_value_f32(ptr addrspace(
; GFX678-GISEL-LABEL: test_fold_canonicalize_snan2_value_f32:
; GFX678-GISEL: ; %bb.0:
; GFX678-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800001
; GFX678-GISEL-NEXT: s_add_i32 s12, s12, s17
-; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800001
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX678-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX678-GISEL-NEXT: s_endpgm
@@ -2806,13 +2806,13 @@ define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f32(ptr addrspace(
; GFX678-GISEL-LABEL: test_fold_canonicalize_snan3_value_f32:
; GFX678-GISEL: ; %bb.0:
; GFX678-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0xffbfffff
; GFX678-GISEL-NEXT: s_add_i32 s12, s12, s17
-; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0xffbfffff
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-GISEL-NEXT: v_mul_f32_e32 v2, 1.0, v0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX678-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX678-GISEL-NEXT: s_endpgm
@@ -3605,9 +3605,9 @@ define amdgpu_kernel void @test_fold_canonicalize_p0_f64(ptr addrspace(1) %out)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, v0
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, v0
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -3619,9 +3619,9 @@ define amdgpu_kernel void @test_fold_canonicalize_p0_f64(ptr addrspace(1) %out)
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX678-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX678-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-GISEL-NEXT: s_endpgm
@@ -3735,9 +3735,9 @@ define amdgpu_kernel void @test_fold_canonicalize_n0_f64(ptr addrspace(1) %out)
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-NEXT: v_bfrev_b32_e32 v1, 1
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_bfrev_b32_e32 v1, 1
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -3851,9 +3851,9 @@ define amdgpu_kernel void @test_fold_canonicalize_p1_f64(ptr addrspace(1) %out)
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-NEXT: v_mov_b32_e32 v1, 0x3ff00000
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_mov_b32_e32 v1, 0x3ff00000
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -3963,9 +3963,9 @@ define amdgpu_kernel void @test_fold_canonicalize_n1_f64(ptr addrspace(1) %out)
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-NEXT: v_mov_b32_e32 v1, 0xbff00000
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_mov_b32_e32 v1, 0xbff00000
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -4075,9 +4075,9 @@ define amdgpu_kernel void @test_fold_canonicalize_literal_f64(ptr addrspace(1) %
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-NEXT: v_mov_b32_e32 v1, 0x40300000
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_mov_b32_e32 v1, 0x40300000
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -4187,9 +4187,9 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f64(ptr
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, v0
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, v0
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -4201,9 +4201,9 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_f64(ptr
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX678-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX678-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-GISEL-NEXT: s_endpgm
@@ -4317,9 +4317,9 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_f64(ptr ad
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, -1
+; GFX678-NEXT: v_mov_b32_e32 v1, 0xfffff
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_mov_b32_e32 v1, 0xfffff
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -4432,9 +4432,9 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal1_f64(ptr
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-NEXT: v_bfrev_b32_e32 v1, 1
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_bfrev_b32_e32 v1, 1
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -4548,9 +4548,9 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_f64(ptr ad
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, -1
+; GFX678-NEXT: v_mov_b32_e32 v1, 0x800fffff
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_mov_b32_e32 v1, 0x800fffff
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -4663,9 +4663,9 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_f64(ptr addrspace(1) %out
; GFX678-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-NEXT: v_mov_b32_e32 v2, s0
; GFX678-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-NEXT: s_endpgm
@@ -4775,9 +4775,9 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_f64(ptr addrsp
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -4789,9 +4789,9 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_f64(ptr addrsp
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, -1
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, -1
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, -1
; GFX678-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX678-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-GISEL-NEXT: s_endpgm
@@ -4901,9 +4901,9 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_f64(ptr addrsp
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -4915,9 +4915,9 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_f64(ptr addrsp
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, -2
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, -1
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, -1
; GFX678-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX678-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-GISEL-NEXT: s_endpgm
@@ -5027,9 +5027,9 @@ define amdgpu_kernel void @test_fold_canonicalize_snan0_value_f64(ptr addrspace(
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -5041,10 +5041,10 @@ define amdgpu_kernel void @test_fold_canonicalize_snan0_value_f64(ptr addrspace(
; GFX6-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff00000
; GFX6-GISEL-NEXT: s_add_i32 s12, s12, s17
; GFX6-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX6-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX6-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX6-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX6-GISEL-NEXT: s_endpgm
@@ -5178,9 +5178,9 @@ define amdgpu_kernel void @test_fold_canonicalize_snan1_value_f64(ptr addrspace(
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -5192,9 +5192,9 @@ define amdgpu_kernel void @test_fold_canonicalize_snan1_value_f64(ptr addrspace(
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, -1
+; GFX678-GISEL-NEXT: v_bfrev_b32_e32 v1, -2
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-GISEL-NEXT: v_bfrev_b32_e32 v1, -2
; GFX678-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX678-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-GISEL-NEXT: s_endpgm
@@ -5306,9 +5306,9 @@ define amdgpu_kernel void @test_fold_canonicalize_snan2_value_f64(ptr addrspace(
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -5320,10 +5320,10 @@ define amdgpu_kernel void @test_fold_canonicalize_snan2_value_f64(ptr addrspace(
; GFX6-GISEL-NEXT: v_mov_b32_e32 v1, 0xfff00000
; GFX6-GISEL-NEXT: s_add_i32 s12, s12, s17
; GFX6-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX6-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX6-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX6-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX6-GISEL-NEXT: s_endpgm
@@ -5457,9 +5457,9 @@ define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f64(ptr addrspace(
; GFX678-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000
; GFX678-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX678-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-SDAG-NEXT: s_endpgm
@@ -5471,9 +5471,9 @@ define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f64(ptr addrspace(
; GFX678-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX678-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX678-GISEL-NEXT: v_mov_b32_e32 v0, -1
+; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, -1
; GFX678-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX678-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX678-GISEL-NEXT: v_mov_b32_e32 v1, -1
; GFX678-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX678-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX678-GISEL-NEXT: s_endpgm
@@ -6900,8 +6900,8 @@ define amdgpu_kernel void @v_test_canonicalize_var_v2f64(ptr addrspace(1) %out)
; GFX6-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX6-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX6-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX6-GISEL-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; GFX6-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX6-GISEL-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
@@ -6939,8 +6939,8 @@ define amdgpu_kernel void @v_test_canonicalize_var_v2f64(ptr addrspace(1) %out)
; GFX8-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX8-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, s1
; GFX8-GISEL-NEXT: v_add_u32_e32 v0, vcc, v4, v0
; GFX8-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-GISEL-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/fceil64.ll b/llvm/test/CodeGen/AMDGPU/fceil64.ll
index dc1a829428724..4910cd81c6b2f 100644
--- a/llvm/test/CodeGen/AMDGPU/fceil64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fceil64.ll
@@ -28,8 +28,8 @@ define amdgpu_kernel void @fceil_f64(ptr addrspace(1) %out, double %x) {
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cmp_gt_i32 s8, 51
-; SI-NEXT: s_cselect_b32 s8, s2, s4
; SI-NEXT: s_cselect_b32 s9, s3, s5
+; SI-NEXT: s_cselect_b32 s8, s2, s4
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[0:1]
@@ -66,8 +66,8 @@ define amdgpu_kernel void @fceil_v2f64(ptr addrspace(1) %out, <2 x double> %x) {
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s12, 51
-; SI-NEXT: s_cselect_b32 s12, s10, s0
; SI-NEXT: s_cselect_b32 s13, s11, s1
+; SI-NEXT: s_cselect_b32 s12, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_mov_b32_e32 v1, s13
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
@@ -86,8 +86,8 @@ define amdgpu_kernel void @fceil_v2f64(ptr addrspace(1) %out, <2 x double> %x) {
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s6, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: s_cselect_b32 s5, s9, s5
+; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[2:3]
@@ -136,8 +136,8 @@ define amdgpu_kernel void @fceil_v4f64(ptr addrspace(1) %out, <4 x double> %x) {
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s16, 51
-; SI-NEXT: s_cselect_b32 s16, s10, s0
; SI-NEXT: s_cselect_b32 s17, s11, s1
+; SI-NEXT: s_cselect_b32 s16, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
@@ -156,8 +156,8 @@ define amdgpu_kernel void @fceil_v4f64(ptr addrspace(1) %out, <4 x double> %x) {
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: s_cselect_b32 s5, s9, s5
+; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]
@@ -176,8 +176,8 @@ define amdgpu_kernel void @fceil_v4f64(ptr addrspace(1) %out, <4 x double> %x) {
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: s_cselect_b32 s9, s15, s9
+; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]
@@ -236,8 +236,8 @@ define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s24, 51
-; SI-NEXT: s_cselect_b32 s24, s10, s0
; SI-NEXT: s_cselect_b32 s25, s11, s1
+; SI-NEXT: s_cselect_b32 s24, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s24
; SI-NEXT: v_mov_b32_e32 v1, s25
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
@@ -256,8 +256,8 @@ define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: s_cselect_b32 s5, s9, s5
+; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]
@@ -276,8 +276,8 @@ define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: s_cselect_b32 s9, s15, s9
+; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]
@@ -296,8 +296,8 @@ define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s4, s12, s4
; SI-NEXT: s_cselect_b32 s5, s13, s5
+; SI-NEXT: s_cselect_b32 s4, s12, s4
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_mov_b32_e32 v5, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[4:5]
@@ -316,8 +316,8 @@ define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s8, s18, s8
; SI-NEXT: s_cselect_b32 s9, s19, s9
+; SI-NEXT: s_cselect_b32 s8, s18, s8
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_mov_b32_e32 v5, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[4:5]
@@ -418,8 +418,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s24, s7
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s26, s10, s6
; SI-NEXT: s_cselect_b32 s27, s11, s7
+; SI-NEXT: s_cselect_b32 s26, s10, s6
; SI-NEXT: v_mov_b32_e32 v0, s26
; SI-NEXT: v_mov_b32_e32 v1, s27
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
@@ -437,8 +437,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s11, s7
; SI-NEXT: s_cmp_gt_i32 s10, 51
-; SI-NEXT: s_cselect_b32 s6, s8, s6
; SI-NEXT: s_cselect_b32 s7, s9, s7
+; SI-NEXT: s_cselect_b32 s6, s8, s6
; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]
@@ -456,8 +456,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s24, s9
; SI-NEXT: s_cmp_gt_i32 s11, 51
-; SI-NEXT: s_cselect_b32 s24, s14, s8
; SI-NEXT: s_cselect_b32 s25, s15, s9
+; SI-NEXT: s_cselect_b32 s24, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s24
; SI-NEXT: v_mov_b32_e32 v1, s25
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]
@@ -475,8 +475,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s14, s9
; SI-NEXT: s_cmp_gt_i32 s11, 51
-; SI-NEXT: s_cselect_b32 s34, s12, s8
; SI-NEXT: s_cselect_b32 s35, s13, s9
+; SI-NEXT: s_cselect_b32 s34, s12, s8
; SI-NEXT: v_mov_b32_e32 v0, s34
; SI-NEXT: v_mov_b32_e32 v1, s35
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[0:1]
@@ -494,8 +494,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s12, s9
; SI-NEXT: s_cmp_gt_i32 s11, 51
-; SI-NEXT: s_cselect_b32 s30, s18, s8
; SI-NEXT: s_cselect_b32 s31, s19, s9
+; SI-NEXT: s_cselect_b32 s30, s18, s8
; SI-NEXT: v_mov_b32_e32 v0, s30
; SI-NEXT: v_mov_b32_e32 v1, s31
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[0:1]
@@ -512,8 +512,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s11, s9
; SI-NEXT: s_cmp_gt_i32 s10, 51
-; SI-NEXT: s_cselect_b32 s28, s16, s8
; SI-NEXT: s_cselect_b32 s29, s17, s9
+; SI-NEXT: s_cselect_b32 s28, s16, s8
; SI-NEXT: v_mov_b32_e32 v0, s28
; SI-NEXT: v_mov_b32_e32 v1, s29
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[16:17], v[0:1]
@@ -531,8 +531,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s9, s7
; SI-NEXT: s_cmp_gt_i32 s8, 51
-; SI-NEXT: s_cselect_b32 s26, s22, s6
; SI-NEXT: s_cselect_b32 s27, s23, s7
+; SI-NEXT: s_cselect_b32 s26, s22, s6
; SI-NEXT: v_mov_b32_e32 v4, s26
; SI-NEXT: v_mov_b32_e32 v5, s27
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[22:23], v[4:5]
@@ -550,8 +550,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s9, s7
; SI-NEXT: s_cmp_gt_i32 s8, 51
-; SI-NEXT: s_cselect_b32 s6, s20, s6
; SI-NEXT: s_cselect_b32 s7, s21, s7
+; SI-NEXT: s_cselect_b32 s6, s20, s6
; SI-NEXT: v_mov_b32_e32 v4, s6
; SI-NEXT: v_mov_b32_e32 v5, s7
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[20:21], v[4:5]
@@ -572,8 +572,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s24, 0, s24
; SI-NEXT: s_cselect_b32 s25, s35, s25
; SI-NEXT: s_cmp_gt_i32 s34, 51
-; SI-NEXT: s_cselect_b32 s24, s10, s24
; SI-NEXT: s_cselect_b32 s25, s11, s25
+; SI-NEXT: s_cselect_b32 s24, s10, s24
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[8:9]
@@ -592,8 +592,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s10, 0, s10
; SI-NEXT: s_cselect_b32 s11, s34, s11
; SI-NEXT: s_cmp_gt_i32 s31, 51
-; SI-NEXT: s_cselect_b32 s10, s8, s10
; SI-NEXT: s_cselect_b32 s11, s9, s11
+; SI-NEXT: s_cselect_b32 s10, s8, s10
; SI-NEXT: v_mov_b32_e32 v8, s10
; SI-NEXT: v_mov_b32_e32 v9, s11
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[8:9]
@@ -611,8 +611,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s35, s9
; SI-NEXT: s_cmp_gt_i32 s34, 51
-; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: s_cselect_b32 s9, s15, s9
+; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v8, s8
; SI-NEXT: v_mov_b32_e32 v9, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[8:9]
@@ -630,8 +630,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s14, 0, s14
; SI-NEXT: s_cselect_b32 s15, s34, s15
; SI-NEXT: s_cmp_gt_i32 s29, 51
-; SI-NEXT: s_cselect_b32 s14, s12, s14
; SI-NEXT: s_cselect_b32 s15, s13, s15
+; SI-NEXT: s_cselect_b32 s14, s12, s14
; SI-NEXT: v_mov_b32_e32 v12, s14
; SI-NEXT: v_mov_b32_e32 v13, s15
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[12:13]
@@ -649,8 +649,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s12, 0, s12
; SI-NEXT: s_cselect_b32 s13, s34, s13
; SI-NEXT: s_cmp_gt_i32 s29, 51
-; SI-NEXT: s_cselect_b32 s12, s18, s12
; SI-NEXT: s_cselect_b32 s13, s19, s13
+; SI-NEXT: s_cselect_b32 s12, s18, s12
; SI-NEXT: v_mov_b32_e32 v12, s12
; SI-NEXT: v_mov_b32_e32 v13, s13
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[12:13]
@@ -668,8 +668,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s18, 0, s18
; SI-NEXT: s_cselect_b32 s19, s29, s19
; SI-NEXT: s_cmp_gt_i32 s27, 51
-; SI-NEXT: s_cselect_b32 s18, s16, s18
; SI-NEXT: s_cselect_b32 s19, s17, s19
+; SI-NEXT: s_cselect_b32 s18, s16, s18
; SI-NEXT: v_mov_b32_e32 v12, s18
; SI-NEXT: v_mov_b32_e32 v13, s19
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[16:17], v[12:13]
@@ -687,8 +687,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s17, s33, s17
; SI-NEXT: s_cselect_b32 s16, 0, s16
; SI-NEXT: s_cmp_gt_i32 s29, 51
-; SI-NEXT: s_cselect_b32 s16, s22, s16
; SI-NEXT: s_cselect_b32 s17, s23, s17
+; SI-NEXT: s_cselect_b32 s16, s22, s16
; SI-NEXT: v_mov_b32_e32 v12, s16
; SI-NEXT: v_mov_b32_e32 v13, s17
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[22:23], v[12:13]
@@ -706,8 +706,8 @@ define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x)
; SI-NEXT: s_cselect_b32 s1, s7, s1
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cmp_gt_i32 s6, 51
-; SI-NEXT: s_cselect_b32 s1, s21, s1
; SI-NEXT: v_mov_b32_e32 v17, s30
+; SI-NEXT: s_cselect_b32 s1, s21, s1
; SI-NEXT: s_cselect_b32 s0, s20, s0
; SI-NEXT: v_mov_b32_e32 v19, s1
; SI-NEXT: v_mov_b32_e32 v18, s0
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
index 6c37316d33d03..b996628633c6e 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
@@ -34,9 +34,9 @@ define amdgpu_kernel void @s_test_copysign_f64(ptr addrspace(1) %out, [8 x i32],
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_mov_b32_e32 v0, s1
; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_bfi_b32 v1, s2, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -80,9 +80,9 @@ define amdgpu_kernel void @s_test_copysign_f64_0(ptr addrspace(1) %out, [8 x i32
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset0_b32 s1, 31
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -124,9 +124,9 @@ define amdgpu_kernel void @s_test_copysign_f64_1(ptr addrspace(1) %out, [8 x i32
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset0_b32 s1, 31
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -168,9 +168,9 @@ define amdgpu_kernel void @s_test_copysign_f64_10(ptr addrspace(1) %out, [8 x i3
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset0_b32 s1, 31
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -212,9 +212,9 @@ define amdgpu_kernel void @s_test_copysign_f64_neg1(ptr addrspace(1) %out, [8 x
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset1_b32 s1, 31
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -256,9 +256,9 @@ define amdgpu_kernel void @s_test_copysign_f64_neg10(ptr addrspace(1) %out, [8 x
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset1_b32 s1, 31
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -306,9 +306,9 @@ define amdgpu_kernel void @s_test_copysign_f64_f32(ptr addrspace(1) %out, [8 x i
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s1
; VI-NEXT: v_mov_b32_e32 v1, s6
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_bfi_b32 v1, s4, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -359,9 +359,9 @@ define amdgpu_kernel void @s_test_copysign_f64_f16(ptr addrspace(1) %out, [8 x i
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_lshlrev_b32_e64 v0, 16, s6
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_bfi_b32 v1, s4, v1, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -634,10 +634,10 @@ define amdgpu_kernel void @s_test_copysign_v2f64(ptr addrspace(1) %out, <2 x dou
; VI-NEXT: v_mov_b32_e32 v2, s9
; VI-NEXT: v_bfi_b32 v3, s2, v0, v1
; VI-NEXT: v_mov_b32_e32 v0, s13
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_bfi_b32 v1, s2, v2, v0
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v2, s10
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -704,13 +704,13 @@ define amdgpu_kernel void @s_test_copysign_v3f64(ptr addrspace(1) %out, <3 x dou
; VI-NEXT: v_bfi_b32 v5, s2, v0, v2
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
-; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: v_mov_b32_e32 v4, s12
+; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: flat_store_dwordx2 v[6:7], v[4:5]
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v2, s10
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -787,14 +787,14 @@ define amdgpu_kernel void @s_test_copysign_v4f64(ptr addrspace(1) %out, <4 x dou
; VI-NEXT: v_bfi_b32 v5, s2, v0, v2
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
-; VI-NEXT: v_mov_b32_e32 v9, s3
; VI-NEXT: v_mov_b32_e32 v4, s12
; VI-NEXT: v_mov_b32_e32 v6, s14
+; VI-NEXT: v_mov_b32_e32 v9, s3
; VI-NEXT: v_mov_b32_e32 v8, s2
; VI-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; VI-NEXT: v_mov_b32_e32 v0, s8
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v2, s10
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
index 2813568787190..f44c33edd3d93 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
@@ -1673,11 +1673,11 @@ define amdgpu_kernel void @div_afn_2_x_pat_f16(ptr addrspace(1) %out) #0 {
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mul_f16_e32 v2, 0.5, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -1749,11 +1749,11 @@ define amdgpu_kernel void @div_afn_k_x_pat_f16(ptr addrspace(1) %out) #0 {
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mul_f16_e32 v2, 0x2e66, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -1825,11 +1825,11 @@ define amdgpu_kernel void @div_afn_neg_k_x_pat_f16(ptr addrspace(1) %out) #0 {
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mul_f16_e32 v2, 0xae66, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.ll b/llvm/test/CodeGen/AMDGPU/fdiv.ll
index 73d55bd72a0f9..58e08c96173a2 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.ll
@@ -540,9 +540,9 @@ define amdgpu_kernel void @s_fdiv_fast_ieee_f32(ptr addrspace(1) %out, float %a,
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -601,9 +601,9 @@ define amdgpu_kernel void @s_fdiv_f32_fast_math(ptr addrspace(1) %out, float %a,
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -662,9 +662,9 @@ define amdgpu_kernel void @s_fdiv_ulp25_f32_fast_math(ptr addrspace(1) %out, flo
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -886,9 +886,9 @@ define amdgpu_kernel void @s_fdiv_f32_arcp_ninf(ptr addrspace(1) %out, float %a,
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -1282,10 +1282,10 @@ define amdgpu_kernel void @s_fdiv_v2f32_fast_math(ptr addrspace(1) %out, <2 x fl
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_rcp_f32_e32 v0, s3
; GFX8-NEXT: v_rcp_f32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: v_mul_f32_e32 v1, s1, v0
; GFX8-NEXT: v_mul_f32_e32 v0, s0, v2
; GFX8-NEXT: v_mov_b32_e32 v2, s4
-; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
@@ -1358,10 +1358,10 @@ define amdgpu_kernel void @s_fdiv_v2f32_arcp_math(ptr addrspace(1) %out, <2 x fl
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_rcp_f32_e32 v0, s3
; GFX8-NEXT: v_rcp_f32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: v_mul_f32_e32 v1, s1, v0
; GFX8-NEXT: v_mul_f32_e32 v0, s0, v2
; GFX8-NEXT: v_mov_b32_e32 v2, s4
-; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
@@ -2157,10 +2157,10 @@ define amdgpu_kernel void @s_fdiv_f32_correctly_rounded_divide_sqrt(ptr addrspac
; GFX8-NEXT: v_fma_f32 v0, -v0, v3, v1
; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; GFX8-NEXT: v_div_fmas_f32 v0, v0, v2, v3
-; GFX8-NEXT: v_div_fixup_f32 v2, v0, s2, 1.0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_div_fixup_f32 v2, v0, s2, 1.0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -2307,10 +2307,10 @@ define amdgpu_kernel void @s_fdiv_f32_denorms_correctly_rounded_divide_sqrt(ptr
; GFX8-NEXT: v_fma_f32 v3, v4, v2, v3
; GFX8-NEXT: v_fma_f32 v0, -v0, v3, v1
; GFX8-NEXT: v_div_fmas_f32 v0, v0, v2, v3
-; GFX8-NEXT: v_div_fixup_f32 v2, v0, s2, 1.0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_div_fixup_f32 v2, v0, s2, 1.0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll b/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
index 607ed85274e40..4a5fb7d4a511f 100644
--- a/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
+++ b/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
@@ -9,17 +9,17 @@
define amdgpu_kernel void @same_address_fence_merge_write2() #0 {
; GCN-LABEL: same_address_fence_merge_write2:
; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GCN-NEXT: s_mov_b32 s1, 0x40100000
+; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_add_u32_e32 v3, 0x800, v2
+; GCN-NEXT: s_mov_b32 s1, 0x3ff00000
; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:66
; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:198
; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:8 offset1:74
; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:140 offset1:206
-; GCN-NEXT: s_mov_b32 s1, 0x3ff00000
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
index d1efb7a35b122..21cd49230b5ff 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
@@ -22,8 +22,8 @@ define amdgpu_kernel void @zero_init_kernel() {
; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: s_mov_b32 s2, s0
; GFX9-NEXT: s_mov_b32 s3, s0
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
@@ -97,8 +97,8 @@ define amdgpu_kernel void @zero_init_kernel() {
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s13, s13, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s12, s11
-; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics.ll
index b35f07002a48a..9e6ac75a2ee3d 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics.ll
@@ -5603,8 +5603,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_offset(ptr %out, i32 %in, i32 %old
; GCN1-NEXT: s_add_u32 s0, s0, 16
; GCN1-NEXT: s_addc_u32 s1, s1, 0
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_cmpswap v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5618,8 +5618,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_offset(ptr %out, i32 %in, i32 %old
; GCN2-NEXT: s_add_u32 s0, s0, 16
; GCN2-NEXT: s_addc_u32 s1, s1, 0
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_cmpswap v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5631,8 +5631,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_offset(ptr %out, i32 %in, i32 %old
; GCN3-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN3-NEXT: s_waitcnt lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v0, s0
-; GCN3-NEXT: v_mov_b32_e32 v2, s2
; GCN3-NEXT: v_mov_b32_e32 v1, s1
+; GCN3-NEXT: v_mov_b32_e32 v2, s2
; GCN3-NEXT: v_mov_b32_e32 v3, s3
; GCN3-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] offset:16
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5666,8 +5666,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(ptr %out, ptr %out2, i3
; GCN1-NEXT: s_add_u32 s0, s0, 16
; GCN1-NEXT: s_addc_u32 s1, s1, 0
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5685,8 +5685,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(ptr %out, ptr %out2, i3
; GCN2-NEXT: s_add_u32 s0, s0, 16
; GCN2-NEXT: s_addc_u32 s1, s1, 0
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5702,8 +5702,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(ptr %out, ptr %out2, i3
; GCN3-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GCN3-NEXT: s_waitcnt lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v0, s0
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s1
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:16 glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5750,8 +5750,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(ptr %out, i32 %in, i
; GCN1-NEXT: s_addc_u32 s1, s3, s1
; GCN1-NEXT: s_add_u32 s0, s0, 16
; GCN1-NEXT: s_addc_u32 s1, s1, 0
-; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v1, s4
+; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v2, s0
; GCN1-NEXT: flat_atomic_cmpswap v[2:3], v[0:1]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5771,8 +5771,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(ptr %out, i32 %in, i
; GCN2-NEXT: s_addc_u32 s1, s3, s1
; GCN2-NEXT: s_add_u32 s0, s0, 16
; GCN2-NEXT: s_addc_u32 s1, s1, 0
-; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v1, s4
+; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v2, s0
; GCN2-NEXT: flat_atomic_cmpswap v[2:3], v[0:1]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5790,8 +5790,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(ptr %out, i32 %in, i
; GCN3-NEXT: v_mov_b32_e32 v0, s6
; GCN3-NEXT: s_add_u32 s0, s2, s0
; GCN3-NEXT: s_addc_u32 s1, s3, s1
-; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v1, s7
+; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v2, s0
; GCN3-NEXT: flat_atomic_cmpswap v[2:3], v[0:1] offset:16
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5839,8 +5839,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(ptr %out, ptr %o
; GCN1-NEXT: s_addc_u32 s1, s1, s5
; GCN1-NEXT: s_add_u32 s0, s0, 16
; GCN1-NEXT: s_addc_u32 s1, s1, 0
-; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v1, s9
+; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v2, s0
; GCN1-NEXT: flat_atomic_cmpswap v2, v[2:3], v[0:1] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5863,8 +5863,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(ptr %out, ptr %o
; GCN2-NEXT: s_addc_u32 s1, s1, s5
; GCN2-NEXT: s_add_u32 s0, s0, 16
; GCN2-NEXT: s_addc_u32 s1, s1, 0
-; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v1, s9
+; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v2, s0
; GCN2-NEXT: flat_atomic_cmpswap v2, v[2:3], v[0:1] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5885,8 +5885,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(ptr %out, ptr %o
; GCN3-NEXT: v_mov_b32_e32 v0, s8
; GCN3-NEXT: s_add_u32 s0, s0, s4
; GCN3-NEXT: s_addc_u32 s1, s1, s5
-; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v1, s9
+; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v2, s0
; GCN3-NEXT: flat_atomic_cmpswap v2, v[2:3], v[0:1] offset:16 glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5932,8 +5932,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32(ptr %out, i32 %in, i32 %old) {
; GCN1-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_cmpswap v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5945,8 +5945,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32(ptr %out, i32 %in, i32 %old) {
; GCN2-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_cmpswap v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5958,8 +5958,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32(ptr %out, i32 %in, i32 %old) {
; GCN3-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN3-NEXT: s_waitcnt lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v0, s0
-; GCN3-NEXT: v_mov_b32_e32 v2, s2
; GCN3-NEXT: v_mov_b32_e32 v1, s1
+; GCN3-NEXT: v_mov_b32_e32 v2, s2
; GCN3-NEXT: v_mov_b32_e32 v3, s3
; GCN3-NEXT: flat_atomic_cmpswap v[0:1], v[2:3]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5990,8 +5990,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret(ptr %out, ptr %out2, i32 %in,
; GCN1-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6007,8 +6007,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret(ptr %out, ptr %out2, i32 %in,
; GCN2-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6024,8 +6024,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret(ptr %out, ptr %out2, i32 %in,
; GCN3-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GCN3-NEXT: s_waitcnt lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v0, s0
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s1
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6069,8 +6069,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(ptr %out, i32 %in, i64 %ind
; GCN1-NEXT: v_mov_b32_e32 v0, s6
; GCN1-NEXT: s_add_u32 s0, s2, s0
; GCN1-NEXT: s_addc_u32 s1, s3, s1
-; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v1, s4
+; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v2, s0
; GCN1-NEXT: flat_atomic_cmpswap v[2:3], v[0:1]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6088,8 +6088,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(ptr %out, i32 %in, i64 %ind
; GCN2-NEXT: v_mov_b32_e32 v0, s6
; GCN2-NEXT: s_add_u32 s0, s2, s0
; GCN2-NEXT: s_addc_u32 s1, s3, s1
-; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v1, s4
+; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v2, s0
; GCN2-NEXT: flat_atomic_cmpswap v[2:3], v[0:1]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6107,8 +6107,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(ptr %out, i32 %in, i64 %ind
; GCN3-NEXT: v_mov_b32_e32 v0, s6
; GCN3-NEXT: s_add_u32 s0, s2, s0
; GCN3-NEXT: s_addc_u32 s1, s3, s1
-; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v1, s7
+; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v2, s0
; GCN3-NEXT: flat_atomic_cmpswap v[2:3], v[0:1]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6153,8 +6153,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(ptr %out, ptr %out2, i3
; GCN1-NEXT: v_mov_b32_e32 v0, s8
; GCN1-NEXT: s_add_u32 s0, s0, s4
; GCN1-NEXT: s_addc_u32 s1, s1, s5
-; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v1, s9
+; GCN1-NEXT: v_mov_b32_e32 v3, s1
; GCN1-NEXT: v_mov_b32_e32 v2, s0
; GCN1-NEXT: flat_atomic_cmpswap v2, v[2:3], v[0:1] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6175,8 +6175,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(ptr %out, ptr %out2, i3
; GCN2-NEXT: v_mov_b32_e32 v0, s8
; GCN2-NEXT: s_add_u32 s0, s0, s4
; GCN2-NEXT: s_addc_u32 s1, s1, s5
-; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v1, s9
+; GCN2-NEXT: v_mov_b32_e32 v3, s1
; GCN2-NEXT: v_mov_b32_e32 v2, s0
; GCN2-NEXT: flat_atomic_cmpswap v2, v[2:3], v[0:1] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6197,8 +6197,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(ptr %out, ptr %out2, i3
; GCN3-NEXT: v_mov_b32_e32 v0, s8
; GCN3-NEXT: s_add_u32 s0, s0, s4
; GCN3-NEXT: s_addc_u32 s1, s1, s5
-; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v1, s9
+; GCN3-NEXT: v_mov_b32_e32 v3, s1
; GCN3-NEXT: v_mov_b32_e32 v2, s0
; GCN3-NEXT: flat_atomic_cmpswap v2, v[2:3], v[0:1] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -8797,7 +8797,7 @@ define amdgpu_kernel void @atomic_store_i16_addr64_offset(i16 %in, ptr %out, i64
; GFX11-TRUE16-NEXT: s_add_u32 s0, s0, s2
; GFX11-TRUE16-NEXT: s_addc_u32 s1, s1, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0 offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
index 278964334b711..e4b69e045d609 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
@@ -1497,8 +1497,8 @@ define amdgpu_gfx i32 @flat_atomic_sub_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB36_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1522,8 +1522,8 @@ define amdgpu_gfx i32 @flat_atomic_sub_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB36_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1547,8 +1547,8 @@ define amdgpu_gfx i32 @flat_atomic_sub_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB36_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1626,8 +1626,8 @@ define amdgpu_gfx i32 @flat_atomic_sub_i32_ret_offset_scalar(ptr inreg %out, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB37_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2159,8 +2159,8 @@ define amdgpu_gfx i32 @flat_atomic_and_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB46_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2184,8 +2184,8 @@ define amdgpu_gfx i32 @flat_atomic_and_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB46_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2209,8 +2209,8 @@ define amdgpu_gfx i32 @flat_atomic_and_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB46_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2288,8 +2288,8 @@ define amdgpu_gfx i32 @flat_atomic_and_i32_ret_offset_scalar(ptr inreg %out, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB47_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2839,8 +2839,8 @@ define amdgpu_gfx i32 @flat_atomic_nand_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB56_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2865,8 +2865,8 @@ define amdgpu_gfx i32 @flat_atomic_nand_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB56_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2891,8 +2891,8 @@ define amdgpu_gfx i32 @flat_atomic_nand_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB56_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2973,8 +2973,8 @@ define amdgpu_gfx i32 @flat_atomic_nand_i32_ret_offset_scalar(ptr inreg %out, i3
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB57_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3592,8 +3592,8 @@ define amdgpu_gfx i32 @flat_atomic_or_i32_ret_scalar(ptr inreg %ptr, i32 inreg %
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB66_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3617,8 +3617,8 @@ define amdgpu_gfx i32 @flat_atomic_or_i32_ret_scalar(ptr inreg %ptr, i32 inreg %
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB66_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3642,8 +3642,8 @@ define amdgpu_gfx i32 @flat_atomic_or_i32_ret_scalar(ptr inreg %ptr, i32 inreg %
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB66_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3721,8 +3721,8 @@ define amdgpu_gfx i32 @flat_atomic_or_i32_ret_offset_scalar(ptr inreg %out, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB67_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4254,8 +4254,8 @@ define amdgpu_gfx i32 @flat_atomic_xor_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB76_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4279,8 +4279,8 @@ define amdgpu_gfx i32 @flat_atomic_xor_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB76_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4304,8 +4304,8 @@ define amdgpu_gfx i32 @flat_atomic_xor_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB76_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4383,8 +4383,8 @@ define amdgpu_gfx i32 @flat_atomic_xor_i32_ret_offset_scalar(ptr inreg %out, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB77_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4916,8 +4916,8 @@ define amdgpu_gfx i32 @flat_atomic_max_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB86_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4941,8 +4941,8 @@ define amdgpu_gfx i32 @flat_atomic_max_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB86_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4966,8 +4966,8 @@ define amdgpu_gfx i32 @flat_atomic_max_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB86_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5045,8 +5045,8 @@ define amdgpu_gfx i32 @flat_atomic_max_i32_ret_offset_scalar(ptr inreg %out, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB87_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5980,8 +5980,8 @@ define amdgpu_gfx i32 @flat_atomic_umax_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB100_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6005,8 +6005,8 @@ define amdgpu_gfx i32 @flat_atomic_umax_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB100_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6030,8 +6030,8 @@ define amdgpu_gfx i32 @flat_atomic_umax_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB100_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6109,8 +6109,8 @@ define amdgpu_gfx i32 @flat_atomic_umax_i32_ret_offset_scalar(ptr inreg %out, i3
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB101_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6954,8 +6954,8 @@ define amdgpu_gfx i32 @flat_atomic_umin_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB113_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6979,8 +6979,8 @@ define amdgpu_gfx i32 @flat_atomic_umin_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB113_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7004,8 +7004,8 @@ define amdgpu_gfx i32 @flat_atomic_umin_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB113_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7083,8 +7083,8 @@ define amdgpu_gfx i32 @flat_atomic_umin_i32_ret_offset_scalar(ptr inreg %out, i3
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB114_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7616,8 +7616,8 @@ define amdgpu_gfx i32 @flat_atomic_min_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB123_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7641,8 +7641,8 @@ define amdgpu_gfx i32 @flat_atomic_min_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB123_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7666,8 +7666,8 @@ define amdgpu_gfx i32 @flat_atomic_min_i32_ret_scalar(ptr inreg %ptr, i32 inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB123_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7745,8 +7745,8 @@ define amdgpu_gfx i32 @flat_atomic_min_i32_ret_offset_scalar(ptr inreg %out, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB124_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8703,8 +8703,8 @@ define amdgpu_gfx i32 @flat_atomic_uinc_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[34:35], 0
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB137_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8730,8 +8730,8 @@ define amdgpu_gfx i32 @flat_atomic_uinc_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[34:35], 0
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB137_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8757,8 +8757,8 @@ define amdgpu_gfx i32 @flat_atomic_uinc_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB137_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8842,8 +8842,8 @@ define amdgpu_gfx i32 @flat_atomic_uinc_wrap_i32_ret_offset_scalar(ptr inreg %ou
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[34:35], 0
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB138_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9262,9 +9262,9 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_scalar(ptr inreg %ptr, i
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v1, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: s_mov_b64 s[36:37], 0
; GCN1-NEXT: v_mov_b32_e32 v4, s6
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: .LBB145_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9291,9 +9291,9 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_scalar(ptr inreg %ptr, i
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v1, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: s_mov_b64 s[36:37], 0
; GCN2-NEXT: v_mov_b32_e32 v4, s6
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: .LBB145_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9320,9 +9320,9 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_scalar(ptr inreg %ptr, i
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v1, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v2, s4
; GCN3-NEXT: s_mov_b64 s[36:37], 0
; GCN3-NEXT: v_mov_b32_e32 v4, s6
+; GCN3-NEXT: v_mov_b32_e32 v2, s4
; GCN3-NEXT: v_mov_b32_e32 v3, s5
; GCN3-NEXT: .LBB145_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9411,9 +9411,9 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i32_noret_offset_scalar(ptr inreg
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v1, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v2, s4
; GCN3-NEXT: s_mov_b64 s[36:37], 0
; GCN3-NEXT: v_mov_b32_e32 v4, s6
+; GCN3-NEXT: v_mov_b32_e32 v2, s4
; GCN3-NEXT: v_mov_b32_e32 v3, s5
; GCN3-NEXT: .LBB146_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9445,9 +9445,9 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN1-NEXT: v_mov_b32_e32 v0, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s5
; GCN1-NEXT: flat_load_dword v0, v[0:1]
-; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: s_mov_b64 s[36:37], 0
; GCN1-NEXT: v_mov_b32_e32 v3, s6
+; GCN1-NEXT: v_mov_b32_e32 v1, s4
; GCN1-NEXT: v_mov_b32_e32 v2, s5
; GCN1-NEXT: .LBB147_1: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9474,9 +9474,9 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN2-NEXT: v_mov_b32_e32 v0, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s5
; GCN2-NEXT: flat_load_dword v0, v[0:1]
-; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: s_mov_b64 s[36:37], 0
; GCN2-NEXT: v_mov_b32_e32 v3, s6
+; GCN2-NEXT: v_mov_b32_e32 v1, s4
; GCN2-NEXT: v_mov_b32_e32 v2, s5
; GCN2-NEXT: .LBB147_1: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9503,9 +9503,9 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_scalar(ptr inreg %ptr, i32
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1]
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[36:37], 0
; GCN3-NEXT: v_mov_b32_e32 v3, s6
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB147_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9594,9 +9594,9 @@ define amdgpu_gfx i32 @flat_atomic_udec_wrap_i32_ret_offset_scalar(ptr inreg %ou
; GCN3-NEXT: v_mov_b32_e32 v0, s4
; GCN3-NEXT: v_mov_b32_e32 v1, s5
; GCN3-NEXT: flat_load_dword v0, v[0:1] offset:16
-; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: s_mov_b64 s[36:37], 0
; GCN3-NEXT: v_mov_b32_e32 v3, s6
+; GCN3-NEXT: v_mov_b32_e32 v1, s4
; GCN3-NEXT: v_mov_b32_e32 v2, s5
; GCN3-NEXT: .LBB148_1: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
index 735e754a05882..9abe89a4cc959 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
@@ -24,8 +24,8 @@ define amdgpu_kernel void @atomic_add_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB0_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -75,8 +75,8 @@ define amdgpu_kernel void @atomic_add_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB0_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -168,8 +168,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB1_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -226,8 +226,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB1_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -338,8 +338,8 @@ define amdgpu_kernel void @atomic_add_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB2_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -394,8 +394,8 @@ define amdgpu_kernel void @atomic_add_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB2_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -495,8 +495,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB3_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -555,8 +555,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB3_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -663,8 +663,8 @@ define amdgpu_kernel void @atomic_add_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB4_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -712,8 +712,8 @@ define amdgpu_kernel void @atomic_add_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB4_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -801,8 +801,8 @@ define amdgpu_kernel void @atomic_add_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB5_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -857,8 +857,8 @@ define amdgpu_kernel void @atomic_add_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB5_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -965,8 +965,8 @@ define amdgpu_kernel void @atomic_add_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB6_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1018,8 +1018,8 @@ define amdgpu_kernel void @atomic_add_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB6_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1115,8 +1115,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB7_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1173,8 +1173,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB7_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1281,8 +1281,8 @@ define amdgpu_kernel void @atomic_and_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB8_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1331,8 +1331,8 @@ define amdgpu_kernel void @atomic_and_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB8_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1422,8 +1422,8 @@ define amdgpu_kernel void @atomic_and_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB9_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1479,8 +1479,8 @@ define amdgpu_kernel void @atomic_and_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB9_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1589,8 +1589,8 @@ define amdgpu_kernel void @atomic_and_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB10_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1644,8 +1644,8 @@ define amdgpu_kernel void @atomic_and_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB10_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1743,8 +1743,8 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB11_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1802,8 +1802,8 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB11_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1908,8 +1908,8 @@ define amdgpu_kernel void @atomic_and_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB12_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1956,8 +1956,8 @@ define amdgpu_kernel void @atomic_and_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB12_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2043,8 +2043,8 @@ define amdgpu_kernel void @atomic_and_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB13_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2098,8 +2098,8 @@ define amdgpu_kernel void @atomic_and_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB13_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2204,8 +2204,8 @@ define amdgpu_kernel void @atomic_and_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB14_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2256,8 +2256,8 @@ define amdgpu_kernel void @atomic_and_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB14_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2351,8 +2351,8 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB15_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2408,8 +2408,8 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB15_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2514,8 +2514,8 @@ define amdgpu_kernel void @atomic_sub_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB16_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2565,8 +2565,8 @@ define amdgpu_kernel void @atomic_sub_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB16_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2658,8 +2658,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB17_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2716,8 +2716,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB17_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2828,8 +2828,8 @@ define amdgpu_kernel void @atomic_sub_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB18_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2884,8 +2884,8 @@ define amdgpu_kernel void @atomic_sub_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB18_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2985,8 +2985,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB19_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3045,8 +3045,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB19_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3153,8 +3153,8 @@ define amdgpu_kernel void @atomic_sub_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB20_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3202,8 +3202,8 @@ define amdgpu_kernel void @atomic_sub_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB20_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3291,8 +3291,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB21_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3347,8 +3347,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB21_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3455,8 +3455,8 @@ define amdgpu_kernel void @atomic_sub_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB22_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3508,8 +3508,8 @@ define amdgpu_kernel void @atomic_sub_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB22_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3605,8 +3605,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB23_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3663,8 +3663,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB23_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3771,8 +3771,8 @@ define amdgpu_kernel void @atomic_max_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB24_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -3822,8 +3822,8 @@ define amdgpu_kernel void @atomic_max_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB24_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -3915,8 +3915,8 @@ define amdgpu_kernel void @atomic_max_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB25_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -3974,8 +3974,8 @@ define amdgpu_kernel void @atomic_max_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB25_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -4087,8 +4087,8 @@ define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB26_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -4143,8 +4143,8 @@ define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB26_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -4244,8 +4244,8 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB27_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -4305,8 +4305,8 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB27_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -4414,8 +4414,8 @@ define amdgpu_kernel void @atomic_max_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB28_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -4463,8 +4463,8 @@ define amdgpu_kernel void @atomic_max_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB28_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -4552,8 +4552,8 @@ define amdgpu_kernel void @atomic_max_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB29_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -4609,8 +4609,8 @@ define amdgpu_kernel void @atomic_max_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB29_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -4718,8 +4718,8 @@ define amdgpu_kernel void @atomic_max_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB30_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -4771,8 +4771,8 @@ define amdgpu_kernel void @atomic_max_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB30_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -4868,8 +4868,8 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB31_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -4927,8 +4927,8 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB31_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -5036,8 +5036,8 @@ define amdgpu_kernel void @atomic_umax_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB32_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -5087,8 +5087,8 @@ define amdgpu_kernel void @atomic_umax_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB32_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -5180,8 +5180,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB33_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -5239,8 +5239,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB33_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -5352,8 +5352,8 @@ define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN1-NEXT: s_cbranch_scc0 .LBB34_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -5408,8 +5408,8 @@ define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN2-NEXT: s_cbranch_scc0 .LBB34_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -5509,8 +5509,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN1-NEXT: s_cbranch_scc0 .LBB35_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -5570,8 +5570,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN2-NEXT: s_cbranch_scc0 .LBB35_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -5679,8 +5679,8 @@ define amdgpu_kernel void @atomic_umax_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB36_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -5728,8 +5728,8 @@ define amdgpu_kernel void @atomic_umax_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB36_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -5817,8 +5817,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB37_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -5874,8 +5874,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB37_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -5983,8 +5983,8 @@ define amdgpu_kernel void @atomic_umax_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB38_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -6036,8 +6036,8 @@ define amdgpu_kernel void @atomic_umax_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB38_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -6133,8 +6133,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB39_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -6192,8 +6192,8 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB39_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -6301,8 +6301,8 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB40_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -6352,8 +6352,8 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB40_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -6445,8 +6445,8 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB41_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -6504,8 +6504,8 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB41_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -6617,8 +6617,8 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB42_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -6673,8 +6673,8 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB42_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -6774,8 +6774,8 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB43_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -6835,8 +6835,8 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB43_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -6944,8 +6944,8 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB44_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -6993,8 +6993,8 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB44_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -7082,8 +7082,8 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB45_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -7139,8 +7139,8 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB45_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -7248,8 +7248,8 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB46_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -7301,8 +7301,8 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB46_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -7398,8 +7398,8 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB47_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -7457,8 +7457,8 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB47_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -7566,8 +7566,8 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB48_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -7617,8 +7617,8 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB48_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -7710,8 +7710,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB49_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -7769,8 +7769,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB49_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -7882,8 +7882,8 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN1-NEXT: s_cbranch_scc0 .LBB50_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -7938,8 +7938,8 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN2-NEXT: s_cbranch_scc0 .LBB50_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -8039,8 +8039,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN1-NEXT: s_cbranch_scc0 .LBB51_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -8100,8 +8100,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN2-NEXT: s_cbranch_scc0 .LBB51_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -8209,8 +8209,8 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB52_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -8258,8 +8258,8 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB52_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -8347,8 +8347,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB53_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -8404,8 +8404,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB53_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -8513,8 +8513,8 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB54_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -8566,8 +8566,8 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB54_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -8663,8 +8663,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB55_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt lgkmcnt(0)
@@ -8722,8 +8722,8 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB55_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt lgkmcnt(0)
@@ -8831,8 +8831,8 @@ define amdgpu_kernel void @atomic_or_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB56_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -8881,8 +8881,8 @@ define amdgpu_kernel void @atomic_or_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB56_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -8972,8 +8972,8 @@ define amdgpu_kernel void @atomic_or_i64_ret_offset(ptr %out, ptr %out2, i64 %in
; GCN1-NEXT: s_cbranch_scc0 .LBB57_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9029,8 +9029,8 @@ define amdgpu_kernel void @atomic_or_i64_ret_offset(ptr %out, ptr %out2, i64 %in
; GCN2-NEXT: s_cbranch_scc0 .LBB57_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9139,8 +9139,8 @@ define amdgpu_kernel void @atomic_or_i64_addr64_offset(ptr %out, i64 %in, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB58_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9194,8 +9194,8 @@ define amdgpu_kernel void @atomic_or_i64_addr64_offset(ptr %out, i64 %in, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB58_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9293,8 +9293,8 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB59_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9352,8 +9352,8 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB59_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9458,8 +9458,8 @@ define amdgpu_kernel void @atomic_or_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB60_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9506,8 +9506,8 @@ define amdgpu_kernel void @atomic_or_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB60_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9593,8 +9593,8 @@ define amdgpu_kernel void @atomic_or_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB61_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9648,8 +9648,8 @@ define amdgpu_kernel void @atomic_or_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB61_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9754,8 +9754,8 @@ define amdgpu_kernel void @atomic_or_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-NEXT: s_cbranch_scc0 .LBB62_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9806,8 +9806,8 @@ define amdgpu_kernel void @atomic_or_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN2-NEXT: s_cbranch_scc0 .LBB62_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9901,8 +9901,8 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64(ptr %out, ptr %out2, i64 %in
; GCN1-NEXT: s_cbranch_scc0 .LBB63_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -9958,8 +9958,8 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64(ptr %out, ptr %out2, i64 %in
; GCN2-NEXT: s_cbranch_scc0 .LBB63_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10064,8 +10064,8 @@ define amdgpu_kernel void @atomic_xchg_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB64_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10110,8 +10110,8 @@ define amdgpu_kernel void @atomic_xchg_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB64_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10194,8 +10194,8 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr %out, double %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB65_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10240,8 +10240,8 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr %out, double %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB65_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10324,8 +10324,8 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr %out, ptr %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB66_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10370,8 +10370,8 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr %out, ptr %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB66_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10454,8 +10454,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB67_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10510,8 +10510,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB67_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10618,8 +10618,8 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN1-NEXT: s_cbranch_scc0 .LBB68_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10669,8 +10669,8 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN2-NEXT: s_cbranch_scc0 .LBB68_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10761,8 +10761,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN1-NEXT: s_cbranch_scc0 .LBB69_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10819,8 +10819,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN2-NEXT: s_cbranch_scc0 .LBB69_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10923,8 +10923,8 @@ define amdgpu_kernel void @atomic_xchg_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB70_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -10967,8 +10967,8 @@ define amdgpu_kernel void @atomic_xchg_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB70_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11047,8 +11047,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB71_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11101,8 +11101,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB71_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11205,8 +11205,8 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB72_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11253,8 +11253,8 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB72_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11341,8 +11341,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB73_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11397,8 +11397,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB73_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11501,8 +11501,8 @@ define amdgpu_kernel void @atomic_xor_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB74_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11551,8 +11551,8 @@ define amdgpu_kernel void @atomic_xor_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB74_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11642,8 +11642,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB75_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11699,8 +11699,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB75_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11809,8 +11809,8 @@ define amdgpu_kernel void @atomic_xor_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB76_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11864,8 +11864,8 @@ define amdgpu_kernel void @atomic_xor_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB76_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -11963,8 +11963,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB77_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12022,8 +12022,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB77_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12128,8 +12128,8 @@ define amdgpu_kernel void @atomic_xor_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB78_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12176,8 +12176,8 @@ define amdgpu_kernel void @atomic_xor_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB78_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12263,8 +12263,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB79_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12318,8 +12318,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB79_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12424,8 +12424,8 @@ define amdgpu_kernel void @atomic_xor_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB80_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12476,8 +12476,8 @@ define amdgpu_kernel void @atomic_xor_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB80_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12571,8 +12571,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB81_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -12628,8 +12628,8 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB81_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13146,11 +13146,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr %out, i64 %in, i64 %old
; GCN1-NEXT: s_mov_b64 s[6:7], -1
; GCN1-NEXT: s_cbranch_scc0 .LBB90_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v0, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s3
; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
+; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v4, s0
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13201,11 +13201,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr %out, i64 %in, i64 %old
; GCN2-NEXT: s_mov_b64 s[6:7], -1
; GCN2-NEXT: s_cbranch_scc0 .LBB90_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v0, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s3
; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
+; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v4, s0
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13301,11 +13301,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr %out, i64 %in, i64 %ol
; GCN1-NEXT: s_mov_b64 s[6:7], -1
; GCN1-NEXT: s_cbranch_scc0 .LBB91_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v0, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s3
; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
+; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v4, s0
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13356,11 +13356,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr %out, i64 %in, i64 %ol
; GCN2-NEXT: s_mov_b64 s[6:7], -1
; GCN2-NEXT: s_cbranch_scc0 .LBB91_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v0, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s3
; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
+; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v4, s0
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13454,11 +13454,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(ptr %out, ptr %out2, i6
; GCN1-NEXT: s_cmp_lg_u32 s2, 1
; GCN1-NEXT: s_cbranch_scc0 .LBB92_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v0, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s13
; GCN1-NEXT: v_mov_b32_e32 v2, s14
; GCN1-NEXT: v_mov_b32_e32 v3, s15
+; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v4, s0
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13514,11 +13514,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(ptr %out, ptr %out2, i6
; GCN2-NEXT: s_cmp_lg_u32 s2, 1
; GCN2-NEXT: s_cbranch_scc0 .LBB92_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v0, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s13
; GCN2-NEXT: v_mov_b32_e32 v2, s14
; GCN2-NEXT: v_mov_b32_e32 v3, s15
+; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v4, s0
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13628,11 +13628,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr %out, i64 %in, i
; GCN1-NEXT: s_mov_b64 s[2:3], -1
; GCN1-NEXT: s_cbranch_scc0 .LBB93_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v0, s10
; GCN1-NEXT: v_mov_b32_e32 v1, s11
; GCN1-NEXT: v_mov_b32_e32 v2, s14
; GCN1-NEXT: v_mov_b32_e32 v3, s15
+; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v4, s0
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13685,11 +13685,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr %out, i64 %in, i
; GCN2-NEXT: s_mov_b64 s[2:3], -1
; GCN2-NEXT: s_cbranch_scc0 .LBB93_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v0, s10
; GCN2-NEXT: v_mov_b32_e32 v1, s11
; GCN2-NEXT: v_mov_b32_e32 v2, s14
; GCN2-NEXT: v_mov_b32_e32 v3, s15
+; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v4, s0
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13789,11 +13789,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr %out, ptr %o
; GCN1-NEXT: s_cmp_lg_u32 s4, 1
; GCN1-NEXT: s_cbranch_scc0 .LBB94_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s3
; GCN1-NEXT: v_mov_b32_e32 v0, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s13
; GCN1-NEXT: v_mov_b32_e32 v2, s0
; GCN1-NEXT: v_mov_b32_e32 v3, s1
+; GCN1-NEXT: v_mov_b32_e32 v5, s3
; GCN1-NEXT: v_mov_b32_e32 v4, s2
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13853,11 +13853,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr %out, ptr %o
; GCN2-NEXT: s_cmp_lg_u32 s4, 1
; GCN2-NEXT: s_cbranch_scc0 .LBB94_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s3
; GCN2-NEXT: v_mov_b32_e32 v0, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s13
; GCN2-NEXT: v_mov_b32_e32 v2, s0
; GCN2-NEXT: v_mov_b32_e32 v3, s1
+; GCN2-NEXT: v_mov_b32_e32 v5, s3
; GCN2-NEXT: v_mov_b32_e32 v4, s2
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -13969,11 +13969,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64(ptr %out, i64 %in, i64 %old) {
; GCN1-NEXT: s_mov_b64 s[6:7], -1
; GCN1-NEXT: s_cbranch_scc0 .LBB95_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v0, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s3
; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
+; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v4, s0
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14022,11 +14022,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64(ptr %out, i64 %in, i64 %old) {
; GCN2-NEXT: s_mov_b64 s[6:7], -1
; GCN2-NEXT: s_cbranch_scc0 .LBB95_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v0, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s3
; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
+; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v4, s0
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14116,11 +14116,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret(ptr %out, ptr %out2, i64 %in,
; GCN1-NEXT: s_cmp_lg_u32 s0, 1
; GCN1-NEXT: s_cbranch_scc0 .LBB96_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v4, s8
; GCN1-NEXT: v_mov_b32_e32 v0, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s13
; GCN1-NEXT: v_mov_b32_e32 v2, s14
; GCN1-NEXT: v_mov_b32_e32 v3, s15
+; GCN1-NEXT: v_mov_b32_e32 v4, s8
; GCN1-NEXT: v_mov_b32_e32 v5, s9
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14174,11 +14174,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret(ptr %out, ptr %out2, i64 %in,
; GCN2-NEXT: s_cmp_lg_u32 s0, 1
; GCN2-NEXT: s_cbranch_scc0 .LBB96_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v4, s8
; GCN2-NEXT: v_mov_b32_e32 v0, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s13
; GCN2-NEXT: v_mov_b32_e32 v2, s14
; GCN2-NEXT: v_mov_b32_e32 v3, s15
+; GCN2-NEXT: v_mov_b32_e32 v4, s8
; GCN2-NEXT: v_mov_b32_e32 v5, s9
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14284,11 +14284,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr %out, i64 %in, i64 %ind
; GCN1-NEXT: s_mov_b64 s[2:3], -1
; GCN1-NEXT: s_cbranch_scc0 .LBB97_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v0, s10
; GCN1-NEXT: v_mov_b32_e32 v1, s11
; GCN1-NEXT: v_mov_b32_e32 v2, s14
; GCN1-NEXT: v_mov_b32_e32 v3, s15
+; GCN1-NEXT: v_mov_b32_e32 v5, s1
; GCN1-NEXT: v_mov_b32_e32 v4, s0
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14339,11 +14339,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr %out, i64 %in, i64 %ind
; GCN2-NEXT: s_mov_b64 s[2:3], -1
; GCN2-NEXT: s_cbranch_scc0 .LBB97_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v0, s10
; GCN2-NEXT: v_mov_b32_e32 v1, s11
; GCN2-NEXT: v_mov_b32_e32 v2, s14
; GCN2-NEXT: v_mov_b32_e32 v3, s15
+; GCN2-NEXT: v_mov_b32_e32 v5, s1
; GCN2-NEXT: v_mov_b32_e32 v4, s0
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14439,11 +14439,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr %out, ptr %out2, i6
; GCN1-NEXT: s_cmp_lg_u32 s4, 1
; GCN1-NEXT: s_cbranch_scc0 .LBB98_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN1-NEXT: v_mov_b32_e32 v5, s3
; GCN1-NEXT: v_mov_b32_e32 v0, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s13
; GCN1-NEXT: v_mov_b32_e32 v2, s0
; GCN1-NEXT: v_mov_b32_e32 v3, s1
+; GCN1-NEXT: v_mov_b32_e32 v5, s3
; GCN1-NEXT: v_mov_b32_e32 v4, s2
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14501,11 +14501,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr %out, ptr %out2, i6
; GCN2-NEXT: s_cmp_lg_u32 s4, 1
; GCN2-NEXT: s_cbranch_scc0 .LBB98_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
-; GCN2-NEXT: v_mov_b32_e32 v5, s3
; GCN2-NEXT: v_mov_b32_e32 v0, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s13
; GCN2-NEXT: v_mov_b32_e32 v2, s0
; GCN2-NEXT: v_mov_b32_e32 v3, s1
+; GCN2-NEXT: v_mov_b32_e32 v5, s3
; GCN2-NEXT: v_mov_b32_e32 v4, s2
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15029,8 +15029,8 @@ define amdgpu_kernel void @atomic_inc_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB107_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15082,8 +15082,8 @@ define amdgpu_kernel void @atomic_inc_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB107_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15180,8 +15180,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB108_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15240,8 +15240,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB108_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15357,8 +15357,8 @@ define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB109_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15415,8 +15415,8 @@ define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB109_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15521,8 +15521,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB110_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15583,8 +15583,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB110_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15696,8 +15696,8 @@ define amdgpu_kernel void @atomic_inc_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB111_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15747,8 +15747,8 @@ define amdgpu_kernel void @atomic_inc_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB111_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15841,8 +15841,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB112_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15899,8 +15899,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB112_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16012,8 +16012,8 @@ define amdgpu_kernel void @atomic_inc_i64_incr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB113_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16067,8 +16067,8 @@ define amdgpu_kernel void @atomic_inc_i64_incr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB113_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16169,8 +16169,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB114_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16229,8 +16229,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB114_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16342,8 +16342,8 @@ define amdgpu_kernel void @atomic_dec_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB115_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16397,8 +16397,8 @@ define amdgpu_kernel void @atomic_dec_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB115_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16499,8 +16499,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB116_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16562,8 +16562,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB116_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16684,8 +16684,8 @@ define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: s_cbranch_scc0 .LBB117_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16744,8 +16744,8 @@ define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: s_cbranch_scc0 .LBB117_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16854,8 +16854,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_cbranch_scc0 .LBB118_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16919,8 +16919,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_cbranch_scc0 .LBB118_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17037,8 +17037,8 @@ define amdgpu_kernel void @atomic_dec_i64(ptr %out, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB119_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17090,8 +17090,8 @@ define amdgpu_kernel void @atomic_dec_i64(ptr %out, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB119_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17188,8 +17188,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: s_cbranch_scc0 .LBB120_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s4
; GCN1-NEXT: v_mov_b32_e32 v3, s5
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17249,8 +17249,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: s_cbranch_scc0 .LBB120_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s4
; GCN2-NEXT: v_mov_b32_e32 v3, s5
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17367,8 +17367,8 @@ define amdgpu_kernel void @atomic_dec_i64_decr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: s_cbranch_scc0 .LBB121_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s2
; GCN1-NEXT: v_mov_b32_e32 v3, s3
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17424,8 +17424,8 @@ define amdgpu_kernel void @atomic_dec_i64_decr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: s_cbranch_scc0 .LBB121_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s2
; GCN2-NEXT: v_mov_b32_e32 v3, s3
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17530,8 +17530,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_cbranch_scc0 .LBB122_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s0
-; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v1, s1
+; GCN1-NEXT: v_mov_b32_e32 v2, s12
; GCN1-NEXT: v_mov_b32_e32 v3, s13
; GCN1-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17593,8 +17593,8 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_cbranch_scc0 .LBB122_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s0
-; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v1, s1
+; GCN2-NEXT: v_mov_b32_e32 v2, s12
; GCN2-NEXT: v_mov_b32_e32 v3, s13
; GCN2-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
index 86e9e4f0b2292..f59729f936544 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
@@ -10,9 +10,9 @@ define amdgpu_kernel void @atomic_add_i64_offset(ptr %out, i64 %in) {
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_atomic_add_x2 v[2:3], v[0:1]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -25,9 +25,9 @@ define amdgpu_kernel void @atomic_add_i64_offset(ptr %out, i64 %in) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_atomic_add_x2 v[2:3], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -59,8 +59,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -78,8 +78,8 @@ define amdgpu_kernel void @atomic_add_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1215,8 +1215,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v8, v3
; GFX7-NEXT: v_mov_b32_e32 v7, v2
+; GFX7-NEXT: v_mov_b32_e32 v8, v3
; GFX7-NEXT: v_subrev_i32_e32 v5, vcc, s4, v7
; GFX7-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[5:8] glc
@@ -1249,8 +1249,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v8, v3
; GFX8-NEXT: v_mov_b32_e32 v7, v2
+; GFX8-NEXT: v_mov_b32_e32 v8, v3
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v7
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[5:8] glc
@@ -1396,8 +1396,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX7-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v8, v3
; GFX7-NEXT: v_mov_b32_e32 v7, v2
+; GFX7-NEXT: v_mov_b32_e32 v8, v3
; GFX7-NEXT: v_subrev_i32_e32 v5, vcc, s4, v7
; GFX7-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[5:8] glc
@@ -1432,8 +1432,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX8-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v8, v3
; GFX8-NEXT: v_mov_b32_e32 v7, v2
+; GFX8-NEXT: v_mov_b32_e32 v8, v3
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v7
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[5:8] glc
@@ -1483,8 +1483,8 @@ define amdgpu_kernel void @atomic_sub_i64(ptr %out, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v6, s3
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1512,8 +1512,8 @@ define amdgpu_kernel void @atomic_sub_i64(ptr %out, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1558,14 +1558,14 @@ define amdgpu_kernel void @atomic_sub_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s5
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v8, v1
; GFX7-NEXT: v_mov_b32_e32 v7, v0
+; GFX7-NEXT: v_mov_b32_e32 v8, v1
; GFX7-NEXT: v_subrev_i32_e32 v5, vcc, s4, v7
; GFX7-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1592,14 +1592,14 @@ define amdgpu_kernel void @atomic_sub_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s5
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_mov_b32_e32 v7, v0
+; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v7
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1737,8 +1737,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v8, v3
; GFX7-NEXT: v_mov_b32_e32 v7, v2
+; GFX7-NEXT: v_mov_b32_e32 v8, v3
; GFX7-NEXT: v_subrev_i32_e32 v5, vcc, s4, v7
; GFX7-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[5:8] glc
@@ -1771,8 +1771,8 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v8, v3
; GFX8-NEXT: v_mov_b32_e32 v7, v2
+; GFX8-NEXT: v_mov_b32_e32 v8, v3
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v7
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[5:8] glc
@@ -2179,9 +2179,9 @@ define amdgpu_kernel void @atomic_max_i64(ptr %out, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v6, s3
; GFX7-NEXT: v_mov_b32_e32 v7, s2
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2209,9 +2209,9 @@ define amdgpu_kernel void @atomic_max_i64(ptr %out, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2256,9 +2256,9 @@ define amdgpu_kernel void @atomic_max_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s5
; GFX7-NEXT: v_mov_b32_e32 v5, s4
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: .LBB29_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2291,9 +2291,9 @@ define amdgpu_kernel void @atomic_max_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: .LBB29_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2883,9 +2883,9 @@ define amdgpu_kernel void @atomic_umax_i64(ptr %out, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v6, s3
; GFX7-NEXT: v_mov_b32_e32 v7, s2
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: .LBB36_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2913,9 +2913,9 @@ define amdgpu_kernel void @atomic_umax_i64(ptr %out, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: .LBB36_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2960,9 +2960,9 @@ define amdgpu_kernel void @atomic_umax_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s5
; GFX7-NEXT: v_mov_b32_e32 v5, s4
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: .LBB37_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2995,9 +2995,9 @@ define amdgpu_kernel void @atomic_umax_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: .LBB37_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3587,9 +3587,9 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v6, s3
; GFX7-NEXT: v_mov_b32_e32 v7, s2
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: .LBB44_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3617,9 +3617,9 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: .LBB44_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3664,9 +3664,9 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s5
; GFX7-NEXT: v_mov_b32_e32 v5, s4
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: .LBB45_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3699,9 +3699,9 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: .LBB45_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4291,9 +4291,9 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v6, s3
; GFX7-NEXT: v_mov_b32_e32 v7, s2
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4321,9 +4321,9 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4368,9 +4368,9 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s5
; GFX7-NEXT: v_mov_b32_e32 v5, s4
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4403,9 +4403,9 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5306,9 +5306,9 @@ define amdgpu_kernel void @atomic_xchg_i64_offset(ptr %out, i64 %in) {
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5321,9 +5321,9 @@ define amdgpu_kernel void @atomic_xchg_i64_offset(ptr %out, i64 %in) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5353,9 +5353,9 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr %out, double %in) {
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5368,9 +5368,9 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr %out, double %in) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5400,9 +5400,9 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr %out, ptr %in) {
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5415,9 +5415,9 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr %out, ptr %in) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5449,8 +5449,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -5468,8 +5468,8 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6933,11 +6933,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr %out, i64 %in, i64 %old
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6951,11 +6951,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr %out, i64 %in, i64 %old
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -6989,11 +6989,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr %out, i64 %in, i64 %ol
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s0, s0, 0x11940
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7007,11 +7007,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr %out, i64 %in, i64 %ol
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s0, 0x11940
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7044,11 +7044,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(ptr %out, ptr %out2, i6
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mov_b32_e32 v2, s6
; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7064,11 +7064,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(ptr %out, ptr %out2, i6
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7109,11 +7109,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr %out, i64 %in, i
; GFX7-NEXT: s_addc_u32 s1, s1, s5
; GFX7-NEXT: s_add_u32 s0, s0, 32
; GFX7-NEXT: s_addc_u32 s1, s1, 0
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_mov_b32_e32 v2, s6
; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7129,11 +7129,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr %out, i64 %in, i
; GFX8-NEXT: s_addc_u32 s1, s1, s5
; GFX8-NEXT: s_add_u32 s0, s0, 32
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7172,10 +7172,10 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr %out, ptr %o
; GFX7-NEXT: s_addc_u32 s3, s9, s3
; GFX7-NEXT: s_add_u32 s2, s0, 32
; GFX7-NEXT: s_addc_u32 s3, s3, 0
-; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v0, s12
; GFX7-NEXT: v_mov_b32_e32 v1, s13
; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v4, s2
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7196,10 +7196,10 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr %out, ptr %o
; GFX8-NEXT: s_addc_u32 s3, s9, s3
; GFX8-NEXT: s_add_u32 s2, s0, 32
; GFX8-NEXT: s_addc_u32 s3, s3, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7351,11 +7351,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr %out, i64 %in, i64 %ind
; GFX7-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
; GFX7-NEXT: s_add_u32 s0, s0, s4
; GFX7-NEXT: s_addc_u32 s1, s1, s5
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_mov_b32_e32 v2, s6
; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7369,11 +7369,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr %out, i64 %in, i64 %ind
; GFX8-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
; GFX8-NEXT: s_add_u32 s0, s0, s4
; GFX8-NEXT: s_addc_u32 s1, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7408,11 +7408,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr %out, ptr %out2, i6
; GFX7-NEXT: s_lshl_b64 s[2:3], s[14:15], 3
; GFX7-NEXT: s_add_u32 s2, s8, s2
; GFX7-NEXT: s_addc_u32 s3, s9, s3
-; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v0, s12
; GFX7-NEXT: v_mov_b32_e32 v1, s13
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
; GFX7-NEXT: v_mov_b32_e32 v4, s2
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7430,11 +7430,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr %out, ptr %out2, i6
; GFX8-NEXT: s_lshl_b64 s[2:3], s[14:15], 3
; GFX8-NEXT: s_add_u32 s2, s8, s2
; GFX8-NEXT: s_addc_u32 s3, s9, s3
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -7976,8 +7976,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: .LBB108_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_mov_b32_e32 v4, v2
+; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 1, v4
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8012,8 +8012,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: .LBB108_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_mov_b32_e32 v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v4
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8165,8 +8165,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64_offset(ptr %out, ptr %out2,
; GFX7-NEXT: .LBB110_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_mov_b32_e32 v4, v2
+; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 1, v4
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8203,8 +8203,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64_offset(ptr %out, ptr %out2,
; GFX8-NEXT: .LBB110_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_mov_b32_e32 v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v4
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8339,8 +8339,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: .LBB112_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_mov_b32_e32 v4, v2
+; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 1, v4
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8373,8 +8373,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: .LBB112_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_mov_b32_e32 v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v4
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8518,8 +8518,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: .LBB114_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_mov_b32_e32 v4, v2
+; GFX7-NEXT: v_mov_b32_e32 v5, v3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 1, v4
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8554,8 +8554,8 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: .LBB114_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_mov_b32_e32 v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v5, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v4
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[4:5]
@@ -8997,9 +8997,9 @@ define amdgpu_kernel void @atomic_dec_i64(ptr %out, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v6, s3
; GFX7-NEXT: v_mov_b32_e32 v7, s2
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: .LBB119_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9031,9 +9031,9 @@ define amdgpu_kernel void @atomic_dec_i64(ptr %out, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: .LBB119_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
index 1630609012d6a..b6a06fa87b869 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
@@ -473,8 +473,8 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN1-NEXT: s_cbranch_scc0 .LBB4_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s4
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s5
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -513,8 +513,8 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN2-NEXT: s_cbranch_scc0 .LBB4_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s4
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s5
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -550,8 +550,8 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN3-NEXT: s_cbranch_scc0 .LBB4_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s4
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s5
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -593,8 +593,8 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: s_cbranch_scc0 .LBB5_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s34
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s35
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -635,8 +635,8 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: s_cbranch_scc0 .LBB5_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s34
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s35
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -674,8 +674,8 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: s_cbranch_scc0 .LBB5_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s34
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s35
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -715,8 +715,8 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN1-NEXT: s_cbranch_scc0 .LBB6_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s4
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s5
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -760,8 +760,8 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN2-NEXT: s_cbranch_scc0 .LBB6_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s4
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s5
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -802,8 +802,8 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN3-NEXT: s_cbranch_scc0 .LBB6_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s4
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s5
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -850,8 +850,8 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN1-NEXT: s_cbranch_scc0 .LBB7_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s34
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s35
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -897,8 +897,8 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN2-NEXT: s_cbranch_scc0 .LBB7_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s34
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s35
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -941,8 +941,8 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN3-NEXT: s_cbranch_scc0 .LBB7_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s34
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s35
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1675,8 +1675,8 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_scalar(ptr inreg %ptr, double
; GCN1-NEXT: s_cbranch_scc0 .LBB14_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s4
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s5
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1715,8 +1715,8 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_scalar(ptr inreg %ptr, double
; GCN2-NEXT: s_cbranch_scc0 .LBB14_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s4
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s5
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1752,8 +1752,8 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_scalar(ptr inreg %ptr, double
; GCN3-NEXT: s_cbranch_scc0 .LBB14_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s4
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s5
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1795,8 +1795,8 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: s_cbranch_scc0 .LBB15_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s34
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s35
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1837,8 +1837,8 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: s_cbranch_scc0 .LBB15_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s34
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s35
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1876,8 +1876,8 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: s_cbranch_scc0 .LBB15_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s34
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s35
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1917,8 +1917,8 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_scalar(ptr inreg %ptr, double
; GCN1-NEXT: s_cbranch_scc0 .LBB16_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s4
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s5
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1962,8 +1962,8 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_scalar(ptr inreg %ptr, double
; GCN2-NEXT: s_cbranch_scc0 .LBB16_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s4
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s5
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2004,8 +2004,8 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_scalar(ptr inreg %ptr, double
; GCN3-NEXT: s_cbranch_scc0 .LBB16_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s4
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s5
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2052,8 +2052,8 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: s_cbranch_scc0 .LBB17_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s34
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s35
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2099,8 +2099,8 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: s_cbranch_scc0 .LBB17_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s34
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s35
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2143,8 +2143,8 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: s_cbranch_scc0 .LBB17_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s34
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s35
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2935,8 +2935,8 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN1-NEXT: s_cbranch_scc0 .LBB24_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s4
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s5
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2980,8 +2980,8 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN2-NEXT: s_cbranch_scc0 .LBB24_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s4
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s5
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3022,8 +3022,8 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN3-NEXT: s_cbranch_scc0 .LBB24_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s4
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s5
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3070,8 +3070,8 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: s_cbranch_scc0 .LBB25_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s34
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s35
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3117,8 +3117,8 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: s_cbranch_scc0 .LBB25_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s34
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s35
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3161,8 +3161,8 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: s_cbranch_scc0 .LBB25_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s34
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s35
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_add_x2 v[0:1], v[2:3]
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3207,8 +3207,8 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN1-NEXT: s_cbranch_scc0 .LBB26_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s4
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s5
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3255,8 +3255,8 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN2-NEXT: s_cbranch_scc0 .LBB26_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s4
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s5
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3300,8 +3300,8 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN3-NEXT: s_cbranch_scc0 .LBB26_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s4
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s5
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3351,8 +3351,8 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN1-NEXT: s_cbranch_scc0 .LBB27_2
; GCN1-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN1-NEXT: v_mov_b32_e32 v0, s34
-; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v1, s35
+; GCN1-NEXT: v_mov_b32_e32 v2, s6
; GCN1-NEXT: v_mov_b32_e32 v3, s7
; GCN1-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3401,8 +3401,8 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN2-NEXT: s_cbranch_scc0 .LBB27_2
; GCN2-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN2-NEXT: v_mov_b32_e32 v0, s34
-; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v1, s35
+; GCN2-NEXT: v_mov_b32_e32 v2, s6
; GCN2-NEXT: v_mov_b32_e32 v3, s7
; GCN2-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3448,8 +3448,8 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN3-NEXT: s_cbranch_scc0 .LBB27_2
; GCN3-NEXT: ; %bb.1: ; %atomicrmw.global
; GCN3-NEXT: v_mov_b32_e32 v0, s34
-; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v1, s35
+; GCN3-NEXT: v_mov_b32_e32 v2, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -4126,8 +4126,8 @@ define i64 @flat_atomic_sub_i64_ret(ptr %ptr, i64 %in) {
; GCN1-NEXT: .LBB32_2: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v7, v5
; GCN1-NEXT: v_mov_b32_e32 v6, v4
+; GCN1-NEXT: v_mov_b32_e32 v7, v5
; GCN1-NEXT: v_sub_i32_e32 v4, vcc, v6, v2
; GCN1-NEXT: v_subb_u32_e32 v5, vcc, v7, v3, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -4184,8 +4184,8 @@ define i64 @flat_atomic_sub_i64_ret(ptr %ptr, i64 %in) {
; GCN2-NEXT: .LBB32_2: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v7, v5
; GCN2-NEXT: v_mov_b32_e32 v6, v4
+; GCN2-NEXT: v_mov_b32_e32 v7, v5
; GCN2-NEXT: v_sub_u32_e32 v4, vcc, v6, v2
; GCN2-NEXT: v_subb_u32_e32 v5, vcc, v7, v3, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -4245,8 +4245,8 @@ define i64 @flat_atomic_sub_i64_ret(ptr %ptr, i64 %in) {
; GCN3-NEXT: .LBB32_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
+; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_sub_co_u32_e32 v6, vcc, v8, v2
; GCN3-NEXT: v_subb_co_u32_e32 v7, vcc, v9, v3, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -4310,8 +4310,8 @@ define i64 @flat_atomic_sub_i64_ret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: .LBB33_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
+; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_sub_i32_e32 v6, vcc, v8, v2
; GCN1-NEXT: v_subb_u32_e32 v7, vcc, v9, v3, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -4372,8 +4372,8 @@ define i64 @flat_atomic_sub_i64_ret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: .LBB33_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
+; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_sub_u32_e32 v6, vcc, v8, v2
; GCN2-NEXT: v_subb_u32_e32 v7, vcc, v9, v3, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -4429,8 +4429,8 @@ define i64 @flat_atomic_sub_i64_ret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: .LBB33_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
+; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_sub_co_u32_e32 v6, vcc, v8, v2
; GCN3-NEXT: v_subb_co_u32_e32 v7, vcc, v9, v3, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -4862,8 +4862,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN1-NEXT: .LBB36_2: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v8, v1
; GCN1-NEXT: v_mov_b32_e32 v7, v0
+; GCN1-NEXT: v_mov_b32_e32 v8, v1
; GCN1-NEXT: v_subrev_i32_e32 v5, vcc, s6, v7
; GCN1-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -4923,8 +4923,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN2-NEXT: .LBB36_2: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v8, v1
; GCN2-NEXT: v_mov_b32_e32 v7, v0
+; GCN2-NEXT: v_mov_b32_e32 v8, v1
; GCN2-NEXT: v_subrev_u32_e32 v5, vcc, s6, v7
; GCN2-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -4976,8 +4976,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN3-NEXT: .LBB36_2: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v8, v1
; GCN3-NEXT: v_mov_b32_e32 v7, v0
+; GCN3-NEXT: v_mov_b32_e32 v8, v1
; GCN3-NEXT: v_subrev_co_u32_e32 v5, vcc, s6, v7
; GCN3-NEXT: v_subb_co_u32_e32 v6, vcc, v8, v4, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -5040,8 +5040,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN1-NEXT: .LBB37_2: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v8, v1
; GCN1-NEXT: v_mov_b32_e32 v7, v0
+; GCN1-NEXT: v_mov_b32_e32 v8, v1
; GCN1-NEXT: v_subrev_i32_e32 v5, vcc, s6, v7
; GCN1-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -5103,8 +5103,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN2-NEXT: .LBB37_2: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v8, v1
; GCN2-NEXT: v_mov_b32_e32 v7, v0
+; GCN2-NEXT: v_mov_b32_e32 v8, v1
; GCN2-NEXT: v_subrev_u32_e32 v5, vcc, s6, v7
; GCN2-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -5158,8 +5158,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN3-NEXT: .LBB37_2: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v8, v1
; GCN3-NEXT: v_mov_b32_e32 v7, v0
+; GCN3-NEXT: v_mov_b32_e32 v8, v1
; GCN3-NEXT: v_subrev_co_u32_e32 v5, vcc, s6, v7
; GCN3-NEXT: v_subb_co_u32_e32 v6, vcc, v8, v4, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -22168,8 +22168,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret(ptr %ptr, i64 %in) {
; GCN1-NEXT: .LBB133_2: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v7, v5
; GCN1-NEXT: v_mov_b32_e32 v6, v4
+; GCN1-NEXT: v_mov_b32_e32 v7, v5
; GCN1-NEXT: v_add_i32_e32 v4, vcc, 1, v6
; GCN1-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -22231,8 +22231,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret(ptr %ptr, i64 %in) {
; GCN2-NEXT: .LBB133_2: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v7, v5
; GCN2-NEXT: v_mov_b32_e32 v6, v4
+; GCN2-NEXT: v_mov_b32_e32 v7, v5
; GCN2-NEXT: v_add_u32_e32 v4, vcc, 1, v6
; GCN2-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -22297,8 +22297,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret(ptr %ptr, i64 %in) {
; GCN3-NEXT: .LBB133_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
+; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_add_co_u32_e32 v0, vcc, 1, v8
; GCN3-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v9, vcc
; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
@@ -22367,8 +22367,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: .LBB134_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
+; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_add_i32_e32 v0, vcc, 1, v8
; GCN1-NEXT: v_addc_u32_e32 v1, vcc, 0, v9, vcc
; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
@@ -22434,8 +22434,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: .LBB134_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
+; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_add_u32_e32 v0, vcc, 1, v8
; GCN2-NEXT: v_addc_u32_e32 v1, vcc, 0, v9, vcc
; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
@@ -22496,8 +22496,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: .LBB134_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
+; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_add_co_u32_e32 v0, vcc, 1, v8
; GCN3-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v9, vcc
; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
@@ -22957,8 +22957,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GCN1-NEXT: .LBB137_2: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v7, v1
; GCN1-NEXT: v_mov_b32_e32 v6, v0
+; GCN1-NEXT: v_mov_b32_e32 v7, v1
; GCN1-NEXT: v_add_i32_e32 v0, vcc, 1, v6
; GCN1-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -23022,8 +23022,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GCN2-NEXT: .LBB137_2: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v7, v1
; GCN2-NEXT: v_mov_b32_e32 v6, v0
+; GCN2-NEXT: v_mov_b32_e32 v7, v1
; GCN2-NEXT: v_add_u32_e32 v0, vcc, 1, v6
; GCN2-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -23079,8 +23079,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GCN3-NEXT: .LBB137_2: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v7, v1
; GCN3-NEXT: v_mov_b32_e32 v6, v0
+; GCN3-NEXT: v_mov_b32_e32 v7, v1
; GCN3-NEXT: v_add_co_u32_e32 v0, vcc, 1, v6
; GCN3-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc
; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -23147,8 +23147,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_offset_scalar(ptr inreg %ou
; GCN1-NEXT: .LBB138_2: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_mov_b32_e32 v7, v1
; GCN1-NEXT: v_mov_b32_e32 v6, v0
+; GCN1-NEXT: v_mov_b32_e32 v7, v1
; GCN1-NEXT: v_add_i32_e32 v0, vcc, 1, v6
; GCN1-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -23214,8 +23214,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_offset_scalar(ptr inreg %ou
; GCN2-NEXT: .LBB138_2: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_mov_b32_e32 v7, v1
; GCN2-NEXT: v_mov_b32_e32 v6, v0
+; GCN2-NEXT: v_mov_b32_e32 v7, v1
; GCN2-NEXT: v_add_u32_e32 v0, vcc, 1, v6
; GCN2-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -23273,8 +23273,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_offset_scalar(ptr inreg %ou
; GCN3-NEXT: .LBB138_2: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_mov_b32_e32 v7, v1
; GCN3-NEXT: v_mov_b32_e32 v6, v0
+; GCN3-NEXT: v_mov_b32_e32 v7, v1
; GCN3-NEXT: v_add_co_u32_e32 v0, vcc, 1, v6
; GCN3-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc
; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
index 8650baaf69a56..b334965dc228e 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
@@ -175,9 +175,9 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_offset_scalar(ptr inreg %out,
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s34, s4, 32
; GFX7-NEXT: s_addc_u32 s35, s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -189,9 +189,9 @@ define amdgpu_gfx void @flat_atomic_xchg_i64_noret_offset_scalar(ptr inreg %out,
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s34, s4, 32
; GFX8-NEXT: s_addc_u32 s35, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -260,9 +260,9 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s34, s4, 32
; GFX7-NEXT: s_addc_u32 s35, s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -274,9 +274,9 @@ define amdgpu_gfx i64 @flat_atomic_xchg_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s34, s4, 32
; GFX8-NEXT: s_addc_u32 s35, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -537,9 +537,9 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_offset_scalar(ptr inreg %out,
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s34, s4, 32
; GFX7-NEXT: s_addc_u32 s35, s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -551,9 +551,9 @@ define amdgpu_gfx void @flat_atomic_xchg_f64_noret_offset_scalar(ptr inreg %out,
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s34, s4, 32
; GFX8-NEXT: s_addc_u32 s35, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -622,9 +622,9 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_offset_scalar(ptr inreg %out,
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s34, s4, 32
; GFX7-NEXT: s_addc_u32 s35, s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -636,9 +636,9 @@ define amdgpu_gfx double @flat_atomic_xchg_f64_ret_offset_scalar(ptr inreg %out,
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s34, s4, 32
; GFX8-NEXT: s_addc_u32 s35, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -899,9 +899,9 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_offset_scalar(ptr inreg %out,
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s34, s4, 32
; GFX7-NEXT: s_addc_u32 s35, s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_atomic_add_x2 v[2:3], v[0:1]
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -913,9 +913,9 @@ define amdgpu_gfx void @flat_atomic_add_i64_noret_offset_scalar(ptr inreg %out,
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s34, s4, 32
; GFX8-NEXT: s_addc_u32 s35, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_atomic_add_x2 v[2:3], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -984,9 +984,9 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_add_u32 s34, s4, 32
; GFX7-NEXT: s_addc_u32 s35, s5, 0
-; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v0, s6
; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -998,9 +998,9 @@ define amdgpu_gfx i64 @flat_atomic_add_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_add_u32 s34, s4, 32
; GFX8-NEXT: s_addc_u32 s35, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1268,8 +1268,8 @@ define i64 @flat_atomic_sub_i64_ret(ptr %ptr, i64 %in) {
; GFX7-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_mov_b32_e32 v6, v4
+; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_sub_i32_e32 v4, vcc, v6, v2
; GFX7-NEXT: v_subb_u32_e32 v5, vcc, v7, v3, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -1296,8 +1296,8 @@ define i64 @flat_atomic_sub_i64_ret(ptr %ptr, i64 %in) {
; GFX8-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v7, v5
; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v6, v2
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v7, v3, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -1321,8 +1321,8 @@ define i64 @flat_atomic_sub_i64_ret(ptr %ptr, i64 %in) {
; GFX9-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v6, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v7, v3, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -1355,8 +1355,8 @@ define i64 @flat_atomic_sub_i64_ret_offset(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
+; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_sub_i32_e32 v6, vcc, v8, v2
; GFX7-NEXT: v_subb_u32_e32 v7, vcc, v9, v3, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -1383,8 +1383,8 @@ define i64 @flat_atomic_sub_i64_ret_offset(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
+; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v8, v2
; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v9, v3, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -1406,8 +1406,8 @@ define i64 @flat_atomic_sub_i64_ret_offset(ptr %out, i64 %in) {
; GFX9-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v6, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v7, v3, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] offset:32 glc
@@ -1431,17 +1431,17 @@ define amdgpu_gfx void @flat_atomic_sub_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX7-LABEL: flat_atomic_sub_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1464,17 +1464,17 @@ define amdgpu_gfx void @flat_atomic_sub_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX8-LABEL: flat_atomic_sub_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v6, s7
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1500,9 +1500,9 @@ define amdgpu_gfx void @flat_atomic_sub_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB34_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1598,9 +1598,9 @@ define amdgpu_gfx void @flat_atomic_sub_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB35_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1628,23 +1628,23 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_sub_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v4, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB36_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v8, v1
; GFX7-NEXT: v_mov_b32_e32 v7, v0
+; GFX7-NEXT: v_mov_b32_e32 v8, v1
; GFX7-NEXT: v_subrev_i32_e32 v5, vcc, s6, v7
; GFX7-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1661,23 +1661,23 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_sub_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v4, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB36_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_mov_b32_e32 v7, v0
+; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s6, v7
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1697,15 +1697,15 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB36_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
+; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s6, v7
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v8, v4, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1741,8 +1741,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX7-NEXT: .LBB37_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v8, v1
; GFX7-NEXT: v_mov_b32_e32 v7, v0
+; GFX7-NEXT: v_mov_b32_e32 v8, v1
; GFX7-NEXT: v_subrev_i32_e32 v5, vcc, s6, v7
; GFX7-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1774,8 +1774,8 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX8-NEXT: .LBB37_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_mov_b32_e32 v7, v0
+; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s6, v7
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1795,15 +1795,15 @@ define amdgpu_gfx i64 @flat_atomic_sub_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB37_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
+; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s6, v7
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v8, v4, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] offset:32 glc
@@ -2229,16 +2229,16 @@ define amdgpu_gfx void @flat_atomic_and_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX7-LABEL: flat_atomic_and_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB44_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2261,16 +2261,16 @@ define amdgpu_gfx void @flat_atomic_and_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX8-LABEL: flat_atomic_and_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB44_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2296,8 +2296,8 @@ define amdgpu_gfx void @flat_atomic_and_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB44_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2391,8 +2391,8 @@ define amdgpu_gfx void @flat_atomic_and_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB45_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2420,16 +2420,16 @@ define amdgpu_gfx i64 @flat_atomic_and_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_and_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2452,16 +2452,16 @@ define amdgpu_gfx i64 @flat_atomic_and_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_and_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2487,8 +2487,8 @@ define amdgpu_gfx i64 @flat_atomic_and_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2582,8 +2582,8 @@ define amdgpu_gfx i64 @flat_atomic_and_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB47_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3039,16 +3039,16 @@ define amdgpu_gfx void @flat_atomic_nand_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX7-LABEL: flat_atomic_nand_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3073,16 +3073,16 @@ define amdgpu_gfx void @flat_atomic_nand_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX8-LABEL: flat_atomic_nand_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3110,8 +3110,8 @@ define amdgpu_gfx void @flat_atomic_nand_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3211,8 +3211,8 @@ define amdgpu_gfx void @flat_atomic_nand_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3242,16 +3242,16 @@ define amdgpu_gfx i64 @flat_atomic_nand_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_nand_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3276,16 +3276,16 @@ define amdgpu_gfx i64 @flat_atomic_nand_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_nand_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3313,8 +3313,8 @@ define amdgpu_gfx i64 @flat_atomic_nand_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3414,8 +3414,8 @@ define amdgpu_gfx i64 @flat_atomic_nand_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3965,16 +3965,16 @@ define amdgpu_gfx void @flat_atomic_or_i64_noret_scalar(ptr inreg %ptr, i64 inre
; GFX7-LABEL: flat_atomic_or_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB64_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3997,16 +3997,16 @@ define amdgpu_gfx void @flat_atomic_or_i64_noret_scalar(ptr inreg %ptr, i64 inre
; GFX8-LABEL: flat_atomic_or_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB64_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4032,8 +4032,8 @@ define amdgpu_gfx void @flat_atomic_or_i64_noret_scalar(ptr inreg %ptr, i64 inre
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB64_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4127,8 +4127,8 @@ define amdgpu_gfx void @flat_atomic_or_i64_noret_offset_scalar(ptr inreg %out, i
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB65_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4156,16 +4156,16 @@ define amdgpu_gfx i64 @flat_atomic_or_i64_ret_scalar(ptr inreg %ptr, i64 inreg %
; GFX7-LABEL: flat_atomic_or_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB66_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4188,16 +4188,16 @@ define amdgpu_gfx i64 @flat_atomic_or_i64_ret_scalar(ptr inreg %ptr, i64 inreg %
; GFX8-LABEL: flat_atomic_or_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB66_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4223,8 +4223,8 @@ define amdgpu_gfx i64 @flat_atomic_or_i64_ret_scalar(ptr inreg %ptr, i64 inreg %
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB66_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4318,8 +4318,8 @@ define amdgpu_gfx i64 @flat_atomic_or_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB67_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4751,16 +4751,16 @@ define amdgpu_gfx void @flat_atomic_xor_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX7-LABEL: flat_atomic_xor_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB74_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4783,16 +4783,16 @@ define amdgpu_gfx void @flat_atomic_xor_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX8-LABEL: flat_atomic_xor_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB74_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4818,8 +4818,8 @@ define amdgpu_gfx void @flat_atomic_xor_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB74_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4913,8 +4913,8 @@ define amdgpu_gfx void @flat_atomic_xor_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB75_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4942,16 +4942,16 @@ define amdgpu_gfx i64 @flat_atomic_xor_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_xor_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB76_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4974,16 +4974,16 @@ define amdgpu_gfx i64 @flat_atomic_xor_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_xor_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB76_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5009,8 +5009,8 @@ define amdgpu_gfx i64 @flat_atomic_xor_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB76_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5104,8 +5104,8 @@ define amdgpu_gfx i64 @flat_atomic_xor_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB77_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5549,18 +5549,18 @@ define amdgpu_gfx void @flat_atomic_max_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX7-LABEL: flat_atomic_max_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
; GFX7-NEXT: v_mov_b32_e32 v7, s6
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB84_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5584,18 +5584,18 @@ define amdgpu_gfx void @flat_atomic_max_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX8-LABEL: flat_atomic_max_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v6, s7
; GFX8-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB84_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5622,10 +5622,10 @@ define amdgpu_gfx void @flat_atomic_max_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB84_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5726,10 +5726,10 @@ define amdgpu_gfx void @flat_atomic_max_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB85_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5758,18 +5758,18 @@ define amdgpu_gfx i64 @flat_atomic_max_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_max_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v4, s7
; GFX7-NEXT: v_mov_b32_e32 v5, s6
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB86_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5793,18 +5793,18 @@ define amdgpu_gfx i64 @flat_atomic_max_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_max_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v4, s7
; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB86_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5831,10 +5831,10 @@ define amdgpu_gfx i64 @flat_atomic_max_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB86_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5935,10 +5935,10 @@ define amdgpu_gfx i64 @flat_atomic_max_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB87_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6821,18 +6821,18 @@ define amdgpu_gfx void @flat_atomic_umax_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX7-LABEL: flat_atomic_umax_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
; GFX7-NEXT: v_mov_b32_e32 v7, s6
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB98_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6856,18 +6856,18 @@ define amdgpu_gfx void @flat_atomic_umax_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX8-LABEL: flat_atomic_umax_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v6, s7
; GFX8-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB98_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6894,10 +6894,10 @@ define amdgpu_gfx void @flat_atomic_umax_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB98_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6998,10 +6998,10 @@ define amdgpu_gfx void @flat_atomic_umax_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB99_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7030,18 +7030,18 @@ define amdgpu_gfx i64 @flat_atomic_umax_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_umax_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v4, s7
; GFX7-NEXT: v_mov_b32_e32 v5, s6
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB100_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7065,18 +7065,18 @@ define amdgpu_gfx i64 @flat_atomic_umax_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_umax_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v4, s7
; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB100_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7103,10 +7103,10 @@ define amdgpu_gfx i64 @flat_atomic_umax_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB100_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7207,10 +7207,10 @@ define amdgpu_gfx i64 @flat_atomic_umax_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB101_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7991,18 +7991,18 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX7-LABEL: flat_atomic_umin_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
; GFX7-NEXT: v_mov_b32_e32 v7, s6
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB111_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8026,18 +8026,18 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX8-LABEL: flat_atomic_umin_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v6, s7
; GFX8-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB111_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8064,10 +8064,10 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB111_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8168,10 +8168,10 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB112_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8200,18 +8200,18 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_umin_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v4, s7
; GFX7-NEXT: v_mov_b32_e32 v5, s6
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB113_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8235,18 +8235,18 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_umin_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v4, s7
; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB113_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8273,10 +8273,10 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB113_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8377,10 +8377,10 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB114_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8825,18 +8825,18 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX7-LABEL: flat_atomic_min_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
; GFX7-NEXT: v_mov_b32_e32 v7, s6
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB121_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8860,18 +8860,18 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX8-LABEL: flat_atomic_min_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v6, s7
; GFX8-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB121_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8898,10 +8898,10 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB121_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9002,10 +9002,10 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB122_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9034,18 +9034,18 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-LABEL: flat_atomic_min_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
; GFX7-NEXT: v_mov_b32_e32 v4, s7
; GFX7-NEXT: v_mov_b32_e32 v5, s6
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB123_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9069,18 +9069,18 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-LABEL: flat_atomic_min_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
; GFX8-NEXT: v_mov_b32_e32 v4, s7
; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB123_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9107,10 +9107,10 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB123_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9211,10 +9211,10 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB124_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9472,9 +9472,9 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v6, s3
; GFX7-NEXT: v_mov_b32_e32 v7, s2
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9502,9 +9502,9 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9532,9 +9532,9 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_mov_b32_e32 v6, s3
; GFX9-NEXT: v_mov_b32_e32 v7, s2
+; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_mov_b32_e32 v4, s0
; GFX9-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9933,8 +9933,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret(ptr %ptr, i64 %in) {
; GFX7-NEXT: .LBB133_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_mov_b32_e32 v6, v4
+; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_add_i32_e32 v4, vcc, 1, v6
; GFX7-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GFX7-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -9964,8 +9964,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret(ptr %ptr, i64 %in) {
; GFX8-NEXT: .LBB133_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v7, v5
; GFX8-NEXT: v_mov_b32_e32 v6, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, v5
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v6
; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -9992,8 +9992,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret(ptr %ptr, i64 %in) {
; GFX9-NEXT: .LBB133_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -10029,8 +10029,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret_offset(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB134_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
+; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 1, v8
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v9, vcc
; GFX7-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
@@ -10060,8 +10060,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret_offset(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB134_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
+; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v8
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v9, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
@@ -10086,8 +10086,8 @@ define i64 @flat_atomic_uinc_wrap_i64_ret_offset(ptr %out, i64 %in) {
; GFX9-NEXT: .LBB134_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -10114,16 +10114,16 @@ define amdgpu_gfx void @flat_atomic_uinc_wrap_i64_noret_scalar(ptr inreg %ptr, i
; GFX7-LABEL: flat_atomic_uinc_wrap_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB135_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10149,16 +10149,16 @@ define amdgpu_gfx void @flat_atomic_uinc_wrap_i64_noret_scalar(ptr inreg %ptr, i
; GFX8-LABEL: flat_atomic_uinc_wrap_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB135_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10187,8 +10187,8 @@ define amdgpu_gfx void @flat_atomic_uinc_wrap_i64_noret_scalar(ptr inreg %ptr, i
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB135_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10291,8 +10291,8 @@ define amdgpu_gfx void @flat_atomic_uinc_wrap_i64_noret_offset_scalar(ptr inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB136_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10323,22 +10323,22 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GFX7-LABEL: flat_atomic_uinc_wrap_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[34:35], 0
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB137_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v7, v1
; GFX7-NEXT: v_mov_b32_e32 v6, v0
+; GFX7-NEXT: v_mov_b32_e32 v7, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 1, v6
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -10358,22 +10358,22 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GFX8-LABEL: flat_atomic_uinc_wrap_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[34:35], 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB137_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v7, v1
; GFX8-NEXT: v_mov_b32_e32 v6, v0
+; GFX8-NEXT: v_mov_b32_e32 v7, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v6
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -10396,14 +10396,14 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB137_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_mov_b32_e32 v6, v0
+; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -10441,8 +10441,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_offset_scalar(ptr inreg %ou
; GFX7-NEXT: .LBB138_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v7, v1
; GFX7-NEXT: v_mov_b32_e32 v6, v0
+; GFX7-NEXT: v_mov_b32_e32 v7, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 1, v6
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -10476,8 +10476,8 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_offset_scalar(ptr inreg %ou
; GFX8-NEXT: .LBB138_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v7, v1
; GFX8-NEXT: v_mov_b32_e32 v6, v0
+; GFX8-NEXT: v_mov_b32_e32 v7, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v6
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -10500,14 +10500,14 @@ define amdgpu_gfx i64 @flat_atomic_uinc_wrap_i64_ret_offset_scalar(ptr inreg %ou
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB138_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_mov_b32_e32 v6, v0
+; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -10984,18 +10984,18 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i64_noret_scalar(ptr inreg %ptr, i
; GFX7-LABEL: flat_atomic_udec_wrap_i64_noret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v3, s34
; GFX7-NEXT: v_mov_b32_e32 v4, s35
; GFX7-NEXT: flat_load_dword v2, v[0:1]
; GFX7-NEXT: flat_load_dword v3, v[3:4]
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: s_mov_b64 s[36:37], 0
; GFX7-NEXT: v_mov_b32_e32 v6, s7
; GFX7-NEXT: v_mov_b32_e32 v7, s6
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: .LBB145_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11022,18 +11022,18 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i64_noret_scalar(ptr inreg %ptr, i
; GFX8-LABEL: flat_atomic_udec_wrap_i64_noret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s34
; GFX8-NEXT: v_mov_b32_e32 v4, s35
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v3, v[3:4]
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: s_mov_b64 s[36:37], 0
; GFX8-NEXT: v_mov_b32_e32 v6, s7
; GFX8-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: .LBB145_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11063,10 +11063,10 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i64_noret_scalar(ptr inreg %ptr, i
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[36:37], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB145_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11176,10 +11176,10 @@ define amdgpu_gfx void @flat_atomic_udec_wrap_i64_noret_offset_scalar(ptr inreg
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: s_mov_b64 s[36:37], 0
; GFX9-NEXT: v_mov_b32_e32 v6, s7
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: .LBB146_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11211,18 +11211,18 @@ define amdgpu_gfx i64 @flat_atomic_udec_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GFX7-LABEL: flat_atomic_udec_wrap_i64_ret_scalar:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s34, s4, 4
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s35, s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s34
; GFX7-NEXT: v_mov_b32_e32 v3, s35
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: flat_load_dword v1, v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b64 s[36:37], 0
; GFX7-NEXT: v_mov_b32_e32 v4, s7
; GFX7-NEXT: v_mov_b32_e32 v5, s6
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: .LBB147_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11249,18 +11249,18 @@ define amdgpu_gfx i64 @flat_atomic_udec_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GFX8-LABEL: flat_atomic_udec_wrap_i64_ret_scalar:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s34, s4, 4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s35, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: flat_load_dword v1, v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b64 s[36:37], 0
; GFX8-NEXT: v_mov_b32_e32 v4, s7
; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: .LBB147_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11290,10 +11290,10 @@ define amdgpu_gfx i64 @flat_atomic_udec_wrap_i64_ret_scalar(ptr inreg %ptr, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[36:37], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB147_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11403,10 +11403,10 @@ define amdgpu_gfx i64 @flat_atomic_udec_wrap_i64_ret_offset_scalar(ptr inreg %ou
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: flat_load_dwordx2 v[0:1], v[0:1] offset:32
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_mov_b64 s[36:37], 0
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: .LBB148_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index c89576707f28d..1f433f11d120e 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -1160,9 +1160,9 @@ define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s9
; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s10
; GFX9-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s10
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s11
; GFX9-SDAG-NEXT: v_max_f64 v[4:5], s[2:3], v[1:2]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[1:2]
@@ -1196,9 +1196,9 @@ define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s13
; GFX9-GISEL-NEXT: s_cselect_b64 s[10:11], s[0:1], s[8:9]
; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[4:5], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
index 8ec4d3fb29535..f508801330902 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
@@ -1145,9 +1145,9 @@ define amdgpu_kernel void @test_fmax_v16f32(ptr addrspace(1) %out, <16 x float>
; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19
; GFX12-GISEL-NEXT: s_clause 0x3
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.ll b/llvm/test/CodeGen/AMDGPU/fmed3.ll
index 5e170cff3e32f..f918034131378 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.ll
@@ -806,8 +806,8 @@ define amdgpu_kernel void @v_test_fmed3_r_i_i_f64(ptr addrspace(1) %out, ptr add
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; VI-GISEL-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 194bf6377bf2e..8cd003dca8073 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -1160,9 +1160,9 @@ define amdgpu_ps <8 x float> @test_fminimum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s9
; GFX9-SDAG-NEXT: v_min_f64 v[2:3], s[0:1], v[0:1]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s10
; GFX9-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s10
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s11
; GFX9-SDAG-NEXT: v_min_f64 v[4:5], s[2:3], v[1:2]
; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[1:2]
@@ -1196,9 +1196,9 @@ define amdgpu_ps <8 x float> @test_fminimum_v4f64_ss(<4 x double> inreg %a, <4 x
; GFX9-GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[2:3], v[0:1]
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX9-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s13
; GFX9-GISEL-NEXT: s_cselect_b64 s[10:11], s[0:1], s[8:9]
; GFX9-GISEL-NEXT: v_min_f64 v[2:3], s[4:5], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll
index cf927b83c07de..b4aeb148aa670 100644
--- a/llvm/test/CodeGen/AMDGPU/fminnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll
@@ -1060,9 +1060,9 @@ define amdgpu_kernel void @test_fmin_v16f32(ptr addrspace(1) %out, <16 x float>
; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17
; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19
; GFX12-GISEL-NEXT: s_clause 0x3
; GFX12-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], null
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll b/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
index 02ce8be125afc..fd9e2845cdd4c 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
@@ -88,17 +88,17 @@ define amdgpu_kernel void @multiple_use_fadd_fmac_f32(ptr addrspace(1) %out, flo
; VI-NEXT: s_add_i32 s12, s12, s17
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_add_u32 s2, s0, 4
+; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: v_add_f32_e64 v2, s4, s4
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mac_f32_e64 v3, s4, 2.0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mac_f32_e64 v3, s4, 2.0
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -151,16 +151,16 @@ define amdgpu_kernel void @multiple_use_fadd_fmad_f32(ptr addrspace(1) %out, flo
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_add_u32 s4, s0, 4
; VI-NEXT: v_add_f32_e64 v2, |s2|, |s2|
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v3, s3
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_addc_u32 s5, s1, 0
+; VI-NEXT: v_mad_f32 v3, |s2|, 2.0, v3
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: v_mad_f32 v3, |s2|, 2.0, v3
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -212,11 +212,11 @@ define amdgpu_kernel void @multiple_use_fadd_multi_fmad_f32(ptr addrspace(1) %ou
; VI-NEXT: s_add_u32 s6, s4, 4
; VI-NEXT: v_mov_b32_e32 v0, s1
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: s_addc_u32 s7, s5, 0
; VI-NEXT: v_mad_f32 v2, |s0|, 2.0, v0
; VI-NEXT: v_mad_f32 v3, |s0|, 2.0, v1
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
-; VI-NEXT: s_addc_u32 s7, s5, 0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s6
@@ -324,9 +324,9 @@ define amdgpu_kernel void @fmul_x2_xn3_f32(ptr addrspace(1) %out, float %x, floa
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mul_f32_e32 v0, s2, v0
+; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mul_f32_e32 v2, s2, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -556,13 +556,13 @@ define amdgpu_kernel void @multiple_use_fadd_fmac_f16(ptr addrspace(1) %out, i16
; VI-DENORM-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-DENORM-NEXT: s_waitcnt lgkmcnt(0)
; VI-DENORM-NEXT: s_lshr_b32 s3, s4, 16
+; VI-DENORM-NEXT: s_add_u32 s2, s0, 2
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s3
+; VI-DENORM-NEXT: v_add_f16_e64 v2, s4, s4
+; VI-DENORM-NEXT: s_addc_u32 s3, s1, 0
; VI-DENORM-NEXT: v_fma_f16 v3, s4, 2.0, v0
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s0
-; VI-DENORM-NEXT: v_add_f16_e64 v2, s4, s4
-; VI-DENORM-NEXT: s_add_u32 s2, s0, 2
; VI-DENORM-NEXT: v_mov_b32_e32 v1, s1
-; VI-DENORM-NEXT: s_addc_u32 s3, s1, 0
; VI-DENORM-NEXT: flat_store_short v[0:1], v2
; VI-DENORM-NEXT: s_waitcnt vmcnt(0)
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s2
@@ -580,16 +580,16 @@ define amdgpu_kernel void @multiple_use_fadd_fmac_f16(ptr addrspace(1) %out, i16
; VI-FLUSH-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-FLUSH-NEXT: s_waitcnt lgkmcnt(0)
; VI-FLUSH-NEXT: s_lshr_b32 s3, s4, 16
-; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s0
-; VI-FLUSH-NEXT: v_add_f16_e64 v2, s4, s4
; VI-FLUSH-NEXT: s_add_u32 s2, s0, 2
-; VI-FLUSH-NEXT: v_mov_b32_e32 v1, s1
+; VI-FLUSH-NEXT: v_add_f16_e64 v2, s4, s4
; VI-FLUSH-NEXT: v_mov_b32_e32 v3, s3
; VI-FLUSH-NEXT: s_addc_u32 s3, s1, 0
+; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s0
+; VI-FLUSH-NEXT: v_mov_b32_e32 v1, s1
+; VI-FLUSH-NEXT: v_mac_f16_e64 v3, s4, 2.0
; VI-FLUSH-NEXT: flat_store_short v[0:1], v2
; VI-FLUSH-NEXT: s_waitcnt vmcnt(0)
; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s2
-; VI-FLUSH-NEXT: v_mac_f16_e64 v3, s4, 2.0
; VI-FLUSH-NEXT: v_mov_b32_e32 v1, s3
; VI-FLUSH-NEXT: flat_store_short v[0:1], v3
; VI-FLUSH-NEXT: s_waitcnt vmcnt(0)
@@ -712,13 +712,13 @@ define amdgpu_kernel void @multiple_use_fadd_fmad_f16(ptr addrspace(1) %out, i16
; VI-DENORM-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-DENORM-NEXT: s_waitcnt lgkmcnt(0)
; VI-DENORM-NEXT: s_lshr_b32 s3, s4, 16
+; VI-DENORM-NEXT: s_add_u32 s2, s0, 2
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s3
+; VI-DENORM-NEXT: v_add_f16_e64 v2, |s4|, |s4|
+; VI-DENORM-NEXT: s_addc_u32 s3, s1, 0
; VI-DENORM-NEXT: v_fma_f16 v3, |s4|, 2.0, v0
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s0
-; VI-DENORM-NEXT: v_add_f16_e64 v2, |s4|, |s4|
-; VI-DENORM-NEXT: s_add_u32 s2, s0, 2
; VI-DENORM-NEXT: v_mov_b32_e32 v1, s1
-; VI-DENORM-NEXT: s_addc_u32 s3, s1, 0
; VI-DENORM-NEXT: flat_store_short v[0:1], v2
; VI-DENORM-NEXT: s_waitcnt vmcnt(0)
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s2
@@ -736,13 +736,13 @@ define amdgpu_kernel void @multiple_use_fadd_fmad_f16(ptr addrspace(1) %out, i16
; VI-FLUSH-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-FLUSH-NEXT: s_waitcnt lgkmcnt(0)
; VI-FLUSH-NEXT: s_lshr_b32 s3, s4, 16
+; VI-FLUSH-NEXT: s_add_u32 s2, s0, 2
; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s3
+; VI-FLUSH-NEXT: v_add_f16_e64 v2, |s4|, |s4|
+; VI-FLUSH-NEXT: s_addc_u32 s3, s1, 0
; VI-FLUSH-NEXT: v_mad_f16 v3, |s4|, 2.0, v0
; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s0
-; VI-FLUSH-NEXT: v_add_f16_e64 v2, |s4|, |s4|
-; VI-FLUSH-NEXT: s_add_u32 s2, s0, 2
; VI-FLUSH-NEXT: v_mov_b32_e32 v1, s1
-; VI-FLUSH-NEXT: s_addc_u32 s3, s1, 0
; VI-FLUSH-NEXT: flat_store_short v[0:1], v2
; VI-FLUSH-NEXT: s_waitcnt vmcnt(0)
; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s2
@@ -869,13 +869,13 @@ define amdgpu_kernel void @multiple_use_fadd_multi_fmad_f16(ptr addrspace(1) %ou
; VI-DENORM-NEXT: s_waitcnt lgkmcnt(0)
; VI-DENORM-NEXT: s_lshr_b32 s5, s2, 16
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s3
+; VI-DENORM-NEXT: s_add_u32 s4, s0, 2
; VI-DENORM-NEXT: v_mov_b32_e32 v1, s5
; VI-DENORM-NEXT: v_fma_f16 v2, |s2|, 2.0, v0
+; VI-DENORM-NEXT: s_addc_u32 s5, s1, 0
; VI-DENORM-NEXT: v_fma_f16 v3, |s2|, 2.0, v1
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s0
-; VI-DENORM-NEXT: s_add_u32 s4, s0, 2
; VI-DENORM-NEXT: v_mov_b32_e32 v1, s1
-; VI-DENORM-NEXT: s_addc_u32 s5, s1, 0
; VI-DENORM-NEXT: flat_store_short v[0:1], v3
; VI-DENORM-NEXT: s_waitcnt vmcnt(0)
; VI-DENORM-NEXT: v_mov_b32_e32 v0, s4
@@ -893,13 +893,13 @@ define amdgpu_kernel void @multiple_use_fadd_multi_fmad_f16(ptr addrspace(1) %ou
; VI-FLUSH-NEXT: s_waitcnt lgkmcnt(0)
; VI-FLUSH-NEXT: s_lshr_b32 s5, s2, 16
; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s3
+; VI-FLUSH-NEXT: s_add_u32 s4, s0, 2
; VI-FLUSH-NEXT: v_mov_b32_e32 v1, s5
; VI-FLUSH-NEXT: v_mad_f16 v2, |s2|, 2.0, v0
+; VI-FLUSH-NEXT: s_addc_u32 s5, s1, 0
; VI-FLUSH-NEXT: v_mad_f16 v3, |s2|, 2.0, v1
; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s0
-; VI-FLUSH-NEXT: s_add_u32 s4, s0, 2
; VI-FLUSH-NEXT: v_mov_b32_e32 v1, s1
-; VI-FLUSH-NEXT: s_addc_u32 s5, s1, 0
; VI-FLUSH-NEXT: flat_store_short v[0:1], v3
; VI-FLUSH-NEXT: s_waitcnt vmcnt(0)
; VI-FLUSH-NEXT: v_mov_b32_e32 v0, s4
@@ -1086,9 +1086,9 @@ define amdgpu_kernel void @fmul_x2_xn3_f16(ptr addrspace(1) %out, i16 zeroext %x
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mul_f16_e32 v0, s2, v0
+; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mul_f16_e32 v2, s2, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/fnearbyint.ll b/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
index 6113cde077bc5..4ca8b53125af2 100644
--- a/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
@@ -121,9 +121,9 @@ define amdgpu_kernel void @fnearbyint_v2f32(ptr addrspace(1) %out, <2 x float> %
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_rndne_f32_e32 v1, s3
; VI-NEXT: v_rndne_f32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -164,10 +164,10 @@ define amdgpu_kernel void @fnearbyint_v4f32(ptr addrspace(1) %out, <4 x float> %
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_rndne_f32_e32 v3, s3
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_rndne_f32_e32 v2, s2
; VI-NEXT: v_rndne_f32_e32 v1, s1
; VI-NEXT: v_rndne_f32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -256,14 +256,14 @@ define amdgpu_kernel void @nearbyint_v2f64(ptr addrspace(1) %out, <2 x double> %
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; SI-NEXT: s_brev_b32 s10, -2
; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
-; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v7, s3
; SI-NEXT: v_bfi_b32 v1, s10, v6, v7
-; SI-NEXT: v_mov_b32_e32 v0, 0
-; SI-NEXT: s_mov_b32 s8, s6
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_add_f64 v[2:3], s[2:3], v[0:1]
; SI-NEXT: s_mov_b32 s9, 0x432fffff
+; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_mov_b32_e32 v5, s9
; SI-NEXT: v_add_f64 v[2:3], v[2:3], -v[0:1]
@@ -332,14 +332,14 @@ define amdgpu_kernel void @nearbyint_v4f64(ptr addrspace(1) %out, <4 x double> %
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x11
; SI-NEXT: s_brev_b32 s6, -2
; SI-NEXT: v_mov_b32_e32 v10, 0x43300000
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: v_mov_b32_e32 v4, 0
+; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s11
; SI-NEXT: v_bfi_b32 v5, s6, v10, v2
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_mov_b32 s5, 0x432fffff
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: v_add_f64 v[0:1], s[10:11], v[4:5]
+; SI-NEXT: s_mov_b32 s5, 0x432fffff
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: v_mov_b32_e32 v9, s5
; SI-NEXT: v_mov_b32_e32 v8, s4
@@ -373,6 +373,7 @@ define amdgpu_kernel void @nearbyint_v4f64(ptr addrspace(1) %out, <4 x double> %
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
@@ -404,8 +405,8 @@ define amdgpu_kernel void @nearbyint_v4f64(ptr addrspace(1) %out, <4 x double> %
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: v_mov_b32_e32 v11, s3
-; VI-NEXT: v_mov_b32_e32 v9, s1
; VI-NEXT: v_mov_b32_e32 v10, s2
+; VI-NEXT: v_mov_b32_e32 v9, s1
; VI-NEXT: v_mov_b32_e32 v8, s0
; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
index cfa5247267559..a432aae9f9757 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
@@ -7825,21 +7825,21 @@ define amdgpu_kernel void @one_use_cost_to_fold_into_src_f32(ptr addrspace(1) %o
; SI-NEXT: v_mov_b32_e32 v5, s15
; SI-NEXT: v_add_i32_e32 v4, vcc, s14, v6
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; SI-NEXT: v_mov_b32_e32 v7, s1
; SI-NEXT: flat_load_dword v8, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_load_dword v2, v[2:3] glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: flat_load_dword v3, v[4:5] glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v7, s1
; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v6
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; SI-NEXT: flat_load_dword v0, v[0:1] glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_trunc_f32_e32 v0, v8
; SI-NEXT: v_fma_f32 v2, -v0, v2, v3
; SI-NEXT: v_mov_b32_e32 v0, s8
-; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: flat_store_dword v[0:1], v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm
@@ -7859,21 +7859,21 @@ define amdgpu_kernel void @one_use_cost_to_fold_into_src_f32(ptr addrspace(1) %o
; VI-NEXT: v_mov_b32_e32 v5, s15
; VI-NEXT: v_add_u32_e32 v4, vcc, s14, v6
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: flat_load_dword v8, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s9
; VI-NEXT: v_trunc_f32_e32 v0, v8
; VI-NEXT: v_fma_f32 v2, -v0, v2, v3
; VI-NEXT: v_mov_b32_e32 v0, s8
-; VI-NEXT: v_mov_b32_e32 v1, s9
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 3cbde439cdf99..b46fc3aa5bc6b 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -4252,9 +4252,9 @@ define amdgpu_kernel void @s_fneg_select_infloop_regression_f64(double %arg, i1
; SI-NEXT: s_and_b64 s[6:7], s[4:5], exec
; SI-NEXT: v_cndmask_b32_e64 v0, -v1, v0, s[4:5]
; SI-NEXT: s_cselect_b32 s0, 0, s0
-; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: v_mov_b32_e32 v3, s3
; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SI-NEXT: s_endpgm
@@ -4272,9 +4272,9 @@ define amdgpu_kernel void @s_fneg_select_infloop_regression_f64(double %arg, i1
; VI-NEXT: s_and_b64 s[6:7], s[4:5], exec
; VI-NEXT: v_cndmask_b32_e64 v0, -v1, v0, s[4:5]
; VI-NEXT: s_cselect_b32 s0, 0, s0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
index 5424ebfcffcd1..4c994814dbc6f 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
@@ -410,9 +410,9 @@ define amdgpu_kernel void @s_fneg_fabs_v2bf16_non_bc_src(ptr addrspace(1) %out,
; CI-NEXT: v_add_f32_e64 v0, s3, 1.0
; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; CI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
+; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_or_b32_e32 v2, 0x80008000, v0
; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
;
@@ -442,9 +442,9 @@ define amdgpu_kernel void @s_fneg_fabs_v2bf16_non_bc_src(ptr addrspace(1) %out,
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_or_b32_e32 v2, 0x80008000, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -626,9 +626,9 @@ define amdgpu_kernel void @fneg_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat>
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_or_b32 s3, s3, 0x80008000
; CI-NEXT: s_or_b32 s2, s2, 0x80008000
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -652,9 +652,9 @@ define amdgpu_kernel void @fneg_fabs_v4bf16(ptr addrspace(1) %out, <4 x bfloat>
; VI-NEXT: s_lshl_b32 s4, s4, 16
; VI-NEXT: s_or_b32 s3, s3, s5
; VI-NEXT: s_or_b32 s2, s2, s4
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
index 00d53cd265c28..56f62a7f68218 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
@@ -408,9 +408,9 @@ define amdgpu_kernel void @s_fneg_fabs_v2f16_non_bc_src(ptr addrspace(1) %out, <
; VI-NEXT: v_add_f16_e64 v1, s2, 1.0
; VI-NEXT: v_add_f16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v1, v0
+; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_or_b32_e32 v2, 0x80008000, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
@@ -517,9 +517,9 @@ define amdgpu_kernel void @fneg_fabs_v4f16(ptr addrspace(1) %out, <4 x half> %in
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
; CIVI-NEXT: s_or_b32 s3, s3, 0x80008000
; CIVI-NEXT: s_or_b32 s2, s2, 0x80008000
-; CIVI-NEXT: v_mov_b32_e32 v3, s1
; CIVI-NEXT: v_mov_b32_e32 v0, s2
; CIVI-NEXT: v_mov_b32_e32 v1, s3
+; CIVI-NEXT: v_mov_b32_e32 v3, s1
; CIVI-NEXT: v_mov_b32_e32 v2, s0
; CIVI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CIVI-NEXT: s_endpgm
@@ -589,9 +589,9 @@ define amdgpu_kernel void @fold_user_fneg_fabs_v2f16(ptr addrspace(1) %out, <2 x
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: v_mul_f16_e64 v1, |s2|, -4.0
; VI-NEXT: v_mul_f16_sdwa v0, |v2|, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_or_b32_e32 v2, v1, v0
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
index 32af52aeb7e8d..7b367319be9db 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
@@ -158,9 +158,9 @@ define amdgpu_kernel void @fneg_fabs_f64(ptr addrspace(1) %out, [8 x i32], doubl
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset1_b32 s1, 31
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -194,11 +194,11 @@ define amdgpu_kernel void @fneg_fabs_v2f64(ptr addrspace(1) %out, <2 x double> %
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset1_b32 s3, 31
; VI-NEXT: s_bitset1_b32 s1, 31
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v3, s3
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -246,9 +246,9 @@ define amdgpu_kernel void @fneg_fabs_v4f64(ptr addrspace(1) %out, <4 x double> %
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_addc_u32 s3, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v0, s12
; VI-NEXT: v_mov_b32_e32 v2, s14
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_mov_b32_e32 v5, s1
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
index 99120c996d875..bb575d42238ed 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
@@ -185,9 +185,9 @@ define amdgpu_kernel void @fneg_fabsf_v2f32(ptr addrspace(1) %out, <2 x float> %
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bitset1_b32 s3, 31
; VI-NEXT: s_bitset1_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -225,11 +225,11 @@ define amdgpu_kernel void @fneg_fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %
; VI-NEXT: s_bitset1_b32 s2, 31
; VI-NEXT: s_bitset1_b32 s1, 31
; VI-NEXT: s_bitset1_b32 s0, 31
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
index 68e66ba0ed1fb..3553ee04729f0 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
@@ -1616,10 +1616,10 @@ define amdgpu_kernel void @multiple_uses_fneg_select_f64(double %x, double %y, i
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: s_cselect_b32 s0, s0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, -v0, vcc
; GFX7-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX7-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
index 63aadaacbeb3a..15e68055f6af2 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
@@ -416,8 +416,8 @@ define amdgpu_kernel void @s_fneg_v2bf16(ptr addrspace(1) %out, <2 x bfloat> %in
define amdgpu_kernel void @s_fneg_v2bf16_nonload(ptr addrspace(1) %out) #0 {
; CI-LABEL: s_fneg_v2bf16_nonload:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CI-NEXT: s_add_i32 s12, s12, s17
+; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CI-NEXT: ;;#ASMSTART
; CI-NEXT: ; def s2
; CI-NEXT: ;;#ASMEND
@@ -426,10 +426,10 @@ define amdgpu_kernel void @s_fneg_v2bf16_nonload(ptr addrspace(1) %out) #0 {
; CI-NEXT: s_and_b32 s2, s2, 0xffff
; CI-NEXT: s_or_b32 s2, s2, s3
; CI-NEXT: s_add_i32 s2, s2, 0x80000000
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: flat_store_dword v[0:1], v2
@@ -444,9 +444,9 @@ define amdgpu_kernel void @s_fneg_v2bf16_nonload(ptr addrspace(1) %out) #0 {
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_xor_b32 s2, s2, 0x80008000
; GFX8-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
index 3140b87c8108e..7639b2bce1d39 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
@@ -376,9 +376,9 @@ define amdgpu_kernel void @s_fneg_v2f16_nonload(ptr addrspace(1) %out) #0 {
; CIVI-NEXT: ;;#ASMEND
; CIVI-NEXT: s_xor_b32 s2, s2, 0x80008000
; CIVI-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CIVI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
; CIVI-NEXT: v_mov_b32_e32 v0, s0
-; CIVI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CIVI-NEXT: v_mov_b32_e32 v1, s1
; CIVI-NEXT: v_mov_b32_e32 v2, s2
; CIVI-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.ll b/llvm/test/CodeGen/AMDGPU/fneg.ll
index 4fe0882a19f18..d74626066446d 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.ll
@@ -69,9 +69,9 @@ define amdgpu_kernel void @s_fneg_v2f32(ptr addrspace(1) nocapture %out, <2 x fl
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_xor_b32 s3, s3, 0x80000000
; VI-NEXT: s_xor_b32 s2, s2, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -120,11 +120,11 @@ define amdgpu_kernel void @s_fneg_v4f32(ptr addrspace(1) nocapture %out, <4 x fl
; VI-NEXT: s_xor_b32 s2, s2, 0x80000000
; VI-NEXT: s_xor_b32 s1, s1, 0x80000000
; VI-NEXT: s_xor_b32 s0, s0, 0x80000000
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll b/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
index 278a77affd22a..ebcf9b7e2a1d6 100644
--- a/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
@@ -23,9 +23,9 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat(ptr %ptr) {
; GFX12-LABEL: flat_atomic_fadd_f32_noret_pat:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT: v_mov_b32_e32 v2, 4.0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_dual_mov_b32 v2, 4.0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_add_f32 v[0:1], v2 scope:SCOPE_SYS
@@ -67,9 +67,9 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat_ieee(ptr %ptr) #0 {
; GFX12-LABEL: flat_atomic_fadd_f32_noret_pat_ieee:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT: v_mov_b32_e32 v2, 4.0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_dual_mov_b32 v2, 4.0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: flat_atomic_add_f32 v[0:1], v2 scope:SCOPE_SYS
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
index 1d6b1d58945e7..3c4e3eaafc408 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
@@ -434,9 +434,11 @@ define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(ptr addrspace(1) %out, <2 x
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s7 :: v_dual_mov_b32 v0, s4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX11-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
@@ -662,27 +664,27 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(ptr addrspace(1) %out, <4 x
; GFX11-GISEL-NEXT: v_dual_fmac_f32 v0, 0xcf800000, v4 :: v_dual_fmac_f32 v1, 0xcf800000, v5
; GFX11-GISEL-NEXT: v_dual_fmac_f32 v2, 0xcf800000, v6 :: v_dual_fmac_f32 v3, 0xcf800000, v7
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v1
-; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v6
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s7, v7
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v3
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s1
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5
; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, s6
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: global_store_b128 v8, v[0:3], s[8:9]
; GFX11-GISEL-NEXT: global_store_b128 v8, v[4:7], s[8:9] offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
index f2a0193a655f0..e21bb3a3e8e03 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
@@ -436,11 +436,11 @@ define i128 @fptosi_f32_to_i128(float %x) {
; GISEL: ; %bb.0: ; %fp-to-i-entry
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v4, v0
+; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_bfe_u32 v6, v4, 23, 8
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7f
-; GISEL-NEXT: s_mov_b64 s[4:5], 0
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
; GISEL-NEXT: v_mov_b32_e32 v0, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s5
; GISEL-NEXT: v_mov_b32_e32 v2, s6
@@ -627,11 +627,11 @@ define i128 @fptoui_f32_to_i128(float %x) {
; GISEL: ; %bb.0: ; %fp-to-i-entry
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v4, v0
+; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_bfe_u32 v6, v4, 23, 8
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7f
-; GISEL-NEXT: s_mov_b64 s[4:5], 0
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0
; GISEL-NEXT: v_mov_b32_e32 v0, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s5
; GISEL-NEXT: v_mov_b32_e32 v2, s6
@@ -797,11 +797,11 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
; GISEL: ; %bb.0: ; %fp-to-i-entry
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v4, v0
+; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_lshrrev_b16_e32 v6, 7, v4
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7f
-; GISEL-NEXT: s_mov_b64 s[4:5], 0
-; GISEL-NEXT: v_cmp_ge_u16_sdwa s[8:9], v6, v0 src0_sel:BYTE_0 src1_sel:DWORD
; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GISEL-NEXT: v_cmp_ge_u16_sdwa s[8:9], v6, v0 src0_sel:BYTE_0 src1_sel:DWORD
; GISEL-NEXT: v_mov_b32_e32 v0, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s5
; GISEL-NEXT: v_mov_b32_e32 v2, s6
@@ -986,11 +986,11 @@ define i128 @fptoui_bf16_to_i128(bfloat %x) {
; GISEL: ; %bb.0: ; %fp-to-i-entry
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v4, v0
+; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_lshrrev_b16_e32 v5, 7, v4
; GISEL-NEXT: v_mov_b32_e32 v0, 0x7f
-; GISEL-NEXT: s_mov_b64 s[4:5], 0
-; GISEL-NEXT: v_cmp_ge_u16_sdwa s[8:9], v5, v0 src0_sel:BYTE_0 src1_sel:DWORD
; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GISEL-NEXT: v_cmp_ge_u16_sdwa s[8:9], v5, v0 src0_sel:BYTE_0 src1_sel:DWORD
; GISEL-NEXT: v_mov_b32_e32 v0, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s5
; GISEL-NEXT: v_mov_b32_e32 v2, s6
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index afd9ec131865c..d4db120b5520c 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2202,9 +2202,9 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX7-ISEL-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
; GFX7-ISEL-NEXT: v_trunc_f64_e32 v[2:3], s[18:19]
; GFX7-ISEL-NEXT: s_movk_i32 s4, 0xffe0
-; GFX7-ISEL-NEXT: s_mov_b32 s5, 0x43dfffff
; GFX7-ISEL-NEXT: v_mov_b32_e32 v8, 0
; GFX7-ISEL-NEXT: v_mov_b32_e32 v9, 0xc3e00000
+; GFX7-ISEL-NEXT: s_mov_b32 s5, 0x43dfffff
; GFX7-ISEL-NEXT: s_mov_b32 s6, 0
; GFX7-ISEL-NEXT: s_mov_b32 s7, 0xc1f00000
; GFX7-ISEL-NEXT: v_ldexp_f64 v[4:5], v[0:1], s4
@@ -2303,9 +2303,9 @@ define <2 x i64> @test_s_signed_v2f64_v2i64(<2 x double> inreg %f) {
; GFX9-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
; GFX9-NEXT: v_trunc_f64_e32 v[2:3], s[18:19]
; GFX9-NEXT: s_movk_i32 s4, 0xffe0
-; GFX9-NEXT: s_mov_b32 s5, 0x43dfffff
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc3e00000
+; GFX9-NEXT: s_mov_b32 s5, 0x43dfffff
; GFX9-NEXT: s_mov_b32 s6, 0
; GFX9-NEXT: s_mov_b32 s7, 0xc1f00000
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[0:1], s4
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 9b6156ee44b94..24272040124a7 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -237,8 +237,8 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s4, 8
+; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_addc_u32 s3, s5, 0
; VI-NEXT: flat_load_ushort v0, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, s2
@@ -2476,8 +2476,8 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s4, 16
+; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_addc_u32 s3, s5, 0
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, s2
@@ -4210,8 +4210,8 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX10-NEXT: s_cbranch_scc1 .LBB6_6
; GFX10-NEXT: ; %bb.7: ; %Flow
-; GFX10-NEXT: v_mov_b32_e32 v6, v10
; GFX10-NEXT: v_mov_b32_e32 v13, s2
+; GFX10-NEXT: v_mov_b32_e32 v6, v10
; GFX10-NEXT: v_mov_b32_e32 v7, v11
; GFX10-NEXT: .LBB6_8: ; %frem.loop_exit
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
@@ -5550,8 +5550,8 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_add_u32 s2, s4, 16
+; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: s_addc_u32 s3, s5, 0
; VI-NEXT: flat_load_dword v0, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, s2
@@ -16924,8 +16924,8 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_readfirstlane_b32 s7, v1
; SI-NEXT: v_readfirstlane_b32 s6, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_readfirstlane_b32 s11, v3
+; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_mov_b32_e32 v1, s11
; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |s[6:7]|, |v[0:1]|
@@ -17825,8 +17825,8 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
; GFX10-NEXT: s_cbranch_scc1 .LBB13_6
; GFX10-NEXT: ; %bb.7: ; %Flow51
-; GFX10-NEXT: v_mov_b32_e32 v10, v14
; GFX10-NEXT: v_mov_b32_e32 v17, s2
+; GFX10-NEXT: v_mov_b32_e32 v10, v14
; GFX10-NEXT: v_mov_b32_e32 v11, v15
; GFX10-NEXT: .LBB13_8: ; %frem.loop_exit24
; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
@@ -17903,8 +17903,8 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; GFX10-NEXT: s_cbranch_scc1 .LBB13_15
; GFX10-NEXT: ; %bb.16: ; %Flow
-; GFX10-NEXT: v_mov_b32_e32 v12, v16
; GFX10-NEXT: v_mov_b32_e32 v19, s2
+; GFX10-NEXT: v_mov_b32_e32 v12, v16
; GFX10-NEXT: v_mov_b32_e32 v13, v17
; GFX10-NEXT: .LBB13_17: ; %frem.loop_exit
; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
@@ -19427,8 +19427,8 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT: s_cbranch_scc1 .LBB15_6
; GFX10-NEXT: ; %bb.7: ; %Flow50
-; GFX10-NEXT: v_mov_b32_e32 v4, v6
; GFX10-NEXT: v_mov_b32_e32 v8, s2
+; GFX10-NEXT: v_mov_b32_e32 v4, v6
; GFX10-NEXT: v_mov_b32_e32 v5, v7
; GFX10-NEXT: .LBB15_8: ; %frem.loop_exit24
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
@@ -19484,8 +19484,8 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX10-NEXT: s_cbranch_scc1 .LBB15_15
; GFX10-NEXT: ; %bb.16: ; %Flow
-; GFX10-NEXT: v_mov_b32_e32 v6, v8
; GFX10-NEXT: v_mov_b32_e32 v10, s2
+; GFX10-NEXT: v_mov_b32_e32 v6, v8
; GFX10-NEXT: v_mov_b32_e32 v7, v9
; GFX10-NEXT: .LBB15_17: ; %frem.loop_exit
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
@@ -19564,10 +19564,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX11-NEXT: s_cbranch_scc1 .LBB15_6
; GFX11-NEXT: ; %bb.7: ; %Flow50
-; GFX11-NEXT: v_mov_b32_e32 v4, v6
; GFX11-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
+; GFX11-NEXT: v_mov_b32_e32 v4, v6
; GFX11-NEXT: .LBB15_8: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -19629,10 +19629,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX11-NEXT: s_cbranch_scc1 .LBB15_15
; GFX11-NEXT: ; %bb.16: ; %Flow
-; GFX11-NEXT: v_mov_b32_e32 v6, v8
; GFX11-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
+; GFX11-NEXT: v_mov_b32_e32 v6, v8
; GFX11-NEXT: .LBB15_17: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -19710,10 +19710,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1150-NEXT: s_cbranch_scc1 .LBB15_6
; GFX1150-NEXT: ; %bb.7: ; %Flow50
-; GFX1150-NEXT: v_mov_b32_e32 v4, v6
; GFX1150-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
+; GFX1150-NEXT: v_mov_b32_e32 v4, v6
; GFX1150-NEXT: .LBB15_8: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -19775,10 +19775,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1150-NEXT: s_cbranch_scc1 .LBB15_15
; GFX1150-NEXT: ; %bb.16: ; %Flow
-; GFX1150-NEXT: v_mov_b32_e32 v6, v8
; GFX1150-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
+; GFX1150-NEXT: v_mov_b32_e32 v6, v8
; GFX1150-NEXT: .LBB15_17: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -19857,10 +19857,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1200-NEXT: s_cbranch_scc1 .LBB15_6
; GFX1200-NEXT: ; %bb.7: ; %Flow50
-; GFX1200-NEXT: v_mov_b32_e32 v4, v6
; GFX1200-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
+; GFX1200-NEXT: v_mov_b32_e32 v4, v6
; GFX1200-NEXT: .LBB15_8: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -19928,10 +19928,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX1200-NEXT: s_cbranch_scc1 .LBB15_15
; GFX1200-NEXT: ; %bb.16: ; %Flow
-; GFX1200-NEXT: v_mov_b32_e32 v6, v8
; GFX1200-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
+; GFX1200-NEXT: v_mov_b32_e32 v6, v8
; GFX1200-NEXT: .LBB15_17: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/fshl.ll b/llvm/test/CodeGen/AMDGPU/fshl.ll
index 1233c1fe12f72..5d45167d7ab57 100644
--- a/llvm/test/CodeGen/AMDGPU/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshl.ll
@@ -256,9 +256,9 @@ define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_and_b32 s2, s2, 31
; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
-; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s8
+; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -397,9 +397,9 @@ define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; VI-NEXT: s_mov_b32 s3, s0
; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 23
; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 25
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -555,11 +555,11 @@ define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_and_b32 s0, s0, 31
; VI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
-; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s4
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -768,11 +768,11 @@ define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; VI-NEXT: s_lshr_b64 s[4:5], s[14:15], 23
; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 25
; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s2
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index be49838f86417..1b6a241805b30 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -356,9 +356,9 @@ define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; VI-NEXT: s_and_b32 s0, s6, 31
; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], s1
; VI-NEXT: s_lshr_b64 s[0:1], s[2:3], s0
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s8
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -489,9 +489,9 @@ define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2
; VI-NEXT: s_mov_b32 s3, s0
; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 9
; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 7
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -616,9 +616,9 @@ define amdgpu_kernel void @fshr_v2i32_imm_src1(ptr addrspace(1) %in, <2 x i32> %
; VI-NEXT: s_and_b32 s0, s2, 31
; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s1
; VI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -771,11 +771,11 @@ define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; VI-NEXT: s_lshr_b64 s[2:3], s[14:15], s2
; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], s1
; VI-NEXT: s_lshr_b64 s[0:1], s[12:13], s0
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s6
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -956,11 +956,11 @@ define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4
; VI-NEXT: s_lshr_b64 s[4:5], s[14:15], 9
; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 7
; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s2
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -1127,11 +1127,11 @@ define amdgpu_kernel void @fshr_v4i32_imm_src0(ptr addrspace(1) %in, <4 x i32> %
; VI-NEXT: s_mov_b32 s9, 1
; VI-NEXT: s_and_b32 s1, s12, 31
; VI-NEXT: s_lshr_b64 s[8:9], s[8:9], s1
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s0
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
index 04f7c3583bd73..816f555cdb4e3 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
@@ -2016,10 +2016,10 @@ define amdgpu_gfx <512 x i32> @return_512xi32() #0 {
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0
-; GFX11-NEXT: s_mov_b32 s3, s0
; GFX11-NEXT: s_mov_b32 s1, s0
; GFX11-NEXT: s_mov_b32 s2, s0
-; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:2032
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index dbf99aa1c8577..0d73abf5bf46d 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -7626,9 +7626,9 @@ define double @global_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[8:9], v[10:11], v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v0, v8
; GFX7-NEXT: v_mov_b32_e32 v1, v9
-; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v3, v11
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -7661,9 +7661,9 @@ define double @global_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[8:9], v[10:11], v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v0, v8
; GFX6-NEXT: v_mov_b32_e32 v1, v9
-; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v3, v11
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -7861,9 +7861,9 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[8:9], v[10:11], v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v0, v8
; GFX7-NEXT: v_mov_b32_e32 v1, v9
-; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v3, v11
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 offset:2040 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -7896,9 +7896,9 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[8:9], v[10:11], v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v0, v8
; GFX6-NEXT: v_mov_b32_e32 v1, v9
-; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v3, v11
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 offset:2040 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -8099,9 +8099,9 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v0, v6
; GFX7-NEXT: v_mov_b32_e32 v1, v7
-; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v3, v9
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[10:11], s[4:7], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -8136,9 +8136,9 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[6:7], v[8:9], v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v0, v6
; GFX6-NEXT: v_mov_b32_e32 v1, v7
-; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v3, v9
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[10:11], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index 93443914d3f97..bf3688338bf8c 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -4215,9 +4215,9 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
; GFX7-NEXT: v_max_f64 v[6:7], v[0:1], v[10:11]
+; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v0, v6
; GFX7-NEXT: v_mov_b32_e32 v1, v7
-; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v3, v9
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[4:7], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -4249,9 +4249,9 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
; GFX6-NEXT: v_max_f64 v[6:7], v[0:1], v[10:11]
+; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v0, v6
; GFX6-NEXT: v_mov_b32_e32 v1, v7
-; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v3, v9
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index b8217cf862b3a..ec43bca792888 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -4215,9 +4215,9 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
; GFX7-NEXT: v_min_f64 v[6:7], v[0:1], v[10:11]
+; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v0, v6
; GFX7-NEXT: v_mov_b32_e32 v1, v7
-; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v3, v9
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[4:7], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -4249,9 +4249,9 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: v_max_f64 v[0:1], v[8:9], v[8:9]
; GFX6-NEXT: v_min_f64 v[6:7], v[0:1], v[10:11]
+; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v0, v6
; GFX6-NEXT: v_mov_b32_e32 v1, v7
-; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v3, v9
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
index 4ab68e8822676..f42947b97e4d5 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
@@ -3925,9 +3925,9 @@ define double @global_agent_atomic_fsub_ret_f64(ptr addrspace(1) %ptr, double %v
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[8:9], v[10:11], -v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v0, v8
; GFX7-NEXT: v_mov_b32_e32 v1, v9
-; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v3, v11
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -3960,9 +3960,9 @@ define double @global_agent_atomic_fsub_ret_f64(ptr addrspace(1) %ptr, double %v
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[8:9], v[10:11], -v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v0, v8
; GFX6-NEXT: v_mov_b32_e32 v1, v9
-; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v3, v11
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -4177,9 +4177,9 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_pos(ptr addrspace(1)
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[8:9], v[10:11], -v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v0, v8
; GFX7-NEXT: v_mov_b32_e32 v1, v9
-; GFX7-NEXT: v_mov_b32_e32 v2, v10
; GFX7-NEXT: v_mov_b32_e32 v3, v11
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 offset:2040 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -4212,9 +4212,9 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_pos(ptr addrspace(1)
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[8:9], v[10:11], -v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v0, v8
; GFX6-NEXT: v_mov_b32_e32 v1, v9
-; GFX6-NEXT: v_mov_b32_e32 v2, v10
; GFX6-NEXT: v_mov_b32_e32 v3, v11
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[6:7], s[4:7], 0 addr64 offset:2040 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -4432,9 +4432,9 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_neg(ptr addrspace(1)
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_f64 v[6:7], v[8:9], -v[4:5]
+; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v0, v6
; GFX7-NEXT: v_mov_b32_e32 v1, v7
-; GFX7-NEXT: v_mov_b32_e32 v2, v8
; GFX7-NEXT: v_mov_b32_e32 v3, v9
; GFX7-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[10:11], s[4:7], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -4469,9 +4469,9 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_neg(ptr addrspace(1)
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_add_f64 v[6:7], v[8:9], -v[4:5]
; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v0, v6
; GFX6-NEXT: v_mov_b32_e32 v1, v7
-; GFX6-NEXT: v_mov_b32_e32 v2, v8
; GFX6-NEXT: v_mov_b32_e32 v3, v9
; GFX6-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[10:11], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics.ll b/llvm/test/CodeGen/AMDGPU/global_atomics.ll
index cdbed4a26be1e..6615fb0467718 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics.ll
@@ -328,8 +328,8 @@ define amdgpu_kernel void @atomic_add_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -405,11 +405,11 @@ define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -620,8 +620,8 @@ define amdgpu_kernel void @atomic_add_i32_addr64(ptr addrspace(1) %out, i32 %in,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -694,11 +694,11 @@ define amdgpu_kernel void @atomic_add_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -908,8 +908,8 @@ define amdgpu_kernel void @atomic_and_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_and v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -985,11 +985,11 @@ define amdgpu_kernel void @atomic_and_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_and v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -1200,8 +1200,8 @@ define amdgpu_kernel void @atomic_and_i32_addr64(ptr addrspace(1) %out, i32 %in,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_and v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -1274,11 +1274,11 @@ define amdgpu_kernel void @atomic_and_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_and v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -1488,8 +1488,8 @@ define amdgpu_kernel void @atomic_sub_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_sub v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -1565,11 +1565,11 @@ define amdgpu_kernel void @atomic_sub_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_sub v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -1780,8 +1780,8 @@ define amdgpu_kernel void @atomic_sub_i32_addr64(ptr addrspace(1) %out, i32 %in,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_sub v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -1854,11 +1854,11 @@ define amdgpu_kernel void @atomic_sub_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_sub v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -2064,8 +2064,8 @@ define amdgpu_kernel void @atomic_max_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_smax v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_endpgm
@@ -2134,11 +2134,11 @@ define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_smax v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -2334,8 +2334,8 @@ define amdgpu_kernel void @atomic_max_i32_addr64(ptr addrspace(1) %out, i32 %in,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_smax v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm
@@ -2401,11 +2401,11 @@ define amdgpu_kernel void @atomic_max_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_smax v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -2600,8 +2600,8 @@ define amdgpu_kernel void @atomic_umax_i32_addr64_offset(ptr addrspace(1) %out,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_umax v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_endpgm
@@ -2670,11 +2670,11 @@ define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(ptr addrspace(1) %o
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_umax v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -2870,8 +2870,8 @@ define amdgpu_kernel void @atomic_umax_i32_addr64(ptr addrspace(1) %out, i32 %in
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_umax v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm
@@ -2937,11 +2937,11 @@ define amdgpu_kernel void @atomic_umax_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_umax v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -3136,8 +3136,8 @@ define amdgpu_kernel void @atomic_min_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_smin v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_endpgm
@@ -3206,11 +3206,11 @@ define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_smin v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -3406,8 +3406,8 @@ define amdgpu_kernel void @atomic_min_i32_addr64(ptr addrspace(1) %out, i32 %in,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_smin v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm
@@ -3473,11 +3473,11 @@ define amdgpu_kernel void @atomic_min_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_smin v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -3672,8 +3672,8 @@ define amdgpu_kernel void @atomic_umin_i32_addr64_offset(ptr addrspace(1) %out,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_umin v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_endpgm
@@ -3742,11 +3742,11 @@ define amdgpu_kernel void @atomic_umin_i32_ret_addr64_offset(ptr addrspace(1) %o
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_umin v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -3942,8 +3942,8 @@ define amdgpu_kernel void @atomic_umin_i32_addr64(ptr addrspace(1) %out, i32 %in
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_umin v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm
@@ -4009,11 +4009,11 @@ define amdgpu_kernel void @atomic_umin_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_umin v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_mov_b32 s6, -1
@@ -4219,8 +4219,8 @@ define amdgpu_kernel void @atomic_or_i32_addr64_offset(ptr addrspace(1) %out, i3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_or v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -4296,11 +4296,11 @@ define amdgpu_kernel void @atomic_or_i32_ret_addr64_offset(ptr addrspace(1) %out
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_or v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -4511,8 +4511,8 @@ define amdgpu_kernel void @atomic_or_i32_addr64(ptr addrspace(1) %out, i32 %in,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_or v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -4585,11 +4585,11 @@ define amdgpu_kernel void @atomic_or_i32_ret_addr64(ptr addrspace(1) %out, ptr a
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_or v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -4856,8 +4856,8 @@ define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(ptr addrspace(1) %out,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_swap v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -4933,11 +4933,11 @@ define amdgpu_kernel void @atomic_xchg_i32_ret_addr64_offset(ptr addrspace(1) %o
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_swap v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5148,8 +5148,8 @@ define amdgpu_kernel void @atomic_xchg_i32_addr64(ptr addrspace(1) %out, i32 %in
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_swap v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5222,11 +5222,11 @@ define amdgpu_kernel void @atomic_xchg_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_swap v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5306,9 +5306,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_offset(ptr addrspace(1) %out, i32
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5321,9 +5321,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_offset(ptr addrspace(1) %out, i32
; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5345,9 +5345,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_offset(ptr addrspace(1) %out, i32
; GFX11-LABEL: atomic_cmpxchg_i32_offset:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], s[0:1] offset:16
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: buffer_gl1_inv
@@ -5368,10 +5368,10 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(ptr addrspace(1) %out,
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5387,10 +5387,10 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(ptr addrspace(1) %out,
; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, s2
-; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: s_mov_b32 s5, s3
; VI-NEXT: s_mov_b32 s2, s6
; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s9
; VI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5417,9 +5417,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(ptr addrspace(1) %out,
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s7
+; GFX11-NEXT: v_mov_b32_e32 v0, s6
; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] offset:16 glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -5444,10 +5444,10 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
+; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: buffer_atomic_cmpswap v[0:1], v[2:3], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5467,8 +5467,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_addc_u32 s1, s3, s1
; VI-NEXT: s_add_u32 s0, s0, 16
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_cmpswap v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5528,13 +5528,13 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(ptr addrspace(1)
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: v_mov_b32_e32 v1, s10
+; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: v_mov_b32_e32 v3, s9
; SI-NEXT: buffer_atomic_cmpswap v[0:1], v[2:3], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5556,8 +5556,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(ptr addrspace(1)
; VI-NEXT: s_addc_u32 s1, s1, s5
; VI-NEXT: s_add_u32 s0, s0, 16
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5623,9 +5623,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32(ptr addrspace(1) %out, i32 %in, i3
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5638,9 +5638,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32(ptr addrspace(1) %out, i32 %in, i3
; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5662,9 +5662,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32(ptr addrspace(1) %out, i32 %in, i3
; GFX11-LABEL: atomic_cmpxchg_i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: buffer_gl1_inv
@@ -5684,8 +5684,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret(ptr addrspace(1) %out, ptr add
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5703,8 +5703,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret(ptr addrspace(1) %out, ptr add
; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, s0
-; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s9
; VI-NEXT: buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5733,9 +5733,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret(ptr addrspace(1) %out, ptr add
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s7
+; GFX11-NEXT: v_mov_b32_e32 v0, s6
; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -5760,9 +5760,9 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(ptr addrspace(1) %out, i32
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
+; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: buffer_atomic_cmpswap v[0:1], v[2:3], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5780,8 +5780,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(ptr addrspace(1) %out, i32
; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_add_u32 s0, s2, s0
; VI-NEXT: s_addc_u32 s1, s3, s1
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_cmpswap v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5833,20 +5833,20 @@ entry:
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(ptr addrspace(1) %out, ptr addrspace(1) %out2, i32 %in, i64 %index, i32 %old) {
; SI-LABEL: atomic_cmpxchg_i32_ret_addr64:
; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dword s6, s[4:5], 0xd
; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xf
; SI-NEXT: s_load_dword s10, s[4:5], 0x11
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v1, s10
+; SI-NEXT: v_mov_b32_e32 v2, s8
; SI-NEXT: v_mov_b32_e32 v3, s9
; SI-NEXT: buffer_atomic_cmpswap v[0:1], v[2:3], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -5866,8 +5866,8 @@ define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(ptr addrspace(1) %out,
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: s_add_u32 s0, s0, s4
; VI-NEXT: s_addc_u32 s1, s1, s5
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -6062,8 +6062,8 @@ define amdgpu_kernel void @atomic_xor_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_xor v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -6139,11 +6139,11 @@ define amdgpu_kernel void @atomic_xor_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_xor v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -6354,8 +6354,8 @@ define amdgpu_kernel void @atomic_xor_i32_addr64(ptr addrspace(1) %out, i32 %in,
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_xor v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -6428,11 +6428,11 @@ define amdgpu_kernel void @atomic_xor_i32_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_xor v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -6770,10 +6770,10 @@ define amdgpu_kernel void @atomic_load_i32_addr64_offset(ptr addrspace(1) %in, p
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -6853,10 +6853,10 @@ define amdgpu_kernel void @atomic_load_i32_addr64(ptr addrspace(1) %in, ptr addr
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -6933,10 +6933,10 @@ define amdgpu_kernel void @atomic_load_f32_addr64_offset(ptr addrspace(1) %in, p
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -7157,10 +7157,10 @@ define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, ptr addrspace
; SI-NEXT: s_load_dword s6, s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_endpgm
@@ -7221,10 +7221,10 @@ define amdgpu_kernel void @atomic_store_f32_addr64_offset(float %in, ptr addrspa
; SI-NEXT: s_load_dword s6, s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_endpgm
@@ -7288,8 +7288,8 @@ define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
; SI-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
-; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_endpgm
@@ -7350,8 +7350,8 @@ define amdgpu_kernel void @atomic_store_f32_addr64(float %in, ptr addrspace(1) %
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
; SI-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
-; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT: s_endpgm
@@ -8502,8 +8502,8 @@ define amdgpu_kernel void @atomic_inc_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_inc v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -8579,11 +8579,11 @@ define amdgpu_kernel void @atomic_inc_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_inc v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -8981,8 +8981,8 @@ define amdgpu_kernel void @atomic_dec_i32_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 2
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_atomic_dec v2, v[0:1], s[0:3], 0 addr64 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -9058,11 +9058,11 @@ define amdgpu_kernel void @atomic_dec_i32_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s2
; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_mov_b32 s5, s3
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: s_mov_b32 s3, s7
; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: buffer_atomic_dec v2, v[0:1], s[0:3], 0 addr64 offset:16 glc
; SI-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
index 6c3bb717ec7a5..72b27579b500c 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
@@ -1812,8 +1812,8 @@ define amdgpu_gfx i32 @global_atomic_sub_i32_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB36_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2597,8 +2597,8 @@ define amdgpu_gfx i32 @global_atomic_and_i32_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB47_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3364,8 +3364,8 @@ define amdgpu_gfx i32 @global_atomic_nand_i32_ret_scalar(ptr addrspace(1) inreg
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB57_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4208,8 +4208,8 @@ define amdgpu_gfx i32 @global_atomic_or_i32_ret_scalar(ptr addrspace(1) inreg %p
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB67_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4993,8 +4993,8 @@ define amdgpu_gfx i32 @global_atomic_xor_i32_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB78_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5778,8 +5778,8 @@ define amdgpu_gfx i32 @global_atomic_max_i32_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB89_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5958,8 +5958,8 @@ define amdgpu_kernel void @atomic_max_i32_addr64_offset(ptr addrspace(1) %out, i
; VI-NEXT: s_load_dword s3, s[4:5], 0x10
; VI-NEXT: s_add_u32 s4, s4, 16
; VI-NEXT: s_addc_u32 s5, s5, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: v_mov_b32_e32 v1, s5
@@ -6064,8 +6064,8 @@ define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_load_dword s7, s[4:5], 0x10
; VI-NEXT: s_add_u32 s4, s4, 16
; VI-NEXT: s_addc_u32 s5, s5, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s7
; VI-NEXT: v_mov_b32_e32 v1, s5
@@ -6169,8 +6169,8 @@ define amdgpu_kernel void @atomic_max_i32_addr64(ptr addrspace(1) %out, i32 %in,
; VI-NEXT: s_add_u32 s4, s0, s4
; VI-NEXT: s_addc_u32 s5, s1, s5
; VI-NEXT: s_load_dword s3, s[4:5], 0x0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s3
@@ -6272,8 +6272,8 @@ define amdgpu_kernel void @atomic_max_i32_ret_addr64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_add_u32 s4, s0, s4
; VI-NEXT: s_addc_u32 s5, s1, s5
; VI-NEXT: s_load_dword s7, s[4:5], 0x0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s7
@@ -6946,8 +6946,8 @@ define amdgpu_gfx i32 @global_atomic_umax_i32_ret_scalar(ptr addrspace(1) inreg
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB103_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7126,8 +7126,8 @@ define amdgpu_kernel void @atomic_umax_i32_addr64_offset(ptr addrspace(1) %out,
; VI-NEXT: s_load_dword s3, s[4:5], 0x10
; VI-NEXT: s_add_u32 s4, s4, 16
; VI-NEXT: s_addc_u32 s5, s5, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: v_mov_b32_e32 v1, s5
@@ -7232,8 +7232,8 @@ define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(ptr addrspace(1) %o
; VI-NEXT: s_load_dword s7, s[4:5], 0x10
; VI-NEXT: s_add_u32 s4, s4, 16
; VI-NEXT: s_addc_u32 s5, s5, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s7
; VI-NEXT: v_mov_b32_e32 v1, s5
@@ -7345,8 +7345,8 @@ define amdgpu_kernel void @atomic_umax_i32_ret_addr64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_add_u32 s4, s0, s4
; VI-NEXT: s_addc_u32 s5, s1, s5
; VI-NEXT: s_load_dword s7, s[4:5], 0x0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s7
@@ -8019,8 +8019,8 @@ define amdgpu_gfx i32 @global_atomic_umin_i32_ret_scalar(ptr addrspace(1) inreg
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB116_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8767,8 +8767,8 @@ define amdgpu_gfx i32 @global_atomic_min_i32_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB126_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8947,8 +8947,8 @@ define amdgpu_kernel void @atomic_min_i32_addr64_offset(ptr addrspace(1) %out, i
; VI-NEXT: s_load_dword s3, s[4:5], 0x10
; VI-NEXT: s_add_u32 s4, s4, 16
; VI-NEXT: s_addc_u32 s5, s5, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: v_mov_b32_e32 v1, s5
@@ -9053,8 +9053,8 @@ define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_load_dword s7, s[4:5], 0x10
; VI-NEXT: s_add_u32 s4, s4, 16
; VI-NEXT: s_addc_u32 s5, s5, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s7
; VI-NEXT: v_mov_b32_e32 v1, s5
@@ -9248,8 +9248,8 @@ define amdgpu_kernel void @atomic_min_i32_ret_addr64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_add_u32 s4, s0, s4
; VI-NEXT: s_addc_u32 s5, s1, s5
; VI-NEXT: s_load_dword s7, s[4:5], 0x0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s7
@@ -9960,8 +9960,8 @@ define amdgpu_gfx i32 @global_atomic_uinc_wrap_i32_ret_scalar(ptr addrspace(1) i
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB140_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10579,9 +10579,9 @@ define amdgpu_gfx void @global_atomic_udec_wrap_i32_noret_scalar(ptr addrspace(1
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v1, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[36:37], 0
; VI-NEXT: v_mov_b32_e32 v4, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB148_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10784,9 +10784,9 @@ define amdgpu_gfx i32 @global_atomic_udec_wrap_i32_ret_scalar(ptr addrspace(1) i
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dword v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: s_mov_b64 s[36:37], 0
; VI-NEXT: v_mov_b32_e32 v3, s6
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: .LBB150_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
index daa053ceea161..022b226aa7704 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
@@ -140,10 +140,10 @@ define amdgpu_kernel void @atomic_add_i64_addr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_add_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -217,11 +217,11 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_add_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -428,10 +428,10 @@ define amdgpu_kernel void @atomic_add_i64_addr64(ptr addrspace(1) %out, i64 %in,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_add_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -502,11 +502,11 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_add_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -708,10 +708,10 @@ define amdgpu_kernel void @atomic_and_i64_addr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_and_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -785,11 +785,11 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_and_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -996,10 +996,10 @@ define amdgpu_kernel void @atomic_and_i64_addr64(ptr addrspace(1) %out, i64 %in,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_and_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1070,11 +1070,11 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_and_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1276,10 +1276,10 @@ define amdgpu_kernel void @atomic_sub_i64_addr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_sub_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1353,11 +1353,11 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_sub_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1564,10 +1564,10 @@ define amdgpu_kernel void @atomic_sub_i64_addr64(ptr addrspace(1) %out, i64 %in,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_sub_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1638,11 +1638,11 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_sub_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -1835,10 +1835,10 @@ define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smax_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_endpgm
@@ -1906,11 +1906,11 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smax_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -2105,10 +2105,10 @@ define amdgpu_kernel void @atomic_max_i64_addr64(ptr addrspace(1) %out, i64 %in,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smax_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_endpgm
@@ -2173,11 +2173,11 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smax_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -2367,10 +2367,10 @@ define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr addrspace(1) %out,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umax_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_endpgm
@@ -2438,11 +2438,11 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr addrspace(1) %o
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umax_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -2637,10 +2637,10 @@ define amdgpu_kernel void @atomic_umax_i64_addr64(ptr addrspace(1) %out, i64 %in
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umax_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_endpgm
@@ -2705,11 +2705,11 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umax_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -2899,10 +2899,10 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smin_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_endpgm
@@ -2970,11 +2970,11 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smin_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3169,10 +3169,10 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr addrspace(1) %out, i64 %in,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smin_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_endpgm
@@ -3237,11 +3237,11 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_smin_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3431,10 +3431,10 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr addrspace(1) %out,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umin_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_endpgm
@@ -3502,11 +3502,11 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr addrspace(1) %o
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umin_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3701,10 +3701,10 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr addrspace(1) %out, i64 %in
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umin_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_endpgm
@@ -3769,11 +3769,11 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_umin_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -3972,10 +3972,10 @@ define amdgpu_kernel void @atomic_or_i64_addr64_offset(ptr addrspace(1) %out, i6
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_or_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -4049,11 +4049,11 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(ptr addrspace(1) %out
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_or_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -4260,10 +4260,10 @@ define amdgpu_kernel void @atomic_or_i64_addr64(ptr addrspace(1) %out, i64 %in,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_or_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -4334,11 +4334,11 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64(ptr addrspace(1) %out, ptr a
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_or_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -4650,10 +4650,10 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(ptr addrspace(1) %out,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_swap_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -4727,11 +4727,11 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(ptr addrspace(1) %o
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_swap_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -4938,10 +4938,10 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64(ptr addrspace(1) %out, i64 %in
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_swap_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5012,11 +5012,11 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_swap_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5218,10 +5218,10 @@ define amdgpu_kernel void @atomic_xor_i64_addr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_xor_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5295,11 +5295,11 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_xor_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5506,10 +5506,10 @@ define amdgpu_kernel void @atomic_xor_i64_addr64(ptr addrspace(1) %out, i64 %in,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_xor_x2 v[0:1], v[2:3], s[0:3], 0 addr64
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5580,11 +5580,11 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64(ptr addrspace(1) %out, ptr
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: v_mov_b32_e32 v1, s5
; CI-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: s_mov_b32 s8, s2
; CI-NEXT: s_mov_b32 s9, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s11
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_xor_x2 v[0:1], v[2:3], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5878,12 +5878,12 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr addrspace(1) %ou
; CI-NEXT: s_mov_b32 s10, 0
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v4, s4
; CI-NEXT: s_mov_b64 s[8:9], s[0:1]
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_mov_b32_e32 v2, s6
; CI-NEXT: v_mov_b32_e32 v3, s7
+; CI-NEXT: v_mov_b32_e32 v4, s4
; CI-NEXT: v_mov_b32_e32 v5, s5
; CI-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[8:11], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5899,11 +5899,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_addc_u32 s1, s1, s5
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5957,7 +5957,6 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr addrspace(1)
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshl_b64 s[6:7], s[14:15], 3
-; CI-NEXT: v_mov_b32_e32 v4, s6
; CI-NEXT: s_mov_b32 s0, s10
; CI-NEXT: s_mov_b32 s1, s11
; CI-NEXT: s_mov_b32 s10, 0
@@ -5966,6 +5965,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr addrspace(1)
; CI-NEXT: v_mov_b32_e32 v1, s13
; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
+; CI-NEXT: v_mov_b32_e32 v4, s6
; CI-NEXT: v_mov_b32_e32 v5, s7
; CI-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[8:11], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -5984,10 +5984,10 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr addrspace(1)
; VI-NEXT: s_addc_u32 s3, s9, s3
; VI-NEXT: s_add_u32 s2, s0, 32
; VI-NEXT: s_addc_u32 s3, s3, 0
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v0, s12
; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -6198,11 +6198,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr addrspace(1) %out, i64
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[8:9], s[0:1]
; CI-NEXT: s_lshl_b64 s[0:1], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_mov_b32_e32 v2, s6
; CI-NEXT: v_mov_b32_e32 v3, s7
+; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_mov_b32_e32 v4, s0
; CI-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[8:11], 0 addr64
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -6216,11 +6216,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr addrspace(1) %out, i64
; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
; VI-NEXT: s_add_u32 s0, s0, s4
; VI-NEXT: s_addc_u32 s1, s1, s5
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -6273,7 +6273,6 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr addrspace(1) %out,
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshl_b64 s[6:7], s[14:15], 3
-; CI-NEXT: v_mov_b32_e32 v4, s6
; CI-NEXT: s_mov_b32 s0, s10
; CI-NEXT: s_mov_b32 s1, s11
; CI-NEXT: s_mov_b32 s10, 0
@@ -6282,6 +6281,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr addrspace(1) %out,
; CI-NEXT: v_mov_b32_e32 v1, s13
; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
+; CI-NEXT: v_mov_b32_e32 v4, s6
; CI-NEXT: v_mov_b32_e32 v5, s7
; CI-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v[4:5], s[8:11], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -6297,11 +6297,11 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr addrspace(1) %out,
; VI-NEXT: s_lshl_b64 s[2:3], s[14:15], 3
; VI-NEXT: s_add_u32 s2, s8, s2
; VI-NEXT: s_addc_u32 s3, s9, s3
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v0, s12
; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -6555,10 +6555,10 @@ define amdgpu_kernel void @atomic_load_i64_addr64_offset(ptr addrspace(1) %in, p
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b32 s4, s2
; CI-NEXT: s_lshl_b64 s[8:9], s[8:9], 3
-; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: s_mov_b32 s5, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: v_mov_b32_e32 v1, s9
; CI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -6636,10 +6636,10 @@ define amdgpu_kernel void @atomic_load_i64_addr64(ptr addrspace(1) %in, ptr addr
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b32 s4, s2
; CI-NEXT: s_lshl_b64 s[8:9], s[8:9], 3
-; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: s_mov_b32 s5, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: v_mov_b32_e32 v1, s9
; CI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -6714,10 +6714,10 @@ define amdgpu_kernel void @atomic_load_f64_addr64_offset(ptr addrspace(1) %in, p
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b32 s4, s2
; CI-NEXT: s_lshl_b64 s[8:9], s[8:9], 3
-; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: s_mov_b32 s5, s3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_mov_b32_e32 v0, s8
; CI-NEXT: v_mov_b32_e32 v1, s9
; CI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64 offset:32 glc
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -6899,8 +6899,8 @@ define amdgpu_kernel void @atomic_store_i64_addr64_offset(i64 %in, ptr addrspace
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_lshl_b64 s[0:1], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: buffer_store_dwordx2 v[0:1], v[2:3], s[4:7], 0 addr64 offset:32
; CI-NEXT: s_endpgm
@@ -6969,8 +6969,8 @@ define amdgpu_kernel void @atomic_store_i64_addr64(i64 %in, ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_lshl_b64 s[0:1], s[8:9], 3
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: buffer_store_dwordx2 v[0:1], v[2:3], s[4:7], 0 addr64
; CI-NEXT: s_endpgm
@@ -7036,8 +7036,8 @@ define amdgpu_kernel void @atomic_store_f64_addr64_offset(double %in, ptr addrsp
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_lshl_b64 s[0:1], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: buffer_store_dwordx2 v[0:1], v[2:3], s[4:7], 0 addr64 offset:32
; CI-NEXT: s_endpgm
@@ -7231,10 +7231,10 @@ define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_inc_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
@@ -7434,10 +7434,10 @@ define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr addrspace(1) %out, i
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: s_lshl_b64 s[4:5], s[4:5], 3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: buffer_atomic_dec_x2 v[0:1], v[2:3], s[0:3], 0 addr64 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
index 29c2c10730126..fa5e47f323ef1 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
@@ -234,9 +234,9 @@ define amdgpu_gfx void @global_atomic_xchg_i64_noret_offset_scalar(ptr addrspace
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_add_u32 s34, s4, 32
; VI-NEXT: s_addc_u32 s35, s5, 0
-; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v3, s35
; VI-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -343,9 +343,9 @@ define amdgpu_gfx i64 @global_atomic_xchg_i64_ret_offset_scalar(ptr addrspace(1)
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_add_u32 s34, s4, 32
; VI-NEXT: s_addc_u32 s35, s5, 0
-; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v3, s35
; VI-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -672,9 +672,9 @@ define amdgpu_gfx void @global_atomic_xchg_f64_noret_offset_scalar(ptr addrspace
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_add_u32 s34, s4, 32
; VI-NEXT: s_addc_u32 s35, s5, 0
-; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v3, s35
; VI-NEXT: flat_atomic_swap_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -781,9 +781,9 @@ define amdgpu_gfx double @global_atomic_xchg_f64_ret_offset_scalar(ptr addrspace
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_add_u32 s34, s4, 32
; VI-NEXT: s_addc_u32 s35, s5, 0
-; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v3, s35
; VI-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1110,9 +1110,9 @@ define amdgpu_gfx void @global_atomic_add_i64_noret_offset_scalar(ptr addrspace(
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_add_u32 s34, s4, 32
; VI-NEXT: s_addc_u32 s35, s5, 0
-; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v3, s35
; VI-NEXT: flat_atomic_add_x2 v[2:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1219,9 +1219,9 @@ define amdgpu_gfx i64 @global_atomic_add_i64_ret_offset_scalar(ptr addrspace(1)
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_add_u32 s34, s4, 32
; VI-NEXT: s_addc_u32 s35, s5, 0
-; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_mov_b32_e32 v2, s34
; VI-NEXT: v_mov_b32_e32 v3, s35
; VI-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1536,8 +1536,8 @@ define i64 @global_atomic_sub_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; VI-NEXT: .LBB32_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mov_b32_e32 v6, v4
+; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_sub_u32_e32 v4, vcc, v6, v2
; VI-NEXT: v_subb_u32_e32 v5, vcc, v7, v3, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -1561,8 +1561,8 @@ define i64 @global_atomic_sub_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; GFX9-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v6, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v7, v3, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off glc
@@ -1629,8 +1629,8 @@ define i64 @global_atomic_sub_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; VI-NEXT: .LBB33_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
+; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_sub_u32_e32 v6, vcc, v8, v2
; VI-NEXT: v_subb_u32_e32 v7, vcc, v9, v3, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -1652,8 +1652,8 @@ define i64 @global_atomic_sub_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; GFX9-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v6, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v7, v3, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:32 glc
@@ -1725,9 +1725,9 @@ define amdgpu_gfx void @global_atomic_sub_i64_noret_scalar(ptr addrspace(1) inre
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v6, s7
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB34_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1929,15 +1929,15 @@ define amdgpu_gfx i64 @global_atomic_sub_i64_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB36_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v8, v1
; VI-NEXT: v_mov_b32_e32 v7, v0
+; VI-NEXT: v_mov_b32_e32 v8, v1
; VI-NEXT: v_subrev_u32_e32 v5, vcc, s6, v7
; VI-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -1961,8 +1961,8 @@ define amdgpu_gfx i64 @global_atomic_sub_i64_ret_scalar(ptr addrspace(1) inreg %
; GFX9-NEXT: .LBB36_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_mov_b32_e32 v6, v0
+; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s6, v6
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v7, v3, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v2, v[4:7], s[4:5] glc
@@ -2037,8 +2037,8 @@ define amdgpu_gfx i64 @global_atomic_sub_i64_ret_offset_scalar(ptr addrspace(1)
; VI-NEXT: .LBB37_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v8, v1
; VI-NEXT: v_mov_b32_e32 v7, v0
+; VI-NEXT: v_mov_b32_e32 v8, v1
; VI-NEXT: v_subrev_u32_e32 v5, vcc, s6, v7
; VI-NEXT: v_subb_u32_e32 v6, vcc, v8, v4, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[5:8] glc
@@ -2062,8 +2062,8 @@ define amdgpu_gfx i64 @global_atomic_sub_i64_ret_offset_scalar(ptr addrspace(1)
; GFX9-NEXT: .LBB37_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_mov_b32_e32 v6, v0
+; GFX9-NEXT: v_mov_b32_e32 v7, v1
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s6, v6
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v7, v3, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v2, v[4:7], s[4:5] offset:32 glc
@@ -2345,8 +2345,8 @@ define i64 @global_atomic_and_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB42_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, v10, v7
; SI-NEXT: v_and_b32_e32 v9, v11, v6
+; SI-NEXT: v_and_b32_e32 v8, v10, v7
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -2436,8 +2436,8 @@ define i64 @global_atomic_and_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: .LBB43_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v8, v10, v7
; SI-NEXT: v_and_b32_e32 v9, v11, v6
+; SI-NEXT: v_and_b32_e32 v8, v10, v7
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -2562,8 +2562,8 @@ define amdgpu_gfx void @global_atomic_and_i64_noret_scalar(ptr addrspace(1) inre
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB44_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -2760,8 +2760,8 @@ define amdgpu_gfx i64 @global_atomic_and_i64_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB46_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3183,10 +3183,10 @@ define i64 @global_atomic_nand_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB52_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, v10, v7
; SI-NEXT: v_and_b32_e32 v0, v11, v6
-; SI-NEXT: v_not_b32_e32 v8, v1
+; SI-NEXT: v_and_b32_e32 v1, v10, v7
; SI-NEXT: v_not_b32_e32 v9, v0
+; SI-NEXT: v_not_b32_e32 v8, v1
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
; SI-NEXT: v_mov_b32_e32 v2, v10
@@ -3279,10 +3279,10 @@ define i64 @global_atomic_nand_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: .LBB53_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, v10, v7
; SI-NEXT: v_and_b32_e32 v0, v11, v6
-; SI-NEXT: v_not_b32_e32 v8, v1
+; SI-NEXT: v_and_b32_e32 v1, v10, v7
; SI-NEXT: v_not_b32_e32 v9, v0
+; SI-NEXT: v_not_b32_e32 v8, v1
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
; SI-NEXT: v_mov_b32_e32 v2, v10
@@ -3412,8 +3412,8 @@ define amdgpu_gfx void @global_atomic_nand_i64_noret_scalar(ptr addrspace(1) inr
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB54_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3622,8 +3622,8 @@ define amdgpu_gfx i64 @global_atomic_nand_i64_ret_scalar(ptr addrspace(1) inreg
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB56_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3888,10 +3888,10 @@ define i64 @global_atomic_nand_i64_ret_offset__amdgpu_no_remote_memory(ptr addrs
; SI-NEXT: .LBB59_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, v10, v7
; SI-NEXT: v_and_b32_e32 v0, v11, v6
-; SI-NEXT: v_not_b32_e32 v8, v1
+; SI-NEXT: v_and_b32_e32 v1, v10, v7
; SI-NEXT: v_not_b32_e32 v9, v0
+; SI-NEXT: v_not_b32_e32 v8, v1
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
; SI-NEXT: v_mov_b32_e32 v2, v10
@@ -4158,8 +4158,8 @@ define i64 @global_atomic_or_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB62_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v8, v10, v7
; SI-NEXT: v_or_b32_e32 v9, v11, v6
+; SI-NEXT: v_or_b32_e32 v8, v10, v7
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -4249,8 +4249,8 @@ define i64 @global_atomic_or_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: .LBB63_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v8, v10, v7
; SI-NEXT: v_or_b32_e32 v9, v11, v6
+; SI-NEXT: v_or_b32_e32 v8, v10, v7
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -4375,8 +4375,8 @@ define amdgpu_gfx void @global_atomic_or_i64_noret_scalar(ptr addrspace(1) inreg
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB64_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4573,8 +4573,8 @@ define amdgpu_gfx i64 @global_atomic_or_i64_ret_scalar(ptr addrspace(1) inreg %p
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB66_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -4984,8 +4984,8 @@ define i64 @global_atomic_xor_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB72_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_xor_b32_e32 v8, v10, v7
; SI-NEXT: v_xor_b32_e32 v9, v11, v6
+; SI-NEXT: v_xor_b32_e32 v8, v10, v7
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -5075,8 +5075,8 @@ define i64 @global_atomic_xor_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: .LBB73_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_xor_b32_e32 v8, v10, v7
; SI-NEXT: v_xor_b32_e32 v9, v11, v6
+; SI-NEXT: v_xor_b32_e32 v8, v10, v7
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -5201,8 +5201,8 @@ define amdgpu_gfx void @global_atomic_xor_i64_noret_scalar(ptr addrspace(1) inre
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB74_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5399,8 +5399,8 @@ define amdgpu_gfx i64 @global_atomic_xor_i64_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB76_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5817,8 +5817,8 @@ define i64 @global_atomic_max_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -5911,8 +5911,8 @@ define i64 @global_atomic_max_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_i64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -6042,10 +6042,10 @@ define amdgpu_gfx void @global_atomic_max_i64_noret_scalar(ptr addrspace(1) inre
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_mov_b32_e32 v7, s6
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB84_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6259,10 +6259,10 @@ define amdgpu_gfx i64 @global_atomic_max_i64_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_mov_b32_e32 v5, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB86_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6474,12 +6474,12 @@ define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr addrspace(1) %out, i
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v6, s3
+; VI-NEXT: v_mov_b32_e32 v7, s2
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_mov_b32_e32 v7, s2
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: .LBB88_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6593,12 +6593,12 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v4, s5
+; VI-NEXT: v_mov_b32_e32 v5, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_mov_b32_e32 v5, s4
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: .LBB89_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -6712,10 +6712,10 @@ define amdgpu_kernel void @atomic_max_i64_addr64(ptr addrspace(1) %out, i64 %in,
; VI-NEXT: s_add_u32 s4, s0, s4
; VI-NEXT: s_addc_u32 s5, s1, s5
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[0:1], 0
; VI-NEXT: v_mov_b32_e32 v6, s3
; VI-NEXT: v_mov_b32_e32 v7, s2
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
@@ -6828,10 +6828,10 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_add_u32 s6, s0, s6
; VI-NEXT: s_addc_u32 s7, s1, s7
; VI-NEXT: s_load_dwordx2 s[8:9], s[6:7], 0x0
-; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_mov_b64 s[0:1], 0
; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: v_mov_b32_e32 v5, s4
+; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s8
; VI-NEXT: v_mov_b32_e32 v3, s9
@@ -7169,8 +7169,8 @@ define i64 @global_atomic_umax_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -7263,8 +7263,8 @@ define i64 @global_atomic_umax_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_gt_u64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -7394,10 +7394,10 @@ define amdgpu_gfx void @global_atomic_umax_i64_noret_scalar(ptr addrspace(1) inr
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_mov_b32_e32 v7, s6
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB98_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7611,10 +7611,10 @@ define amdgpu_gfx i64 @global_atomic_umax_i64_ret_scalar(ptr addrspace(1) inreg
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_mov_b32_e32 v5, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB100_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7826,12 +7826,12 @@ define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr addrspace(1) %out,
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v6, s3
+; VI-NEXT: v_mov_b32_e32 v7, s2
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_mov_b32_e32 v7, s2
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: .LBB102_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -7945,12 +7945,12 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr addrspace(1) %o
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v4, s5
+; VI-NEXT: v_mov_b32_e32 v5, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_mov_b32_e32 v5, s4
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: .LBB103_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8068,10 +8068,10 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_add_u32 s6, s0, s6
; VI-NEXT: s_addc_u32 s7, s1, s7
; VI-NEXT: s_load_dwordx2 s[8:9], s[6:7], 0x0
-; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_mov_b64 s[0:1], 0
; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: v_mov_b32_e32 v5, s4
+; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s8
; VI-NEXT: v_mov_b32_e32 v3, s9
@@ -8409,8 +8409,8 @@ define i64 @global_atomic_umin_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_le_u64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -8503,8 +8503,8 @@ define i64 @global_atomic_umin_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_le_u64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -8634,10 +8634,10 @@ define amdgpu_gfx void @global_atomic_umin_i64_noret_scalar(ptr addrspace(1) inr
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_mov_b32_e32 v7, s6
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB111_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -8851,10 +8851,10 @@ define amdgpu_gfx i64 @global_atomic_umin_i64_ret_scalar(ptr addrspace(1) inreg
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_mov_b32_e32 v5, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB113_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9285,8 +9285,8 @@ define i64 @global_atomic_min_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_le_i64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -9379,8 +9379,8 @@ define i64 @global_atomic_min_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_le_i64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
@@ -9510,10 +9510,10 @@ define amdgpu_gfx void @global_atomic_min_i64_noret_scalar(ptr addrspace(1) inre
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_mov_b32_e32 v7, s6
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB121_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9727,10 +9727,10 @@ define amdgpu_gfx i64 @global_atomic_min_i64_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_mov_b32_e32 v5, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB123_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -9942,12 +9942,12 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr addrspace(1) %out, i
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v6, s3
+; VI-NEXT: v_mov_b32_e32 v7, s2
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_mov_b32_e32 v7, s2
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: .LBB125_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10061,12 +10061,12 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr addrspace(1) %ou
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v4, s5
+; VI-NEXT: v_mov_b32_e32 v5, s4
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
-; VI-NEXT: v_mov_b32_e32 v5, s4
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: .LBB126_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -10175,9 +10175,9 @@ define amdgpu_kernel void @atomic_min_i64(ptr addrspace(1) %out, i64 %in) {
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v6, s3
; VI-NEXT: v_mov_b32_e32 v7, s2
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s6
@@ -10285,10 +10285,10 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr addrspace(1) %out, ptr
; VI-NEXT: s_add_u32 s6, s0, s6
; VI-NEXT: s_addc_u32 s7, s1, s7
; VI-NEXT: s_load_dwordx2 s[8:9], s[6:7], 0x0
-; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_mov_b64 s[0:1], 0
; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: v_mov_b32_e32 v5, s4
+; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s8
; VI-NEXT: v_mov_b32_e32 v3, s9
@@ -10640,8 +10640,8 @@ define i64 @global_atomic_uinc_wrap_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v10
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v11, vcc
; SI-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
; SI-NEXT: v_mov_b32_e32 v2, v10
@@ -10668,8 +10668,8 @@ define i64 @global_atomic_uinc_wrap_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; VI-NEXT: .LBB133_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mov_b32_e32 v6, v4
+; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v6
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; VI-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -10696,8 +10696,8 @@ define i64 @global_atomic_uinc_wrap_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; GFX9-NEXT: .LBB133_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -10739,8 +10739,8 @@ define i64 @global_atomic_uinc_wrap_i64_ret_offset(ptr addrspace(1) %out, i64 %i
; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v10
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v11, vcc
; SI-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
; SI-NEXT: v_mov_b32_e32 v2, v10
@@ -10769,8 +10769,8 @@ define i64 @global_atomic_uinc_wrap_i64_ret_offset(ptr addrspace(1) %out, i64 %i
; VI-NEXT: .LBB134_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
+; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v8
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v9, vcc
; VI-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
@@ -10795,8 +10795,8 @@ define i64 @global_atomic_uinc_wrap_i64_ret_offset(ptr addrspace(1) %out, i64 %i
; GFX9-NEXT: .LBB134_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
@@ -10873,8 +10873,8 @@ define amdgpu_gfx void @global_atomic_uinc_wrap_i64_noret_scalar(ptr addrspace(1
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB135_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -11089,14 +11089,14 @@ define amdgpu_gfx i64 @global_atomic_uinc_wrap_i64_ret_scalar(ptr addrspace(1) i
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[34:35], 0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB137_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v7, v1
; VI-NEXT: v_mov_b32_e32 v6, v0
+; VI-NEXT: v_mov_b32_e32 v7, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -11122,8 +11122,8 @@ define amdgpu_gfx i64 @global_atomic_uinc_wrap_i64_ret_scalar(ptr addrspace(1) i
; GFX9-NEXT: .LBB137_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v6, v1
; GFX9-NEXT: v_mov_b32_e32 v5, v0
+; GFX9-NEXT: v_mov_b32_e32 v6, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v5
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[5:6]
@@ -11202,8 +11202,8 @@ define amdgpu_gfx i64 @global_atomic_uinc_wrap_i64_ret_offset_scalar(ptr addrspa
; VI-NEXT: .LBB138_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v7, v1
; VI-NEXT: v_mov_b32_e32 v6, v0
+; VI-NEXT: v_mov_b32_e32 v7, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 1, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc
; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[6:7]
@@ -11229,8 +11229,8 @@ define amdgpu_gfx i64 @global_atomic_uinc_wrap_i64_ret_offset_scalar(ptr addrspa
; GFX9-NEXT: .LBB138_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v6, v1
; GFX9-NEXT: v_mov_b32_e32 v5, v0
+; GFX9-NEXT: v_mov_b32_e32 v6, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v5
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[5:6]
@@ -11544,8 +11544,8 @@ define i64 @global_atomic_udec_wrap_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: v_subrev_i32_e64 v0, s[4:5], 1, v10
; SI-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v11, s[4:5]
; SI-NEXT: s_or_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e32 v8, v0, v4, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v1, v5, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
; SI-NEXT: v_mov_b32_e32 v2, v10
@@ -11647,8 +11647,8 @@ define i64 @global_atomic_udec_wrap_i64_ret_offset(ptr addrspace(1) %out, i64 %i
; SI-NEXT: v_subrev_i32_e64 v0, s[4:5], 1, v10
; SI-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v11, s[4:5]
; SI-NEXT: s_or_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e32 v8, v0, v4, vcc
; SI-NEXT: v_cndmask_b32_e32 v9, v1, v5, vcc
+; SI-NEXT: v_cndmask_b32_e32 v8, v0, v4, vcc
; SI-NEXT: v_mov_b32_e32 v0, v8
; SI-NEXT: v_mov_b32_e32 v1, v9
; SI-NEXT: v_mov_b32_e32 v2, v10
@@ -11786,10 +11786,10 @@ define amdgpu_gfx void @global_atomic_udec_wrap_i64_noret_scalar(ptr addrspace(1
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: s_mov_b64 s[36:37], 0
; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_mov_b32_e32 v7, s6
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: .LBB145_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -12021,10 +12021,10 @@ define amdgpu_gfx i64 @global_atomic_udec_wrap_i64_ret_scalar(ptr addrspace(1) i
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: s_mov_b64 s[36:37], 0
; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_mov_b32_e32 v5, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: .LBB147_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
index ce5577e85c061..f1ecc94398192 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
@@ -380,14 +380,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -453,14 +453,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -750,14 +750,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -801,14 +801,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -1607,14 +1607,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -1680,14 +1680,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -1977,14 +1977,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -2028,14 +2028,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -2894,14 +2894,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -2967,14 +2967,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -3264,14 +3264,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -3315,14 +3315,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -3677,14 +3677,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -3750,14 +3750,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -4047,14 +4047,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -4098,14 +4098,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -4963,14 +4963,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_default_scop
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -5036,14 +5036,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_default_scop
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -5359,14 +5359,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_default_scop
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -5410,14 +5410,14 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_default_scop
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -5829,8 +5829,8 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_uni_value_agent
; GFX9-NEXT: s_cbranch_execz .LBB9_3
; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -5862,10 +5862,10 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_uni_value_agent
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz .LBB9_3
; GFX1064-NEXT: ; %bb.1:
-; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1064-NEXT: v_mov_b32_e32 v6, 0
+; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX1064-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1064-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -5896,10 +5896,10 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_uni_value_agent
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz .LBB9_3
; GFX1032-NEXT: ; %bb.1:
-; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1032-NEXT: v_mov_b32_e32 v6, 0
+; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_cvt_f64_u32_e32 v[0:1], s3
+; GFX1032-NEXT: v_mov_b32_e32 v6, 0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX1032-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6043,8 +6043,8 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_uni_value_agent
; GFX9-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX9-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-DPP-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX9-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX9-DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX9-DPP-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6076,10 +6076,10 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_uni_value_agent
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1064-DPP-NEXT: ; %bb.1:
-; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-DPP-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-DPP-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1064-DPP-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6110,10 +6110,10 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_uni_value_agent
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1032-DPP-NEXT: ; %bb.1:
-; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-DPP-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-DPP-NEXT: v_cvt_f64_u32_e32 v[0:1], s3
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX1032-DPP-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6229,14 +6229,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -6307,14 +6307,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -6644,14 +6644,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -6698,14 +6698,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -7670,14 +7670,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -7748,14 +7748,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -8085,14 +8085,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -8139,14 +8139,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -9111,14 +9111,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -9189,14 +9189,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -9526,14 +9526,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -9580,14 +9580,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -10034,14 +10034,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -10112,14 +10112,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -10449,14 +10449,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -10503,14 +10503,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -11475,14 +11475,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -11553,14 +11553,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -11890,14 +11890,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -11944,14 +11944,14 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
index 25b079f881b98..92c54d4c20252 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
@@ -256,14 +256,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -316,14 +316,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -602,14 +602,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -636,14 +636,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -1235,14 +1235,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -1295,14 +1295,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -1581,14 +1581,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -1615,14 +1615,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -2214,14 +2214,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_default_scop
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -2274,14 +2274,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_default_scop
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -2560,14 +2560,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_default_scop
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -2594,14 +2594,14 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_default_scop
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -3268,14 +3268,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -3330,14 +3330,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -3660,14 +3660,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -3694,14 +3694,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -4465,14 +4465,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -4527,14 +4527,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -4857,14 +4857,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -4891,14 +4891,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -5662,14 +5662,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -5724,14 +5724,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -6054,14 +6054,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -6088,14 +6088,14 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
index 5f86e306eac45..a59a1d518022b 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
@@ -256,14 +256,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -316,14 +316,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -602,14 +602,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -636,14 +636,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -1235,14 +1235,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -1295,14 +1295,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -1581,14 +1581,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -1615,14 +1615,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -2214,14 +2214,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_default_scop
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -2274,14 +2274,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_default_scop
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -2560,14 +2560,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_default_scop
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -2594,14 +2594,14 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_default_scop
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -3268,14 +3268,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -3330,14 +3330,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -3660,14 +3660,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -3694,14 +3694,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -4465,14 +4465,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -4527,14 +4527,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -4857,14 +4857,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -4891,14 +4891,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -5662,14 +5662,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -5724,14 +5724,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -6054,14 +6054,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -6088,14 +6088,14 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
index 4b7e553fcddbd..8aeffd7fae1a6 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
@@ -440,14 +440,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -513,14 +513,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -836,14 +836,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -887,14 +887,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -1779,14 +1779,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -1852,14 +1852,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -2175,14 +2175,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -2226,14 +2226,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -3118,14 +3118,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -3191,14 +3191,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -3514,14 +3514,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -3565,14 +3565,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -3953,14 +3953,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -4026,14 +4026,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -4349,14 +4349,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -4400,14 +4400,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -5291,14 +5291,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_default_scop
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -5364,14 +5364,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_default_scop
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -5687,14 +5687,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_default_scop
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -5738,14 +5738,14 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_default_scop
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -6157,8 +6157,8 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_uni_value_agent
; GFX9-NEXT: s_cbranch_execz .LBB9_3
; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6190,10 +6190,10 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_uni_value_agent
; GFX1064-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-NEXT: s_cbranch_execz .LBB9_3
; GFX1064-NEXT: ; %bb.1:
-; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1064-NEXT: v_mov_b32_e32 v6, 0
+; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX1064-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1064-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6224,10 +6224,10 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_uni_value_agent
; GFX1032-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-NEXT: s_cbranch_execz .LBB9_3
; GFX1032-NEXT: ; %bb.1:
-; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1032-NEXT: v_mov_b32_e32 v6, 0
+; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_cvt_f64_u32_e32 v[0:1], s3
+; GFX1032-NEXT: v_mov_b32_e32 v6, 0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX1032-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6371,8 +6371,8 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_uni_value_agent
; GFX9-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX9-DPP-NEXT: ; %bb.1:
; GFX9-DPP-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX9-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-DPP-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX9-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], 0
; GFX9-DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX9-DPP-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6404,10 +6404,10 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_uni_value_agent
; GFX1064-DPP-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1064-DPP-NEXT: ; %bb.1:
-; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-DPP-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1064-DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1064-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-DPP-NEXT: v_cvt_f64_u32_e32 v[0:1], s2
+; GFX1064-DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-DPP-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1064-DPP-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6438,10 +6438,10 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_uni_value_agent
; GFX1032-DPP-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX1032-DPP-NEXT: s_cbranch_execz .LBB9_3
; GFX1032-DPP-NEXT: ; %bb.1:
-; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-DPP-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1032-DPP-NEXT: v_mov_b32_e32 v6, 0
+; GFX1032-DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-DPP-NEXT: v_cvt_f64_u32_e32 v[0:1], s3
+; GFX1032-DPP-NEXT: v_mov_b32_e32 v6, 0
; GFX1032-DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-DPP-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX1032-DPP-NEXT: v_mul_f64 v[4:5], v[0:1], 4.0
@@ -6557,14 +6557,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -6635,14 +6635,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -6972,14 +6972,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -7026,14 +7026,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -7997,14 +7997,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -8075,14 +8075,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -8412,14 +8412,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -8466,14 +8466,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -9438,14 +9438,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -9516,14 +9516,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -9853,14 +9853,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -9907,14 +9907,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.double.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.double.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -10361,14 +10361,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -10439,14 +10439,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -10776,14 +10776,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -10830,14 +10830,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
@@ -11801,14 +11801,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX7LESS-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX7LESS-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX7LESS-NEXT: s_mov_b32 s32, 0
; GFX7LESS-NEXT: ; implicit-def: $sgpr15
@@ -11879,14 +11879,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX9-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ; implicit-def: $sgpr15
@@ -12216,14 +12216,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX7LESS-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX7LESS-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
-; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX7LESS-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX7LESS-DPP-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7LESS-DPP-NEXT: s_mov_b32 s14, s10
+; GFX7LESS-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7LESS-DPP-NEXT: s_mov_b64 s[0:1], s[48:49]
-; GFX7LESS-DPP-NEXT: v_or_b32_e32 v31, v0, v2
; GFX7LESS-DPP-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX7LESS-DPP-NEXT: s_mov_b32 s32, 0
; GFX7LESS-DPP-NEXT: s_mov_b32 s39, 0xf000
@@ -12270,14 +12270,14 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX9-DPP-NEXT: s_add_u32 s4, s4, div.float.value at gotpcrel32@lo+4
; GFX9-DPP-NEXT: s_addc_u32 s5, s5, div.float.value at gotpcrel32@hi+12
; GFX9-DPP-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-DPP-NEXT: s_mov_b32 s14, s10
-; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-DPP-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-DPP-NEXT: s_mov_b32 s14, s10
+; GFX9-DPP-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-DPP-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-DPP-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-DPP-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-DPP-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-DPP-NEXT: s_mov_b32 s32, 0
; GFX9-DPP-NEXT: ; implicit-def: $sgpr15
diff --git a/llvm/test/CodeGen/AMDGPU/half.ll b/llvm/test/CodeGen/AMDGPU/half.ll
index a61d6a6cc071f..88baf69fd9cde 100644
--- a/llvm/test/CodeGen/AMDGPU/half.ll
+++ b/llvm/test/CodeGen/AMDGPU/half.ll
@@ -100,10 +100,10 @@ define amdgpu_kernel void @load_v3f16_arg(ptr addrspace(1) %out, <3 x half> %arg
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
; CIVI-NEXT: s_add_u32 s4, s0, 4
; CIVI-NEXT: s_addc_u32 s5, s1, 0
-; CIVI-NEXT: v_mov_b32_e32 v2, s4
; CIVI-NEXT: v_mov_b32_e32 v4, s3
-; CIVI-NEXT: v_mov_b32_e32 v0, s0
+; CIVI-NEXT: v_mov_b32_e32 v2, s4
; CIVI-NEXT: v_mov_b32_e32 v3, s5
+; CIVI-NEXT: v_mov_b32_e32 v0, s0
; CIVI-NEXT: v_mov_b32_e32 v1, s1
; CIVI-NEXT: v_mov_b32_e32 v5, s2
; CIVI-NEXT: flat_store_short v[2:3], v4
@@ -135,8 +135,8 @@ define amdgpu_kernel void @load_v4f16_arg(ptr addrspace(1) %out, <4 x half> %arg
; CIVI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
; CIVI-NEXT: v_mov_b32_e32 v0, s0
-; CIVI-NEXT: v_mov_b32_e32 v2, s2
; CIVI-NEXT: v_mov_b32_e32 v1, s1
+; CIVI-NEXT: v_mov_b32_e32 v2, s2
; CIVI-NEXT: v_mov_b32_e32 v3, s3
; CIVI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; CIVI-NEXT: s_endpgm
@@ -144,9 +144,9 @@ define amdgpu_kernel void @load_v4f16_arg(ptr addrspace(1) %out, <4 x half> %arg
; GFX11-LABEL: load_v4f16_arg:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
store <4 x half> %arg, ptr addrspace(1) %out
@@ -163,8 +163,8 @@ define amdgpu_kernel void @load_v8f16_arg(ptr addrspace(1) %out, <8 x half> %arg
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s4
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v5, s5
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
@@ -180,8 +180,8 @@ define amdgpu_kernel void @load_v8f16_arg(ptr addrspace(1) %out, <8 x half> %arg
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v5, s5
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
@@ -193,10 +193,10 @@ define amdgpu_kernel void @load_v8f16_arg(ptr addrspace(1) %out, <8 x half> %arg
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]
; GFX11-NEXT: s_endpgm
store <8 x half> %arg, ptr addrspace(1) %out
@@ -466,14 +466,14 @@ define amdgpu_kernel void @extload_v8f16_to_v8f32_arg(ptr addrspace(1) %out, <8
; CI-NEXT: s_lshr_b32 s9, s1, 16
; CI-NEXT: v_cvt_f32_f16_e32 v7, s7
; CI-NEXT: v_cvt_f32_f16_e32 v5, s6
-; CI-NEXT: v_cvt_f32_f16_e32 v0, s0
; CI-NEXT: v_cvt_f32_f16_e32 v6, s3
; CI-NEXT: v_cvt_f32_f16_e32 v4, s2
-; CI-NEXT: s_add_u32 s0, s4, 16
-; CI-NEXT: v_cvt_f32_f16_e32 v2, s1
-; CI-NEXT: s_addc_u32 s1, s5, 0
; CI-NEXT: v_cvt_f32_f16_e32 v3, s9
; CI-NEXT: v_cvt_f32_f16_e32 v1, s8
+; CI-NEXT: v_cvt_f32_f16_e32 v2, s1
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s0
+; CI-NEXT: s_add_u32 s0, s4, 16
+; CI-NEXT: s_addc_u32 s1, s5, 0
; CI-NEXT: v_mov_b32_e32 v9, s1
; CI-NEXT: v_mov_b32_e32 v8, s0
; CI-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
@@ -492,19 +492,19 @@ define amdgpu_kernel void @extload_v8f16_to_v8f32_arg(ptr addrspace(1) %out, <8
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s6, s1, 16
-; VI-NEXT: s_lshr_b32 s7, s0, 16
; VI-NEXT: s_lshr_b32 s8, s3, 16
; VI-NEXT: v_cvt_f32_f16_e32 v3, s6
; VI-NEXT: s_lshr_b32 s6, s2, 16
+; VI-NEXT: s_lshr_b32 s7, s0, 16
; VI-NEXT: v_cvt_f32_f16_e32 v7, s8
; VI-NEXT: v_cvt_f32_f16_e32 v5, s6
-; VI-NEXT: v_cvt_f32_f16_e32 v0, s0
; VI-NEXT: v_cvt_f32_f16_e32 v6, s3
; VI-NEXT: v_cvt_f32_f16_e32 v4, s2
-; VI-NEXT: s_add_u32 s0, s4, 16
+; VI-NEXT: v_cvt_f32_f16_e32 v1, s7
; VI-NEXT: v_cvt_f32_f16_e32 v2, s1
+; VI-NEXT: v_cvt_f32_f16_e32 v0, s0
+; VI-NEXT: s_add_u32 s0, s4, 16
; VI-NEXT: s_addc_u32 s1, s5, 0
-; VI-NEXT: v_cvt_f32_f16_e32 v1, s7
; VI-NEXT: v_mov_b32_e32 v9, s1
; VI-NEXT: v_mov_b32_e32 v8, s0
; VI-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
@@ -659,15 +659,15 @@ define amdgpu_kernel void @extload_v3f16_to_v3f64_arg(ptr addrspace(1) %out, <3
; CIVI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CIVI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
-; CIVI-NEXT: v_cvt_f32_f16_e32 v1, s3
; CIVI-NEXT: s_lshr_b32 s4, s2, 16
+; CIVI-NEXT: v_cvt_f32_f16_e32 v1, s3
; CIVI-NEXT: v_cvt_f32_f16_e32 v0, s2
; CIVI-NEXT: v_cvt_f32_f16_e32 v2, s4
; CIVI-NEXT: s_add_u32 s2, s0, 16
; CIVI-NEXT: v_cvt_f64_f32_e32 v[4:5], v1
-; CIVI-NEXT: s_addc_u32 s3, s1, 0
; CIVI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; CIVI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; CIVI-NEXT: s_addc_u32 s3, s1, 0
; CIVI-NEXT: v_mov_b32_e32 v7, s3
; CIVI-NEXT: v_mov_b32_e32 v6, s2
; CIVI-NEXT: flat_store_dwordx2 v[6:7], v[4:5]
@@ -708,17 +708,17 @@ define amdgpu_kernel void @extload_v4f16_to_v4f64_arg(ptr addrspace(1) %out, <4
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_lshr_b32 s4, s3, 16
+; CI-NEXT: s_lshr_b32 s5, s2, 16
; CI-NEXT: v_cvt_f32_f16_e32 v0, s3
; CI-NEXT: v_cvt_f32_f16_e32 v2, s4
-; CI-NEXT: s_lshr_b32 s5, s2, 16
; CI-NEXT: v_cvt_f32_f16_e32 v4, s2
; CI-NEXT: v_cvt_f32_f16_e32 v6, s5
-; CI-NEXT: s_add_u32 s2, s0, 16
; CI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; CI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
-; CI-NEXT: s_addc_u32 s3, s1, 0
+; CI-NEXT: s_add_u32 s2, s0, 16
; CI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; CI-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
+; CI-NEXT: s_addc_u32 s3, s1, 0
; CI-NEXT: v_mov_b32_e32 v9, s3
; CI-NEXT: v_mov_b32_e32 v8, s2
; CI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
@@ -736,17 +736,17 @@ define amdgpu_kernel void @extload_v4f16_to_v4f64_arg(ptr addrspace(1) %out, <4
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshr_b32 s5, s3, 16
+; VI-NEXT: s_lshr_b32 s4, s2, 16
; VI-NEXT: v_cvt_f32_f16_e32 v0, s3
; VI-NEXT: v_cvt_f32_f16_e32 v2, s5
-; VI-NEXT: s_lshr_b32 s4, s2, 16
; VI-NEXT: v_cvt_f32_f16_e32 v4, s2
; VI-NEXT: v_cvt_f32_f16_e32 v6, s4
-; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
-; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; VI-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
+; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: v_mov_b32_e32 v9, s3
; VI-NEXT: v_mov_b32_e32 v8, s2
; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
@@ -791,37 +791,38 @@ define amdgpu_kernel void @extload_v8f16_to_v8f64_arg(ptr addrspace(1) %out, <8
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_lshr_b32 s9, s0, 16
-; CI-NEXT: s_lshr_b32 s6, s3, 16
; CI-NEXT: s_lshr_b32 s7, s2, 16
-; CI-NEXT: v_cvt_f32_f16_e32 v0, s9
+; CI-NEXT: s_lshr_b32 s6, s3, 16
+; CI-NEXT: s_lshr_b32 s9, s0, 16
; CI-NEXT: v_cvt_f32_f16_e32 v4, s7
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s9
; CI-NEXT: v_cvt_f32_f16_e32 v5, s6
; CI-NEXT: v_cvt_f32_f16_e32 v12, s3
; CI-NEXT: s_lshr_b32 s8, s1, 16
-; CI-NEXT: v_cvt_f64_f32_e32 v[2:3], v0
-; CI-NEXT: v_cvt_f32_f16_e32 v0, s0
; CI-NEXT: v_cvt_f32_f16_e32 v8, s2
-; CI-NEXT: s_add_u32 s0, s4, 48
+; CI-NEXT: v_cvt_f32_f16_e32 v1, s8
; CI-NEXT: v_cvt_f64_f32_e32 v[10:11], v4
-; CI-NEXT: v_cvt_f64_f32_e32 v[14:15], v5
; CI-NEXT: v_cvt_f32_f16_e32 v4, s1
+; CI-NEXT: v_cvt_f64_f32_e32 v[2:3], v0
+; CI-NEXT: v_cvt_f64_f32_e32 v[14:15], v5
+; CI-NEXT: v_cvt_f32_f16_e32 v0, s0
; CI-NEXT: v_cvt_f64_f32_e32 v[12:13], v12
+; CI-NEXT: s_add_u32 s0, s4, 48
; CI-NEXT: s_addc_u32 s1, s5, 0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, s8
+; CI-NEXT: v_cvt_f64_f32_e32 v[8:9], v8
; CI-NEXT: v_mov_b32_e32 v17, s1
; CI-NEXT: v_mov_b32_e32 v16, s0
; CI-NEXT: s_add_u32 s0, s4, 32
-; CI-NEXT: v_cvt_f64_f32_e32 v[8:9], v8
+; CI-NEXT: v_cvt_f64_f32_e32 v[6:7], v1
+; CI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; CI-NEXT: s_addc_u32 s1, s5, 0
+; CI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; CI-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
-; CI-NEXT: v_cvt_f64_f32_e32 v[6:7], v1
+; CI-NEXT: s_nop 0
; CI-NEXT: v_mov_b32_e32 v13, s1
-; CI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; CI-NEXT: v_mov_b32_e32 v12, s0
; CI-NEXT: s_add_u32 s0, s4, 16
; CI-NEXT: s_addc_u32 s1, s5, 0
-; CI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; CI-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
; CI-NEXT: s_nop 0
; CI-NEXT: v_mov_b32_e32 v9, s1
@@ -841,37 +842,38 @@ define amdgpu_kernel void @extload_v8f16_to_v8f64_arg(ptr addrspace(1) %out, <8
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_lshr_b32 s6, s0, 16
; VI-NEXT: s_lshr_b32 s8, s2, 16
+; VI-NEXT: s_lshr_b32 s6, s0, 16
; VI-NEXT: s_lshr_b32 s9, s3, 16
-; VI-NEXT: v_cvt_f32_f16_e32 v0, s6
; VI-NEXT: v_cvt_f32_f16_e32 v4, s8
+; VI-NEXT: v_cvt_f32_f16_e32 v0, s6
; VI-NEXT: v_cvt_f32_f16_e32 v5, s9
; VI-NEXT: v_cvt_f32_f16_e32 v12, s3
; VI-NEXT: s_lshr_b32 s7, s1, 16
-; VI-NEXT: v_cvt_f64_f32_e32 v[2:3], v0
-; VI-NEXT: v_cvt_f32_f16_e32 v0, s0
; VI-NEXT: v_cvt_f32_f16_e32 v8, s2
-; VI-NEXT: s_add_u32 s0, s4, 48
+; VI-NEXT: v_cvt_f32_f16_e32 v1, s7
; VI-NEXT: v_cvt_f64_f32_e32 v[10:11], v4
-; VI-NEXT: v_cvt_f64_f32_e32 v[14:15], v5
; VI-NEXT: v_cvt_f32_f16_e32 v4, s1
+; VI-NEXT: v_cvt_f64_f32_e32 v[2:3], v0
+; VI-NEXT: v_cvt_f64_f32_e32 v[14:15], v5
+; VI-NEXT: v_cvt_f32_f16_e32 v0, s0
; VI-NEXT: v_cvt_f64_f32_e32 v[12:13], v12
+; VI-NEXT: s_add_u32 s0, s4, 48
; VI-NEXT: s_addc_u32 s1, s5, 0
-; VI-NEXT: v_cvt_f32_f16_e32 v1, s7
+; VI-NEXT: v_cvt_f64_f32_e32 v[8:9], v8
; VI-NEXT: v_mov_b32_e32 v17, s1
; VI-NEXT: v_mov_b32_e32 v16, s0
; VI-NEXT: s_add_u32 s0, s4, 32
-; VI-NEXT: v_cvt_f64_f32_e32 v[8:9], v8
+; VI-NEXT: v_cvt_f64_f32_e32 v[6:7], v1
+; VI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; VI-NEXT: s_addc_u32 s1, s5, 0
+; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
-; VI-NEXT: v_cvt_f64_f32_e32 v[6:7], v1
+; VI-NEXT: s_nop 0
; VI-NEXT: v_mov_b32_e32 v13, s1
-; VI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; VI-NEXT: v_mov_b32_e32 v12, s0
; VI-NEXT: s_add_u32 s0, s4, 16
; VI-NEXT: s_addc_u32 s1, s5, 0
-; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
; VI-NEXT: s_nop 0
; VI-NEXT: v_mov_b32_e32 v9, s1
@@ -1481,25 +1483,25 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f32(ptr addrspace(1) %out
; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
; CI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
; CI-NEXT: flat_store_dwordx4 v[15:16], v[8:11]
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v4
-; CI-NEXT: v_lshrrev_b32_e32 v16, 16, v4
-; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
-; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_cvt_f32_f16_e32 v15, v17
; CI-NEXT: v_cvt_f32_f16_e32 v13, v13
; CI-NEXT: v_cvt_f32_f16_e32 v8, v7
; CI-NEXT: v_cvt_f32_f16_e32 v6, v6
-; CI-NEXT: v_mov_b32_e32 v4, s0
-; CI-NEXT: s_add_u32 s0, s0, 32
+; CI-NEXT: v_lshrrev_b32_e32 v16, 16, v4
+; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v5
; CI-NEXT: v_cvt_f32_f16_e32 v9, v18
; CI-NEXT: v_cvt_f32_f16_e32 v7, v1
-; CI-NEXT: s_addc_u32 s1, s1, 0
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v5
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v4
+; CI-NEXT: v_mov_b32_e32 v5, s1
+; CI-NEXT: v_mov_b32_e32 v4, s0
+; CI-NEXT: s_add_u32 s0, s0, 32
; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cvt_f32_f16_e32 v1, v16
+; CI-NEXT: s_addc_u32 s1, s1, 0
; CI-NEXT: v_mov_b32_e32 v11, s3
-; CI-NEXT: v_mov_b32_e32 v17, s1
; CI-NEXT: v_mov_b32_e32 v10, s2
+; CI-NEXT: v_mov_b32_e32 v17, s1
; CI-NEXT: v_mov_b32_e32 v16, s0
; CI-NEXT: flat_store_dwordx4 v[4:5], v[12:15]
; CI-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
@@ -1526,8 +1528,8 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f32(ptr addrspace(1) %out
; VI-NEXT: v_mov_b32_e32 v19, s3
; VI-NEXT: v_mov_b32_e32 v18, s2
; VI-NEXT: s_add_u32 s2, s0, 48
-; VI-NEXT: v_mov_b32_e32 v17, s1
; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: v_mov_b32_e32 v17, s1
; VI-NEXT: v_mov_b32_e32 v16, s0
; VI-NEXT: s_add_u32 s0, s0, 32
; VI-NEXT: s_addc_u32 s1, s1, 0
@@ -1793,8 +1795,8 @@ define amdgpu_kernel void @global_extload_v3f16_to_v3f64(ptr addrspace(1) %out,
; CI-NEXT: v_mov_b32_e32 v7, s3
; CI-NEXT: v_mov_b32_e32 v6, s2
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; CI-NEXT: v_cvt_f64_f32_e32 v[4:5], v1
@@ -1818,6 +1820,7 @@ define amdgpu_kernel void @global_extload_v3f16_to_v3f64(ptr addrspace(1) %out,
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: v_mov_b32_e32 v9, s3
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1827,7 +1830,6 @@ define amdgpu_kernel void @global_extload_v3f16_to_v3f64(ptr addrspace(1) %out,
; VI-NEXT: v_cvt_f64_f32_e32 v[6:7], v3
; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
; VI-NEXT: v_cvt_f64_f32_e32 v[2:3], v8
-; VI-NEXT: v_mov_b32_e32 v9, s3
; VI-NEXT: v_mov_b32_e32 v8, s2
; VI-NEXT: flat_store_dwordx2 v[8:9], v[6:7]
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -1894,8 +1896,8 @@ define amdgpu_kernel void @global_extload_v4f16_to_v4f64(ptr addrspace(1) %out,
; CI-NEXT: s_add_u32 s2, s0, 16
; CI-NEXT: s_addc_u32 s3, s1, 0
; CI-NEXT: v_mov_b32_e32 v11, s3
-; CI-NEXT: v_mov_b32_e32 v9, s1
; CI-NEXT: v_mov_b32_e32 v10, s2
+; CI-NEXT: v_mov_b32_e32 v9, s1
; CI-NEXT: v_mov_b32_e32 v8, s0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
@@ -1924,6 +1926,7 @@ define amdgpu_kernel void @global_extload_v4f16_to_v4f64(ptr addrspace(1) %out,
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: v_mov_b32_e32 v11, s3
; VI-NEXT: v_mov_b32_e32 v9, s1
; VI-NEXT: v_mov_b32_e32 v8, s0
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1935,7 +1938,6 @@ define amdgpu_kernel void @global_extload_v4f16_to_v4f64(ptr addrspace(1) %out,
; VI-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
; VI-NEXT: v_cvt_f64_f32_e32 v[2:3], v10
-; VI-NEXT: v_mov_b32_e32 v11, s3
; VI-NEXT: v_mov_b32_e32 v10, s2
; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
@@ -2012,13 +2014,13 @@ define amdgpu_kernel void @global_extload_v8f16_to_v8f64(ptr addrspace(1) %out,
; CI-NEXT: v_mov_b32_e32 v7, s3
; CI-NEXT: v_mov_b32_e32 v6, s2
; CI-NEXT: s_add_u32 s2, s0, 32
-; CI-NEXT: v_mov_b32_e32 v13, s1
; CI-NEXT: s_addc_u32 s3, s1, 0
+; CI-NEXT: v_mov_b32_e32 v13, s1
; CI-NEXT: v_mov_b32_e32 v12, s0
; CI-NEXT: s_add_u32 s0, s0, 16
; CI-NEXT: v_mov_b32_e32 v15, s3
-; CI-NEXT: s_addc_u32 s1, s1, 0
; CI-NEXT: v_mov_b32_e32 v14, s2
+; CI-NEXT: s_addc_u32 s1, s1, 0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
@@ -2063,13 +2065,13 @@ define amdgpu_kernel void @global_extload_v8f16_to_v8f64(ptr addrspace(1) %out,
; VI-NEXT: v_mov_b32_e32 v8, s3
; VI-NEXT: v_mov_b32_e32 v7, s2
; VI-NEXT: s_add_u32 s2, s0, 32
-; VI-NEXT: v_mov_b32_e32 v13, s1
; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: v_mov_b32_e32 v13, s1
; VI-NEXT: v_mov_b32_e32 v12, s0
; VI-NEXT: s_add_u32 s0, s0, 16
; VI-NEXT: v_mov_b32_e32 v15, s3
-; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v14, s2
+; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_f16_e32 v9, v0
; VI-NEXT: v_cvt_f32_f16_sdwa v16, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
@@ -2196,18 +2198,18 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f64(ptr addrspace(1) %out
; CI-NEXT: s_addc_u32 s3, s1, 0
; CI-NEXT: v_mov_b32_e32 v18, s3
; CI-NEXT: v_mov_b32_e32 v17, s2
-; CI-NEXT: s_add_u32 s2, s0, 0x70
-; CI-NEXT: s_addc_u32 s3, s1, 0
; CI-NEXT: v_mov_b32_e32 v12, s1
; CI-NEXT: v_mov_b32_e32 v11, s0
+; CI-NEXT: s_add_u32 s2, s0, 0x70
+; CI-NEXT: s_addc_u32 s3, s1, 0
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
; CI-NEXT: v_cvt_f32_f16_e32 v7, v7
; CI-NEXT: v_cvt_f32_f16_e32 v9, v8
-; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_lshrrev_b32_e32 v19, 16, v2
; CI-NEXT: v_cvt_f64_f32_e32 v[7:8], v7
; CI-NEXT: v_cvt_f64_f32_e32 v[9:10], v9
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_lshrrev_b32_e32 v19, 16, v2
; CI-NEXT: v_cvt_f32_f16_e32 v20, v2
; CI-NEXT: v_cvt_f32_f16_e32 v21, v3
; CI-NEXT: flat_store_dwordx4 v[13:14], v[7:10]
@@ -2247,19 +2249,19 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f64(ptr addrspace(1) %out
; CI-NEXT: v_cvt_f32_f16_e32 v12, v4
; CI-NEXT: v_cvt_f64_f32_e32 v[0:1], v21
; CI-NEXT: v_cvt_f64_f32_e32 v[2:3], v8
-; CI-NEXT: s_addc_u32 s3, s1, 0
; CI-NEXT: v_cvt_f64_f32_e32 v[8:9], v20
; CI-NEXT: v_cvt_f64_f32_e32 v[10:11], v10
-; CI-NEXT: s_add_u32 s0, s0, 64
+; CI-NEXT: s_addc_u32 s3, s1, 0
; CI-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
-; CI-NEXT: s_addc_u32 s1, s1, 0
+; CI-NEXT: s_add_u32 s0, s0, 64
; CI-NEXT: v_cvt_f64_f32_e32 v[0:1], v7
; CI-NEXT: v_cvt_f64_f32_e32 v[2:3], v12
; CI-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; CI-NEXT: v_cvt_f64_f32_e32 v[6:7], v22
+; CI-NEXT: s_addc_u32 s1, s1, 0
; CI-NEXT: v_mov_b32_e32 v18, s3
-; CI-NEXT: v_mov_b32_e32 v13, s1
; CI-NEXT: v_mov_b32_e32 v17, s2
+; CI-NEXT: v_mov_b32_e32 v13, s1
; CI-NEXT: v_mov_b32_e32 v12, s0
; CI-NEXT: flat_store_dwordx4 v[15:16], v[8:11]
; CI-NEXT: flat_store_dwordx4 v[17:18], v[0:3]
@@ -2293,10 +2295,10 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f64(ptr addrspace(1) %out
; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: v_mov_b32_e32 v18, s3
; VI-NEXT: v_mov_b32_e32 v17, s2
-; VI-NEXT: s_add_u32 s2, s0, 0x50
; VI-NEXT: v_mov_b32_e32 v12, s1
-; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: v_mov_b32_e32 v11, s0
+; VI-NEXT: s_add_u32 s2, s0, 0x50
+; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cvt_f32_f16_e32 v8, v7
; VI-NEXT: v_cvt_f32_f16_sdwa v9, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
@@ -2340,15 +2342,15 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f64(ptr addrspace(1) %out
; VI-NEXT: v_cvt_f64_f32_e32 v[5:6], v10
; VI-NEXT: v_cvt_f64_f32_e32 v[11:12], v11
; VI-NEXT: v_cvt_f64_f32_e32 v[9:10], v9
-; VI-NEXT: s_add_u32 s0, s0, 0x60
; VI-NEXT: flat_store_dwordx4 v[13:14], v[1:4]
-; VI-NEXT: s_addc_u32 s1, s1, 0
+; VI-NEXT: s_add_u32 s0, s0, 0x60
; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v7
; VI-NEXT: v_cvt_f64_f32_e32 v[2:3], v17
; VI-NEXT: v_cvt_f64_f32_e32 v[7:8], v8
+; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v20, s3
-; VI-NEXT: v_mov_b32_e32 v14, s1
; VI-NEXT: v_mov_b32_e32 v19, s2
+; VI-NEXT: v_mov_b32_e32 v14, s1
; VI-NEXT: v_mov_b32_e32 v13, s0
; VI-NEXT: flat_store_dwordx4 v[15:16], v[9:12]
; VI-NEXT: flat_store_dwordx4 v[19:20], v[0:3]
@@ -2619,8 +2621,8 @@ define amdgpu_kernel void @global_truncstore_v3f32_to_v3f16(ptr addrspace(1) %ou
; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: flat_store_short v[0:1], v2
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_or_b32_e32 v2, v4, v3
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: flat_store_dword v[0:1], v2
; CI-NEXT: s_endpgm
@@ -2638,14 +2640,14 @@ define amdgpu_kernel void @global_truncstore_v3f32_to_v3f16(ptr addrspace(1) %ou
; VI-NEXT: s_add_u32 s2, s0, 4
; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: v_cvt_f16_f32_sdwa v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-NEXT: v_cvt_f16_f32_e32 v4, v0
+; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_endpgm
@@ -2910,10 +2912,10 @@ define amdgpu_kernel void @global_truncstore_v16f32_to_v16f16(ptr addrspace(1) %
; CI-NEXT: s_add_u32 s4, s2, 48
; CI-NEXT: s_addc_u32 s5, s3, 0
; CI-NEXT: v_mov_b32_e32 v9, s3
-; CI-NEXT: v_mov_b32_e32 v4, s4
; CI-NEXT: v_mov_b32_e32 v8, s2
; CI-NEXT: s_add_u32 s2, s2, 16
; CI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; CI-NEXT: v_mov_b32_e32 v4, s4
; CI-NEXT: v_mov_b32_e32 v5, s5
; CI-NEXT: s_addc_u32 s3, s3, 0
; CI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -2927,10 +2929,10 @@ define amdgpu_kernel void @global_truncstore_v16f32_to_v16f16(ptr addrspace(1) %
; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_waitcnt vmcnt(2)
; CI-NEXT: v_cvt_f16_f32_e32 v7, v7
; CI-NEXT: v_cvt_f16_f32_e32 v16, v5
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: v_cvt_f16_f32_e32 v6, v6
; CI-NEXT: v_cvt_f16_f32_e32 v17, v4
; CI-NEXT: s_waitcnt vmcnt(1)
@@ -2944,11 +2946,11 @@ define amdgpu_kernel void @global_truncstore_v16f32_to_v16f16(ptr addrspace(1) %
; CI-NEXT: v_cvt_f16_f32_e32 v14, v14
; CI-NEXT: v_cvt_f16_f32_e32 v12, v12
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; CI-NEXT: v_mov_b32_e32 v5, s3
; CI-NEXT: v_lshlrev_b32_e32 v18, 16, v1
; CI-NEXT: v_or_b32_e32 v1, v2, v3
; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; CI-NEXT: v_lshlrev_b32_e32 v7, 16, v16
+; CI-NEXT: v_mov_b32_e32 v5, s3
; CI-NEXT: v_mov_b32_e32 v4, s2
; CI-NEXT: v_or_b32_e32 v0, v0, v18
; CI-NEXT: v_or_b32_e32 v3, v6, v2
@@ -2981,9 +2983,9 @@ define amdgpu_kernel void @global_truncstore_v16f32_to_v16f16(ptr addrspace(1) %
; VI-NEXT: s_add_u32 s4, s2, 48
; VI-NEXT: s_addc_u32 s5, s3, 0
; VI-NEXT: v_mov_b32_e32 v9, s3
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v8, s2
; VI-NEXT: s_add_u32 s2, s2, 16
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: s_addc_u32 s3, s3, 0
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index d42904f29aa59..a99f92f75484c 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -151,8 +151,8 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: ; %bb.5: ; %bb43
; CHECK-NEXT: s_mov_b32 s16, 0
; CHECK-NEXT: s_mov_b32 s17, s16
-; CHECK-NEXT: v_mov_b32_e32 v0, s16
; CHECK-NEXT: v_readlane_b32 s44, v7, 16
+; CHECK-NEXT: v_mov_b32_e32 v0, s16
; CHECK-NEXT: v_mov_b32_e32 v1, s17
; CHECK-NEXT: s_mov_b32 s18, s16
; CHECK-NEXT: s_mov_b32 s19, s16
@@ -203,10 +203,10 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_mov_b32 s16, 0
; CHECK-NEXT: s_mov_b32 s20, s16
; CHECK-NEXT: s_mov_b32 s21, s16
-; CHECK-NEXT: v_mov_b32_e32 v1, s20
; CHECK-NEXT: s_mov_b32 s17, s16
; CHECK-NEXT: s_mov_b32 s18, s16
; CHECK-NEXT: s_mov_b32 s19, s16
+; CHECK-NEXT: v_mov_b32_e32 v1, s20
; CHECK-NEXT: v_mov_b32_e32 v2, s21
; CHECK-NEXT: image_sample_lz v3, v[1:2], s[8:15], s[16:19] dmask:0x1
; CHECK-NEXT: image_sample_lz v4, v[1:2], s[36:43], s[16:19] dmask:0x1
diff --git a/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll b/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
index 3420cb8a44653..562ae98e058c2 100644
--- a/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
@@ -286,11 +286,11 @@ define amdgpu_kernel void @llvm_ubsantrap() {
define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) #0 {
; GFX8V4-LABEL: llvm_amdgcn_queue_ptr:
; GFX8V4: ; %bb.0:
+; GFX8V4-NEXT: s_add_u32 s0, s8, 8
; GFX8V4-NEXT: v_mov_b32_e32 v0, s6
; GFX8V4-NEXT: v_mov_b32_e32 v1, s7
-; GFX8V4-NEXT: s_add_u32 s0, s8, 8
-; GFX8V4-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V4-NEXT: s_addc_u32 s1, s9, 0
+; GFX8V4-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V4-NEXT: s_waitcnt vmcnt(0)
; GFX8V4-NEXT: v_mov_b32_e32 v0, s0
; GFX8V4-NEXT: v_mov_b32_e32 v1, s1
@@ -311,11 +311,11 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) #0 {
;
; GFX8V5-LABEL: llvm_amdgcn_queue_ptr:
; GFX8V5: ; %bb.0:
+; GFX8V5-NEXT: s_add_u32 s0, s8, 8
; GFX8V5-NEXT: v_mov_b32_e32 v0, s6
; GFX8V5-NEXT: v_mov_b32_e32 v1, s7
-; GFX8V5-NEXT: s_add_u32 s0, s8, 8
-; GFX8V5-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V5-NEXT: s_addc_u32 s1, s9, 0
+; GFX8V5-NEXT: flat_load_ubyte v0, v[0:1] glc
; GFX8V5-NEXT: s_waitcnt vmcnt(0)
; GFX8V5-NEXT: v_mov_b32_e32 v0, s0
; GFX8V5-NEXT: v_mov_b32_e32 v1, s1
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
index 9256fa827046b..5a6ee6abf407c 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
@@ -3298,7 +3298,6 @@ define amdgpu_kernel void @insert_neg_offset_sgpr(ptr addrspace(1) %in, ptr addr
; VI-MOVREL-NEXT: s_add_i32 m0, s2, 0xfffffe00
; VI-MOVREL-NEXT: s_add_u32 s2, s0, 48
; VI-MOVREL-NEXT: s_addc_u32 s3, s1, 0
-; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s3
; VI-MOVREL-NEXT: v_mov_b32_e32 v4, 4
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, 5
; VI-MOVREL-NEXT: v_mov_b32_e32 v6, 6
@@ -3311,6 +3310,7 @@ define amdgpu_kernel void @insert_neg_offset_sgpr(ptr addrspace(1) %in, ptr addr
; VI-MOVREL-NEXT: v_mov_b32_e32 v13, 13
; VI-MOVREL-NEXT: v_mov_b32_e32 v14, 14
; VI-MOVREL-NEXT: v_mov_b32_e32 v15, 15
+; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s3
; VI-MOVREL-NEXT: v_mov_b32_e32 v16, s2
; VI-MOVREL-NEXT: s_add_u32 s2, s0, 32
; VI-MOVREL-NEXT: v_movreld_b32_e32 v0, 16
@@ -3384,6 +3384,7 @@ define amdgpu_kernel void @insert_neg_offset_sgpr(ptr addrspace(1) %in, ptr addr
; GFX9-IDXMODE: ; %bb.0: ; %entry
; GFX9-IDXMODE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; GFX9-IDXMODE-NEXT: s_load_dword s2, s[4:5], 0x34
+; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v0, 0
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v1, 1
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v2, 2
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v3, 3
@@ -3399,10 +3400,9 @@ define amdgpu_kernel void @insert_neg_offset_sgpr(ptr addrspace(1) %in, ptr addr
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v13, 13
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v14, 14
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v15, 15
-; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v16, v15
; GFX9-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-IDXMODE-NEXT: s_addk_i32 s2, 0xfe00
+; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v16, v15
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v15, v14
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v14, v13
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v13, v12
@@ -3596,7 +3596,6 @@ define amdgpu_kernel void @insert_neg_offset_sgpr_loadreg(ptr addrspace(1) %in,
; VI-MOVREL-NEXT: s_add_i32 m0, s2, 0xfffffe00
; VI-MOVREL-NEXT: s_add_u32 s2, s0, 48
; VI-MOVREL-NEXT: s_addc_u32 s3, s1, 0
-; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s3
; VI-MOVREL-NEXT: v_mov_b32_e32 v1, s9
; VI-MOVREL-NEXT: v_mov_b32_e32 v2, s10
; VI-MOVREL-NEXT: v_mov_b32_e32 v3, s11
@@ -3612,6 +3611,7 @@ define amdgpu_kernel void @insert_neg_offset_sgpr_loadreg(ptr addrspace(1) %in,
; VI-MOVREL-NEXT: v_mov_b32_e32 v13, s21
; VI-MOVREL-NEXT: v_mov_b32_e32 v14, s22
; VI-MOVREL-NEXT: v_mov_b32_e32 v15, s23
+; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s3
; VI-MOVREL-NEXT: v_mov_b32_e32 v16, s2
; VI-MOVREL-NEXT: s_add_u32 s2, s0, 32
; VI-MOVREL-NEXT: v_movreld_b32_e32 v0, 5
@@ -4114,9 +4114,9 @@ define amdgpu_kernel void @insert_neg_offset_vgpr(ptr addrspace(1) %in, ptr addr
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 6, v12
; VI-NEXT: v_cndmask_b32_e64 v6, 7, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 5, v12
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; VI-NEXT: v_cndmask_b32_e64 v5, 6, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 4, v12
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; VI-NEXT: v_cndmask_b32_e64 v4, 5, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 11, v12
; VI-NEXT: v_cndmask_b32_e64 v11, 12, 33, vcc
@@ -4127,16 +4127,16 @@ define amdgpu_kernel void @insert_neg_offset_vgpr(ptr addrspace(1) %in, ptr addr
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 8, v12
; VI-NEXT: v_cndmask_b32_e64 v8, 9, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 15, v12
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_add_u32 s2, s0, 48
; VI-NEXT: v_cndmask_b32_e64 v15, 16, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 14, v12
-; VI-NEXT: s_addc_u32 s3, s1, 0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_add_u32 s2, s0, 48
; VI-NEXT: v_cndmask_b32_e64 v14, 15, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 13, v12
-; VI-NEXT: v_mov_b32_e32 v17, s3
+; VI-NEXT: s_addc_u32 s3, s1, 0
; VI-NEXT: v_cndmask_b32_e64 v13, 14, 33, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 12, v12
+; VI-NEXT: v_mov_b32_e32 v17, s3
; VI-NEXT: v_mov_b32_e32 v16, s2
; VI-NEXT: s_add_u32 s2, s0, 32
; VI-NEXT: v_cndmask_b32_e64 v12, 13, 33, vcc
@@ -6412,8 +6412,8 @@ define amdgpu_kernel void @insert_w_offset_multiple_in_block(ptr addrspace(1) %o
; GENERIC-NEXT: v_mov_b32_e32 v15, 0x41800000
; GENERIC-NEXT: v_mov_b32_e32 v32, 0x41880000
; GENERIC-NEXT: v_movreld_b32_e32 v0, v32
-; GENERIC-NEXT: v_mov_b32_e32 v31, v15
; GENERIC-NEXT: s_add_i32 m0, s2, 2
+; GENERIC-NEXT: v_mov_b32_e32 v31, v15
; GENERIC-NEXT: v_mov_b32_e32 v30, v14
; GENERIC-NEXT: v_mov_b32_e32 v29, v13
; GENERIC-NEXT: v_mov_b32_e32 v28, v12
@@ -6658,8 +6658,8 @@ define amdgpu_kernel void @insert_w_offset_multiple_in_block(ptr addrspace(1) %o
; SI-MOVREL-NEXT: v_mov_b32_e32 v15, 0x41800000
; SI-MOVREL-NEXT: v_mov_b32_e32 v32, 0x41880000
; SI-MOVREL-NEXT: v_movreld_b32_e32 v0, v32
-; SI-MOVREL-NEXT: v_mov_b32_e32 v31, v15
; SI-MOVREL-NEXT: s_add_i32 m0, s2, 2
+; SI-MOVREL-NEXT: v_mov_b32_e32 v31, v15
; SI-MOVREL-NEXT: v_mov_b32_e32 v30, v14
; SI-MOVREL-NEXT: v_mov_b32_e32 v29, v13
; SI-MOVREL-NEXT: v_mov_b32_e32 v28, v12
@@ -6713,8 +6713,8 @@ define amdgpu_kernel void @insert_w_offset_multiple_in_block(ptr addrspace(1) %o
; VI-MOVREL-NEXT: v_mov_b32_e32 v32, 0x41880000
; VI-MOVREL-NEXT: v_movreld_b32_e32 v0, v32
; VI-MOVREL-NEXT: s_add_i32 m0, s2, 2
-; VI-MOVREL-NEXT: v_mov_b32_e32 v31, v15
; VI-MOVREL-NEXT: s_add_u32 s2, s0, 48
+; VI-MOVREL-NEXT: v_mov_b32_e32 v31, v15
; VI-MOVREL-NEXT: v_mov_b32_e32 v30, v14
; VI-MOVREL-NEXT: v_mov_b32_e32 v29, v13
; VI-MOVREL-NEXT: v_mov_b32_e32 v28, v12
@@ -6747,23 +6747,24 @@ define amdgpu_kernel void @insert_w_offset_multiple_in_block(ptr addrspace(1) %o
; VI-MOVREL-NEXT: v_mov_b32_e32 v9, s3
; VI-MOVREL-NEXT: v_mov_b32_e32 v8, s2
; VI-MOVREL-NEXT: s_add_u32 s2, s0, 64
-; VI-MOVREL-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; VI-MOVREL-NEXT: s_addc_u32 s3, s1, 0
+; VI-MOVREL-NEXT: s_add_u32 s4, s0, 0x70
+; VI-MOVREL-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; VI-MOVREL-NEXT: s_addc_u32 s5, s1, 0
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, s1
; VI-MOVREL-NEXT: v_mov_b32_e32 v4, s0
-; VI-MOVREL-NEXT: s_add_u32 s4, s0, 0x70
; VI-MOVREL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; VI-MOVREL-NEXT: s_addc_u32 s5, s1, 0
+; VI-MOVREL-NEXT: s_nop 0
; VI-MOVREL-NEXT: v_mov_b32_e32 v0, s4
; VI-MOVREL-NEXT: v_mov_b32_e32 v1, s5
; VI-MOVREL-NEXT: s_add_u32 s4, s0, 0x60
-; VI-MOVREL-NEXT: flat_store_dwordx4 v[0:1], v[28:31]
; VI-MOVREL-NEXT: s_addc_u32 s5, s1, 0
+; VI-MOVREL-NEXT: s_add_u32 s0, s0, 0x50
+; VI-MOVREL-NEXT: flat_store_dwordx4 v[0:1], v[28:31]
; VI-MOVREL-NEXT: v_mov_b32_e32 v0, s4
; VI-MOVREL-NEXT: v_mov_b32_e32 v1, s5
-; VI-MOVREL-NEXT: s_add_u32 s0, s0, 0x50
-; VI-MOVREL-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
; VI-MOVREL-NEXT: s_addc_u32 s1, s1, 0
+; VI-MOVREL-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
; VI-MOVREL-NEXT: v_mov_b32_e32 v0, s0
; VI-MOVREL-NEXT: v_mov_b32_e32 v1, s1
; VI-MOVREL-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
@@ -6798,8 +6799,8 @@ define amdgpu_kernel void @insert_w_offset_multiple_in_block(ptr addrspace(1) %o
; VI-IDXMODE-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, v32
; VI-IDXMODE-NEXT: s_set_gpr_idx_off
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v31, v15
; VI-IDXMODE-NEXT: s_add_i32 s2, s2, 2
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v31, v15
; VI-IDXMODE-NEXT: v_mov_b32_e32 v30, v14
; VI-IDXMODE-NEXT: v_mov_b32_e32 v29, v13
; VI-IDXMODE-NEXT: v_mov_b32_e32 v28, v12
@@ -6835,23 +6836,24 @@ define amdgpu_kernel void @insert_w_offset_multiple_in_block(ptr addrspace(1) %o
; VI-IDXMODE-NEXT: v_mov_b32_e32 v9, s3
; VI-IDXMODE-NEXT: v_mov_b32_e32 v8, s2
; VI-IDXMODE-NEXT: s_add_u32 s2, s0, 64
-; VI-IDXMODE-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; VI-IDXMODE-NEXT: s_addc_u32 s3, s1, 0
+; VI-IDXMODE-NEXT: s_add_u32 s4, s0, 0x70
+; VI-IDXMODE-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; VI-IDXMODE-NEXT: s_addc_u32 s5, s1, 0
; VI-IDXMODE-NEXT: v_mov_b32_e32 v5, s1
; VI-IDXMODE-NEXT: v_mov_b32_e32 v4, s0
-; VI-IDXMODE-NEXT: s_add_u32 s4, s0, 0x70
; VI-IDXMODE-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; VI-IDXMODE-NEXT: s_addc_u32 s5, s1, 0
+; VI-IDXMODE-NEXT: s_nop 0
; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s4
; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s5
; VI-IDXMODE-NEXT: s_add_u32 s4, s0, 0x60
-; VI-IDXMODE-NEXT: flat_store_dwordx4 v[0:1], v[28:31]
; VI-IDXMODE-NEXT: s_addc_u32 s5, s1, 0
+; VI-IDXMODE-NEXT: s_add_u32 s0, s0, 0x50
+; VI-IDXMODE-NEXT: flat_store_dwordx4 v[0:1], v[28:31]
; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s4
; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s5
-; VI-IDXMODE-NEXT: s_add_u32 s0, s0, 0x50
-; VI-IDXMODE-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
; VI-IDXMODE-NEXT: s_addc_u32 s1, s1, 0
+; VI-IDXMODE-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s0
; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s1
; VI-IDXMODE-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
@@ -6886,8 +6888,8 @@ define amdgpu_kernel void @insert_w_offset_multiple_in_block(ptr addrspace(1) %o
; GFX9-IDXMODE-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v0, v32
; GFX9-IDXMODE-NEXT: s_set_gpr_idx_off
-; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v31, v15
; GFX9-IDXMODE-NEXT: s_add_i32 s2, s2, 2
+; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v31, v15
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v30, v14
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v29, v13
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v28, v12
@@ -7808,10 +7810,10 @@ define amdgpu_kernel void @extract_largest_inbounds_offset(ptr addrspace(1) %out
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, s5
; VI-MOVREL-NEXT: s_add_u32 s4, s2, 32
; VI-MOVREL-NEXT: s_addc_u32 s5, s3, 0
+; VI-MOVREL-NEXT: s_add_u32 s2, s2, 16
; VI-MOVREL-NEXT: flat_load_dwordx4 v[12:15], v[4:5] glc
; VI-MOVREL-NEXT: s_waitcnt vmcnt(0)
; VI-MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; VI-MOVREL-NEXT: s_add_u32 s2, s2, 16
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, s5
; VI-MOVREL-NEXT: s_addc_u32 s3, s3, 0
; VI-MOVREL-NEXT: flat_load_dwordx4 v[8:11], v[4:5] glc
@@ -7835,17 +7837,17 @@ define amdgpu_kernel void @extract_largest_inbounds_offset(ptr addrspace(1) %out
; VI-IDXMODE-NEXT: s_add_u32 s4, s2, 48
; VI-IDXMODE-NEXT: s_addc_u32 s5, s3, 0
; VI-IDXMODE-NEXT: v_mov_b32_e32 v4, s4
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s2
; VI-IDXMODE-NEXT: v_mov_b32_e32 v5, s5
; VI-IDXMODE-NEXT: s_add_u32 s4, s2, 32
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s3
; VI-IDXMODE-NEXT: s_addc_u32 s5, s3, 0
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s2
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s3
+; VI-IDXMODE-NEXT: s_add_u32 s2, s2, 16
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[12:15], v[4:5] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
; VI-IDXMODE-NEXT: v_mov_b32_e32 v4, s4
-; VI-IDXMODE-NEXT: s_add_u32 s2, s2, 16
; VI-IDXMODE-NEXT: v_mov_b32_e32 v5, s5
; VI-IDXMODE-NEXT: s_addc_u32 s3, s3, 0
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[8:11], v[4:5] glc
@@ -8071,10 +8073,10 @@ define amdgpu_kernel void @extract_out_of_bounds_offset(ptr addrspace(1) %out, p
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, s5
; VI-MOVREL-NEXT: s_add_u32 s4, s2, 32
; VI-MOVREL-NEXT: s_addc_u32 s5, s3, 0
+; VI-MOVREL-NEXT: s_add_u32 s2, s2, 16
; VI-MOVREL-NEXT: flat_load_dwordx4 v[12:15], v[4:5] glc
; VI-MOVREL-NEXT: s_waitcnt vmcnt(0)
; VI-MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; VI-MOVREL-NEXT: s_add_u32 s2, s2, 16
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, s5
; VI-MOVREL-NEXT: s_addc_u32 s3, s3, 0
; VI-MOVREL-NEXT: flat_load_dwordx4 v[8:11], v[4:5] glc
@@ -8098,17 +8100,17 @@ define amdgpu_kernel void @extract_out_of_bounds_offset(ptr addrspace(1) %out, p
; VI-IDXMODE-NEXT: s_add_u32 s4, s2, 48
; VI-IDXMODE-NEXT: s_addc_u32 s5, s3, 0
; VI-IDXMODE-NEXT: v_mov_b32_e32 v4, s4
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s2
; VI-IDXMODE-NEXT: v_mov_b32_e32 v5, s5
; VI-IDXMODE-NEXT: s_add_u32 s4, s2, 32
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s3
; VI-IDXMODE-NEXT: s_addc_u32 s5, s3, 0
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s2
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s3
+; VI-IDXMODE-NEXT: s_add_u32 s2, s2, 16
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[12:15], v[4:5] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
; VI-IDXMODE-NEXT: v_mov_b32_e32 v4, s4
-; VI-IDXMODE-NEXT: s_add_u32 s2, s2, 16
; VI-IDXMODE-NEXT: v_mov_b32_e32 v5, s5
; VI-IDXMODE-NEXT: s_addc_u32 s3, s3, 0
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[8:11], v[4:5] glc
@@ -8334,10 +8336,10 @@ define amdgpu_kernel void @extractelement_v16i32_or_index(ptr addrspace(1) %out,
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, s5
; VI-MOVREL-NEXT: s_add_u32 s4, s2, 32
; VI-MOVREL-NEXT: s_addc_u32 s5, s3, 0
+; VI-MOVREL-NEXT: s_add_u32 s2, s2, 16
; VI-MOVREL-NEXT: flat_load_dwordx4 v[12:15], v[4:5] glc
; VI-MOVREL-NEXT: s_waitcnt vmcnt(0)
; VI-MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; VI-MOVREL-NEXT: s_add_u32 s2, s2, 16
; VI-MOVREL-NEXT: v_mov_b32_e32 v5, s5
; VI-MOVREL-NEXT: s_addc_u32 s3, s3, 0
; VI-MOVREL-NEXT: flat_load_dwordx4 v[8:11], v[4:5] glc
@@ -8361,17 +8363,17 @@ define amdgpu_kernel void @extractelement_v16i32_or_index(ptr addrspace(1) %out,
; VI-IDXMODE-NEXT: s_add_u32 s4, s2, 48
; VI-IDXMODE-NEXT: s_addc_u32 s5, s3, 0
; VI-IDXMODE-NEXT: v_mov_b32_e32 v4, s4
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s2
; VI-IDXMODE-NEXT: v_mov_b32_e32 v5, s5
; VI-IDXMODE-NEXT: s_add_u32 s4, s2, 32
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s3
; VI-IDXMODE-NEXT: s_addc_u32 s5, s3, 0
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, s2
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, s3
+; VI-IDXMODE-NEXT: s_add_u32 s2, s2, 16
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[0:3], v[0:1] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[12:15], v[4:5] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
; VI-IDXMODE-NEXT: v_mov_b32_e32 v4, s4
-; VI-IDXMODE-NEXT: s_add_u32 s2, s2, 16
; VI-IDXMODE-NEXT: v_mov_b32_e32 v5, s5
; VI-IDXMODE-NEXT: s_addc_u32 s3, s3, 0
; VI-IDXMODE-NEXT: flat_load_dwordx4 v[8:11], v[4:5] glc
diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
index 4a4298fdfe074..2f571cc39cde3 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
@@ -13,7 +13,7 @@ define amdgpu_kernel void @widget(ptr addrspace(1) %arg, i1 %arg1) #0 {
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $sgpr8_sgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr17
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $sgpr22_sgpr23 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr20_sgpr21_sgpr22_sgpr23
+ ; CHECK-NEXT: $sgpr22_sgpr23 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr20_sgpr21 = S_MOV_B64 killed $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: renamable $sgpr2 = S_LOAD_DWORD_IMM renamable $sgpr8_sgpr9, 8, 0 :: (dereferenceable invariant load (s32) from %ir.arg1.kernarg.offset.align.down, align 8, addrspace 4)
; CHECK-NEXT: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr8_sgpr9, 0, 0 :: (dereferenceable invariant load (s64) from %ir.arg.kernarg.offset1, align 16, addrspace 4)
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
index 9e42a6eda9427..5bd8fdae74bc6 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
@@ -24,8 +24,8 @@ define amdgpu_kernel void @float4_inselt(ptr addrspace(1) %out, <4 x float> %vec
; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v5, s5
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm
@@ -115,11 +115,11 @@ define amdgpu_kernel void @int4_inselt(ptr addrspace(1) %out, <4 x i32> %vec, i3
; GCN-NEXT: s_cselect_b32 s1, s1, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 0
; GCN-NEXT: s_cselect_b32 s0, s0, 1
-; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v5, s5
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm
@@ -166,8 +166,8 @@ define amdgpu_kernel void @float2_inselt(ptr addrspace(1) %out, <2 x float> %vec
; GCN-NEXT: v_cndmask_b32_e32 v1, 1.0, v0, vcc
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
+; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_mov_b32_e32 v3, s5
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GCN-NEXT: s_endpgm
@@ -210,7 +210,6 @@ define amdgpu_kernel void @float8_inselt(ptr addrspace(1) %out, <8 x float> %vec
; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: s_mov_b32 m0, s2
; GCN-NEXT: s_add_u32 s2, s0, 16
-; GCN-NEXT: s_addc_u32 s3, s1, 0
; GCN-NEXT: v_mov_b32_e32 v1, s9
; GCN-NEXT: v_mov_b32_e32 v2, s10
; GCN-NEXT: v_mov_b32_e32 v3, s11
@@ -218,8 +217,9 @@ define amdgpu_kernel void @float8_inselt(ptr addrspace(1) %out, <8 x float> %vec
; GCN-NEXT: v_mov_b32_e32 v5, s13
; GCN-NEXT: v_mov_b32_e32 v6, s14
; GCN-NEXT: v_mov_b32_e32 v7, s15
-; GCN-NEXT: v_mov_b32_e32 v9, s3
+; GCN-NEXT: s_addc_u32 s3, s1, 0
; GCN-NEXT: v_movreld_b32_e32 v0, 1.0
+; GCN-NEXT: v_mov_b32_e32 v9, s3
; GCN-NEXT: v_mov_b32_e32 v8, s2
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCN-NEXT: s_nop 0
@@ -299,7 +299,6 @@ define amdgpu_kernel void @float16_inselt(ptr addrspace(1) %out, <16 x float> %v
; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: s_add_u32 s2, s0, 48
; GCN-NEXT: s_addc_u32 s3, s1, 0
-; GCN-NEXT: v_mov_b32_e32 v17, s3
; GCN-NEXT: v_mov_b32_e32 v1, s9
; GCN-NEXT: v_mov_b32_e32 v2, s10
; GCN-NEXT: v_mov_b32_e32 v3, s11
@@ -316,6 +315,7 @@ define amdgpu_kernel void @float16_inselt(ptr addrspace(1) %out, <16 x float> %v
; GCN-NEXT: v_mov_b32_e32 v14, s22
; GCN-NEXT: v_mov_b32_e32 v15, s23
; GCN-NEXT: s_mov_b32 m0, s4
+; GCN-NEXT: v_mov_b32_e32 v17, s3
; GCN-NEXT: v_mov_b32_e32 v16, s2
; GCN-NEXT: s_add_u32 s2, s0, 32
; GCN-NEXT: v_movreld_b32_e32 v0, 1.0
@@ -457,7 +457,6 @@ define amdgpu_kernel void @float32_inselt(ptr addrspace(1) %out, <32 x float> %v
; GCN-NEXT: s_mov_b32 m0, s2
; GCN-NEXT: s_add_u32 s2, s0, 0x70
; GCN-NEXT: s_addc_u32 s3, s1, 0
-; GCN-NEXT: v_mov_b32_e32 v33, s3
; GCN-NEXT: v_mov_b32_e32 v1, s37
; GCN-NEXT: v_mov_b32_e32 v2, s38
; GCN-NEXT: v_mov_b32_e32 v3, s39
@@ -489,6 +488,7 @@ define amdgpu_kernel void @float32_inselt(ptr addrspace(1) %out, <32 x float> %v
; GCN-NEXT: v_mov_b32_e32 v29, s21
; GCN-NEXT: v_mov_b32_e32 v30, s22
; GCN-NEXT: v_mov_b32_e32 v31, s23
+; GCN-NEXT: v_mov_b32_e32 v33, s3
; GCN-NEXT: v_mov_b32_e32 v32, s2
; GCN-NEXT: s_add_u32 s2, s0, 0x60
; GCN-NEXT: v_movreld_b32_e32 v0, 1.0
@@ -826,8 +826,8 @@ define amdgpu_kernel void @half4_inselt(ptr addrspace(1) %out, <4 x half> %vec,
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GCN-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NEXT: s_endpgm
@@ -1094,8 +1094,8 @@ define amdgpu_kernel void @short4_inselt(ptr addrspace(1) %out, <4 x i16> %vec,
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GCN-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NEXT: s_endpgm
@@ -1148,8 +1148,8 @@ define amdgpu_kernel void @byte8_inselt(ptr addrspace(1) %out, <8 x i8> %vec, i3
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GCN-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NEXT: s_endpgm
@@ -1550,11 +1550,11 @@ define amdgpu_kernel void @byte16_inselt(ptr addrspace(1) %out, <16 x i8> %vec,
; GCN-NEXT: s_or_b32 s0, s0, s8
; GCN-NEXT: s_and_b32 s0, s0, 0xffff
; GCN-NEXT: s_or_b32 s0, s0, s7
-; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v5, s5
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm
@@ -2070,11 +2070,11 @@ define amdgpu_kernel void @double2_inselt(ptr addrspace(1) %out, <2 x double> %v
; GCN-NEXT: s_cmp_eq_u32 s6, 0
; GCN-NEXT: s_cselect_b32 s1, 0x3ff00000, s1
; GCN-NEXT: s_cselect_b32 s0, 0, s0
-; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NEXT: v_mov_b32_e32 v4, s4
; GCN-NEXT: v_mov_b32_e32 v5, s5
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm
@@ -2145,13 +2145,13 @@ define amdgpu_kernel void @double5_inselt(ptr addrspace(1) %out, <5 x double> %v
; GCN-NEXT: s_add_u32 s0, s10, 16
; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: s_addc_u32 s1, s11, 0
-; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NEXT: s_add_u32 s0, s10, 32
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: v_mov_b32_e32 v4, s10
-; GCN-NEXT: s_add_u32 s0, s10, 32
; GCN-NEXT: v_mov_b32_e32 v0, s14
; GCN-NEXT: v_mov_b32_e32 v1, s13
; GCN-NEXT: v_mov_b32_e32 v2, s2
@@ -2160,9 +2160,9 @@ define amdgpu_kernel void @double5_inselt(ptr addrspace(1) %out, <5 x double> %v
; GCN-NEXT: s_addc_u32 s1, s11, 0
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_nop 0
-; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: v_mov_b32_e32 v1, s9
+; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GCN-NEXT: s_endpgm
@@ -2550,17 +2550,18 @@ define amdgpu_kernel void @double7_inselt(ptr addrspace(1) %out, <7 x double> %v
; GCN-NEXT: s_addc_u32 s1, s7, 0
; GCN-NEXT: v_mov_b32_e32 v15, s1
; GCN-NEXT: v_mov_b32_e32 v14, s0
-; GCN-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
; GCN-NEXT: s_add_u32 s0, s6, 48
+; GCN-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
+; GCN-NEXT: s_addc_u32 s1, s7, 0
; GCN-NEXT: v_mov_b32_e32 v4, s6
; GCN-NEXT: v_mov_b32_e32 v5, s7
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NEXT: s_addc_u32 s1, s7, 0
+; GCN-NEXT: s_nop 0
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: s_add_u32 s0, s6, 32
-; GCN-NEXT: flat_store_dwordx2 v[0:1], v[12:13]
; GCN-NEXT: s_addc_u32 s1, s7, 0
+; GCN-NEXT: flat_store_dwordx2 v[0:1], v[12:13]
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
@@ -3254,17 +3255,18 @@ define amdgpu_kernel void @double15_inselt(ptr addrspace(1) %out, <15 x double>
; GCN-NEXT: s_nop 0
; GCN-NEXT: v_mov_b32_e32 v9, s3
; GCN-NEXT: v_mov_b32_e32 v8, s2
-; GCN-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCN-NEXT: s_add_u32 s2, s0, 0x70
+; GCN-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GCN-NEXT: s_nop 0
; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NEXT: s_add_u32 s0, s0, 0x60
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NEXT: s_add_u32 s0, s0, 0x60
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[28:29]
-; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
@@ -4843,9 +4845,9 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_readlane_b32 s0, v6, 0
; GCN-NEXT: v_readlane_b32 s1, v6, 1
-; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
index 9a94ec60de87f..49101a68bae70 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
@@ -1984,10 +1984,10 @@ define amdgpu_kernel void @insert_split_bb(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_load_dword s5, s[2:3], 0x0
; SI-NEXT: .LBB42_5: ; %endif
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_mov_b32 s3, 0x100f000
; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
@@ -2014,10 +2014,10 @@ define amdgpu_kernel void @insert_split_bb(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dword s5, s[2:3], 0x0
; VI-NEXT: .LBB42_5: ; %endif
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b32 s3, 0x1100f000
; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll b/llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
index 300124848c1aa..cb9b6888d1fbc 100644
--- a/llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
+++ b/llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
@@ -40,10 +40,10 @@ define amdgpu_gfx [13 x i32] @issue130120() {
; CHECK-NEXT: s_mov_b32 s50, s48
; CHECK-NEXT: s_cselect_b32 s51, 0, s1
; CHECK-NEXT: s_cselect_b32 s55, 0, s35
-; CHECK-NEXT: v_dual_mov_b32 v2, s48 :: v_dual_mov_b32 v3, s49
; CHECK-NEXT: s_cselect_b32 s52, 0, s2
; CHECK-NEXT: s_cselect_b32 s56, 0, s36
; CHECK-NEXT: s_cselect_b32 vcc_lo, 0, s43
+; CHECK-NEXT: v_dual_mov_b32 v2, s48 :: v_dual_mov_b32 v3, s49
; CHECK-NEXT: v_mov_b32_e32 v4, s50
; CHECK-NEXT: s_cselect_b32 s47, s45, 0xf0
; CHECK-NEXT: s_cselect_b32 s53, 0, s3
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index 4bc09f2c9abe5..ad89c3a0638d0 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -682,9 +682,9 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v4, v0
; GISEL-NEXT: v_mov_b32_e32 v5, v1
-; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_or_b32_e32 v0, v4, v2
; GISEL-NEXT: v_or_b32_e32 v1, v5, v3
+; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_mov_b32_e32 v0, s4
; GISEL-NEXT: v_mov_b32_e32 v1, s5
@@ -975,9 +975,9 @@ define double @uitofp_i128_to_f64(i128 %x) {
; GISEL-LABEL: uitofp_i128_to_f64:
; GISEL: ; %bb.0: ; %itofp-entry
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_or_b32_e32 v4, v0, v2
; GISEL-NEXT: v_or_b32_e32 v5, v1, v3
+; GISEL-NEXT: s_mov_b64 s[4:5], 0
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GISEL-NEXT: v_mov_b32_e32 v4, s4
; GISEL-NEXT: v_mov_b32_e32 v5, s5
@@ -1067,8 +1067,8 @@ define double @uitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: s_cbranch_execz .LBB3_9
; GISEL-NEXT: ; %bb.8: ; %itofp-sw-bb
-; GISEL-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1]
; GISEL-NEXT: v_lshlrev_b64 v[10:11], 1, v[2:3]
+; GISEL-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1]
; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GISEL-NEXT: v_or_b32_e32 v10, v10, v0
; GISEL-NEXT: v_mov_b32_e32 v0, v8
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
index 6fdc636020df5..312336b817d7d 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
@@ -722,9 +722,9 @@ define amdgpu_kernel void @v2i32_arg(ptr addrspace(1) nocapture %out, <2 x i32>
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
@@ -734,8 +734,8 @@ define amdgpu_kernel void @v2i32_arg(ptr addrspace(1) nocapture %out, <2 x i32>
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
@@ -785,9 +785,9 @@ define amdgpu_kernel void @v2f32_arg(ptr addrspace(1) nocapture %out, <2 x float
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
@@ -797,8 +797,8 @@ define amdgpu_kernel void @v2f32_arg(ptr addrspace(1) nocapture %out, <2 x float
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
@@ -866,8 +866,8 @@ define amdgpu_kernel void @v3i8_arg(ptr addrspace(1) nocapture %out, <3 x i8> %i
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_add_u32 s0, s0, 2
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v5, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_byte v[2:3], v5
@@ -1002,10 +1002,10 @@ define amdgpu_kernel void @v3i16_arg(ptr addrspace(1) nocapture %out, <3 x i16>
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s4, s0, 4
; VI-NEXT: s_addc_u32 s5, s1, 0
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v4, s3
-; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v5, s2
; VI-NEXT: flat_store_short v[2:3], v4
@@ -1121,9 +1121,9 @@ define amdgpu_kernel void @v3i32_arg(ptr addrspace(1) nocapture %out, <3 x i32>
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-NEXT: s_endpgm
@@ -1196,9 +1196,9 @@ define amdgpu_kernel void @v3f32_arg(ptr addrspace(1) nocapture %out, <3 x float
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-NEXT: s_endpgm
@@ -1315,9 +1315,9 @@ define amdgpu_kernel void @v4i16_arg(ptr addrspace(1) %out, <4 x i16> %in) {
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
@@ -1327,8 +1327,8 @@ define amdgpu_kernel void @v4i16_arg(ptr addrspace(1) %out, <4 x i16> %in) {
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
@@ -1392,8 +1392,8 @@ define amdgpu_kernel void @v4i32_arg(ptr addrspace(1) nocapture %out, <4 x i32>
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
@@ -1466,8 +1466,8 @@ define amdgpu_kernel void @v4f32_arg(ptr addrspace(1) nocapture %out, <4 x float
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
@@ -1541,10 +1541,10 @@ define amdgpu_kernel void @v5i8_arg(ptr addrspace(1) nocapture %out, <5 x i8> %i
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s4, s0, 4
; VI-NEXT: s_addc_u32 s5, s1, 0
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v4, s3
-; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v5, s2
; VI-NEXT: flat_store_byte v[2:3], v4
@@ -1685,13 +1685,13 @@ define amdgpu_kernel void @v5i16_arg(ptr addrspace(1) nocapture %out, <5 x i16>
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s4, s0, 8
; VI-NEXT: s_addc_u32 s5, s1, 0
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v4, s6
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_short v[2:3], v4
; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
@@ -1918,13 +1918,13 @@ define amdgpu_kernel void @v5i32_arg(ptr addrspace(1) nocapture %out, <5 x i32>
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s4, s6, 16
; VI-NEXT: s_addc_u32 s5, s7, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v2, s8
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v4, s6
+; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
@@ -2012,15 +2012,15 @@ define amdgpu_kernel void @v5f32_arg(ptr addrspace(1) nocapture %out, <5 x float
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s4, s6, 16
; VI-NEXT: s_addc_u32 s5, s7, 0
-; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v3, s8
+; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
-; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: flat_store_dword v[1:2], v3
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -2113,19 +2113,19 @@ define amdgpu_kernel void @v5i64_arg(ptr addrspace(1) nocapture %out, <5 x i64>
; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x64
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s12, s8, 32
-; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: s_addc_u32 s13, s9, 0
-; VI-NEXT: v_mov_b32_e32 v3, s12
+; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_mov_b32_e32 v2, s11
; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_mov_b32_e32 v4, s13
; VI-NEXT: s_add_u32 s4, s8, 16
; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_addc_u32 s5, s9, 0
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_mov_b32_e32 v4, s8
@@ -2248,19 +2248,19 @@ define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture %out, <5 x doubl
; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x64
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_add_u32 s12, s8, 32
-; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: s_addc_u32 s13, s9, 0
-; VI-NEXT: v_mov_b32_e32 v3, s12
+; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_mov_b32_e32 v2, s11
; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_mov_b32_e32 v4, s13
; VI-NEXT: s_add_u32 s4, s8, 16
; VI-NEXT: flat_store_dwordx2 v[3:4], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_addc_u32 s5, s9, 0
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_mov_b32_e32 v4, s8
@@ -2358,9 +2358,9 @@ define amdgpu_kernel void @v8i8_arg(ptr addrspace(1) %out, <8 x i8> %in) {
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
@@ -2370,8 +2370,8 @@ define amdgpu_kernel void @v8i8_arg(ptr addrspace(1) %out, <8 x i8> %in) {
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
@@ -2623,8 +2623,8 @@ define amdgpu_kernel void @v8i16_arg(ptr addrspace(1) %out, <8 x i16> %in) {
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
@@ -2879,10 +2879,10 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture %out, <8 x i32>
; VI-NEXT: v_mov_b32_e32 v0, s12
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_mov_b32_e32 v2, s14
; VI-NEXT: v_mov_b32_e32 v3, s15
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_mov_b32_e32 v5, s1
@@ -2986,10 +2986,10 @@ define amdgpu_kernel void @v8f32_arg(ptr addrspace(1) nocapture %out, <8 x float
; VI-NEXT: v_mov_b32_e32 v0, s12
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_mov_b32_e32 v2, s14
; VI-NEXT: v_mov_b32_e32 v3, s15
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_mov_b32_e32 v5, s1
@@ -3086,8 +3086,8 @@ define amdgpu_kernel void @v16i8_arg(ptr addrspace(1) %out, <16 x i8> %in) {
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v5, s7
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
@@ -3544,10 +3544,10 @@ define amdgpu_kernel void @v16i16_arg(ptr addrspace(1) %out, <16 x i16> %in) {
; VI-NEXT: v_mov_b32_e32 v0, s12
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: s_addc_u32 s3, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_mov_b32_e32 v2, s14
; VI-NEXT: v_mov_b32_e32 v3, s15
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_mov_b32_e32 v5, s1
@@ -4485,10 +4485,10 @@ define amdgpu_kernel void @i65_arg(ptr addrspace(1) nocapture %out, i65 %in) nou
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_add_u32 s0, s0, 8
; VI-NEXT: s_addc_u32 s1, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v6, s4
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_byte v[4:5], v6
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -4501,8 +4501,8 @@ define amdgpu_kernel void @i65_arg(ptr addrspace(1) nocapture %out, i65 %in) nou
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s4, s4, 1
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_store_byte v2, v3, s[0:1] offset:8
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -4759,8 +4759,8 @@ define amdgpu_kernel void @i1_arg_zext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_and_b32 s2, s2, 1
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -4909,8 +4909,8 @@ define amdgpu_kernel void @i1_arg_sext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x10000
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
@@ -5033,10 +5033,10 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32,
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -5058,10 +5058,10 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32,
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -5176,11 +5176,11 @@ define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0,
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: s_add_u32 s0, s4, 51
-; VI-NEXT: s_addc_u32 s1, s5, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: s_addc_u32 s1, s5, 0
; VI-NEXT: v_mov_b32_e32 v6, s0
+; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: flat_load_ubyte v8, v[0:1]
; VI-NEXT: flat_load_ubyte v9, v[2:3]
; VI-NEXT: flat_load_ubyte v10, v[4:5]
@@ -5622,8 +5622,8 @@ define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) {
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: s_add_u32 s0, s4, 42
; VI-NEXT: s_addc_u32 s1, s5, 0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_load_ushort v4, v[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
index 50e7a3a322e09..4a3a1b481af69 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
@@ -142,8 +142,8 @@ define amdgpu_kernel void @v5i32_arg(<5 x i32> %in) nounwind {
; GCN-NEXT: v_mov_b32_e32 v6, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v8, s4
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v7, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -165,8 +165,8 @@ define amdgpu_kernel void @v6i32_arg(<6 x i32> %in) nounwind {
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v9, s5
; GCN-NEXT: v_mov_b32_e32 v8, s4
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v7, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -185,8 +185,8 @@ define amdgpu_kernel void @i65_arg(ptr addrspace(1) nocapture %out, i65 %in) #0
; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_and_b32 s4, s4, 1
-; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v3, s4
+; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: global_store_byte v2, v3, s[0:1] offset:8
; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -225,10 +225,10 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32,
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: global_store_dword v[0:1], v2, off
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -587,8 +587,8 @@ define amdgpu_kernel void @byref_flat_i32_arg(ptr addrspace(1) nocapture %out, p
; GCN-LABEL: byref_flat_i32_arg:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_u32 flat_scratch_lo, s12, s17
-; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: v_mov_b32_e32 v1, s9
; GCN-NEXT: flat_load_dword v0, v[0:1] offset:8
; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
index 6e58fb9d1853d..9fae66e86994a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
@@ -10908,7 +10908,7 @@ define <4 x float> @global_load_saddr_i8_vgpr64_sgpr32(ptr addrspace(1) %vbase,
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: s_mov_b32 s1, 0
; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1100-ISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1100-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
@@ -11031,7 +11031,7 @@ define <4 x float> @global_load_saddr_i8_vgpr64_sgpr32_offset_4095(ptr addrspace
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: s_mov_b32 s1, 0
; GFX1100-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1100-ISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1100-ISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-ISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
@@ -11180,8 +11180,8 @@ define <4 x float> @global_load_saddr_f32_natural_addressing(ptr addrspace(1) in
; GFX1100-ISEL: ; %bb.0:
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: global_load_b32 v0, v[0:1], off
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1100-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX1100-ISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
@@ -11658,8 +11658,8 @@ define <4 x float> @global_load_f32_saddr_zext_vgpr_range_too_large(ptr addrspac
; GFX1100-ISEL: ; %bb.0:
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-ISEL-NEXT: global_load_b32 v0, v[0:1], off
-; GFX1100-ISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1100-ISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1100-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX1100-ISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX1100-ISEL-NEXT: s_waitcnt vmcnt(0)
; GFX1100-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-ISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
index fd498417a2df8..c418d9e95050a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
@@ -1172,9 +1172,9 @@ define void @global_store_saddr_i8_zext_vgpr_offset_neg2048(ptr addrspace(1) inr
define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, <4 x i32> %data) {
; GFX906-SDAG-LABEL: global_store_saddr_uniform_ptr_in_vgprs:
; GFX906-SDAG: ; %bb.0:
+; GFX906-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX906-SDAG-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX906-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX906-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX906-SDAG-NEXT: ds_read_b64 v[4:5], v0
; GFX906-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX906-SDAG-NEXT: v_mov_b32_e32 v6, s6
@@ -1190,9 +1190,9 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset,
;
; GFX942-SDAG-LABEL: global_store_saddr_uniform_ptr_in_vgprs:
; GFX942-SDAG: ; %bb.0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX942-SDAG-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX942-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX942-SDAG-NEXT: ds_read_b64 v[0:1], v0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s6
@@ -1230,9 +1230,9 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset,
; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX1100-SDAG-NEXT: ds_load_b64 v[4:5], v0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, s6
+; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v1, s1
; GFX1100-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX1100-SDAG-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX1100-SDAG-NEXT: v_mov_b32_e32 v2, s2
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s1, v5
; GFX1100-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1]
@@ -1263,13 +1263,14 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset,
; GFX906-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX906-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX906-ISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX906-ISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX906-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX906-ISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX906-ISEL-NEXT: s_nop 0
; GFX906-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]
; GFX906-ISEL-NEXT: s_endpgm
;
@@ -1280,12 +1281,12 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset,
; GFX942-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX942-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX942-ISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-ISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX942-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX942-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-ISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX942-ISEL-NEXT: s_nop 1
+; GFX942-ISEL-NEXT: s_nop 2
; GFX942-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]
; GFX942-ISEL-NEXT: s_endpgm
;
@@ -1350,9 +1351,9 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset,
define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset, <4 x i32> %data) {
; GFX906-SDAG-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX906-SDAG: ; %bb.0:
+; GFX906-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX906-SDAG-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX906-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX906-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX906-SDAG-NEXT: ds_read_b64 v[4:5], v0
; GFX906-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX906-SDAG-NEXT: v_mov_b32_e32 v6, s6
@@ -1368,9 +1369,9 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32
;
; GFX942-SDAG-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset:
; GFX942-SDAG: ; %bb.0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX942-SDAG-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX942-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX942-SDAG-NEXT: ds_read_b64 v[0:1], v0
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s6
@@ -1408,9 +1409,9 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32
; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
; GFX1100-SDAG-NEXT: ds_load_b64 v[4:5], v0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, s6
+; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v1, s1
; GFX1100-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX1100-SDAG-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX1100-SDAG-NEXT: v_mov_b32_e32 v2, s2
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s1, v5
; GFX1100-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1] offset:-120
@@ -1441,13 +1442,14 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32
; GFX906-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX906-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX906-ISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX906-ISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX906-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX906-ISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX906-ISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX906-ISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX906-ISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX906-ISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX906-ISEL-NEXT: s_nop 0
; GFX906-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5] offset:-120
; GFX906-ISEL-NEXT: s_endpgm
;
@@ -1458,12 +1460,12 @@ define amdgpu_kernel void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32
; GFX942-ISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GFX942-ISEL-NEXT: s_load_dword s6, s[4:5], 0x24
; GFX942-ISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-ISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX942-ISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX942-ISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-ISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-ISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX942-ISEL-NEXT: s_nop 1
+; GFX942-ISEL-NEXT: s_nop 2
; GFX942-ISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5] offset:-120 sc0
; GFX942-ISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
index 373648ace8621..ae478f6b167a3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
@@ -110,18 +110,18 @@ define amdgpu_ps <10 x float> @image_bvh8_intersect_ray_ssssss(i64 inreg %node_p
; GFX12-GISEL-LABEL: image_bvh8_intersect_ray_ssssss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_mov_b32 s16, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s17, s4
; GFX12-GISEL-NEXT: s_mov_b32 s18, s5
; GFX12-GISEL-NEXT: s_mov_b32 s20, s6
-; GFX12-GISEL-NEXT: s_mov_b32 s17, s4
; GFX12-GISEL-NEXT: s_mov_b32 s21, s7
; GFX12-GISEL-NEXT: s_mov_b32 s22, s8
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v15, s17
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v17, s20
; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, v0 :: v_dual_mov_b32 v11, v1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v13, v3
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v15, s17
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v17, s20
; GFX12-GISEL-NEXT: v_dual_mov_b32 v18, s21 :: v_dual_mov_b32 v19, s22
; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s9
; GFX12-GISEL-NEXT: s_mov_b32 s4, s10
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
index ba5ef32de735a..0996a0ebc7a5e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
@@ -231,8 +231,8 @@ define amdgpu_kernel void @s_cvt_pkrtz_undef_undef(ptr addrspace(1) %out) #0 {
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_cvt_pkrtz_f16_f32 v2, s0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
index a5755c8779f77..610d18ca877be 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
@@ -213,21 +213,21 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp8_ss(<2 x i32> inreg %src, i32 i
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp8 v[2:9], v[10:11], s2 scale_sel:8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -280,21 +280,21 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_ss(<2 x i32> inreg %src, i32 i
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_bf8 v[2:9], v[10:11], s2
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -345,21 +345,21 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_ss(i32 inreg %src, i32 inreg %
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp4 v[2:9], v2, s1 scale_sel:1
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -412,21 +412,21 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], s3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -456,21 +456,21 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], 0x64 scale_sel:1
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -554,21 +554,21 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], s3 scale_sel:4
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -598,21 +598,21 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], 0x64 scale_sel:5
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -702,24 +702,24 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v18, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_fp6 v[2:17], v[18:20], s3 scale_sel:5
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v12
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v13
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v10
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v11
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v16
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v17
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v12
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v13
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v14
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v15
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v16
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v17
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
@@ -788,24 +788,24 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v18, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_bf6 v[2:17], v[18:20], s3 scale_sel:6
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v12
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v13
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v10
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v11
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v16
-; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v17
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v12
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v13
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v14
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v15
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v16
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v17
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
index f690e06f495d9..d676c412a943b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
@@ -59,8 +59,8 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_vv(<16 x float> %src, float %s
define amdgpu_ps void @test_scalef32_pk32_fp6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f32_sl:
; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: s_mov_b32 s16, 0x42c80000
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
@@ -86,13 +86,13 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_sl(<16 x float> inreg %src, pt
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_fp6_f32 v[18:23], v[2:17], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -130,8 +130,8 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_vv(<16 x float> %src, float %s
define amdgpu_ps void @test_scalef32_pk32_bf6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f32_sl:
; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: s_mov_b32 s16, 0x42c80000
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
@@ -157,13 +157,13 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_sl(<16 x float> inreg %src, pt
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_bf6_f32 v[18:23], v[2:17], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -1524,13 +1524,13 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_ss(<16 x float> inreg %src, fl
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_fp6_f32 v[18:23], v[2:17], v[2:17], s16
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -1545,8 +1545,8 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_ss(<16 x float> inreg %src, fl
define amdgpu_ps void @test_scalef32_pk32_fp6_f32_sl_inreg_src(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f32_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: s_mov_b32 s16, 0x42c80000
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
@@ -1572,13 +1572,13 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_sl_inreg_src(<16 x float> inre
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_fp6_f32 v[18:23], v[2:17], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -1657,13 +1657,13 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_ss(<16 x float> inreg %src, fl
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_bf6_f32 v[18:23], v[2:17], v[2:17], s16
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -1678,8 +1678,8 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_ss(<16 x float> inreg %src, fl
define amdgpu_ps void @test_scalef32_pk32_bf6_f32_sl_inreg_src(<16 x float> inreg inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f32_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: s_mov_b32 s16, 0x42c80000
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
@@ -1705,13 +1705,13 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_sl_inreg_src(<16 x float> inre
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_bf6_f32 v[18:23], v[2:17], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -2486,8 +2486,8 @@ define <32 x float> @test_cvt_scale_pk32_f32_fp6_inreg_src(<6 x i32> inreg %src,
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v32, v0
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[34:39], v32
@@ -2542,8 +2542,8 @@ define <32 x float> @test_cvt_scale_pk32_f32_bf6_inreg_src(<6 x i32> inreg %src,
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v32, v0
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[34:39], v32
@@ -2598,8 +2598,8 @@ define <32 x half> @test_cvt_scalef32_pk32_f16_fp6_vv_inreg_src(<6 x i32> inreg
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, v0
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f16_fp6 v[0:15], v[18:23], v16
@@ -2717,8 +2717,8 @@ define <32 x half> @test_cvt_scalef32_pk32_f16_bf6_vv_inreg_src(<6 x i32> inreg
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, v0
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f16_bf6 v[0:15], v[18:23], v16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
index eacaf5e1dea41..9f3c420c0d052 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
@@ -144,13 +144,13 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f16_sl(<32 x half> inreg %src, ptr
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -299,13 +299,13 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f16_sl(<32 x half> inreg %src, ptr
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -508,13 +508,13 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f16_ss(<32 x half> inreg %src, flo
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], s16
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -564,13 +564,13 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f16_sl_inreg_src(<32 x half> inreg
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -773,13 +773,13 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f16_ss(<32 x half> inreg %src, flo
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], s16
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
@@ -829,13 +829,13 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f16_sl_inreg_src(<32 x half> inreg
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v24
; GFX950-GISEL-NEXT: s_nop 0
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
-; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX950-GISEL-NEXT: s_nop 1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
index aaa59b68a3e07..b73053e554e1c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
@@ -150,21 +150,21 @@ define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1)
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s4, 0
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s1, 0x3fc00000
; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s7, s4
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s5, s4
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s6, s4
+; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s7, s4
+; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_add_nc_u32 v0, 15, v19
; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v13, s6
-; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_add_nc_u32 v0, 15, v19
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v12, s5 :: v_dual_mov_b32 v11, s4
+; ASM-GISEL-TRUE16-NEXT: global_store_b32 v[17:18], v0, off
+; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr8
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr9_vgpr10
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr15
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr16
-; ASM-GISEL-TRUE16-NEXT: global_store_b32 v[17:18], v0, off
-; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-TRUE16-NEXT: .LBB1_2: ; %if.end
; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -195,21 +195,21 @@ define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1)
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s4, 0
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s1, 0x3fc00000
; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s7, s4
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s5, s4
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s6, s4
+; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s7, s4
+; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_add_nc_u32 v0, 15, v19
; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v13, s6
-; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_add_nc_u32 v0, 15, v19
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v12, s5 :: v_dual_mov_b32 v11, s4
+; ASM-GISEL-FAKE16-NEXT: global_store_b32 v[17:18], v0, off
+; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr6_vgpr7
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr8
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr9_vgpr10
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr15
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr16
-; ASM-GISEL-FAKE16-NEXT: global_store_b32 v[17:18], v0, off
-; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-FAKE16-NEXT: .LBB1_2: ; %if.end
; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
index 7e1ae37fddf17..6e39e35c8b69b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
@@ -75,8 +75,8 @@ define amdgpu_kernel void @ds_bpermute_imm_index(ptr addrspace(1) %out, i32 %bas
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s2
; CHECK-SDAG-NEXT: ds_bpermute_b32 v2, v0, v1 offset:64
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s0
; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s0
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s1
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: flat_store_dword v[0:1], v2
@@ -92,8 +92,8 @@ define amdgpu_kernel void @ds_bpermute_imm_index(ptr addrspace(1) %out, i32 %bas
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s2
; CHECK-GISEL-NEXT: ds_bpermute_b32 v2, v0, v1
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
index 195e72ecaf336..2b06c74e84ca5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
@@ -113,20 +113,20 @@ define amdgpu_ps <10 x float> @image_bvh_dual_intersect_ray_ssssss(i64 inreg %no
; GFX12-GISEL-LABEL: image_bvh_dual_intersect_ray_ssssss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_mov_b32 s16, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s17, s4
; GFX12-GISEL-NEXT: s_mov_b32 s18, s5
; GFX12-GISEL-NEXT: s_mov_b32 s20, s6
-; GFX12-GISEL-NEXT: s_mov_b32 s17, s4
; GFX12-GISEL-NEXT: s_mov_b32 s21, s7
; GFX12-GISEL-NEXT: s_mov_b32 s22, s8
; GFX12-GISEL-NEXT: s_mov_b32 s8, s9
; GFX12-GISEL-NEXT: s_mov_b32 s9, s10
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v15, s17
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v17, s20
; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, v0 :: v_dual_mov_b32 v11, v1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v13, v3
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v15, s17
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v17, s20
; GFX12-GISEL-NEXT: v_dual_mov_b32 v18, s21 :: v_dual_mov_b32 v19, s22
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
; GFX12-GISEL-NEXT: s_mov_b32 s4, s11
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
index 697dc4b12aad8..102a9617e038f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
@@ -57,8 +57,8 @@ define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(ptr addrspace(1) %out, float
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
; VI-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0|
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -70,8 +70,8 @@ define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(ptr addrspace(1) %out, float
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], v0, |s3|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -125,8 +125,8 @@ define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(ptr addrspace(
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
; VI-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -138,8 +138,8 @@ define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(ptr addrspace(
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], |v0|, |s3|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -228,8 +228,8 @@ define amdgpu_kernel void @v_fcmp_f32_oeq(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -242,8 +242,8 @@ define amdgpu_kernel void @v_fcmp_f32_oeq(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -288,8 +288,8 @@ define amdgpu_kernel void @v_fcmp_f32_one(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -302,8 +302,8 @@ define amdgpu_kernel void @v_fcmp_f32_one(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -348,8 +348,8 @@ define amdgpu_kernel void @v_fcmp_f32_ogt(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -362,8 +362,8 @@ define amdgpu_kernel void @v_fcmp_f32_ogt(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -408,8 +408,8 @@ define amdgpu_kernel void @v_fcmp_f32_oge(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -422,8 +422,8 @@ define amdgpu_kernel void @v_fcmp_f32_oge(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -468,8 +468,8 @@ define amdgpu_kernel void @v_fcmp_f32_olt(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -482,8 +482,8 @@ define amdgpu_kernel void @v_fcmp_f32_olt(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -528,8 +528,8 @@ define amdgpu_kernel void @v_fcmp_f32_ole(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -542,8 +542,8 @@ define amdgpu_kernel void @v_fcmp_f32_ole(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -588,8 +588,8 @@ define amdgpu_kernel void @v_fcmp_f32_o(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_o_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -602,8 +602,8 @@ define amdgpu_kernel void @v_fcmp_f32_o(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_o_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -648,8 +648,8 @@ define amdgpu_kernel void @v_fcmp_f32_uo(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_u_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -662,8 +662,8 @@ define amdgpu_kernel void @v_fcmp_f32_uo(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_u_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -708,8 +708,8 @@ define amdgpu_kernel void @v_fcmp_f32_ueq(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -722,8 +722,8 @@ define amdgpu_kernel void @v_fcmp_f32_ueq(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -768,8 +768,8 @@ define amdgpu_kernel void @v_fcmp_f32_une(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -782,8 +782,8 @@ define amdgpu_kernel void @v_fcmp_f32_une(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -828,8 +828,8 @@ define amdgpu_kernel void @v_fcmp_f32_ugt(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -842,8 +842,8 @@ define amdgpu_kernel void @v_fcmp_f32_ugt(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -888,8 +888,8 @@ define amdgpu_kernel void @v_fcmp_f32_uge(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -902,8 +902,8 @@ define amdgpu_kernel void @v_fcmp_f32_uge(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -948,8 +948,8 @@ define amdgpu_kernel void @v_fcmp_f32_ult(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -962,8 +962,8 @@ define amdgpu_kernel void @v_fcmp_f32_ult(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -1008,8 +1008,8 @@ define amdgpu_kernel void @v_fcmp_f32_ule(ptr addrspace(1) %out, float %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -1022,8 +1022,8 @@ define amdgpu_kernel void @v_fcmp_f32_ule(ptr addrspace(1) %out, float %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -1899,8 +1899,8 @@ define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(ptr addrspace(1) %out, half
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
; VI-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |v0|
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -1914,8 +1914,8 @@ define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(ptr addrspace(1) %out, half
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], v0, |s3|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -1980,8 +1980,8 @@ define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(ptr addrspace(
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
; VI-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |v0|
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -1995,8 +1995,8 @@ define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(ptr addrspace(
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], |v0|, |s3|
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2086,8 +2086,8 @@ define amdgpu_kernel void @v_fcmp_f16_oeq(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2100,8 +2100,8 @@ define amdgpu_kernel void @v_fcmp_f16_oeq(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2147,8 +2147,8 @@ define amdgpu_kernel void @v_fcmp_f16_one(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2161,8 +2161,8 @@ define amdgpu_kernel void @v_fcmp_f16_one(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2208,8 +2208,8 @@ define amdgpu_kernel void @v_fcmp_f16_ogt(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2222,8 +2222,8 @@ define amdgpu_kernel void @v_fcmp_f16_ogt(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2269,8 +2269,8 @@ define amdgpu_kernel void @v_fcmp_f16_oge(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2283,8 +2283,8 @@ define amdgpu_kernel void @v_fcmp_f16_oge(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2330,8 +2330,8 @@ define amdgpu_kernel void @v_fcmp_f16_olt(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2344,8 +2344,8 @@ define amdgpu_kernel void @v_fcmp_f16_olt(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2391,8 +2391,8 @@ define amdgpu_kernel void @v_fcmp_f16_ole(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2405,8 +2405,8 @@ define amdgpu_kernel void @v_fcmp_f16_ole(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2452,8 +2452,8 @@ define amdgpu_kernel void @v_fcmp_f16_ueq(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2466,8 +2466,8 @@ define amdgpu_kernel void @v_fcmp_f16_ueq(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2513,8 +2513,8 @@ define amdgpu_kernel void @v_fcmp_f16_une(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2527,8 +2527,8 @@ define amdgpu_kernel void @v_fcmp_f16_une(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2574,8 +2574,8 @@ define amdgpu_kernel void @v_fcmp_f16_ugt(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2588,8 +2588,8 @@ define amdgpu_kernel void @v_fcmp_f16_ugt(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2635,8 +2635,8 @@ define amdgpu_kernel void @v_fcmp_f16_uge(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2649,8 +2649,8 @@ define amdgpu_kernel void @v_fcmp_f16_uge(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2696,8 +2696,8 @@ define amdgpu_kernel void @v_fcmp_f16_ult(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2710,8 +2710,8 @@ define amdgpu_kernel void @v_fcmp_f16_ult(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2756,8 +2756,8 @@ define amdgpu_kernel void @v_fcmp_f16_o(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_o_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2770,8 +2770,8 @@ define amdgpu_kernel void @v_fcmp_f16_o(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_o_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2816,8 +2816,8 @@ define amdgpu_kernel void @v_fcmp_f16_uo(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_u_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2830,8 +2830,8 @@ define amdgpu_kernel void @v_fcmp_f16_uo(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_u_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -2876,8 +2876,8 @@ define amdgpu_kernel void @v_fcmp_f16_ule(ptr addrspace(1) %out, half %src) {
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-SDAG-NEXT: s_endpgm
@@ -2890,8 +2890,8 @@ define amdgpu_kernel void @v_fcmp_f16_ule(ptr addrspace(1) %out, half %src) {
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
index b8a2aa462a4ca..b7c138d4bed09 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
@@ -35,8 +35,8 @@ define amdgpu_kernel void @v_icmp_i32_eq(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_eq_u32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -62,8 +62,8 @@ define amdgpu_kernel void @v_icmp_i32_eq(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_eq_u32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -137,8 +137,8 @@ define amdgpu_kernel void @v_icmp_i32_ne(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -164,8 +164,8 @@ define amdgpu_kernel void @v_icmp_i32_ne(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -197,8 +197,8 @@ define amdgpu_kernel void @v_icmp_i32_ugt(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_gt_u32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -224,8 +224,8 @@ define amdgpu_kernel void @v_icmp_i32_ugt(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_gt_u32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -257,8 +257,8 @@ define amdgpu_kernel void @v_icmp_i32_uge(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ge_u32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -284,8 +284,8 @@ define amdgpu_kernel void @v_icmp_i32_uge(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_ge_u32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -317,8 +317,8 @@ define amdgpu_kernel void @v_icmp_i32_ult(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_lt_u32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -344,8 +344,8 @@ define amdgpu_kernel void @v_icmp_i32_ult(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_lt_u32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -377,8 +377,8 @@ define amdgpu_kernel void @v_icmp_i32_ule(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -404,8 +404,8 @@ define amdgpu_kernel void @v_icmp_i32_ule(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -437,8 +437,8 @@ define amdgpu_kernel void @v_icmp_i32_sgt(ptr addrspace(1) %out, i32 %src) #1 {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_gt_i32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -464,8 +464,8 @@ define amdgpu_kernel void @v_icmp_i32_sgt(ptr addrspace(1) %out, i32 %src) #1 {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_gt_i32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -497,8 +497,8 @@ define amdgpu_kernel void @v_icmp_i32_sge(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ge_i32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -524,8 +524,8 @@ define amdgpu_kernel void @v_icmp_i32_sge(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_ge_i32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -557,8 +557,8 @@ define amdgpu_kernel void @v_icmp_i32_slt(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_lt_i32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -584,8 +584,8 @@ define amdgpu_kernel void @v_icmp_i32_slt(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_lt_i32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -617,8 +617,8 @@ define amdgpu_kernel void @v_icmp_i32_sle(ptr addrspace(1) %out, i32 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_le_i32_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -644,8 +644,8 @@ define amdgpu_kernel void @v_icmp_i32_sle(ptr addrspace(1) %out, i32 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_le_i32_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -675,8 +675,8 @@ define amdgpu_kernel void @v_icmp_i64_eq(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -733,8 +733,8 @@ define amdgpu_kernel void @v_icmp_i64_ne(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -791,8 +791,8 @@ define amdgpu_kernel void @v_icmp_u64_ugt(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -849,8 +849,8 @@ define amdgpu_kernel void @v_icmp_u64_uge(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -907,8 +907,8 @@ define amdgpu_kernel void @v_icmp_u64_ult(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -965,8 +965,8 @@ define amdgpu_kernel void @v_icmp_u64_ule(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -1023,8 +1023,8 @@ define amdgpu_kernel void @v_icmp_i64_sgt(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -1081,8 +1081,8 @@ define amdgpu_kernel void @v_icmp_i64_sge(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -1139,8 +1139,8 @@ define amdgpu_kernel void @v_icmp_i64_slt(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -1197,8 +1197,8 @@ define amdgpu_kernel void @v_icmp_i64_sle(ptr addrspace(1) %out, i64 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SDAG-VI-NEXT: s_endpgm
@@ -1257,8 +1257,8 @@ define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_eq_u16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1284,8 +1284,8 @@ define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_eq_u16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1359,8 +1359,8 @@ define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ne_u16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1386,8 +1386,8 @@ define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_ne_u16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1419,8 +1419,8 @@ define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_gt_u16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1446,8 +1446,8 @@ define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_gt_u16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1479,8 +1479,8 @@ define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ge_u16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1506,8 +1506,8 @@ define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_ge_u16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1539,8 +1539,8 @@ define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_lt_u16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1566,8 +1566,8 @@ define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_lt_u16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1599,8 +1599,8 @@ define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_le_u16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1626,8 +1626,8 @@ define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_le_u16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1659,8 +1659,8 @@ define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_gt_i16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1686,8 +1686,8 @@ define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_gt_i16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1719,8 +1719,8 @@ define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_ge_i16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1746,8 +1746,8 @@ define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_ge_i16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1779,8 +1779,8 @@ define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_lt_i16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1806,8 +1806,8 @@ define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_lt_i16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1839,8 +1839,8 @@ define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-VI-NEXT: v_cmp_le_i16_e64 s[2:3], s2, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1866,8 +1866,8 @@ define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-VI-NEXT: v_cmp_le_i16_e64 s[2:3], s2, v0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
@@ -1903,8 +1903,8 @@ define amdgpu_kernel void @v_icmp_i1_ne0(ptr addrspace(1) %out, i32 %a, i32 %b)
; SDAG-VI-NEXT: s_cselect_b64 s[2:3], -1, 0
; SDAG-VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; SDAG-VI-NEXT: s_endpgm
@@ -1955,8 +1955,8 @@ define amdgpu_kernel void @v_icmp_i1_ne0(ptr addrspace(1) %out, i32 %a, i32 %b)
; GISEL-VI-NEXT: s_cmp_lg_u32 s2, 0
; GISEL-VI-NEXT: s_cselect_b64 s[2:3], exec, 0
; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GISEL-VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
index 51bcb393dfd4f..5e5d6b552fee8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
@@ -15,8 +15,8 @@ define amdgpu_kernel void @MFMAExpInterleave(ptr addrspace(1) %out0, ptr addrspa
; GCN-NEXT: v_sub_f32_e32 v8, v6, v7
; GCN-NEXT: v_fma_f32 v5, s6, v5, -v6
; GCN-NEXT: v_mov_b32_e32 v6, 0x32a5705f
-; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GCN-NEXT: v_fmac_f32_e32 v5, s6, v6
+; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GCN-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GCN-NEXT: v_add_f32_e32 v5, v8, v5
; GCN-NEXT: v_cvt_i32_f32_e32 v6, v7
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
index d1b25582fba9b..fa1d88d4ffe6b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
@@ -563,6 +563,13 @@ define amdgpu_kernel void @test_iglp_opt_rev_mfma_gemm(ptr addrspace(3) noalias
; GISEL-NEXT: ds_read_b128 a[84:87], v0 offset:24656
; GISEL-NEXT: ds_read_b128 a[88:91], v0 offset:24672
; GISEL-NEXT: ds_read_b128 a[92:95], v0 offset:24688
+; GISEL-NEXT: v_accvgpr_read_b32 v2, a2
+; GISEL-NEXT: v_accvgpr_read_b32 v3, a3
+; GISEL-NEXT: v_accvgpr_read_b32 v4, a4
+; GISEL-NEXT: v_accvgpr_read_b32 v5, a5
+; GISEL-NEXT: v_accvgpr_read_b32 v6, a6
+; GISEL-NEXT: v_accvgpr_read_b32 v7, a7
+; GISEL-NEXT: v_accvgpr_read_b32 v8, a8
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mfma_f32_32x32x1f32 a[64:95], v33, v34, a[64:95]
; GISEL-NEXT: ds_read_b128 a[96:99], v0 offset:49152
@@ -573,6 +580,13 @@ define amdgpu_kernel void @test_iglp_opt_rev_mfma_gemm(ptr addrspace(3) noalias
; GISEL-NEXT: ds_read_b128 a[116:119], v0 offset:49232
; GISEL-NEXT: ds_read_b128 a[120:123], v0 offset:49248
; GISEL-NEXT: ds_read_b128 a[124:127], v0 offset:49264
+; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
+; GISEL-NEXT: v_accvgpr_read_b32 v9, a9
+; GISEL-NEXT: v_accvgpr_read_b32 v10, a10
+; GISEL-NEXT: v_accvgpr_read_b32 v11, a11
+; GISEL-NEXT: v_accvgpr_read_b32 v12, a12
+; GISEL-NEXT: v_accvgpr_read_b32 v13, a13
+; GISEL-NEXT: v_accvgpr_read_b32 v14, a14
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mfma_f32_32x32x1f32 a[96:127], v33, v34, a[96:127]
; GISEL-NEXT: ds_read_b128 a[128:131], v1 offset:32768
@@ -583,29 +597,15 @@ define amdgpu_kernel void @test_iglp_opt_rev_mfma_gemm(ptr addrspace(3) noalias
; GISEL-NEXT: ds_read_b128 a[148:151], v1 offset:32848
; GISEL-NEXT: ds_read_b128 a[152:155], v1 offset:32864
; GISEL-NEXT: ds_read_b128 a[156:159], v1 offset:32880
-; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
; GISEL-NEXT: v_accvgpr_read_b32 v1, a1
-; GISEL-NEXT: v_accvgpr_read_b32 v2, a2
-; GISEL-NEXT: v_accvgpr_read_b32 v3, a3
-; GISEL-NEXT: v_accvgpr_read_b32 v4, a4
-; GISEL-NEXT: v_accvgpr_read_b32 v5, a5
-; GISEL-NEXT: v_accvgpr_read_b32 v6, a6
-; GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-NEXT: v_mfma_f32_32x32x1f32 a[128:159], v33, v34, a[128:159]
-; GISEL-NEXT: v_accvgpr_read_b32 v7, a7
-; GISEL-NEXT: v_accvgpr_read_b32 v8, a8
-; GISEL-NEXT: v_accvgpr_read_b32 v9, a9
-; GISEL-NEXT: v_accvgpr_read_b32 v10, a10
-; GISEL-NEXT: v_accvgpr_read_b32 v11, a11
-; GISEL-NEXT: v_accvgpr_read_b32 v12, a12
-; GISEL-NEXT: v_accvgpr_read_b32 v13, a13
-; GISEL-NEXT: v_accvgpr_read_b32 v14, a14
; GISEL-NEXT: v_accvgpr_read_b32 v15, a15
; GISEL-NEXT: v_accvgpr_read_b32 v16, a16
; GISEL-NEXT: v_accvgpr_read_b32 v17, a17
; GISEL-NEXT: v_accvgpr_read_b32 v18, a18
; GISEL-NEXT: v_accvgpr_read_b32 v19, a19
; GISEL-NEXT: v_accvgpr_read_b32 v20, a20
+; GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-NEXT: v_mfma_f32_32x32x1f32 a[128:159], v33, v34, a[128:159]
; GISEL-NEXT: v_accvgpr_read_b32 v21, a21
; GISEL-NEXT: v_accvgpr_read_b32 v22, a22
; GISEL-NEXT: v_accvgpr_read_b32 v23, a23
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
index 5171995981515..da97b50dd0872 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
@@ -18,11 +18,11 @@ define amdgpu_ps <4 x float> @load_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1
; GCN-LABEL: load_1d_lwe:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: v_mov_b32_e32 v8, 0
-; GCN-NEXT: v_mov_b32_e32 v6, v0
; GCN-NEXT: v_mov_b32_e32 v9, v8
; GCN-NEXT: v_mov_b32_e32 v10, v8
; GCN-NEXT: v_mov_b32_e32 v11, v8
; GCN-NEXT: v_mov_b32_e32 v12, v8
+; GCN-NEXT: v_mov_b32_e32 v6, v0
; GCN-NEXT: v_mov_b32_e32 v0, v8
; GCN-NEXT: v_mov_b32_e32 v1, v9
; GCN-NEXT: v_mov_b32_e32 v2, v10
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
index f1278ececbe03..6d45abd3e0b42 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
@@ -85,11 +85,11 @@ define amdgpu_ps <4 x float> @load_1d_tfe(<8 x i32> inreg %rsrc, ptr addrspace(1
; GFX6789-LABEL: load_1d_tfe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v6, 0
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v7, v6
; GFX6789-NEXT: v_mov_b32_e32 v8, v6
; GFX6789-NEXT: v_mov_b32_e32 v9, v6
; GFX6789-NEXT: v_mov_b32_e32 v10, v6
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v6
; GFX6789-NEXT: v_mov_b32_e32 v1, v7
; GFX6789-NEXT: v_mov_b32_e32 v2, v8
@@ -200,11 +200,11 @@ define amdgpu_ps <4 x float> @load_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1
; GFX6789-LABEL: load_1d_lwe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v6, 0
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v7, v6
; GFX6789-NEXT: v_mov_b32_e32 v8, v6
; GFX6789-NEXT: v_mov_b32_e32 v9, v6
; GFX6789-NEXT: v_mov_b32_e32 v10, v6
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v6
; GFX6789-NEXT: v_mov_b32_e32 v1, v7
; GFX6789-NEXT: v_mov_b32_e32 v2, v8
@@ -353,12 +353,12 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, ptr addrspace(1
; GFX6789-LABEL: load_2d_tfe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v7, 0
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v8, v7
; GFX6789-NEXT: v_mov_b32_e32 v9, v7
; GFX6789-NEXT: v_mov_b32_e32 v10, v7
; GFX6789-NEXT: v_mov_b32_e32 v11, v7
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v7
; GFX6789-NEXT: v_mov_b32_e32 v1, v8
; GFX6789-NEXT: v_mov_b32_e32 v2, v9
@@ -530,13 +530,13 @@ define amdgpu_ps <4 x float> @load_3d_tfe_lwe(<8 x i32> inreg %rsrc, ptr addrspa
; GFX6789-LABEL: load_3d_tfe_lwe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v8, 0
-; GFX6789-NEXT: v_mov_b32_e32 v7, v2
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v9, v8
; GFX6789-NEXT: v_mov_b32_e32 v10, v8
; GFX6789-NEXT: v_mov_b32_e32 v11, v8
; GFX6789-NEXT: v_mov_b32_e32 v12, v8
+; GFX6789-NEXT: v_mov_b32_e32 v7, v2
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v8
; GFX6789-NEXT: v_mov_b32_e32 v1, v9
; GFX6789-NEXT: v_mov_b32_e32 v2, v10
@@ -696,13 +696,13 @@ define amdgpu_ps <4 x float> @load_cube_lwe(<8 x i32> inreg %rsrc, ptr addrspace
; GFX6789-LABEL: load_cube_lwe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v8, 0
-; GFX6789-NEXT: v_mov_b32_e32 v7, v2
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v9, v8
; GFX6789-NEXT: v_mov_b32_e32 v10, v8
; GFX6789-NEXT: v_mov_b32_e32 v11, v8
; GFX6789-NEXT: v_mov_b32_e32 v12, v8
+; GFX6789-NEXT: v_mov_b32_e32 v7, v2
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v8
; GFX6789-NEXT: v_mov_b32_e32 v1, v9
; GFX6789-NEXT: v_mov_b32_e32 v2, v10
@@ -854,12 +854,12 @@ define amdgpu_ps <4 x float> @load_1darray_tfe(<8 x i32> inreg %rsrc, ptr addrsp
; GFX6789-LABEL: load_1darray_tfe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v7, 0
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v8, v7
; GFX6789-NEXT: v_mov_b32_e32 v9, v7
; GFX6789-NEXT: v_mov_b32_e32 v10, v7
; GFX6789-NEXT: v_mov_b32_e32 v11, v7
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v7
; GFX6789-NEXT: v_mov_b32_e32 v1, v8
; GFX6789-NEXT: v_mov_b32_e32 v2, v9
@@ -1031,13 +1031,13 @@ define amdgpu_ps <4 x float> @load_2darray_lwe(<8 x i32> inreg %rsrc, ptr addrsp
; GFX6789-LABEL: load_2darray_lwe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v8, 0
-; GFX6789-NEXT: v_mov_b32_e32 v7, v2
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v9, v8
; GFX6789-NEXT: v_mov_b32_e32 v10, v8
; GFX6789-NEXT: v_mov_b32_e32 v11, v8
; GFX6789-NEXT: v_mov_b32_e32 v12, v8
+; GFX6789-NEXT: v_mov_b32_e32 v7, v2
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v8
; GFX6789-NEXT: v_mov_b32_e32 v1, v9
; GFX6789-NEXT: v_mov_b32_e32 v2, v10
@@ -1191,13 +1191,13 @@ define amdgpu_ps <4 x float> @load_2dmsaa_both(<8 x i32> inreg %rsrc, ptr addrsp
; GFX6789-LABEL: load_2dmsaa_both:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v8, 0
-; GFX6789-NEXT: v_mov_b32_e32 v7, v2
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v9, v8
; GFX6789-NEXT: v_mov_b32_e32 v10, v8
; GFX6789-NEXT: v_mov_b32_e32 v11, v8
; GFX6789-NEXT: v_mov_b32_e32 v12, v8
+; GFX6789-NEXT: v_mov_b32_e32 v7, v2
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v8
; GFX6789-NEXT: v_mov_b32_e32 v1, v9
; GFX6789-NEXT: v_mov_b32_e32 v2, v10
@@ -1359,14 +1359,14 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, ptr ad
; GFX6789-LABEL: load_2darraymsaa_tfe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v9, 0
-; GFX6789-NEXT: v_mov_b32_e32 v8, v3
-; GFX6789-NEXT: v_mov_b32_e32 v7, v2
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v10, v9
; GFX6789-NEXT: v_mov_b32_e32 v11, v9
; GFX6789-NEXT: v_mov_b32_e32 v12, v9
; GFX6789-NEXT: v_mov_b32_e32 v13, v9
+; GFX6789-NEXT: v_mov_b32_e32 v8, v3
+; GFX6789-NEXT: v_mov_b32_e32 v7, v2
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v9
; GFX6789-NEXT: v_mov_b32_e32 v1, v10
; GFX6789-NEXT: v_mov_b32_e32 v2, v11
@@ -1541,12 +1541,12 @@ define amdgpu_ps <4 x float> @load_mip_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspa
; GFX6789-LABEL: load_mip_1d_lwe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v7, 0
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v8, v7
; GFX6789-NEXT: v_mov_b32_e32 v9, v7
; GFX6789-NEXT: v_mov_b32_e32 v10, v7
; GFX6789-NEXT: v_mov_b32_e32 v11, v7
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v7
; GFX6789-NEXT: v_mov_b32_e32 v1, v8
; GFX6789-NEXT: v_mov_b32_e32 v2, v9
@@ -1698,13 +1698,13 @@ define amdgpu_ps <4 x float> @load_mip_2d_tfe(<8 x i32> inreg %rsrc, ptr addrspa
; GFX6789-LABEL: load_mip_2d_tfe:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v8, 0
-; GFX6789-NEXT: v_mov_b32_e32 v7, v2
-; GFX6789-NEXT: v_mov_b32_e32 v6, v1
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v9, v8
; GFX6789-NEXT: v_mov_b32_e32 v10, v8
; GFX6789-NEXT: v_mov_b32_e32 v11, v8
; GFX6789-NEXT: v_mov_b32_e32 v12, v8
+; GFX6789-NEXT: v_mov_b32_e32 v7, v2
+; GFX6789-NEXT: v_mov_b32_e32 v6, v1
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v8
; GFX6789-NEXT: v_mov_b32_e32 v1, v9
; GFX6789-NEXT: v_mov_b32_e32 v2, v10
@@ -2177,10 +2177,10 @@ define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask3(<8 x i32> inreg %rsrc, ptr a
; GFX6789-LABEL: load_1d_tfe_V4_dmask3:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v5, 0
-; GFX6789-NEXT: v_mov_b32_e32 v4, v0
; GFX6789-NEXT: v_mov_b32_e32 v6, v5
; GFX6789-NEXT: v_mov_b32_e32 v7, v5
; GFX6789-NEXT: v_mov_b32_e32 v8, v5
+; GFX6789-NEXT: v_mov_b32_e32 v4, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v5
; GFX6789-NEXT: v_mov_b32_e32 v1, v6
; GFX6789-NEXT: v_mov_b32_e32 v2, v7
@@ -2281,9 +2281,9 @@ define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask2(<8 x i32> inreg %rsrc, ptr a
; GFX6789-LABEL: load_1d_tfe_V4_dmask2:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v4, 0
-; GFX6789-NEXT: v_mov_b32_e32 v3, v0
; GFX6789-NEXT: v_mov_b32_e32 v5, v4
; GFX6789-NEXT: v_mov_b32_e32 v6, v4
+; GFX6789-NEXT: v_mov_b32_e32 v3, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v4
; GFX6789-NEXT: v_mov_b32_e32 v1, v5
; GFX6789-NEXT: v_mov_b32_e32 v2, v6
@@ -2377,8 +2377,8 @@ define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask1(<8 x i32> inreg %rsrc, ptr a
; GFX6789-LABEL: load_1d_tfe_V4_dmask1:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v3, 0
-; GFX6789-NEXT: v_mov_b32_e32 v2, v0
; GFX6789-NEXT: v_mov_b32_e32 v4, v3
+; GFX6789-NEXT: v_mov_b32_e32 v2, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v3
; GFX6789-NEXT: v_mov_b32_e32 v1, v4
; GFX6789-NEXT: image_load v[0:1], v2, s[0:7] dmask:0x8 unorm tfe
@@ -2466,8 +2466,8 @@ define amdgpu_ps <2 x float> @load_1d_tfe_V2_dmask1(<8 x i32> inreg %rsrc, ptr a
; GFX6789-LABEL: load_1d_tfe_V2_dmask1:
; GFX6789: ; %bb.0: ; %main_body
; GFX6789-NEXT: v_mov_b32_e32 v3, 0
-; GFX6789-NEXT: v_mov_b32_e32 v2, v0
; GFX6789-NEXT: v_mov_b32_e32 v4, v3
+; GFX6789-NEXT: v_mov_b32_e32 v2, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v3
; GFX6789-NEXT: v_mov_b32_e32 v1, v4
; GFX6789-NEXT: image_load v[0:1], v2, s[0:7] dmask:0x8 unorm tfe
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
index 2021ed60425cd..6448ba7ca3a0b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
@@ -131,8 +131,7 @@ define amdgpu_ps half @image_sample_2d_f16_tfe(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14
; GFX11-TRUE16-NEXT: image_sample v[3:4], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -160,8 +159,7 @@ define amdgpu_ps half @image_sample_2d_f16_tfe(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12PLUS-TRUE16-NEXT: v_mov_b32_e32 v3, v2
+; GFX12PLUS-TRUE16-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14
; GFX12PLUS-TRUE16-NEXT: image_sample v[3:4], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
index 75c9b121eb23a..ea34efa38ba92 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
@@ -75,11 +75,11 @@ define amdgpu_ps <4 x float> @sample_1d_tfe(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX6789-NEXT: s_mov_b64 s[14:15], exec
; GFX6789-NEXT: s_wqm_b64 exec, exec
; GFX6789-NEXT: v_mov_b32_e32 v6, 0
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v7, v6
; GFX6789-NEXT: v_mov_b32_e32 v8, v6
; GFX6789-NEXT: v_mov_b32_e32 v9, v6
; GFX6789-NEXT: v_mov_b32_e32 v10, v6
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v6
; GFX6789-NEXT: v_mov_b32_e32 v1, v7
; GFX6789-NEXT: v_mov_b32_e32 v2, v8
@@ -691,11 +691,11 @@ define amdgpu_ps <4 x float> @sample_1d_lwe(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX6789-NEXT: s_mov_b64 s[14:15], exec
; GFX6789-NEXT: s_wqm_b64 exec, exec
; GFX6789-NEXT: v_mov_b32_e32 v6, 0
-; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v7, v6
; GFX6789-NEXT: v_mov_b32_e32 v8, v6
; GFX6789-NEXT: v_mov_b32_e32 v9, v6
; GFX6789-NEXT: v_mov_b32_e32 v10, v6
+; GFX6789-NEXT: v_mov_b32_e32 v5, v0
; GFX6789-NEXT: v_mov_b32_e32 v0, v6
; GFX6789-NEXT: v_mov_b32_e32 v1, v7
; GFX6789-NEXT: v_mov_b32_e32 v2, v8
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
index ad92cbfadb6c7..75817bd114dd0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
@@ -28,8 +28,8 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
; GISEL12-NEXT: s_mov_b64 exec, s[10:11]
-; GISEL12-NEXT: v_mov_b32_e32 v11, s12
; GISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v13
+; GISEL12-NEXT: v_mov_b32_e32 v11, s12
; GISEL12-NEXT: v_mov_b32_e32 v12, s13
; GISEL12-NEXT: ; %bb.2: ; %tail
; GISEL12-NEXT: s_or_b64 exec, exec, s[6:7]
@@ -57,8 +57,8 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
; DAGISEL12-NEXT: s_mov_b64 exec, s[10:11]
-; DAGISEL12-NEXT: v_mov_b32_e32 v11, s12
; DAGISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v13
+; DAGISEL12-NEXT: v_mov_b32_e32 v11, s12
; DAGISEL12-NEXT: v_mov_b32_e32 v12, s13
; DAGISEL12-NEXT: ; %bb.2: ; %tail
; DAGISEL12-NEXT: s_or_b64 exec, exec, s[8:9]
@@ -79,8 +79,8 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; GISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
; GISEL10-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
; GISEL10-NEXT: s_mov_b64 exec, s[10:11]
-; GISEL10-NEXT: v_mov_b32_e32 v11, s12
; GISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v13
+; GISEL10-NEXT: v_mov_b32_e32 v11, s12
; GISEL10-NEXT: v_mov_b32_e32 v12, s13
; GISEL10-NEXT: ; %bb.2: ; %tail
; GISEL10-NEXT: s_or_b64 exec, exec, s[6:7]
@@ -101,8 +101,8 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; DAGISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
; DAGISEL10-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
; DAGISEL10-NEXT: s_mov_b64 exec, s[10:11]
-; DAGISEL10-NEXT: v_mov_b32_e32 v11, s12
; DAGISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v13
+; DAGISEL10-NEXT: v_mov_b32_e32 v11, s12
; DAGISEL10-NEXT: v_mov_b32_e32 v12, s13
; DAGISEL10-NEXT: ; %bb.2: ; %tail
; DAGISEL10-NEXT: s_or_b64 exec, exec, s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
index e6f2bb49c5726..ac2baa13d17f2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
@@ -115,16 +115,16 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_ssssss(i32 inreg %node_ptr
; GFX11-GISEL-LABEL: image_bvh_intersect_ray_ssssss:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_mov_b32 s16, s2
+; GFX11-GISEL-NEXT: s_mov_b32 s17, s3
; GFX11-GISEL-NEXT: s_mov_b32 s18, s4
; GFX11-GISEL-NEXT: s_mov_b32 s20, s5
-; GFX11-GISEL-NEXT: s_mov_b32 s17, s3
; GFX11-GISEL-NEXT: s_mov_b32 s21, s6
; GFX11-GISEL-NEXT: s_mov_b32 s22, s7
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s20
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1
; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s21 :: v_dual_mov_b32 v5, s22
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
; GFX11-GISEL-NEXT: v_mov_b32_e32 v8, s10
; GFX11-GISEL-NEXT: s_mov_b32 s4, s11
; GFX11-GISEL-NEXT: s_mov_b32 s5, s12
@@ -153,16 +153,16 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_ssssss(i32 inreg %node_ptr
; GFX12-GISEL-LABEL: image_bvh_intersect_ray_ssssss:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_mov_b32 s16, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s17, s3
; GFX12-GISEL-NEXT: s_mov_b32 s18, s4
; GFX12-GISEL-NEXT: s_mov_b32 s20, s5
-; GFX12-GISEL-NEXT: s_mov_b32 s17, s3
; GFX12-GISEL-NEXT: s_mov_b32 s21, s6
; GFX12-GISEL-NEXT: s_mov_b32 s22, s7
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s20
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s21 :: v_dual_mov_b32 v5, s22
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
; GFX12-GISEL-NEXT: v_mov_b32_e32 v8, s10
; GFX12-GISEL-NEXT: s_mov_b32 s4, s11
; GFX12-GISEL-NEXT: s_mov_b32 s5, s12
@@ -277,14 +277,14 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f
; GFX11-GISEL-LABEL: image_bvh_intersect_ray_a16:
; GFX11-GISEL: ; %bb.0: ; %main_body
; GFX11-GISEL-NEXT: s_mov_b32 s20, s2
+; GFX11-GISEL-NEXT: s_mov_b32 s21, s3
; GFX11-GISEL-NEXT: s_mov_b32 s22, s4
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s4, s7, s5
-; GFX11-GISEL-NEXT: s_mov_b32 s21, s3
; GFX11-GISEL-NEXT: s_pack_hh_b32_b16 s5, s7, s5
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s6, s8, s6
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v1, s21
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v3, s4
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s6
; GFX11-GISEL-NEXT: s_mov_b32 s16, s9
; GFX11-GISEL-NEXT: s_mov_b32 s17, s10
@@ -319,14 +319,14 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f
; GFX12-GISEL-LABEL: image_bvh_intersect_ray_a16:
; GFX12-GISEL: ; %bb.0: ; %main_body
; GFX12-GISEL-NEXT: s_mov_b32 s20, s2
+; GFX12-GISEL-NEXT: s_mov_b32 s21, s3
; GFX12-GISEL-NEXT: s_mov_b32 s22, s4
; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s4, s7, s5
-; GFX12-GISEL-NEXT: s_mov_b32 s21, s3
; GFX12-GISEL-NEXT: s_pack_hh_b32_b16 s5, s7, s5
; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s6, s8, s6
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v1, s21
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v3, s4
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s6
; GFX12-GISEL-NEXT: s_mov_b32 s16, s9
; GFX12-GISEL-NEXT: s_mov_b32 s17, s10
@@ -404,20 +404,20 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_ssssss(i64 inreg %node_p
;
; GFX11-GISEL-LABEL: image_bvh64_intersect_ray_ssssss:
; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_mov_b32 s16, s3
; GFX11-GISEL-NEXT: s_mov_b32 s17, s4
+; GFX11-GISEL-NEXT: s_mov_b32 s18, s5
; GFX11-GISEL-NEXT: s_mov_b32 s4, s6
-; GFX11-GISEL-NEXT: s_mov_b32 s16, s3
+; GFX11-GISEL-NEXT: s_mov_b32 s5, s7
; GFX11-GISEL-NEXT: s_mov_b32 s6, s8
; GFX11-GISEL-NEXT: s_mov_b32 s8, s9
-; GFX11-GISEL-NEXT: s_mov_b32 s18, s5
-; GFX11-GISEL-NEXT: s_mov_b32 s5, s7
; GFX11-GISEL-NEXT: s_mov_b32 s9, s10
; GFX11-GISEL-NEXT: s_mov_b32 s10, s11
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v0, s16
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s8
; GFX11-GISEL-NEXT: v_dual_mov_b32 v10, s1 :: v_dual_mov_b32 v9, s0
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v0, s16
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s17 :: v_dual_mov_b32 v2, s18
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s8
; GFX11-GISEL-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
; GFX11-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[12:15]
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -437,20 +437,20 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_ssssss(i64 inreg %node_p
;
; GFX12-GISEL-LABEL: image_bvh64_intersect_ray_ssssss:
; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_mov_b32 s16, s3
; GFX12-GISEL-NEXT: s_mov_b32 s17, s4
+; GFX12-GISEL-NEXT: s_mov_b32 s18, s5
; GFX12-GISEL-NEXT: s_mov_b32 s4, s6
-; GFX12-GISEL-NEXT: s_mov_b32 s16, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s5, s7
; GFX12-GISEL-NEXT: s_mov_b32 s6, s8
; GFX12-GISEL-NEXT: s_mov_b32 s8, s9
-; GFX12-GISEL-NEXT: s_mov_b32 s18, s5
-; GFX12-GISEL-NEXT: s_mov_b32 s5, s7
; GFX12-GISEL-NEXT: s_mov_b32 s9, s10
; GFX12-GISEL-NEXT: s_mov_b32 s10, s11
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v0, s16
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s8
; GFX12-GISEL-NEXT: v_dual_mov_b32 v10, s1 :: v_dual_mov_b32 v9, s0
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v0, s16
; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s17 :: v_dual_mov_b32 v2, s18
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s8
; GFX12-GISEL-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
; GFX12-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[12:15]
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
@@ -566,13 +566,13 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr,
; GFX11-GISEL: ; %bb.0: ; %main_body
; GFX11-GISEL-NEXT: s_mov_b32 s20, s3
; GFX11-GISEL-NEXT: s_mov_b32 s21, s4
-; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s4, s8, s6
; GFX11-GISEL-NEXT: s_mov_b32 s22, s5
+; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s4, s8, s6
; GFX11-GISEL-NEXT: s_pack_hh_b32_b16 s5, s8, s6
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s6, s9, s7
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v3, s4
; GFX11-GISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v1, s21
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v3, s4
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v5, s6
; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, s5
; GFX11-GISEL-NEXT: s_mov_b32 s16, s10
@@ -610,13 +610,13 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr,
; GFX12-GISEL: ; %bb.0: ; %main_body
; GFX12-GISEL-NEXT: s_mov_b32 s20, s3
; GFX12-GISEL-NEXT: s_mov_b32 s21, s4
-; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s4, s8, s6
; GFX12-GISEL-NEXT: s_mov_b32 s22, s5
+; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s4, s8, s6
; GFX12-GISEL-NEXT: s_pack_hh_b32_b16 s5, s8, s6
; GFX12-GISEL-NEXT: s_pack_ll_b32_b16 s6, s9, s7
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v3, s4
; GFX12-GISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v1, s21
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v3, s4
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v5, s6
; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s5
; GFX12-GISEL-NEXT: s_mov_b32 s16, s10
@@ -781,18 +781,19 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX11-GISEL-NEXT: s_mov_b32 s10, 0x40a00000
; GFX11-GISEL-NEXT: s_mov_b32 s9, 4.0
; GFX11-GISEL-NEXT: s_mov_b32 s8, 0x40400000
-; GFX11-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX11-GISEL-NEXT: s_mov_b32 s14, 0x41000000
; GFX11-GISEL-NEXT: s_mov_b32 s13, 0x40e00000
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, s12
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v7, s13
+; GFX11-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v8, s14
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v5, s10
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v7, s13
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX11-GISEL-NEXT: s_mov_b32 s2, 2.0
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 1.0
+; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -801,9 +802,9 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-GISEL-NEXT: flat_load_b32 v9, v[0:1]
; GFX11-GISEL-NEXT: flat_load_b32 v10, v[2:3]
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, s9
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[0:2], v[3:5], v[6:8]], s[4:7]
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -845,18 +846,19 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX12-GISEL-NEXT: s_mov_b32 s10, 0x40a00000
; GFX12-GISEL-NEXT: s_mov_b32 s9, 4.0
; GFX12-GISEL-NEXT: s_mov_b32 s8, 0x40400000
-; GFX12-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GFX12-GISEL-NEXT: s_mov_b32 s14, 0x41000000
; GFX12-GISEL-NEXT: s_mov_b32 s13, 0x40e00000
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v6, s12
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v7, s13
+; GFX12-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v8, s14
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v5, s10
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v7, s13
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, 2.0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-GISEL-NEXT: s_mov_b32 s0, 0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT: s_mov_b32 s1, 1.0
+; GFX12-GISEL-NEXT: s_mov_b32 s0, 0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -866,9 +868,9 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX12-GISEL-NEXT: flat_load_b32 v9, v[0:1]
; GFX12-GISEL-NEXT: flat_load_b32 v10, v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s9
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[0:2], v[3:5], v[6:8]], s[4:7]
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
@@ -1026,14 +1028,15 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX11-GISEL-NEXT: s_mov_b32 s8, 0x42004600
; GFX11-GISEL-NEXT: s_mov_b32 s9, 0x44004700
; GFX11-GISEL-NEXT: s_mov_b32 s10, 0x45004800
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v5, s10
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX11-GISEL-NEXT: s_mov_b32 s2, 2.0
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 1.0
+; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -1042,9 +1045,9 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-GISEL-NEXT: flat_load_b32 v6, v[0:1]
; GFX11-GISEL-NEXT: flat_load_b32 v7, v[2:3]
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, s9
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -1083,14 +1086,15 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX12-GISEL-NEXT: s_mov_b32 s8, 0x42004600
; GFX12-GISEL-NEXT: s_mov_b32 s9, 0x44004700
; GFX12-GISEL-NEXT: s_mov_b32 s10, 0x45004800
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v5, s10
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, 2.0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-GISEL-NEXT: s_mov_b32 s0, 0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT: s_mov_b32 s1, 1.0
+; GFX12-GISEL-NEXT: s_mov_b32 s0, 0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
@@ -1100,9 +1104,9 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX12-GISEL-NEXT: flat_load_b32 v6, v[0:1]
; GFX12-GISEL-NEXT: flat_load_b32 v7, v[2:3]
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s9
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
@@ -1275,28 +1279,28 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-GISEL-NEXT: s_mov_b32 s5, 1.0
; GFX11-GISEL-NEXT: s_mov_b32 s4, 0
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v9, 0xb36211c7
-; GFX11-GISEL-NEXT: s_mov_b32 s8, 0x40400000
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX11-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
; GFX11-GISEL-NEXT: s_mov_b32 s10, 0x40a00000
; GFX11-GISEL-NEXT: s_mov_b32 s9, 4.0
+; GFX11-GISEL-NEXT: s_mov_b32 s8, 0x40400000
; GFX11-GISEL-NEXT: s_mov_b32 s14, 0x41000000
; GFX11-GISEL-NEXT: s_mov_b32 s13, 0x40e00000
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, s12
+; GFX11-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v10, 4.0
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v3, s8
; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v7, s13
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, s12
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, 0xb36211c7
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v5, s10
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, s8
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v0, s6
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX11-GISEL-NEXT: s_mov_b32 s6, 2.0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX11-GISEL-NEXT: flat_load_b32 v11, v[0:1]
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[0:3]
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -1337,29 +1341,29 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX12-GISEL-NEXT: s_mov_b32 s5, 1.0
; GFX12-GISEL-NEXT: s_mov_b32 s4, 0
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v9, 0xb36211c7
-; GFX12-GISEL-NEXT: s_mov_b32 s8, 0x40400000
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX12-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
; GFX12-GISEL-NEXT: s_mov_b32 s10, 0x40a00000
; GFX12-GISEL-NEXT: s_mov_b32 s9, 4.0
+; GFX12-GISEL-NEXT: s_mov_b32 s8, 0x40400000
; GFX12-GISEL-NEXT: s_mov_b32 s14, 0x41000000
; GFX12-GISEL-NEXT: s_mov_b32 s13, 0x40e00000
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v6, s12
+; GFX12-GISEL-NEXT: s_mov_b32 s12, 0x40c00000
; GFX12-GISEL-NEXT: v_bfrev_b32_e32 v10, 4.0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v3, s8
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v7, s13
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v6, s12
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, 0xb36211c7
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v5, s10
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s8
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v0, s6
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX12-GISEL-NEXT: s_mov_b32 s6, 2.0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-GISEL-NEXT: flat_load_b32 v11, v[0:1]
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX12-GISEL-NEXT: flat_load_b32 v11, v[0:1]
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[0:3]
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
@@ -1520,21 +1524,21 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
; GFX11-GISEL-NEXT: s_mov_b32 s4, 0
; GFX11-GISEL-NEXT: s_mov_b32 s8, 0x42004600
; GFX11-GISEL-NEXT: s_mov_b32 s9, 0x44004700
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX11-GISEL-NEXT: s_mov_b32 s10, 0x45004800
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v6, 0xb36211c6
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v5, s10
; GFX11-GISEL-NEXT: v_bfrev_b32_e32 v7, 4.0
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v3, s8
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v0, s6
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX11-GISEL-NEXT: s_mov_b32 s6, 2.0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX11-GISEL-NEXT: flat_load_b32 v8, v[0:1]
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -1577,22 +1581,22 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
; GFX12-GISEL-NEXT: s_mov_b32 s4, 0
; GFX12-GISEL-NEXT: s_mov_b32 s8, 0x42004600
; GFX12-GISEL-NEXT: s_mov_b32 s9, 0x44004700
-; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX12-GISEL-NEXT: s_mov_b32 s10, 0x45004800
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v6, 0xb36211c6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v5, s10
; GFX12-GISEL-NEXT: v_bfrev_b32_e32 v7, 4.0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v3, s8
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v0, s6
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX12-GISEL-NEXT: s_mov_b32 s6, 2.0
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-GISEL-NEXT: flat_load_b32 v8, v[0:1]
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX12-GISEL-NEXT: flat_load_b32 v8, v[0:1]
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
index 09dd07d07ed70..522b383e467ed 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
@@ -302,8 +302,8 @@ define amdgpu_cs void @inverse_ballot_branch(i64 inreg %s0_1, i64 inreg %s2, ptr
; GISEL_W64-NEXT: ; %bb.1: ; %if
; GISEL_W64-NEXT: s_add_u32 s0, s0, 1
; GISEL_W64-NEXT: s_addc_u32 s1, s1, 0
-; GISEL_W64-NEXT: v_mov_b32_e32 v3, s1
; GISEL_W64-NEXT: v_mov_b32_e32 v2, s0
+; GISEL_W64-NEXT: v_mov_b32_e32 v3, s1
; GISEL_W64-NEXT: ; %bb.2: ; %endif
; GISEL_W64-NEXT: s_or_b64 exec, exec, s[2:3]
; GISEL_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
@@ -318,8 +318,8 @@ define amdgpu_cs void @inverse_ballot_branch(i64 inreg %s0_1, i64 inreg %s2, ptr
; SDAG_W64-NEXT: ; %bb.1: ; %if
; SDAG_W64-NEXT: s_add_u32 s0, s0, 1
; SDAG_W64-NEXT: s_addc_u32 s1, s1, 0
-; SDAG_W64-NEXT: v_mov_b32_e32 v3, s1
; SDAG_W64-NEXT: v_mov_b32_e32 v2, s0
+; SDAG_W64-NEXT: v_mov_b32_e32 v3, s1
; SDAG_W64-NEXT: ; %bb.2: ; %endif
; SDAG_W64-NEXT: s_or_b64 exec, exec, s[2:3]
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
@@ -334,7 +334,7 @@ define amdgpu_cs void @inverse_ballot_branch(i64 inreg %s0_1, i64 inreg %s2, ptr
; GISEL_W32-NEXT: ; %bb.1: ; %if
; GISEL_W32-NEXT: s_add_u32 s0, s0, 1
; GISEL_W32-NEXT: s_addc_u32 s1, s1, 0
-; GISEL_W32-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GISEL_W32-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GISEL_W32-NEXT: ; %bb.2: ; %endif
; GISEL_W32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GISEL_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
@@ -348,7 +348,7 @@ define amdgpu_cs void @inverse_ballot_branch(i64 inreg %s0_1, i64 inreg %s2, ptr
; SDAG_W32-NEXT: ; %bb.1: ; %if
; SDAG_W32-NEXT: s_add_u32 s0, s0, 1
; SDAG_W32-NEXT: s_addc_u32 s1, s1, 0
-; SDAG_W32-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; SDAG_W32-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; SDAG_W32-NEXT: ; %bb.2: ; %endif
; SDAG_W32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
index 82002401870e1..243823c838f15 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
@@ -2346,8 +2346,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_imm_int_64_in_high_bit
; GFX90A-NEXT: v_mov_b32_e32 v5, v1
; GFX90A-NEXT: v_mov_b32_e32 v6, v0
; GFX90A-NEXT: v_mov_b32_e32 v7, v1
-; GFX90A-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[12:13], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
@@ -2400,8 +2400,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_imm_int_64_in_high_bit
; GFX942-NEXT: v_mov_b32_e32 v5, v1
; GFX942-NEXT: v_mov_b32_e32 v6, v0
; GFX942-NEXT: v_mov_b32_e32 v7, v1
-; GFX942-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GFX942-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
@@ -2454,8 +2454,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_imm_int_64_in_high_bit
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, v1
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, v0
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v7, v1
-; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[12:13], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
@@ -2508,8 +2508,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_imm_int_64_in_high_bit
; GFX942-VGPR-NEXT: v_mov_b32_e32 v5, v1
; GFX942-VGPR-NEXT: v_mov_b32_e32 v6, v0
; GFX942-VGPR-NEXT: v_mov_b32_e32 v7, v1
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[4:5], v[2:3]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
@@ -2983,17 +2983,17 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_imm(ptr addrspace(1) %arg, d
; GFX90A-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX90A-NEXT: v_mov_b32_e32 v0, 0
; GFX90A-NEXT: v_mov_b32_e32 v7, 0x3ff00000
-; GFX90A-NEXT: v_mov_b32_e32 v2, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, v0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v10, s2
; GFX90A-NEXT: v_mov_b32_e32 v11, s3
+; GFX90A-NEXT: v_mov_b32_e32 v2, v0
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
; GFX90A-NEXT: v_mov_b32_e32 v4, v0
; GFX90A-NEXT: v_mov_b32_e32 v5, v0
; GFX90A-NEXT: v_mov_b32_e32 v6, v0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[12:13], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
@@ -3035,17 +3035,17 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_imm(ptr addrspace(1) %arg, d
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: v_mov_b32_e32 v7, 0x3ff00000
-; GFX942-NEXT: v_mov_b32_e32 v2, v0
+; GFX942-NEXT: v_mov_b32_e32 v1, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v10, s2
; GFX942-NEXT: v_mov_b32_e32 v11, s3
+; GFX942-NEXT: v_mov_b32_e32 v2, v0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
; GFX942-NEXT: v_mov_b32_e32 v4, v0
; GFX942-NEXT: v_mov_b32_e32 v5, v0
; GFX942-NEXT: v_mov_b32_e32 v6, v0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GFX942-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
@@ -3087,17 +3087,17 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_imm(ptr addrspace(1) %arg, d
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v0, 0
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v7, 0x3ff00000
-; GFX90A-VGPR-NEXT: v_mov_b32_e32 v2, v0
+; GFX90A-VGPR-NEXT: v_mov_b32_e32 v1, v0
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v10, s2
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v11, s3
+; GFX90A-VGPR-NEXT: v_mov_b32_e32 v2, v0
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v3, v0
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v4, v0
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, v0
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, v0
-; GFX90A-VGPR-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[12:13], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
@@ -3139,17 +3139,17 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_imm(ptr addrspace(1) %arg, d
; GFX942-VGPR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-VGPR-NEXT: v_mov_b32_e32 v0, 0
; GFX942-VGPR-NEXT: v_mov_b32_e32 v7, 0x3ff00000
-; GFX942-VGPR-NEXT: v_mov_b32_e32 v2, v0
+; GFX942-VGPR-NEXT: v_mov_b32_e32 v1, v0
; GFX942-VGPR-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-NEXT: v_mov_b32_e32 v10, s2
; GFX942-VGPR-NEXT: v_mov_b32_e32 v11, s3
+; GFX942-VGPR-NEXT: v_mov_b32_e32 v2, v0
; GFX942-VGPR-NEXT: v_mov_b32_e32 v3, v0
; GFX942-VGPR-NEXT: v_mov_b32_e32 v4, v0
; GFX942-VGPR-NEXT: v_mov_b32_e32 v5, v0
; GFX942-VGPR-NEXT: v_mov_b32_e32 v6, v0
-; GFX942-VGPR-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[4:5], v[2:3]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
@@ -3206,8 +3206,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_lit(ptr addrspace(1) %
; GFX90A-NEXT: v_mov_b32_e32 v5, v1
; GFX90A-NEXT: v_mov_b32_e32 v6, v0
; GFX90A-NEXT: v_mov_b32_e32 v7, v1
-; GFX90A-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[12:13], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
@@ -3259,8 +3259,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_lit(ptr addrspace(1) %
; GFX942-NEXT: v_mov_b32_e32 v5, v1
; GFX942-NEXT: v_mov_b32_e32 v6, v0
; GFX942-NEXT: v_mov_b32_e32 v7, v1
-; GFX942-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GFX942-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
@@ -3312,8 +3312,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_lit(ptr addrspace(1) %
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, v1
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, v0
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v7, v1
-; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[12:13], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[6:7], v[4:5], v[4:5] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[2:3] op_sel:[0,1]
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[0:1] op_sel:[0,1]
@@ -3365,8 +3365,8 @@ define amdgpu_kernel void @test_mfma_f64_16x16x4f64_splat_lit(ptr addrspace(1) %
; GFX942-VGPR-NEXT: v_mov_b32_e32 v5, v1
; GFX942-VGPR-NEXT: v_mov_b32_e32 v6, v0
; GFX942-VGPR-NEXT: v_mov_b32_e32 v7, v1
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[8:9], v[6:7]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[6:7], v[4:5]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[4:5], v[2:3]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
index 0388bb8b6a36d..8831360b35c1f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
@@ -2057,10 +2057,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_i8(ptr addrspace(1) %arg, <2
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_smfmac_i32_16x16x64_i8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -2104,10 +2104,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_i8(ptr addrspace(1) %arg, <2
; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_smfmac_i32_16x16x64_i8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -2267,10 +2267,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_i8(ptr addrspace(1) %arg, <2
; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2299,11 +2299,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_i8(ptr addrspace(1) %arg, <2
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s20, s18
; GFX942-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2332,10 +2332,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_i8(ptr addrspace(1) %arg, <2
; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2364,11 +2364,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_i8(ptr addrspace(1) %arg, <2
; GFX950-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX950-GISEL-NEXT: s_mov_b32 s20, s18
; GFX950-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2571,10 +2571,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_bf8_bf8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_smfmac_f32_16x16x64_bf8_bf8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -2618,10 +2618,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_bf8_bf8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_smfmac_f32_16x16x64_bf8_bf8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -2782,10 +2782,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_bf8_fp8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_smfmac_f32_16x16x64_bf8_fp8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -2829,10 +2829,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_bf8_fp8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_smfmac_f32_16x16x64_bf8_fp8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -2993,10 +2993,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_fp8_bf8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_smfmac_f32_16x16x64_fp8_bf8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -3040,10 +3040,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_fp8_bf8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_smfmac_f32_16x16x64_fp8_bf8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -3204,10 +3204,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_fp8_fp8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX942-SDAG-NEXT: s_nop 1
; GFX942-SDAG-NEXT: v_smfmac_f32_16x16x64_fp8_fp8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -3251,10 +3251,10 @@ define amdgpu_kernel void @test_smfmac_i32_16x16x64_fp8_fp8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s10
; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s11
; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s12
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s13
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, s14
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_smfmac_f32_16x16x64_fp8_fp8 v[6:9], v[10:11], v[2:5], v1 cbsz:1 abid:2
@@ -3414,10 +3414,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_bf8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3446,11 +3446,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_bf8(ptr addrspace(1) %ar
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s20, s18
; GFX942-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3479,10 +3479,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_bf8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3511,11 +3511,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_bf8(ptr addrspace(1) %ar
; GFX950-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX950-GISEL-NEXT: s_mov_b32 s20, s18
; GFX950-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3717,10 +3717,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_fp8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3749,11 +3749,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_fp8(ptr addrspace(1) %ar
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s20, s18
; GFX942-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3782,10 +3782,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_fp8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3814,11 +3814,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_bf8_fp8(ptr addrspace(1) %ar
; GFX950-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX950-GISEL-NEXT: s_mov_b32 s20, s18
; GFX950-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4020,10 +4020,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_bf8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4052,11 +4052,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_bf8(ptr addrspace(1) %ar
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s20, s18
; GFX942-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4085,10 +4085,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_bf8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4117,11 +4117,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_bf8(ptr addrspace(1) %ar
; GFX950-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX950-GISEL-NEXT: s_mov_b32 s20, s18
; GFX950-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4323,10 +4323,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_fp8(ptr addrspace(1) %ar
; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4355,11 +4355,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_fp8(ptr addrspace(1) %ar
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX942-GISEL-NEXT: s_mov_b32 s20, s18
; GFX942-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4388,10 +4388,10 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_fp8(ptr addrspace(1) %ar
; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s18
; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s19
; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s20
-; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s21
; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s22
+; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -4420,11 +4420,11 @@ define amdgpu_kernel void @test_smfmac_i32_32x32x32_fp8_fp8(ptr addrspace(1) %ar
; GFX950-GISEL-NEXT: s_load_dwordx16 s[0:15], s[24:25], 0x0
; GFX950-GISEL-NEXT: s_mov_b32 s20, s18
; GFX950-GISEL-NEXT: s_mov_b32 s21, s19
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v22, s26
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
index eae7c22dcff64..049a1408f9320 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
@@ -89,8 +89,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
-; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
+; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-NEXT: v_accvgpr_write_b32 a1, s9
; AGPR-NEXT: v_accvgpr_write_b32 a2, s10
; AGPR-NEXT: v_accvgpr_write_b32 a3, s11
@@ -155,8 +155,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
; VGPR-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
-; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
+; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -286,8 +286,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0
; AGPR-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
; AGPR-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
; AGPR-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
-; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
+; AGPR-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-NEXT: v_accvgpr_write_b32 a1, s9
; AGPR-NEXT: v_accvgpr_write_b32 a2, s10
; AGPR-NEXT: v_accvgpr_write_b32 a3, s11
@@ -352,8 +352,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
; VGPR-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
-; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
+; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -687,8 +687,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd(<8 x bfloat> %arg
; AGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; AGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; AGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; AGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; AGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -744,8 +744,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd(<8 x bfloat> %arg
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; VGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; VGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; VGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -864,8 +864,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd__flags(<8 x bfloa
; AGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; AGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; AGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; AGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; AGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; AGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -921,8 +921,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd__flags(<8 x bfloa
; VGPR-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; VGPR-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; VGPR-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPR-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; VGPR-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPR-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; VGPR-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; VGPR-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -1011,8 +1011,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac(<8 x bfloat>
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; AGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; AGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -1039,8 +1039,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac(<8 x bfloat>
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -1100,8 +1100,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags(<8 x bf
; AGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; AGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; AGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; AGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; AGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; AGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; AGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -1128,8 +1128,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags(<8 x bf
; VGPR-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; VGPR-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; VGPR-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPR-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPR-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
index 1dbe1a9ee86e3..a156c56c2201a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
@@ -126,8 +126,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd(ptr addrsp
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; SDAG-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; SDAG-NEXT: s_nop 1
; SDAG-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[6:9], v[10:13], v[0:3]
@@ -144,8 +144,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd(ptr addrsp
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
-; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[0:3], v[4:7], v[8:11]
@@ -164,8 +164,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd(ptr addrsp
; HEURRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; HEURRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; HEURRC-NEXT: s_nop 1
; HEURRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[6:9], v[10:13], v[0:3]
@@ -183,8 +183,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd(ptr addrsp
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; VGPRRC-NEXT: s_nop 1
; VGPRRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[6:9], v[10:13], v[0:3]
@@ -245,8 +245,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd__flags(ptr
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; SDAG-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; SDAG-NEXT: s_nop 1
; SDAG-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[6:9], v[10:13], v[0:3] cbsz:3 abid:2 blgp:1
@@ -263,8 +263,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd__flags(ptr
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
-; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[0:3], v[4:7], v[8:11] cbsz:3 abid:2 blgp:1
@@ -283,8 +283,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd__flags(ptr
; HEURRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; HEURRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; HEURRC-NEXT: s_nop 1
; HEURRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[6:9], v[10:13], v[0:3] cbsz:3 abid:2 blgp:1
@@ -302,8 +302,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_f16_no_agpr__vgprcd__flags(ptr
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; VGPRRC-NEXT: s_nop 1
; VGPRRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[6:9], v[10:13], v[0:3] cbsz:3 abid:2 blgp:1
@@ -369,8 +369,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; SDAG-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
; SDAG-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
; SDAG-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -428,8 +428,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -437,8 +437,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
-; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[50:51], 48
+; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[32:35], v[36:39], v[0:15]
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: s_nop 10
@@ -479,8 +479,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; HEURRC-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
; HEURRC-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
; HEURRC-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
-; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
+; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_accvgpr_write_b32 a1, s9
; HEURRC-NEXT: v_accvgpr_write_b32 a2, s10
; HEURRC-NEXT: v_accvgpr_write_b32 a3, s11
@@ -545,8 +545,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16(<8 x half> %arg0, <8 x hal
; VGPRRC-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
; VGPRRC-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
; VGPRRC-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -735,8 +735,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; SDAG-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
; SDAG-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
; SDAG-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -794,8 +794,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -803,8 +803,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
-; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[50:51], 48
+; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[32:35], v[36:39], v[0:15] cbsz:2 abid:3 blgp:1
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: s_nop 10
@@ -845,8 +845,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; HEURRC-NEXT: v_mov_b64_e32 v[8:9], s[24:25]
; HEURRC-NEXT: v_mov_b64_e32 v[10:11], s[26:27]
; HEURRC-NEXT: v_mov_b64_e32 v[12:13], s[28:29]
-; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_mov_b64_e32 v[14:15], s[30:31]
+; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_accvgpr_write_b32 a1, s9
; HEURRC-NEXT: v_accvgpr_write_b32 a2, s10
; HEURRC-NEXT: v_accvgpr_write_b32 a3, s11
@@ -911,8 +911,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__flags(<8 x half> %arg0, <
; VGPRRC-NEXT: v_mov_b64_e32 v[42:43], s[26:27]
; VGPRRC-NEXT: v_mov_b64_e32 v[40:41], s[24:25]
; VGPRRC-NEXT: v_mov_b64_e32 v[46:47], s[30:31]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[44:45], s[28:29]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -1406,8 +1406,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd(<8 x half> %arg0,
; SDAG-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; SDAG-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; SDAG-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; SDAG-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; SDAG-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; SDAG-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; SDAG-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; SDAG-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; SDAG-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -1463,8 +1463,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd(<8 x half> %arg0,
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -1476,10 +1476,10 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd(<8 x half> %arg0,
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[32:35], v[36:39], v[0:15]
; GISEL-NEXT: v_mov_b64_e32 v[46:47], s[14:15]
-; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
-; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[44:45], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[48:49], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[52:53], s[20:21]
; GISEL-NEXT: global_store_dwordx4 v56, v[40:43], s[0:1] sc0 sc1
; GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -1509,8 +1509,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd(<8 x half> %arg0,
; HEURRC-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; HEURRC-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; HEURRC-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; HEURRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; HEURRC-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; HEURRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; HEURRC-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; HEURRC-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; HEURRC-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -1566,8 +1566,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd(<8 x half> %arg0,
; VGPRRC-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; VGPRRC-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; VGPRRC-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; VGPRRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPRRC-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; VGPRRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPRRC-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; VGPRRC-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; VGPRRC-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -1748,8 +1748,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd__flags(<8 x half>
; SDAG-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; SDAG-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; SDAG-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; SDAG-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; SDAG-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; SDAG-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; SDAG-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; SDAG-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; SDAG-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -1805,8 +1805,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd__flags(<8 x half>
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -1818,10 +1818,10 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd__flags(<8 x half>
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: v_mfma_f32_32x32x16_f16 v[16:31], v[32:35], v[36:39], v[0:15] cbsz:1 abid:2 blgp:3
; GISEL-NEXT: v_mov_b64_e32 v[46:47], s[14:15]
-; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
-; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[44:45], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[48:49], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[52:53], s[20:21]
; GISEL-NEXT: global_store_dwordx4 v56, v[40:43], s[0:1] sc0 sc1
; GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -1851,8 +1851,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd__flags(<8 x half>
; HEURRC-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; HEURRC-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; HEURRC-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; HEURRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; HEURRC-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; HEURRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; HEURRC-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; HEURRC-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; HEURRC-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -1908,8 +1908,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd__flags(<8 x half>
; VGPRRC-NEXT: v_mov_b64_e32 v[40:41], s[26:27]
; VGPRRC-NEXT: v_mov_b64_e32 v[38:39], s[24:25]
; VGPRRC-NEXT: v_mov_b64_e32 v[44:45], s[30:31]
-; VGPRRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPRRC-NEXT: v_mov_b64_e32 v[42:43], s[28:29]
+; VGPRRC-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; VGPRRC-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; VGPRRC-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; VGPRRC-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -2089,8 +2089,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac(<8 x half> %ar
; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; SDAG-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2117,8 +2117,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac(<8 x half> %ar
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2145,8 +2145,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac(<8 x half> %ar
; HEURRC-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; HEURRC-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; HEURRC-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; HEURRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; HEURRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2173,8 +2173,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac(<8 x half> %ar
; VGPRRC-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; VGPRRC-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; VGPRRC-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2270,8 +2270,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac_flags(<8 x hal
; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; SDAG-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2298,8 +2298,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac_flags(<8 x hal
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2326,8 +2326,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac_flags(<8 x hal
; HEURRC-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; HEURRC-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; HEURRC-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; HEURRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; HEURRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2354,8 +2354,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_f16__vgprcd_mac_flags(<8 x hal
; VGPRRC-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; VGPRRC-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; VGPRRC-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2586,8 +2586,8 @@ define amdgpu_kernel void @test_mfma_i32_16x16x64_i8_no_agpr__vgprcd(ptr addrspa
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
-; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_i32_16x16x64_i8 v[0:3], v[0:3], v[4:7], v[8:11]
@@ -2733,8 +2733,8 @@ define amdgpu_kernel void @test_mfma_i32_16x16x64_i8_no_agpr__vgprcd__flags(ptr
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
-; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_i32_16x16x64_i8 v[0:3], v[0:3], v[4:7], v[8:11] cbsz:3 abid:2 blgp:1
@@ -2864,11 +2864,11 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; SDAG-NEXT: v_mov_b32_e32 v41, s25
; SDAG-NEXT: v_mov_b32_e32 v42, s26
; SDAG-NEXT: v_mov_b32_e32 v43, s27
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b32_e32 v44, s28
; SDAG-NEXT: v_mov_b32_e32 v45, s29
; SDAG-NEXT: v_mov_b32_e32 v46, s30
; SDAG-NEXT: v_mov_b32_e32 v47, s31
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2928,8 +2928,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -2937,8 +2937,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
-; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[50:51], 48
+; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[16:31], v[32:35], v[36:39], v[0:15]
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: s_nop 10
@@ -2980,11 +2980,11 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; HEURRC-NEXT: v_mov_b32_e32 v9, s25
; HEURRC-NEXT: v_mov_b32_e32 v10, s26
; HEURRC-NEXT: v_mov_b32_e32 v11, s27
-; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_mov_b32_e32 v12, s28
; HEURRC-NEXT: v_mov_b32_e32 v13, s29
; HEURRC-NEXT: v_mov_b32_e32 v14, s30
; HEURRC-NEXT: v_mov_b32_e32 v15, s31
+; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_accvgpr_write_b32 a1, s9
; HEURRC-NEXT: v_accvgpr_write_b32 a2, s10
; HEURRC-NEXT: v_accvgpr_write_b32 a3, s11
@@ -3051,11 +3051,11 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8(<4 x i32> %arg0, <4 x i32>
; VGPRRC-NEXT: v_mov_b32_e32 v41, s25
; VGPRRC-NEXT: v_mov_b32_e32 v42, s26
; VGPRRC-NEXT: v_mov_b32_e32 v43, s27
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b32_e32 v44, s28
; VGPRRC-NEXT: v_mov_b32_e32 v45, s29
; VGPRRC-NEXT: v_mov_b32_e32 v46, s30
; VGPRRC-NEXT: v_mov_b32_e32 v47, s31
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -3259,11 +3259,11 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__flags(<4 x i32> %arg0, <4
; SDAG-NEXT: v_mov_b32_e32 v41, s25
; SDAG-NEXT: v_mov_b32_e32 v42, s26
; SDAG-NEXT: v_mov_b32_e32 v43, s27
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b32_e32 v44, s28
; SDAG-NEXT: v_mov_b32_e32 v45, s29
; SDAG-NEXT: v_mov_b32_e32 v46, s30
; SDAG-NEXT: v_mov_b32_e32 v47, s31
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -3323,8 +3323,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__flags(<4 x i32> %arg0, <4
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -3332,8 +3332,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__flags(<4 x i32> %arg0, <4
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
-; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[50:51], 48
+; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[10:11]
; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[16:31], v[32:35], v[36:39], v[0:15] cbsz:2 abid:3 blgp:1
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: s_nop 10
@@ -3375,11 +3375,11 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__flags(<4 x i32> %arg0, <4
; HEURRC-NEXT: v_mov_b32_e32 v9, s25
; HEURRC-NEXT: v_mov_b32_e32 v10, s26
; HEURRC-NEXT: v_mov_b32_e32 v11, s27
-; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_mov_b32_e32 v12, s28
; HEURRC-NEXT: v_mov_b32_e32 v13, s29
; HEURRC-NEXT: v_mov_b32_e32 v14, s30
; HEURRC-NEXT: v_mov_b32_e32 v15, s31
+; HEURRC-NEXT: v_accvgpr_write_b32 a0, s8
; HEURRC-NEXT: v_accvgpr_write_b32 a1, s9
; HEURRC-NEXT: v_accvgpr_write_b32 a2, s10
; HEURRC-NEXT: v_accvgpr_write_b32 a3, s11
@@ -3446,11 +3446,11 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__flags(<4 x i32> %arg0, <4
; VGPRRC-NEXT: v_mov_b32_e32 v41, s25
; VGPRRC-NEXT: v_mov_b32_e32 v42, s26
; VGPRRC-NEXT: v_mov_b32_e32 v43, s27
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b32_e32 v44, s28
; VGPRRC-NEXT: v_mov_b32_e32 v45, s29
; VGPRRC-NEXT: v_mov_b32_e32 v46, s30
; VGPRRC-NEXT: v_mov_b32_e32 v47, s31
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -4022,8 +4022,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd(<4 x i32> %arg0, <4
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -4035,10 +4035,10 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd(<4 x i32> %arg0, <4
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[16:31], v[32:35], v[36:39], v[0:15]
; GISEL-NEXT: v_mov_b64_e32 v[46:47], s[14:15]
-; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
-; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[44:45], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[48:49], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[52:53], s[20:21]
; GISEL-NEXT: global_store_dwordx4 v56, v[40:43], s[0:1] sc0 sc1
; GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -4399,8 +4399,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd__flags(<4 x i32> %a
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[30:31]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[28:29]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -4412,10 +4412,10 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd__flags(<4 x i32> %a
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[8:9]
; GISEL-NEXT: v_mfma_i32_32x32x32_i8 v[16:31], v[32:35], v[36:39], v[0:15] cbsz:1 abid:2 blgp:3
; GISEL-NEXT: v_mov_b64_e32 v[46:47], s[14:15]
-; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
-; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[44:45], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[50:51], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[48:49], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[54:55], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[52:53], s[20:21]
; GISEL-NEXT: global_store_dwordx4 v56, v[40:43], s[0:1] sc0 sc1
; GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -4744,8 +4744,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd_mac(<4 x i32> %arg0
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -4950,8 +4950,8 @@ define amdgpu_kernel void @test_mfma_i32_32x32x32_i8__vgprcd_mac_flags(<4 x i32>
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -5234,8 +5234,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd(ptr addrs
; GCN-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; GCN-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; GCN-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GCN-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GCN-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GCN-NEXT: s_nop 1
; GCN-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[6:9], v[10:13], v[0:3]
@@ -5253,8 +5253,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd(ptr addrs
; HEURRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; HEURRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; HEURRC-NEXT: s_nop 1
; HEURRC-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[6:9], v[10:13], v[0:3]
@@ -5272,8 +5272,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd(ptr addrs
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; VGPRRC-NEXT: s_nop 1
; VGPRRC-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[6:9], v[10:13], v[0:3]
@@ -5334,8 +5334,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd__flags(pt
; GCN-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; GCN-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; GCN-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GCN-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; GCN-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GCN-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GCN-NEXT: s_nop 1
; GCN-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[6:9], v[10:13], v[0:3] cbsz:3 abid:2 blgp:1
@@ -5353,8 +5353,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd__flags(pt
; HEURRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; HEURRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; HEURRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; HEURRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; HEURRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; HEURRC-NEXT: s_nop 1
; HEURRC-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[6:9], v[10:13], v[0:3] cbsz:3 abid:2 blgp:1
@@ -5372,8 +5372,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x32_bf16_no_agpr__vgprcd__flags(pt
; VGPRRC-NEXT: v_mov_b64_e32 v[6:7], s[8:9]
; VGPRRC-NEXT: v_mov_b64_e32 v[8:9], s[10:11]
; VGPRRC-NEXT: v_mov_b64_e32 v[10:11], s[12:13]
-; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[12:13], s[14:15]
+; VGPRRC-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; VGPRRC-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; VGPRRC-NEXT: s_nop 1
; VGPRRC-NEXT: v_mfma_f32_16x16x32_bf16 v[0:3], v[6:9], v[10:13], v[0:3] cbsz:3 abid:2 blgp:1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
index 4d1684467e7f5..ff42d70bb5125 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
@@ -2762,9 +2762,9 @@ define amdgpu_kernel void @test_mfma_f32_16x16x4f16(ptr addrspace(1) %arg, ptr a
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v16, s20
; GFX90A-NEXT: v_mov_b32_e32 v17, s21
-; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: v_mov_b32_e32 v18, s22
; GFX90A-NEXT: v_mov_b32_e32 v19, s23
+; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
@@ -2790,8 +2790,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x4f16(ptr addrspace(1) %arg, ptr a
; GFX90A-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[16:17], s[20:21], s[20:21] op_sel:[0,1]
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[18:19], s[22:23], s[22:23] op_sel:[0,1]
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
@@ -2818,9 +2818,9 @@ define amdgpu_kernel void @test_mfma_f32_16x16x4f16(ptr addrspace(1) %arg, ptr a
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v16, s20
; GFX942-NEXT: v_mov_b32_e32 v17, s21
-; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-NEXT: v_mov_b32_e32 v18, s22
; GFX942-NEXT: v_mov_b32_e32 v19, s23
+; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2846,8 +2846,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x4f16(ptr addrspace(1) %arg, ptr a
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2874,9 +2874,9 @@ define amdgpu_kernel void @test_mfma_f32_16x16x4f16(ptr addrspace(1) %arg, ptr a
; GFX942-VGPR-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-NEXT: v_mov_b32_e32 v16, s20
; GFX942-VGPR-NEXT: v_mov_b32_e32 v17, s21
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-NEXT: v_mov_b32_e32 v18, s22
; GFX942-VGPR-NEXT: v_mov_b32_e32 v19, s23
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2902,8 +2902,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x4f16(ptr addrspace(1) %arg, ptr a
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-VGPR-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -2976,10 +2976,10 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg, ptr add
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a0, v5
; GFX908-GISEL-NEXT: v_mov_b32_e32 v6, s10
; GFX908-GISEL-NEXT: v_mov_b32_e32 v5, s11
-; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a1, v4
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a2, v6
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a3, v5
+; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX908-GISEL-NEXT: v_mov_b32_e32 v3, s7
; GFX908-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX908-GISEL-NEXT: s_nop 0
@@ -3034,9 +3034,9 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg, ptr add
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v6, s4
; GFX90A-NEXT: v_mov_b32_e32 v7, s5
-; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT: v_mov_b32_e32 v8, s6
; GFX90A-NEXT: v_mov_b32_e32 v9, s7
+; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-NEXT: s_nop 1
; GFX90A-NEXT: v_mfma_f32_4x4x4f16 v[0:3], v[6:7], v[8:9], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3052,8 +3052,8 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg, ptr add
; GFX90A-GISEL-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x0
; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_f32_4x4x4f16 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3072,9 +3072,9 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg, ptr add
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v6, s4
; GFX942-NEXT: v_mov_b32_e32 v7, s5
-; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-NEXT: v_mov_b32_e32 v8, s6
; GFX942-NEXT: v_mov_b32_e32 v9, s7
+; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mfma_f32_4x4x4_16b_f16 v[0:3], v[6:7], v[8:9], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3090,8 +3090,8 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg, ptr add
; GFX942-GISEL-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x0
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_4x4x4_16b_f16 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3110,9 +3110,9 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg, ptr add
; GFX942-VGPR-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-NEXT: v_mov_b32_e32 v6, s4
; GFX942-VGPR-NEXT: v_mov_b32_e32 v7, s5
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-NEXT: v_mov_b32_e32 v8, s6
; GFX942-VGPR-NEXT: v_mov_b32_e32 v9, s7
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-NEXT: s_nop 1
; GFX942-VGPR-NEXT: v_mfma_f32_4x4x4_16b_f16 v[0:3], v[6:7], v[8:9], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3128,8 +3128,8 @@ define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg, ptr add
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x0
; GFX942-VGPR-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_f32_4x4x4_16b_f16 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3367,9 +3367,9 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16(ptr addrspace(1) %arg, ptr a
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v16, s20
; GFX90A-NEXT: v_mov_b32_e32 v17, s21
-; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: v_mov_b32_e32 v18, s22
; GFX90A-NEXT: v_mov_b32_e32 v19, s23
+; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
@@ -3396,8 +3396,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16(ptr addrspace(1) %arg, ptr a
; GFX90A-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[16:17], s[20:21], s[20:21] op_sel:[0,1]
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[18:19], s[22:23], s[22:23] op_sel:[0,1]
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
@@ -3425,9 +3425,9 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16(ptr addrspace(1) %arg, ptr a
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v16, s20
; GFX942-NEXT: v_mov_b32_e32 v17, s21
-; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-NEXT: v_mov_b32_e32 v18, s22
; GFX942-NEXT: v_mov_b32_e32 v19, s23
+; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3453,8 +3453,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16(ptr addrspace(1) %arg, ptr a
; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3481,9 +3481,9 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16(ptr addrspace(1) %arg, ptr a
; GFX942-VGPR-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-NEXT: v_mov_b32_e32 v16, s20
; GFX942-VGPR-NEXT: v_mov_b32_e32 v17, s21
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-NEXT: v_mov_b32_e32 v18, s22
; GFX942-VGPR-NEXT: v_mov_b32_e32 v19, s23
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3509,8 +3509,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16(ptr addrspace(1) %arg, ptr a
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
; GFX942-VGPR-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[20:21]
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[22:23]
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
@@ -3583,10 +3583,10 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg, ptr
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a0, v5
; GFX908-GISEL-NEXT: v_mov_b32_e32 v6, s10
; GFX908-GISEL-NEXT: v_mov_b32_e32 v5, s11
-; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a1, v4
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a2, v6
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a3, v5
+; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX908-GISEL-NEXT: v_mov_b32_e32 v3, s7
; GFX908-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX908-GISEL-NEXT: s_nop 0
@@ -3641,9 +3641,9 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg, ptr
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v6, s4
; GFX90A-NEXT: v_mov_b32_e32 v7, s5
-; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT: v_mov_b32_e32 v8, s6
; GFX90A-NEXT: v_mov_b32_e32 v9, s7
+; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-NEXT: s_nop 1
; GFX90A-NEXT: v_mfma_f32_16x16x16f16 v[0:3], v[6:7], v[8:9], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3659,8 +3659,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg, ptr
; GFX90A-GISEL-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x0
; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_f32_16x16x16f16 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3679,9 +3679,9 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg, ptr
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v6, s4
; GFX942-NEXT: v_mov_b32_e32 v7, s5
-; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-NEXT: v_mov_b32_e32 v8, s6
; GFX942-NEXT: v_mov_b32_e32 v9, s7
+; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[6:7], v[8:9], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3697,8 +3697,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg, ptr
; GFX942-GISEL-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x0
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3717,9 +3717,9 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg, ptr
; GFX942-VGPR-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-NEXT: v_mov_b32_e32 v6, s4
; GFX942-VGPR-NEXT: v_mov_b32_e32 v7, s5
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-NEXT: v_mov_b32_e32 v8, s6
; GFX942-VGPR-NEXT: v_mov_b32_e32 v9, s7
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-NEXT: s_nop 1
; GFX942-VGPR-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[6:7], v[8:9], v[0:3] cbsz:1 abid:2 blgp:3
@@ -3735,8 +3735,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg, ptr
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x0
; GFX942-VGPR-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[4:5], v[6:7], v[0:3] cbsz:1 abid:2 blgp:3
@@ -4966,8 +4966,8 @@ define amdgpu_kernel void @test_mfma_i32_16x16x4i8_splatimm_src2_64(ptr addrspac
; GFX90A-GISEL-NEXT: s_mov_b32 s21, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s22, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v17, 2
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[12:13], s[12:13] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[14:15], s[14:15] op_sel:[0,1]
@@ -5022,8 +5022,8 @@ define amdgpu_kernel void @test_mfma_i32_16x16x4i8_splatimm_src2_64(ptr addrspac
; GFX942-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-GISEL-NEXT: s_mov_b32 s22, s8
; GFX942-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v17, 2
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -5078,8 +5078,8 @@ define amdgpu_kernel void @test_mfma_i32_16x16x4i8_splatimm_src2_64(ptr addrspac
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s22, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v17, 2
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -5302,11 +5302,11 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_imm_src2_1(ptr addrspace(
; NOLIT-SRCC-LABEL: test_mfma_i32_4x4x4i8_splat_imm_src2_1:
; NOLIT-SRCC: ; %bb.0: ; %bb
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v0, 1
+; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a0, 1
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a1, 1
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a2, 1
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a3, 1
-; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, 2
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
; NOLIT-SRCC-NEXT: s_nop 0
@@ -5324,11 +5324,11 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_imm_src2_1(ptr addrspace(
; GFX908-GISEL-NOLIT-SRCC-LABEL: test_mfma_i32_4x4x4i8_splat_imm_src2_1:
; GFX908-GISEL-NOLIT-SRCC: ; %bb.0: ; %bb
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v0, 1
+; GFX908-GISEL-NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a0, 1
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a1, 1
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a2, 1
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a3, 1
-; GFX908-GISEL-NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, 2
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
; GFX908-GISEL-NOLIT-SRCC-NEXT: s_nop 0
@@ -5364,9 +5364,10 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_imm_src2_1(ptr addrspace(
; GFX908-GISEL-LIT-SRCC-LABEL: test_mfma_i32_4x4x4i8_splat_imm_src2_1:
; GFX908-GISEL-LIT-SRCC: ; %bb.0: ; %bb
; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v0, 1
-; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v1, 2
; GFX908-GISEL-LIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v1, 2
; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
+; GFX908-GISEL-LIT-SRCC-NEXT: s_nop 0
; GFX908-GISEL-LIT-SRCC-NEXT: v_mfma_i32_4x4x4i8 a[0:3], v0, v1, 1 cbsz:1 abid:2 blgp:3
; GFX908-GISEL-LIT-SRCC-NEXT: s_nop 3
; GFX908-GISEL-LIT-SRCC-NEXT: v_accvgpr_read_b32 v0, a0
@@ -5395,12 +5396,12 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_imm_src2_1(ptr addrspace(
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v4, 1
; GFX90A-GISEL-NEXT: s_mov_b32 s0, 1
-; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s2, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v5, 2
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_i32_4x4x4i8 v[0:3], v4, v5, v[0:3] cbsz:1 abid:2 blgp:3
@@ -5427,12 +5428,12 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_imm_src2_1(ptr addrspace(
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 1
; GFX942-GISEL-NEXT: s_mov_b32 s0, 1
-; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, 2
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_i32_4x4x4_16b_i8 v[0:3], v4, v5, v[0:3] cbsz:1 abid:2 blgp:3
@@ -5459,12 +5460,12 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_imm_src2_1(ptr addrspace(
; GFX942-VGPR-GISEL: ; %bb.0: ; %bb
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v4, 1
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s0, 1
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v5, 2
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_i32_4x4x4_16b_i8 v[0:3], v4, v5, v[0:3] cbsz:1 abid:2 blgp:3
@@ -5513,10 +5514,10 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_k_src2_1(ptr addrspace(1)
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a0, v5
; GFX908-GISEL-NEXT: v_mov_b32_e32 v3, s2
; GFX908-GISEL-NEXT: v_mov_b32_e32 v5, s2
+; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a1, v2
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a2, v3
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a3, v5
-; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX908-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX908-GISEL-NEXT: s_nop 0
@@ -5575,12 +5576,12 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_k_src2_1(ptr addrspace(1)
; GFX90A-GISEL: ; %bb.0:
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v4, 1
; GFX90A-GISEL-NEXT: s_movk_i32 s0, 0x41
-; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s2, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v5, 2
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_i32_4x4x4i8 v[0:3], v4, v5, v[0:3] cbsz:1 abid:2 blgp:3
@@ -5611,12 +5612,12 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_k_src2_1(ptr addrspace(1)
; GFX942-GISEL: ; %bb.0:
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 1
; GFX942-GISEL-NEXT: s_movk_i32 s0, 0x41
-; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, 2
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_i32_4x4x4_16b_i8 v[0:3], v4, v5, v[0:3] cbsz:1 abid:2 blgp:3
@@ -5647,12 +5648,12 @@ define amdgpu_kernel void @test_mfma_i32_4x4x4i8_splat_k_src2_1(ptr addrspace(1)
; GFX942-VGPR-GISEL: ; %bb.0:
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v4, 1
; GFX942-VGPR-GISEL-NEXT: s_movk_i32 s0, 0x41
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v5, 2
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_i32_4x4x4_16b_i8 v[0:3], v4, v5, v[0:3] cbsz:1 abid:2 blgp:3
@@ -6944,11 +6945,11 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm_splat(ptr addrspace(1) %ar
; NOLIT-SRCC-LABEL: test_mfma_f32_4x4x1f32_imm_splat:
; NOLIT-SRCC: ; %bb.0: ; %bb
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v0, 1.0
+; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a0, 1.0
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a1, 1.0
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a2, 1.0
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a3, 1.0
-; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
; NOLIT-SRCC-NEXT: s_nop 0
@@ -6966,11 +6967,11 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm_splat(ptr addrspace(1) %ar
; GFX908-GISEL-NOLIT-SRCC-LABEL: test_mfma_f32_4x4x1f32_imm_splat:
; GFX908-GISEL-NOLIT-SRCC: ; %bb.0: ; %bb
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX908-GISEL-NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a0, 1.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a1, 1.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a2, 1.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a3, 1.0
-; GFX908-GISEL-NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
; GFX908-GISEL-NOLIT-SRCC-NEXT: s_nop 0
@@ -7006,9 +7007,10 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm_splat(ptr addrspace(1) %ar
; GFX908-GISEL-LIT-SRCC-LABEL: test_mfma_f32_4x4x1f32_imm_splat:
; GFX908-GISEL-LIT-SRCC: ; %bb.0: ; %bb
; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v0, 1.0
-; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; GFX908-GISEL-LIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; GFX908-GISEL-LIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
+; GFX908-GISEL-LIT-SRCC-NEXT: s_nop 0
; GFX908-GISEL-LIT-SRCC-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v0, v1, 1.0
; GFX908-GISEL-LIT-SRCC-NEXT: s_nop 3
; GFX908-GISEL-LIT-SRCC-NEXT: v_accvgpr_read_b32 v0, a0
@@ -7037,12 +7039,12 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm_splat(ptr addrspace(1) %ar
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX90A-GISEL-NEXT: s_mov_b32 s0, 1.0
-; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s2, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_f32_4x4x1f32 v[0:3], v4, v5, v[0:3]
@@ -7069,12 +7071,12 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm_splat(ptr addrspace(1) %ar
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s0, 1.0
-; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v5, v[0:3]
@@ -7101,12 +7103,12 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm_splat(ptr addrspace(1) %ar
; GFX942-VGPR-GISEL: ; %bb.0: ; %bb
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s0, 1.0
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v5, v[0:3]
@@ -7323,8 +7325,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm_splat(ptr addrspace(1) %
; GFX90A-GISEL-NEXT: s_mov_b32 s21, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s22, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v17, 2.0
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[12:13], s[12:13] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[14:15], s[14:15] op_sel:[0,1]
@@ -7379,8 +7381,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm_splat(ptr addrspace(1) %
; GFX942-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-GISEL-NEXT: s_mov_b32 s22, s8
; GFX942-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v17, 2.0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -7435,8 +7437,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm_splat(ptr addrspace(1) %
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s22, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v17, 2.0
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -7527,7 +7529,6 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, s1
; GFX908-GISEL-NOLIT-SRCC-NEXT: s_mov_b32 s2, 0x40004000
; GFX908-GISEL-NOLIT-SRCC-NEXT: s_mov_b32 s3, s2
-; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v2, s2
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a0, 1.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a1, 1.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a2, 1.0
@@ -7544,6 +7545,7 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a13, 1.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a14, 1.0
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a15, 1.0
+; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v2, s2
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v3, s3
; GFX908-GISEL-NOLIT-SRCC-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX908-GISEL-NOLIT-SRCC-NEXT: v_mov_b32_e32 v16, 0
@@ -7671,10 +7673,10 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX90A-GISEL-NEXT: s_mov_b32 s0, 0x3c003c00
; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[16:17], s[0:1], s[0:1] op_sel:[0,1]
-; GFX90A-GISEL-NEXT: s_mov_b32 s8, 1.0
; GFX90A-GISEL-NEXT: s_mov_b32 s2, 0x40004000
-; GFX90A-GISEL-NEXT: s_mov_b32 s9, s8
+; GFX90A-GISEL-NEXT: s_mov_b32 s8, 1.0
; GFX90A-GISEL-NEXT: s_mov_b32 s3, s2
+; GFX90A-GISEL-NEXT: s_mov_b32 s9, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s10, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s11, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s12, s8
@@ -7689,8 +7691,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX90A-GISEL-NEXT: s_mov_b32 s21, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s22, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[18:19], s[2:3], s[2:3] op_sel:[0,1]
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[12:13], s[12:13] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[14:15], s[14:15] op_sel:[0,1]
@@ -7734,10 +7736,10 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX942-GISEL-NEXT: s_mov_b32 s0, 0x3c003c00
; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
-; GFX942-GISEL-NEXT: s_mov_b32 s8, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s2, 0x40004000
-; GFX942-GISEL-NEXT: s_mov_b32 s9, s8
+; GFX942-GISEL-NEXT: s_mov_b32 s8, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s3, s2
+; GFX942-GISEL-NEXT: s_mov_b32 s9, s8
; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
; GFX942-GISEL-NEXT: s_mov_b32 s11, s8
; GFX942-GISEL-NEXT: s_mov_b32 s12, s8
@@ -7752,8 +7754,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX942-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-GISEL-NEXT: s_mov_b32 s22, s8
; GFX942-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -7796,10 +7798,10 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s0, 0x3c003c00
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s8, 1.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s2, 0x40004000
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s9, s8
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s8, 1.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s3, s2
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s9, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s10, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s11, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s12, s8
@@ -7814,8 +7816,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x8f16_imm_splat(ptr addrspace(1) %
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s22, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s23, s8
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -8263,11 +8265,11 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm(ptr addrspace(1) %arg) #0
; NOLIT-SRCC-LABEL: test_mfma_f32_4x4x1f32_imm:
; NOLIT-SRCC: ; %bb.0: ; %bb
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v0, 1.0
+; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a0, 1.0
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a1, 2.0
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a2, 1.0
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a3, 1.0
-; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
; NOLIT-SRCC-NEXT: s_nop 0
@@ -8285,11 +8287,11 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm(ptr addrspace(1) %arg) #0
; GFX908-GISEL-LABEL: test_mfma_f32_4x4x1f32_imm:
; GFX908-GISEL: ; %bb.0: ; %bb
; GFX908-GISEL-NEXT: v_mov_b32_e32 v0, 1.0
+; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a0, 1.0
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a1, 2.0
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a2, 1.0
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a3, 1.0
-; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, 2.0
; GFX908-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX908-GISEL-NEXT: s_nop 0
@@ -8307,11 +8309,11 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm(ptr addrspace(1) %arg) #0
; LIT-SRCC-LABEL: test_mfma_f32_4x4x1f32_imm:
; LIT-SRCC: ; %bb.0: ; %bb
; LIT-SRCC-NEXT: v_mov_b32_e32 v0, 1.0
+; LIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a0, 1.0
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a1, 2.0
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a2, 1.0
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a3, 1.0
-; LIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; LIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; LIT-SRCC-NEXT: v_mov_b32_e32 v4, 0
; LIT-SRCC-NEXT: s_nop 0
@@ -8344,13 +8346,13 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm(ptr addrspace(1) %arg) #0
; GFX90A-GISEL-LABEL: test_mfma_f32_4x4x1f32_imm:
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
-; GFX90A-GISEL-NEXT: s_mov_b32 s1, 2.0
; GFX90A-GISEL-NEXT: s_mov_b32 s0, 1.0
; GFX90A-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_mov_b32 s1, 2.0
; GFX90A-GISEL-NEXT: s_mov_b32 s2, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_f32_4x4x1f32 v[0:3], v4, v5, v[0:3]
@@ -8378,13 +8380,13 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm(ptr addrspace(1) %arg) #0
; GFX942-GISEL-LABEL: test_mfma_f32_4x4x1f32_imm:
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
-; GFX942-GISEL-NEXT: s_mov_b32 s1, 2.0
; GFX942-GISEL-NEXT: s_mov_b32 s0, 1.0
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_mov_b32 s1, 2.0
; GFX942-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v5, v[0:3]
@@ -8412,13 +8414,13 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_imm(ptr addrspace(1) %arg) #0
; GFX942-VGPR-GISEL-LABEL: test_mfma_f32_4x4x1f32_imm:
; GFX942-VGPR-GISEL: ; %bb.0: ; %bb
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, 2.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s0, 1.0
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, 2.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v5, v[0:3]
@@ -8622,8 +8624,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm(ptr addrspace(1) %arg) #
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v16, 1.0
; GFX90A-GISEL-NEXT: s_mov_b32 s8, 1.0
-; GFX90A-GISEL-NEXT: s_mov_b32 s9, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s23, 2.0
+; GFX90A-GISEL-NEXT: s_mov_b32 s9, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s10, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s11, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s12, s8
@@ -8637,8 +8639,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm(ptr addrspace(1) %arg) #
; GFX90A-GISEL-NEXT: s_mov_b32 s20, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s21, s8
; GFX90A-GISEL-NEXT: s_mov_b32 s22, s8
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v17, 2.0
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[12:13], s[12:13] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[14:15], s[14:15] op_sel:[0,1]
@@ -8691,8 +8693,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: v_mov_b32_e32 v16, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s8, 1.0
-; GFX942-GISEL-NEXT: s_mov_b32 s9, s8
; GFX942-GISEL-NEXT: s_mov_b32 s23, 2.0
+; GFX942-GISEL-NEXT: s_mov_b32 s9, s8
; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
; GFX942-GISEL-NEXT: s_mov_b32 s11, s8
; GFX942-GISEL-NEXT: s_mov_b32 s12, s8
@@ -8706,8 +8708,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-GISEL-NEXT: s_mov_b32 s20, s8
; GFX942-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-GISEL-NEXT: s_mov_b32 s22, s8
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v17, 2.0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -8760,8 +8762,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-VGPR-GISEL: ; %bb.0: ; %bb
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v16, 1.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s8, 1.0
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s9, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s23, 2.0
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s9, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s10, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s11, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s12, s8
@@ -8775,8 +8777,8 @@ define amdgpu_kernel void @test_mfma_f32_16x16x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s20, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s21, s8
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s22, s8
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v17, 2.0
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -9118,8 +9120,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_imm(ptr addrspace(1) %arg) #
; GFX90A-NEXT: v_mov_b32_e32 v29, v1
; GFX90A-NEXT: v_mov_b32_e32 v30, v1
; GFX90A-NEXT: v_mov_b32_e32 v31, v1
-; GFX90A-NEXT: v_pk_mov_b32 v[32:33], v[30:31], v[30:31] op_sel:[0,1]
; GFX90A-NEXT: v_mov_b32_e32 v34, 2.0
+; GFX90A-NEXT: v_pk_mov_b32 v[32:33], v[30:31], v[30:31] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[30:31], v[28:29], v[28:29] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[28:29], v[26:27], v[26:27] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[26:27], v[24:25], v[24:25] op_sel:[0,1]
@@ -9186,8 +9188,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_imm(ptr addrspace(1) %arg) #
; GFX90A-GISEL-NEXT: s_mov_b32 s65, s37
; GFX90A-GISEL-NEXT: s_mov_b32 s66, s37
; GFX90A-GISEL-NEXT: s_mov_b32 s67, s37
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[36:37], s[36:37] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v33, 2.0
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[36:37], s[36:37] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[38:39], s[38:39] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[40:41], s[40:41] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[42:43], s[42:43] op_sel:[0,1]
@@ -9254,8 +9256,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-NEXT: v_mov_b32_e32 v29, v1
; GFX942-NEXT: v_mov_b32_e32 v30, v1
; GFX942-NEXT: v_mov_b32_e32 v31, v1
-; GFX942-NEXT: v_mov_b64_e32 v[32:33], v[30:31]
; GFX942-NEXT: v_mov_b32_e32 v34, 2.0
+; GFX942-NEXT: v_mov_b64_e32 v[32:33], v[30:31]
; GFX942-NEXT: v_mov_b64_e32 v[30:31], v[28:29]
; GFX942-NEXT: v_mov_b64_e32 v[28:29], v[26:27]
; GFX942-NEXT: v_mov_b64_e32 v[26:27], v[24:25]
@@ -9322,8 +9324,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-GISEL-NEXT: s_mov_b32 s65, s37
; GFX942-GISEL-NEXT: s_mov_b32 s66, s37
; GFX942-GISEL-NEXT: s_mov_b32 s67, s37
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v33, 2.0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -9389,8 +9391,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-VGPR-NEXT: v_mov_b32_e32 v29, v1
; GFX942-VGPR-NEXT: v_mov_b32_e32 v30, v1
; GFX942-VGPR-NEXT: v_mov_b32_e32 v31, v1
-; GFX942-VGPR-NEXT: v_mov_b64_e32 v[32:33], v[30:31]
; GFX942-VGPR-NEXT: v_mov_b32_e32 v34, 2.0
+; GFX942-VGPR-NEXT: v_mov_b64_e32 v[32:33], v[30:31]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[30:31], v[28:29]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[28:29], v[26:27]
; GFX942-VGPR-NEXT: v_mov_b64_e32 v[26:27], v[24:25]
@@ -9457,8 +9459,8 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_imm(ptr addrspace(1) %arg) #
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s65, s37
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s66, s37
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s67, s37
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v33, 2.0
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -9501,11 +9503,11 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat(ptr addrspace(1) %ar
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, 0x42f60000
; NOLIT-SRCC-NEXT: v_lshlrev_b32_e32 v4, 4, v0
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v0, 1.0
+; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a0, v1
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a1, v1
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a2, v1
; NOLIT-SRCC-NEXT: v_accvgpr_write_b32 a3, v1
-; NOLIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; NOLIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; NOLIT-SRCC-NEXT: s_nop 1
; NOLIT-SRCC-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v0, v1, a[0:3]
@@ -9529,10 +9531,10 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat(ptr addrspace(1) %ar
; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX908-GISEL-NEXT: v_mov_b32_e32 v3, s2
; GFX908-GISEL-NEXT: v_mov_b32_e32 v5, s2
+; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a1, v2
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a2, v3
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a3, v5
-; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, 2.0
; GFX908-GISEL-NEXT: s_nop 1
; GFX908-GISEL-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v0, v1, a[0:3]
@@ -9551,11 +9553,11 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat(ptr addrspace(1) %ar
; LIT-SRCC-NEXT: v_mov_b32_e32 v1, 0x42f60000
; LIT-SRCC-NEXT: v_lshlrev_b32_e32 v4, 4, v0
; LIT-SRCC-NEXT: v_mov_b32_e32 v0, 1.0
+; LIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a0, v1
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a1, v1
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a2, v1
; LIT-SRCC-NEXT: v_accvgpr_write_b32 a3, v1
-; LIT-SRCC-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; LIT-SRCC-NEXT: v_mov_b32_e32 v1, 2.0
; LIT-SRCC-NEXT: s_nop 1
; LIT-SRCC-NEXT: v_mfma_f32_4x4x1f32 a[0:3], v0, v1, a[0:3]
@@ -9591,14 +9593,14 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat(ptr addrspace(1) %ar
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX90A-GISEL-NEXT: s_mov_b32 s0, 0x42f60000
-; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s2, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s3, s0
+; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v5, 4, v0
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v6, 2.0
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_f32_4x4x1f32 v[0:3], v4, v6, v[0:3]
@@ -9629,14 +9631,14 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat(ptr addrspace(1) %ar
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s0, 0x42f60000
-; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-GISEL-NEXT: s_mov_b32 s3, s0
+; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v5, 4, v0
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v6, 2.0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v6, v[0:3]
@@ -9667,14 +9669,14 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat(ptr addrspace(1) %ar
; GFX942-VGPR-GISEL: ; %bb.0: ; %bb
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s0, 0x42f60000
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX942-VGPR-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s3, s0
+; GFX942-VGPR-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX942-VGPR-GISEL-NEXT: v_lshlrev_b32_e32 v5, 4, v0
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v6, 2.0
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v6, v[0:3]
@@ -9724,10 +9726,10 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat_bad_code(ptr addrspa
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a0, v5
; GFX908-GISEL-NEXT: v_mov_b32_e32 v3, s2
; GFX908-GISEL-NEXT: v_mov_b32_e32 v5, s2
+; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a1, v2
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a2, v3
; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a3, v5
-; GFX908-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, 2.0
; GFX908-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX908-GISEL-NEXT: s_nop 0
@@ -9786,12 +9788,12 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat_bad_code(ptr addrspa
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX90A-GISEL-NEXT: s_mov_b32 s0, 0x42f60000
-; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_mov_b32 s1, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s2, s0
; GFX90A-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: s_nop 1
; GFX90A-GISEL-NEXT: v_mfma_f32_4x4x1f32 v[0:3], v4, v5, v[0:3]
@@ -9822,12 +9824,12 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat_bad_code(ptr addrspa
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-GISEL-NEXT: s_mov_b32 s0, 0x42f60000
-; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v5, v[0:3]
@@ -9858,12 +9860,12 @@ define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat_bad_code(ptr addrspa
; GFX942-VGPR-GISEL: ; %bb.0: ; %bb
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v4, 1.0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s0, 0x42f60000
-; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s1, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s2, s0
; GFX942-VGPR-GISEL-NEXT: s_mov_b32 s3, s0
-; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b32_e32 v5, 2.0
+; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-VGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-VGPR-GISEL-NEXT: s_nop 1
; GFX942-VGPR-GISEL-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v4, v5, v[0:3]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
index f085403e39634..c8fcaf70d2d58 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
@@ -1861,10 +1861,10 @@ define <4 x float> @test_mfma_scale_f32_16x16x128_f8f6f4_0_0_sgprs(<8 x i32> inr
; GISEL-NEXT: v_readfirstlane_b32 s30, v0
; GISEL-NEXT: v_readfirstlane_b32 s31, v1
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[28:29]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[30:31]
; GISEL-NEXT: v_readlane_b32 s30, v24, 0
; GISEL-NEXT: v_readlane_b32 s31, v24, 1
@@ -2555,10 +2555,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd(<8 x i32
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; GISEL-NEXT: v_mov_b32_e32 v20, s28
; GISEL-NEXT: v_mov_b32_e32 v21, s29
@@ -2614,10 +2614,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd(<8 x i32
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[24:25]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[26:27]
; AGPR-GISEL-NEXT: v_mov_b32_e32 v20, s28
; AGPR-GISEL-NEXT: v_mov_b32_e32 v21, s29
@@ -2650,7 +2650,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v5, s13
; SDAG-NEXT: v_mov_b32_e32 v6, s14
; SDAG-NEXT: v_mov_b32_e32 v7, s15
-; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b32_e32 v8, s16
; SDAG-NEXT: v_mov_b32_e32 v9, s17
; SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -2659,6 +2658,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v13, s21
; SDAG-NEXT: v_mov_b32_e32 v14, s22
; SDAG-NEXT: v_mov_b32_e32 v15, s23
+; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; SDAG-NEXT: s_nop 1
; SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2679,10 +2679,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2708,7 +2708,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v5, s13
; AGPR-SDAG-NEXT: v_mov_b32_e32 v6, s14
; AGPR-SDAG-NEXT: v_mov_b32_e32 v7, s15
-; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b32_e32 v8, s16
; AGPR-SDAG-NEXT: v_mov_b32_e32 v9, s17
; AGPR-SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -2717,6 +2716,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v13, s21
; AGPR-SDAG-NEXT: v_mov_b32_e32 v14, s22
; AGPR-SDAG-NEXT: v_mov_b32_e32 v15, s23
+; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-SDAG-NEXT: s_nop 1
; AGPR-SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2737,10 +2737,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-GISEL-NEXT: s_nop 1
; AGPR-GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2771,7 +2771,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v5, s13
; SDAG-NEXT: v_mov_b32_e32 v6, s14
; SDAG-NEXT: v_mov_b32_e32 v7, s15
-; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b32_e32 v8, s16
; SDAG-NEXT: v_mov_b32_e32 v9, s17
; SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -2780,6 +2779,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v13, s21
; SDAG-NEXT: v_mov_b32_e32 v14, s22
; SDAG-NEXT: v_mov_b32_e32 v15, s23
+; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; SDAG-NEXT: s_nop 1
; SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2800,10 +2800,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2829,7 +2829,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v5, s13
; AGPR-SDAG-NEXT: v_mov_b32_e32 v6, s14
; AGPR-SDAG-NEXT: v_mov_b32_e32 v7, s15
-; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b32_e32 v8, s16
; AGPR-SDAG-NEXT: v_mov_b32_e32 v9, s17
; AGPR-SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -2838,6 +2837,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v13, s21
; AGPR-SDAG-NEXT: v_mov_b32_e32 v14, s22
; AGPR-SDAG-NEXT: v_mov_b32_e32 v15, s23
+; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-SDAG-NEXT: s_nop 1
; AGPR-SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2858,10 +2858,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-GISEL-NEXT: s_nop 1
; AGPR-GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2892,7 +2892,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v5, s13
; SDAG-NEXT: v_mov_b32_e32 v6, s14
; SDAG-NEXT: v_mov_b32_e32 v7, s15
-; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b32_e32 v8, s16
; SDAG-NEXT: v_mov_b32_e32 v9, s17
; SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -2901,6 +2900,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v13, s21
; SDAG-NEXT: v_mov_b32_e32 v14, s22
; SDAG-NEXT: v_mov_b32_e32 v15, s23
+; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; SDAG-NEXT: s_nop 1
; SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2921,10 +2921,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2950,7 +2950,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v5, s13
; AGPR-SDAG-NEXT: v_mov_b32_e32 v6, s14
; AGPR-SDAG-NEXT: v_mov_b32_e32 v7, s15
-; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b32_e32 v8, s16
; AGPR-SDAG-NEXT: v_mov_b32_e32 v9, s17
; AGPR-SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -2959,6 +2958,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v13, s21
; AGPR-SDAG-NEXT: v_mov_b32_e32 v14, s22
; AGPR-SDAG-NEXT: v_mov_b32_e32 v15, s23
+; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-SDAG-NEXT: s_nop 1
; AGPR-SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -2979,10 +2979,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-GISEL-NEXT: s_nop 1
; AGPR-GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -3013,7 +3013,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v5, s13
; SDAG-NEXT: v_mov_b32_e32 v6, s14
; SDAG-NEXT: v_mov_b32_e32 v7, s15
-; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b32_e32 v8, s16
; SDAG-NEXT: v_mov_b32_e32 v9, s17
; SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -3022,6 +3021,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; SDAG-NEXT: v_mov_b32_e32 v13, s21
; SDAG-NEXT: v_mov_b32_e32 v14, s22
; SDAG-NEXT: v_mov_b32_e32 v15, s23
+; SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; SDAG-NEXT: s_nop 1
; SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -3042,10 +3042,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; GISEL-NEXT: s_nop 1
; GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -3071,7 +3071,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v5, s13
; AGPR-SDAG-NEXT: v_mov_b32_e32 v6, s14
; AGPR-SDAG-NEXT: v_mov_b32_e32 v7, s15
-; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b32_e32 v8, s16
; AGPR-SDAG-NEXT: v_mov_b32_e32 v9, s17
; AGPR-SDAG-NEXT: v_mov_b32_e32 v10, s18
@@ -3080,6 +3079,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-SDAG-NEXT: v_mov_b32_e32 v13, s21
; AGPR-SDAG-NEXT: v_mov_b32_e32 v14, s22
; AGPR-SDAG-NEXT: v_mov_b32_e32 v15, s23
+; AGPR-SDAG-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-SDAG-NEXT: s_nop 1
; AGPR-SDAG-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v22, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
@@ -3100,10 +3100,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_16x16x128_f8f6f4__vgprcd___scaleA
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
; AGPR-GISEL-NEXT: s_nop 1
; AGPR-GISEL-NEXT: v_mfma_scale_f32_16x16x128_f8f6f4 v[0:3], v[0:7], v[8:15], v[16:19], v20, v21 op_sel:[1,1,0] op_sel_hi:[1,0,0]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
index 4a3be7e549011..333af4d9ce393 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
@@ -5338,8 +5338,6 @@ define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4_0_0_sgprs(<8 x i32> inr
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[12:13]
; GISEL-NEXT: s_mov_b32 s36, s28
; GISEL-NEXT: s_mov_b32 s37, s29
-; GISEL-NEXT: v_mov_b32_e32 v16, v14
-; GISEL-NEXT: v_mov_b32_e32 v17, v15
; GISEL-NEXT: v_readfirstlane_b32 s38, v0
; GISEL-NEXT: v_readfirstlane_b32 s39, v1
; GISEL-NEXT: v_readfirstlane_b32 s40, v2
@@ -5354,11 +5352,13 @@ define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4_0_0_sgprs(<8 x i32> inr
; GISEL-NEXT: v_readfirstlane_b32 s49, v11
; GISEL-NEXT: v_readfirstlane_b32 s50, v12
; GISEL-NEXT: v_readfirstlane_b32 s51, v13
+; GISEL-NEXT: v_mov_b32_e32 v16, v14
+; GISEL-NEXT: v_mov_b32_e32 v17, v15
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[26:27]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[24:25]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[20:21]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -6092,6 +6092,8 @@ define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4_0_0_vgpr_vgpr_sgpr__vgp
; GISEL-NEXT: v_mov_b32_e32 v25, v7
; GISEL-NEXT: s_mov_b32 s12, s0
; GISEL-NEXT: s_mov_b32 s13, s1
+; GISEL-NEXT: s_mov_b32 s14, s2
+; GISEL-NEXT: s_mov_b32 s15, s3
; GISEL-NEXT: v_mov_b32_e32 v26, v8
; GISEL-NEXT: v_mov_b32_e32 v27, v9
; GISEL-NEXT: v_mov_b32_e32 v28, v10
@@ -6100,8 +6102,6 @@ define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4_0_0_vgpr_vgpr_sgpr__vgp
; GISEL-NEXT: v_mov_b32_e32 v31, v13
; GISEL-NEXT: v_mov_b32_e32 v32, v14
; GISEL-NEXT: v_mov_b32_e32 v33, v15
-; GISEL-NEXT: s_mov_b32 s14, s2
-; GISEL-NEXT: s_mov_b32 s15, s3
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
@@ -6234,14 +6234,6 @@ define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4_0_0_sgpr_vgpr_sgpr__vgp
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[12:13]
; GISEL-NEXT: s_mov_b32 s36, s20
; GISEL-NEXT: s_mov_b32 s37, s21
-; GISEL-NEXT: v_mov_b32_e32 v18, v0
-; GISEL-NEXT: v_mov_b32_e32 v19, v1
-; GISEL-NEXT: v_mov_b32_e32 v20, v2
-; GISEL-NEXT: v_mov_b32_e32 v21, v3
-; GISEL-NEXT: v_mov_b32_e32 v22, v4
-; GISEL-NEXT: v_mov_b32_e32 v23, v5
-; GISEL-NEXT: v_mov_b32_e32 v24, v6
-; GISEL-NEXT: v_mov_b32_e32 v25, v7
; GISEL-NEXT: s_mov_b32 s38, s22
; GISEL-NEXT: s_mov_b32 s39, s23
; GISEL-NEXT: s_mov_b32 s40, s24
@@ -6250,7 +6242,6 @@ define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4_0_0_sgpr_vgpr_sgpr__vgp
; GISEL-NEXT: s_mov_b32 s43, s27
; GISEL-NEXT: s_mov_b32 s44, s28
; GISEL-NEXT: s_mov_b32 s45, s29
-; GISEL-NEXT: v_mov_b32_e32 v16, v14
; GISEL-NEXT: v_readfirstlane_b32 s46, v8
; GISEL-NEXT: v_readfirstlane_b32 s47, v9
; GISEL-NEXT: v_readfirstlane_b32 s48, v10
@@ -6258,6 +6249,15 @@ define <16 x float> @test_mfma_scale_f32_32x32x64_f8f6f4_0_0_sgpr_vgpr_sgpr__vgp
; GISEL-NEXT: v_readfirstlane_b32 s50, v12
; GISEL-NEXT: v_readfirstlane_b32 s51, v13
; GISEL-NEXT: v_readfirstlane_b32 s0, v15
+; GISEL-NEXT: v_mov_b32_e32 v18, v0
+; GISEL-NEXT: v_mov_b32_e32 v19, v1
+; GISEL-NEXT: v_mov_b32_e32 v20, v2
+; GISEL-NEXT: v_mov_b32_e32 v21, v3
+; GISEL-NEXT: v_mov_b32_e32 v22, v4
+; GISEL-NEXT: v_mov_b32_e32 v23, v5
+; GISEL-NEXT: v_mov_b32_e32 v24, v6
+; GISEL-NEXT: v_mov_b32_e32 v25, v7
+; GISEL-NEXT: v_mov_b32_e32 v16, v14
; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
@@ -7354,10 +7354,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd(<8 x i32>
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -7432,10 +7432,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd(<8 x i32>
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -7477,7 +7477,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd___scaleA_
; SDAG-NEXT: v_mov_b32_e32 v21, s13
; SDAG-NEXT: v_mov_b32_e32 v22, s14
; SDAG-NEXT: v_mov_b32_e32 v23, s15
-; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; SDAG-NEXT: v_mov_b32_e32 v24, s16
; SDAG-NEXT: v_mov_b32_e32 v25, s17
; SDAG-NEXT: v_mov_b32_e32 v26, s18
@@ -7486,6 +7485,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd___scaleA_
; SDAG-NEXT: v_mov_b32_e32 v29, s21
; SDAG-NEXT: v_mov_b32_e32 v30, s22
; SDAG-NEXT: v_mov_b32_e32 v31, s23
+; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -7517,10 +7517,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd___scaleA_
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -7555,7 +7555,6 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd___scaleA_
; AGPR-SDAG-NEXT: v_mov_b32_e32 v21, s13
; AGPR-SDAG-NEXT: v_mov_b32_e32 v22, s14
; AGPR-SDAG-NEXT: v_mov_b32_e32 v23, s15
-; AGPR-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; AGPR-SDAG-NEXT: v_mov_b32_e32 v24, s16
; AGPR-SDAG-NEXT: v_mov_b32_e32 v25, s17
; AGPR-SDAG-NEXT: v_mov_b32_e32 v26, s18
@@ -7564,6 +7563,7 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd___scaleA_
; AGPR-SDAG-NEXT: v_mov_b32_e32 v29, s21
; AGPR-SDAG-NEXT: v_mov_b32_e32 v30, s22
; AGPR-SDAG-NEXT: v_mov_b32_e32 v31, s23
+; AGPR-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; AGPR-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; AGPR-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; AGPR-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -7595,10 +7595,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4__vgprcd___scaleA_
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -7643,9 +7643,9 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__nonmac(<8 x
; SDAG-NEXT: v_mov_b32_e32 v30, s24
; SDAG-NEXT: v_mov_b32_e32 v31, s25
; SDAG-NEXT: v_mov_b32_e32 v32, s26
+; SDAG-NEXT: v_mov_b32_e32 v33, s27
; SDAG-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; SDAG-NEXT: v_mov_b32_e32 v33, s27
; SDAG-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; SDAG-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; SDAG-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -7708,10 +7708,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__nonmac(<8 x
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[40:41]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[42:43]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[44:45]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[46:47]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[48:49]
; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[50:51]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -7726,12 +7726,12 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__nonmac(<8 x
; GISEL-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 v[0:15], v[16:23], v[24:31], v[0:15], v36, v37 op_sel_hi:[0,0,0]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
-; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
-; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
-; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], 32
+; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; GISEL-NEXT: global_store_dwordx4 v[32:33], v[16:19], off sc0 sc1
; GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -7773,9 +7773,9 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__nonmac(<8 x
; AGPR-SDAG-NEXT: v_mov_b32_e32 v14, s24
; AGPR-SDAG-NEXT: v_mov_b32_e32 v15, s25
; AGPR-SDAG-NEXT: v_mov_b32_e32 v16, s26
+; AGPR-SDAG-NEXT: v_mov_b32_e32 v17, s27
; AGPR-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; AGPR-SDAG-NEXT: v_accvgpr_write_b32 a0, s8
-; AGPR-SDAG-NEXT: v_mov_b32_e32 v17, s27
; AGPR-SDAG-NEXT: v_accvgpr_write_b32 a1, s9
; AGPR-SDAG-NEXT: v_accvgpr_write_b32 a2, s10
; AGPR-SDAG-NEXT: v_accvgpr_write_b32 a3, s11
@@ -7846,10 +7846,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__nonmac(<8 x
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[44:45]
-; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[46:47]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[48:49]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[50:51]
+; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a1, s9
; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a2, s10
; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a3, s11
@@ -7871,14 +7871,14 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__nonmac(<8 x
; AGPR-GISEL-NEXT: s_nop 0
; AGPR-GISEL-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 a[0:15], v[0:7], v[8:15], a[0:15], v20, v21 op_sel_hi:[0,0,0]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[20:21], 32
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[20:21], 32
; AGPR-GISEL-NEXT: global_store_dwordx4 v[16:17], v[0:3], off sc0 sc1
; AGPR-GISEL-NEXT: s_waitcnt vmcnt(0)
; AGPR-GISEL-NEXT: global_store_dwordx4 v[18:19], v[4:7], off sc0 sc1
@@ -8005,10 +8005,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__nonmac(<8
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[40:41]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[42:43]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[44:45]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[46:47]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[48:49]
; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[50:51]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -8021,12 +8021,12 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__nonmac(<8
; GISEL-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 v[0:15], v[16:23], v[24:31], v[0:15], v36, v37 op_sel_hi:[0,0,0] blgp:2
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
-; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
-; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
-; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], 32
+; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; GISEL-NEXT: global_store_dwordx4 v[32:33], v[16:19], off sc0 sc1
; GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -8140,10 +8140,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__nonmac(<8
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[44:45]
-; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[46:47]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[48:49]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[50:51]
+; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a0, s8
; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a1, s9
; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a2, s10
; AGPR-GISEL-NEXT: v_accvgpr_write_b32 a3, s11
@@ -8163,14 +8163,14 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__nonmac(<8
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[22:23], 48
; AGPR-GISEL-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 a[0:15], v[0:7], v[8:15], a[0:15], v20, v21 op_sel_hi:[0,0,0] blgp:2
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[20:21], 32
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[16:17]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[18:19]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[22:23]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[20:21], 32
; AGPR-GISEL-NEXT: global_store_dwordx4 v[16:17], v[0:3], off sc0 sc1
; AGPR-GISEL-NEXT: s_waitcnt vmcnt(0)
; AGPR-GISEL-NEXT: global_store_dwordx4 v[18:19], v[4:7], off sc0 sc1
@@ -8294,10 +8294,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__vgprcd_nonma
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[40:41]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[42:43]
; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[44:45]
-; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[42:43], s[46:47]
; GISEL-NEXT: v_mov_b64_e32 v[44:45], s[48:49]
; GISEL-NEXT: v_mov_b64_e32 v[46:47], s[50:51]
+; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -8412,10 +8412,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_0_0__vgprcd_nonma
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[36:37], s[40:41]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[38:39], s[42:43]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[40:41], s[44:45]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[42:43], s[46:47]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[44:45], s[48:49]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[46:47], s[50:51]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
@@ -8540,10 +8540,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__vgprcd_non
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[40:41]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[42:43]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[44:45]
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[46:47]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[48:49]
; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[50:51]
+; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -8554,14 +8554,14 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__vgprcd_non
; GISEL-NEXT: v_mov_b64_e32 v[36:37], 32
; GISEL-NEXT: v_mov_b64_e32 v[38:39], 48
; GISEL-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 v[0:15], v[16:23], v[24:31], v[0:15], v32, v33 op_sel_hi:[0,0,0] blgp:2
-; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], 0
+; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
-; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
-; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; GISEL-NEXT: global_store_dwordx4 v[32:33], v[16:19], off sc0 sc1
; GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -8668,10 +8668,10 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__vgprcd_non
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[40:41]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[42:43]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[44:45]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[46:47]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[48:49]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[50:51]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
@@ -8682,14 +8682,14 @@ define amdgpu_kernel void @test_mfma_scale_f32_32x32x64_f8f6f4_25_42__vgprcd_non
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[36:37], 32
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[38:39], 48
; AGPR-GISEL-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 v[0:15], v[16:23], v[24:31], v[0:15], v32, v33 op_sel_hi:[0,0,0] blgp:2
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[32:33], 0
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[10:11]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[8:9]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[14:15]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
-; AGPR-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[12:13]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[18:19]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[16:17]
+; AGPR-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[22:23]
; AGPR-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[20:21]
; AGPR-GISEL-NEXT: global_store_dwordx4 v[32:33], v[16:19], off sc0 sc1
; AGPR-GISEL-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
index dbe95a8091932..e36b2181bf5c0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
@@ -124,8 +124,8 @@ define amdgpu_ps void @test_call(ptr addrspace(1) inreg %ptr) {
; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
; GFX9-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX9-SDAG-NEXT: s_mov_b32 s6, src_pops_exiting_wave_id
-; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-SDAG-NEXT: s_mov_b64 s[8:9], 36
+; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6
; GFX9-SDAG-NEXT: s_mov_b32 s32, 0
@@ -155,31 +155,51 @@ define amdgpu_ps void @test_call(ptr addrspace(1) inreg %ptr) {
; GFX9-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-GISEL-NEXT: s_endpgm
;
-; GFX10-LABEL: test_call:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
-; GFX10-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
-; GFX10-NEXT: s_mov_b32 s38, -1
-; GFX10-NEXT: s_mov_b32 s39, 0x31c16000
-; GFX10-NEXT: s_add_u32 s36, s36, s2
-; GFX10-NEXT: s_addc_u32 s37, s37, 0
-; GFX10-NEXT: s_getpc_b64 s[0:1]
-; GFX10-NEXT: s_add_u32 s0, s0, foo at gotpcrel32@lo+4
-; GFX10-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
-; GFX10-NEXT: s_mov_b64 s[8:9], 36
-; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX10-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
-; GFX10-NEXT: s_mov_b32 s32, 0
-; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX10-NEXT: s_mov_b64 s[2:3], s[38:39]
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX10-NEXT: s_endpgm
+; GFX10-SDAG-LABEL: test_call:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; GFX10-SDAG-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
+; GFX10-SDAG-NEXT: s_mov_b32 s38, -1
+; GFX10-SDAG-NEXT: s_mov_b32 s39, 0x31c16000
+; GFX10-SDAG-NEXT: s_add_u32 s36, s36, s2
+; GFX10-SDAG-NEXT: s_addc_u32 s37, s37, 0
+; GFX10-SDAG-NEXT: s_getpc_b64 s[0:1]
+; GFX10-SDAG-NEXT: s_add_u32 s0, s0, foo at gotpcrel32@lo+4
+; GFX10-SDAG-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
+; GFX10-SDAG-NEXT: s_mov_b64 s[8:9], 36
+; GFX10-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
+; GFX10-SDAG-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
+; GFX10-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX10-SDAG-NEXT: s_mov_b32 s32, 0
+; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; GFX10-SDAG-NEXT: s_endpgm
+;
+; GFX10-GISEL-LABEL: test_call:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
+; GFX10-GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
+; GFX10-GISEL-NEXT: s_mov_b32 s38, -1
+; GFX10-GISEL-NEXT: s_mov_b32 s39, 0x31c16000
+; GFX10-GISEL-NEXT: s_add_u32 s36, s36, s2
+; GFX10-GISEL-NEXT: s_addc_u32 s37, s37, 0
+; GFX10-GISEL-NEXT: s_getpc_b64 s[0:1]
+; GFX10-GISEL-NEXT: s_add_u32 s0, s0, foo at gotpcrel32@lo+4
+; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
+; GFX10-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
+; GFX10-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
+; GFX10-GISEL-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
+; GFX10-GISEL-NEXT: s_mov_b64 s[8:9], 36
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX10-GISEL-NEXT: s_mov_b32 s32, 0
+; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; GFX10-GISEL-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.pops.exiting.wave.id()
call void @foo(i32 %id)
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
index 58d90c4777a6d..c6e02156d2636 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
@@ -243,8 +243,8 @@ define amdgpu_kernel void @test_scc_quadmask_64(i32 %val0, i64 %val1, ptr addrsp
; GFX11-SDAG-NEXT: s_and_b32 s4, s6, 1
; GFX11-SDAG-NEXT: s_quadmask_b64 s[0:1], s[0:1]
; GFX11-SDAG-NEXT: s_cmp_eq_u32 s4, 0
-; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX11-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX11-SDAG-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s0
; GFX11-SDAG-NEXT: global_store_b64 v4, v[0:1], s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
index 86158db4779c5..066ed77fab494 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
@@ -446,9 +446,9 @@ define amdgpu_kernel void @test_readfirstlane_imm_fold_i64(ptr addrspace(1) %out
; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, 32
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -456,14 +456,14 @@ define amdgpu_kernel void @test_readfirstlane_imm_fold_i64(ptr addrspace(1) %out
; CHECK-GISEL-LABEL: test_readfirstlane_imm_fold_i64:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; CHECK-GISEL-NEXT: s_mov_b64 s[2:3], 32
; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; CHECK-GISEL-NEXT: s_mov_b64 s[2:3], 32
; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
-; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -480,9 +480,9 @@ define amdgpu_kernel void @test_readfirstlane_imm_fold_f64(ptr addrspace(1) %out
; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0x40400000
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0x40400000
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -490,15 +490,15 @@ define amdgpu_kernel void @test_readfirstlane_imm_fold_f64(ptr addrspace(1) %out
; CHECK-GISEL-LABEL: test_readfirstlane_imm_fold_f64:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; CHECK-GISEL-NEXT: s_mov_b32 s2, 0
; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
+; CHECK-GISEL-NEXT: s_mov_b32 s2, 0
; CHECK-GISEL-NEXT: s_mov_b32 s3, 0x40400000
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -517,9 +517,9 @@ define amdgpu_kernel void @test_readfirstlane_m0(ptr addrspace(1) %out) #0 {
; CHECK-SDAG-NEXT: ;;#ASMSTART
; CHECK-SDAG-NEXT: s_mov_b32 m0, -1
; CHECK-SDAG-NEXT: ;;#ASMEND
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, m0
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, m0
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s1
; CHECK-SDAG-NEXT: flat_store_dword v[0:1], v2
; CHECK-SDAG-NEXT: s_endpgm
@@ -533,9 +533,9 @@ define amdgpu_kernel void @test_readfirstlane_m0(ptr addrspace(1) %out) #0 {
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b32 m0, -1
; CHECK-GISEL-NEXT: ;;#ASMEND
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, m0
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, m0
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
; CHECK-GISEL-NEXT: s_endpgm
@@ -571,9 +571,9 @@ define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr_i32(ptr addrspace(1
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b32 s2, 0
; CHECK-GISEL-NEXT: ;;#ASMEND
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s2
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
; CHECK-GISEL-NEXT: s_endpgm
@@ -593,10 +593,10 @@ define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr_i64(ptr addrspace(1
; CHECK-SDAG-NEXT: ;;#ASMSTART
; CHECK-SDAG-NEXT: s_mov_b64 s[2:3], 0
; CHECK-SDAG-NEXT: ;;#ASMEND
-; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s2
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -605,15 +605,15 @@ define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr_i64(ptr addrspace(1
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
+; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b64 s[2:3], 0
; CHECK-GISEL-NEXT: ;;#ASMEND
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -633,10 +633,10 @@ define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr_f64(ptr addrspace(1
; CHECK-SDAG-NEXT: ;;#ASMSTART
; CHECK-SDAG-NEXT: s_mov_b64 s[2:3], 0
; CHECK-SDAG-NEXT: ;;#ASMEND
-; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s2
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -645,15 +645,15 @@ define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr_f64(ptr addrspace(1
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
+; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b64 s[2:3], 0
; CHECK-GISEL-NEXT: ;;#ASMEND
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
index 9d6d5f55727a1..79101418a2b05 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
@@ -214,9 +214,9 @@ define amdgpu_kernel void @test_readlane_imm_sreg_i64(ptr addrspace(1) %out, i32
; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, 32
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -228,9 +228,9 @@ define amdgpu_kernel void @test_readlane_imm_sreg_i64(ptr addrspace(1) %out, i32
; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, 32
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, 0
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, 0
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -247,9 +247,9 @@ define amdgpu_kernel void @test_readlane_imm_sreg_f64(ptr addrspace(1) %out, i32
; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0x40400000
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, 0x40400000
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -261,9 +261,9 @@ define amdgpu_kernel void @test_readlane_imm_sreg_f64(ptr addrspace(1) %out, i32
; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, 0x40400000
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, 0x40400000
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -310,11 +310,11 @@ define amdgpu_kernel void @test_readlane_vregs_i32(ptr addrspace(1) %out, ptr ad
; CHECK-GISEL-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0)
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s2, v1
-; CHECK-GISEL-NEXT: s_nop 3
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; CHECK-GISEL-NEXT: s_nop 2
; CHECK-GISEL-NEXT: v_readlane_b32 s2, v0, s2
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s2
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
; CHECK-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -366,10 +366,10 @@ define amdgpu_kernel void @test_readlane_vregs_i64(ptr addrspace(1) %out, ptr ad
; CHECK-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-GISEL-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0)
-; CHECK-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; CHECK-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; CHECK-GISEL-NEXT: s_nop 1
+; CHECK-GISEL-NEXT: s_nop 2
; CHECK-GISEL-NEXT: v_readlane_b32 s2, v0, s3
; CHECK-GISEL-NEXT: v_readlane_b32 s3, v1, s3
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
@@ -426,10 +426,10 @@ define amdgpu_kernel void @test_readlane_vregs_f64(ptr addrspace(1) %out, ptr ad
; CHECK-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-GISEL-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0)
-; CHECK-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; CHECK-GISEL-NEXT: v_readfirstlane_b32 s3, v2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; CHECK-GISEL-NEXT: s_nop 1
+; CHECK-GISEL-NEXT: s_nop 2
; CHECK-GISEL-NEXT: v_readlane_b32 s2, v0, s3
; CHECK-GISEL-NEXT: v_readlane_b32 s3, v1, s3
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
@@ -458,9 +458,9 @@ define amdgpu_kernel void @test_readlane_m0_sreg(ptr addrspace(1) %out, i32 %src
; CHECK-SDAG-NEXT: ;;#ASMSTART
; CHECK-SDAG-NEXT: s_mov_b32 m0, -1
; CHECK-SDAG-NEXT: ;;#ASMEND
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, m0
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, m0
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s1
; CHECK-SDAG-NEXT: flat_store_dword v[0:1], v2
; CHECK-SDAG-NEXT: s_endpgm
@@ -474,9 +474,9 @@ define amdgpu_kernel void @test_readlane_m0_sreg(ptr addrspace(1) %out, i32 %src
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b32 m0, -1
; CHECK-GISEL-NEXT: ;;#ASMEND
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, m0
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, m0
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
; CHECK-GISEL-NEXT: s_endpgm
@@ -490,15 +490,15 @@ define amdgpu_kernel void @test_readlane_vgpr_imm_i32(ptr addrspace(1) %out) #1
; CHECK-SDAG-LABEL: test_readlane_vgpr_imm_i32:
; CHECK-SDAG: ; %bb.0:
; CHECK-SDAG-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; CHECK-SDAG-NEXT: s_add_i32 s12, s12, s17
; CHECK-SDAG-NEXT: ;;#ASMSTART
; CHECK-SDAG-NEXT: ; def v0
; CHECK-SDAG-NEXT: ;;#ASMEND
-; CHECK-SDAG-NEXT: s_add_i32 s12, s12, s17
; CHECK-SDAG-NEXT: v_readlane_b32 s2, v0, 32
; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s2
; CHECK-SDAG-NEXT: flat_store_dword v[0:1], v2
@@ -507,16 +507,16 @@ define amdgpu_kernel void @test_readlane_vgpr_imm_i32(ptr addrspace(1) %out) #1
; CHECK-GISEL-LABEL: test_readlane_vgpr_imm_i32:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: ; def v0
; CHECK-GISEL-NEXT: ;;#ASMEND
-; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
; CHECK-GISEL-NEXT: v_readlane_b32 s2, v0, 32
; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
-; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
; CHECK-GISEL-NEXT: s_endpgm
@@ -536,12 +536,12 @@ define amdgpu_kernel void @test_readlane_vgpr_imm_i64(ptr addrspace(1) %out) #1
; CHECK-SDAG-NEXT: ;;#ASMEND
; CHECK-SDAG-NEXT: v_readlane_b32 s2, v1, 32
; CHECK-SDAG-NEXT: v_readlane_b32 s3, v0, 32
-; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s3
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -549,18 +549,18 @@ define amdgpu_kernel void @test_readlane_vgpr_imm_i64(ptr addrspace(1) %out) #1
; CHECK-GISEL-LABEL: test_readlane_vgpr_imm_i64:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: ; def v[0:1]
; CHECK-GISEL-NEXT: ;;#ASMEND
; CHECK-GISEL-NEXT: v_readlane_b32 s2, v0, 32
-; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
; CHECK-GISEL-NEXT: v_readlane_b32 s3, v1, 32
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -580,12 +580,12 @@ define amdgpu_kernel void @test_readlane_vgpr_imm_f64(ptr addrspace(1) %out) #1
; CHECK-SDAG-NEXT: ;;#ASMEND
; CHECK-SDAG-NEXT: v_readlane_b32 s2, v1, 32
; CHECK-SDAG-NEXT: v_readlane_b32 s3, v0, 32
-; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s3
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s0
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-SDAG-NEXT: s_endpgm
@@ -593,18 +593,18 @@ define amdgpu_kernel void @test_readlane_vgpr_imm_f64(ptr addrspace(1) %out) #1
; CHECK-GISEL-LABEL: test_readlane_vgpr_imm_f64:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: ; def v[0:1]
; CHECK-GISEL-NEXT: ;;#ASMEND
; CHECK-GISEL-NEXT: v_readlane_b32 s2, v0, 32
-; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
; CHECK-GISEL-NEXT: v_readlane_b32 s3, v1, 32
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -640,9 +640,9 @@ define amdgpu_kernel void @test_readlane_copy_from_sgpr_i32(ptr addrspace(1) %ou
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b32 s2, 0
; CHECK-GISEL-NEXT: ;;#ASMEND
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s2
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s2
; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s1
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
; CHECK-GISEL-NEXT: s_endpgm
@@ -657,15 +657,15 @@ define amdgpu_kernel void @test_readlane_copy_from_sgpr_i64(ptr addrspace(1) %ou
; CHECK-SDAG: ; %bb.0:
; CHECK-SDAG-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-SDAG-NEXT: s_add_i32 s12, s12, s17
+; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: ;;#ASMSTART
; CHECK-SDAG-NEXT: s_mov_b64 s[2:3], 0
; CHECK-SDAG-NEXT: ;;#ASMEND
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s2
; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s3
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; CHECK-SDAG-NEXT: s_endpgm
@@ -674,15 +674,15 @@ define amdgpu_kernel void @test_readlane_copy_from_sgpr_i64(ptr addrspace(1) %ou
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
+; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b64 s[2:3], 0
; CHECK-GISEL-NEXT: ;;#ASMEND
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
@@ -697,15 +697,15 @@ define amdgpu_kernel void @test_readlane_copy_from_sgpr_f64(ptr addrspace(1) %ou
; CHECK-SDAG: ; %bb.0:
; CHECK-SDAG-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-SDAG-NEXT: s_add_i32 s12, s12, s17
+; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: ;;#ASMSTART
; CHECK-SDAG-NEXT: s_mov_b64 s[2:3], 0
; CHECK-SDAG-NEXT: ;;#ASMEND
-; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; CHECK-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; CHECK-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; CHECK-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; CHECK-SDAG-NEXT: v_mov_b32_e32 v2, s2
; CHECK-SDAG-NEXT: v_mov_b32_e32 v3, s3
; CHECK-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; CHECK-SDAG-NEXT: s_endpgm
@@ -714,15 +714,15 @@ define amdgpu_kernel void @test_readlane_copy_from_sgpr_f64(ptr addrspace(1) %ou
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
; CHECK-GISEL-NEXT: s_add_i32 s12, s12, s17
+; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CHECK-GISEL-NEXT: ;;#ASMSTART
; CHECK-GISEL-NEXT: s_mov_b64 s[2:3], 0
; CHECK-GISEL-NEXT: ;;#ASMEND
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; CHECK-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; CHECK-GISEL-NEXT: v_mov_b32_e32 v1, s3
; CHECK-GISEL-NEXT: v_mov_b32_e32 v2, s0
; CHECK-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
index dbf885a1072b8..8579a2a9f64fc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
@@ -41,8 +41,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_sext_i32_i16 s3, s6
; GFX8GISEL-NEXT: s_mul_i32 s2, s3, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -526,8 +526,8 @@ define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) #0 {
; GFX8GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_mul_i32 s2, s6, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -723,9 +723,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -974,8 +974,8 @@ define amdgpu_kernel void @uniform_value_dpp(ptr addrspace(1) %out, i32 %in) #0
; GFX8GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_mul_i32 s2, s6, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -1183,9 +1183,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2477,9 +2477,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_add_u32_dpp v1, vcc, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -3366,8 +3366,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_mul_i32 s3, s3, s5
; GFX8GISEL-NEXT: s_add_u32 s5, s2, s3
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3511,8 +3511,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-NEXT: s_mul_i32 s3, s3, s4
; GFX1132DAGISEL-NEXT: s_mul_i32 s2, s2, s4
; GFX1132DAGISEL-NEXT: s_add_u32 s3, s5, s3
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
@@ -3542,8 +3543,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX12DAGISEL-NEXT: s_mul_i32 s3, s3, s4
; GFX12DAGISEL-NEXT: s_mul_i32 s2, s2, s4
; GFX12DAGISEL-NEXT: s_add_co_u32 s3, s5, s3
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
index d8d927105008d..71b3b979fa059 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
@@ -35,8 +35,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -585,9 +585,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -952,9 +952,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_and_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2137,9 +2137,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_and_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2894,9 +2894,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -2906,8 +2906,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -2975,9 +2975,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-LABEL: uniform_value_i64:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
index db4743740b1ad..ab2f252d5b340 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
@@ -780,8 +780,8 @@ define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in)
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX8GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -3343,9 +3343,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8DAGISEL-NEXT: v_add_f64 v[4:5], s[8:9], v[4:5]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3368,9 +3368,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8GISEL-NEXT: v_add_f64 v[4:5], s[8:9], v[4:5]
; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3393,9 +3393,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9DAGISEL-NEXT: v_add_f64 v[4:5], s[8:9], v[4:5]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3418,9 +3418,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9GISEL-NEXT: v_add_f64 v[4:5], s[8:9], v[4:5]
; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
index 91daefe76a55c..f89fcbb92ac82 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
@@ -3059,9 +3059,9 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -3071,8 +3071,8 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3140,9 +3140,9 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX1132DAGISEL-LABEL: uniform_value_double:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
@@ -3158,9 +3158,9 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX12DAGISEL-LABEL: uniform_value_double:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
@@ -3178,9 +3178,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3203,9 +3203,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3228,9 +3228,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3253,9 +3253,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3507,9 +3507,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3531,9 +3531,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX8DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3565,9 +3565,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3589,9 +3589,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX8GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3623,9 +3623,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3647,9 +3647,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX9DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3681,9 +3681,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3705,9 +3705,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX9GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
index 3ccf8d81dff6a..3bafdf367baac 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
@@ -3059,9 +3059,9 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -3071,8 +3071,8 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3140,9 +3140,9 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX1132DAGISEL-LABEL: uniform_value_double:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
@@ -3158,9 +3158,9 @@ define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %i
; GFX12DAGISEL-LABEL: uniform_value_double:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
@@ -3178,9 +3178,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3203,9 +3203,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8GISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3228,9 +3228,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3253,9 +3253,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) #0 {
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9GISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3507,9 +3507,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3531,9 +3531,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX8DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3565,9 +3565,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX8GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3589,9 +3589,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX8GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3623,9 +3623,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3647,9 +3647,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX9DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3681,9 +3681,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: .LBB9_2: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX9GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
@@ -3705,9 +3705,9 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: .LBB9_6: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX9GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
index 8816ff9c95ce2..3d452e2dd65c7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
@@ -783,8 +783,8 @@ define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in)
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mul_f32_e64 v0, -s2, v0
; GFX8GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -3378,9 +3378,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8DAGISEL-NEXT: v_add_f64 v[4:5], -s[8:9], v[4:5]
; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3402,9 +3402,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX8GISEL-NEXT: v_add_f64 v[4:5], -s[8:9], v[4:5]
; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3426,9 +3426,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9DAGISEL-NEXT: v_add_f64 v[4:5], -s[8:9], v[4:5]
; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
@@ -3450,9 +3450,9 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %id.x) #0 {
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
; GFX9GISEL-NEXT: v_add_f64 v[4:5], -s[8:9], v[4:5]
; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
index ce7f8bac0da5f..1a9e6f3a34475 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
@@ -35,8 +35,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_sext_i32_i16 s2, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -545,9 +545,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -914,9 +914,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_max_i32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2227,9 +2227,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_max_i32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2986,9 +2986,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -2998,8 +2998,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3067,9 +3067,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-LABEL: uniform_value_i64:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
index b23b3096ca9f2..2c564bccf1678 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
@@ -35,8 +35,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_sext_i32_i16 s2, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -545,9 +545,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -914,9 +914,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_min_i32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2227,9 +2227,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_min_i32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2986,9 +2986,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -2998,8 +2998,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3067,9 +3067,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-LABEL: uniform_value_i64:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
index ab122bb88316a..1546037f5b452 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
@@ -35,8 +35,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -585,9 +585,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -952,9 +952,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2137,9 +2137,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_or_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2894,9 +2894,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -2906,8 +2906,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -2975,9 +2975,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-LABEL: uniform_value_i64:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
index bc4eab0eaa107..e5403a9a7d614 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
@@ -43,8 +43,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_sext_i32_i16 s3, s6
; GFX8GISEL-NEXT: s_sub_i32 s3, 0, s3
; GFX8GISEL-NEXT: s_mul_i32 s2, s3, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -548,8 +548,8 @@ define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) #0 {
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_sub_i32 s3, 0, s6
; GFX8GISEL-NEXT: s_mul_i32 s2, s3, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -758,9 +758,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -1011,8 +1011,8 @@ define amdgpu_kernel void @uniform_value_dpp(ptr addrspace(1) %out, i32 %in) #0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_sub_i32 s3, 0, s6
; GFX8GISEL-NEXT: s_mul_i32 s2, s3, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -1235,9 +1235,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
; GFX8GISEL-NEXT: s_sub_i32 s2, 0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2197,8 +2197,8 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) #0 {
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164DAGISEL-NEXT: s_subb_u32 s1, 0, s3
; GFX1164DAGISEL-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX1164DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX1164DAGISEL-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX1164DAGISEL-NEXT: s_clause 0x4 ; 20-byte Folded Reload
@@ -2291,8 +2291,8 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) #0 {
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164GISEL-NEXT: s_subb_u32 s1, 0, s3
; GFX1164GISEL-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX1164GISEL-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX1164GISEL-NEXT: s_clause 0x4 ; 20-byte Folded Reload
@@ -2362,7 +2362,7 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) #0 {
; GFX1132DAGISEL-NEXT: s_sub_u32 s0, 0, s1
; GFX1132DAGISEL-NEXT: s_subb_u32 s1, 0, s2
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1132DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX1132DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1
; GFX1132DAGISEL-NEXT: s_clause 0x3 ; 16-byte Folded Reload
@@ -2431,7 +2431,7 @@ define void @divergent_value_dpp_i64(ptr addrspace(1) %out, i64 %in) #0 {
; GFX1132GISEL-NEXT: s_sub_u32 s0, 0, s1
; GFX1132GISEL-NEXT: s_subb_u32 s1, 0, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX1132GISEL-NEXT: s_xor_saveexec_b32 s0, -1
; GFX1132GISEL-NEXT: s_clause 0x3 ; 16-byte Folded Reload
@@ -2574,9 +2574,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
; GFX8GISEL-NEXT: s_sub_i32 s2, 0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -3497,8 +3497,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_add_u32 s2, s2, s3
; GFX8GISEL-NEXT: s_add_u32 s5, s2, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3517,8 +3517,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX9DAGISEL-NEXT: s_mul_i32 s3, s3, s5
; GFX9DAGISEL-NEXT: s_add_u32 s2, s2, s3
; GFX9DAGISEL-NEXT: s_add_u32 s5, s2, s6
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9DAGISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9DAGISEL-NEXT: s_endpgm
@@ -3681,8 +3681,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-NEXT: s_add_u32 s3, s6, s3
; GFX1132DAGISEL-NEXT: s_mul_i32 s2, s2, s4
; GFX1132DAGISEL-NEXT: s_add_u32 s3, s3, s5
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
@@ -3722,8 +3723,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX12DAGISEL-NEXT: s_add_co_u32 s3, s6, s3
; GFX12DAGISEL-NEXT: s_mul_i32 s2, s2, s4
; GFX12DAGISEL-NEXT: s_add_co_u32 s3, s3, s5
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
index b76883c6284de..b08b8751bfde2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
@@ -35,8 +35,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -597,9 +597,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out, i32 %in) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -964,9 +964,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out, i32 %in) #
; GFX8GISEL-NEXT: v_max_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2233,9 +2233,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_max_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2990,9 +2990,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -3002,8 +3002,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3071,9 +3071,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-LABEL: uniform_value_i64:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
index a7e9f64349218..002406bb70227 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
@@ -35,8 +35,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -585,9 +585,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -952,9 +952,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_min_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2221,9 +2221,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_min_u32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2978,9 +2978,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8DAGISEL: ; %bb.0: ; %entry
; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8DAGISEL-NEXT: s_endpgm
@@ -2990,8 +2990,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3059,9 +3059,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-LABEL: uniform_value_i64:
; GFX1132DAGISEL: ; %bb.0: ; %entry
; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
index 777f33c57493f..a6298a6fdd9c1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
@@ -43,8 +43,8 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_and_b32 s3, s6, 0xffff
; GFX8GISEL-NEXT: s_mul_i32 s2, s3, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_short v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -550,8 +550,8 @@ define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) #0 {
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_mul_i32 s2, s6, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -747,9 +747,9 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB3_1
; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -981,8 +981,8 @@ define amdgpu_kernel void @uniform_value_dpp(ptr addrspace(1) %out, i32 %in) #0
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_mul_i32 s2, s6, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
@@ -1190,9 +1190,9 @@ define amdgpu_kernel void @divergent_value_dpp(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -2375,9 +2375,9 @@ define amdgpu_kernel void @default_stratergy(ptr addrspace(1) %out) #0 {
; GFX8GISEL-NEXT: v_xor_b32_dpp v1, v1, v1 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX8GISEL-NEXT: v_readlane_b32 s4, v1, 63
; GFX8GISEL-NEXT: s_mov_b64 exec, s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dword v[2:3], v0
; GFX8GISEL-NEXT: s_endpgm
@@ -3187,10 +3187,10 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8DAGISEL-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
; GFX8DAGISEL-NEXT: s_and_b32 s4, s4, 1
; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8DAGISEL-NEXT: s_mul_i32 s1, s3, s4
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8DAGISEL-NEXT: s_mul_i32 s0, s2, s4
+; GFX8DAGISEL-NEXT: s_mul_i32 s1, s3, s4
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -3206,8 +3206,8 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX8GISEL-NEXT: s_mul_i32 s2, s2, s4
; GFX8GISEL-NEXT: s_mul_i32 s3, s3, s4
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3344,8 +3344,9 @@ define amdgpu_kernel void @uniform_value_i64(ptr addrspace(1) %out, i64 %in) #0
; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132DAGISEL-NEXT: s_mul_i32 s2, s2, s4
; GFX1132DAGISEL-NEXT: s_mul_i32 s3, s3, s4
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
@@ -4116,9 +4117,9 @@ define amdgpu_kernel void @constant_value(ptr addrspace(1) %out) {
; GFX8GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX8GISEL-NEXT: s_mul_i32 s2, s2, 30
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
index 03b4fef44949a..b12603eff7e99 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
@@ -83,8 +83,8 @@ define amdgpu_kernel void @test_barrier(ptr addrspace(1) %out, i32 %size) #0 {
; VARIANT2-GISEL-NEXT: v_sub_u32_e32 v0, s2, v0
; VARIANT2-GISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VARIANT2-GISEL-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
-; VARIANT2-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VARIANT2-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VARIANT2-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VARIANT2-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0
; VARIANT2-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
; VARIANT2-GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -160,16 +160,15 @@ define amdgpu_kernel void @test_barrier(ptr addrspace(1) %out, i32 %size) #0 {
; VARIANT6-LABEL: test_barrier:
; VARIANT6: ; %bb.0: ; %entry
; VARIANT6-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; VARIANT6-NEXT: v_and_b32_e32 v1, 0x3ff, v0
; VARIANT6-NEXT: s_wait_kmcnt 0x0
+; VARIANT6-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_and_b32 v1, 0x3ff, v0
; VARIANT6-NEXT: s_add_co_i32 s2, s2, -1
-; VARIANT6-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; VARIANT6-NEXT: v_lshlrev_b32_e32 v4, 2, v1
+; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; VARIANT6-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_lshlrev_b32 v4, 2, v1
; VARIANT6-NEXT: v_sub_nc_u32_e32 v0, s2, v1
; VARIANT6-NEXT: global_store_b32 v4, v1, s[0:1]
-; VARIANT6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VARIANT6-NEXT: s_barrier_signal -1
+; VARIANT6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VARIANT6-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; VARIANT6-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
index 20523476a29d5..8302467dcd2f1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
@@ -12,42 +12,39 @@ define amdgpu_kernel void @test_sched_group_barrier_pipeline_WMMA_cluster(ptr ad
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_add_nc_u32_e32 v32, s0, v40
; GCN-NEXT: v_dual_mov_b32 v81, s1 :: v_dual_add_nc_u32 v80, s1, v40
+; GCN-NEXT: ds_load_b128 v[0:3], v32
; GCN-NEXT: ds_load_b128 v[4:7], v32 offset:16
; GCN-NEXT: ds_load_b128 v[12:15], v32 offset:2064
-; GCN-NEXT: ds_load_b128 v[20:23], v32 offset:6160
-; GCN-NEXT: ds_load_b128 v[28:31], v32 offset:12304
-; GCN-NEXT: ds_load_b128 v[36:39], v32 offset:20496
-; GCN-NEXT: ds_load_b128 v[0:3], v32
; GCN-NEXT: ds_load_b128 v[8:11], v32 offset:2048
+; GCN-NEXT: ds_load_b128 v[20:23], v32 offset:6160
; GCN-NEXT: ds_load_b128 v[16:19], v32 offset:6144
+; GCN-NEXT: ds_load_b128 v[28:31], v32 offset:12304
; GCN-NEXT: ds_load_b128 v[24:27], v32 offset:12288
+; GCN-NEXT: ds_load_b128 v[36:39], v32 offset:20496
; GCN-NEXT: ds_load_b128 v[32:35], v32 offset:20480
; GCN-NEXT: ; sched_group_barrier mask(0x00000100) size(10) SyncID(0)
-; GCN-NEXT: s_waitcnt lgkmcnt(4)
-; GCN-NEXT: v_mov_b32_e32 v47, v7
-; GCN-NEXT: s_waitcnt lgkmcnt(3)
-; GCN-NEXT: v_mov_b32_e32 v55, v15
-; GCN-NEXT: s_waitcnt lgkmcnt(2)
-; GCN-NEXT: v_mov_b32_e32 v63, v23
-; GCN-NEXT: s_waitcnt lgkmcnt(1)
-; GCN-NEXT: v_mov_b32_e32 v71, v31
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_dual_mov_b32 v79, v39 :: v_dual_mov_b32 v46, v6
+; GCN-NEXT: s_waitcnt lgkmcnt(8)
+; GCN-NEXT: v_mov_b32_e32 v43, v3
+; GCN-NEXT: v_dual_mov_b32 v47, v7 :: v_dual_mov_b32 v46, v6
; GCN-NEXT: v_dual_mov_b32 v45, v5 :: v_dual_mov_b32 v44, v4
-; GCN-NEXT: v_dual_mov_b32 v43, v3 :: v_dual_mov_b32 v42, v2
-; GCN-NEXT: v_dual_mov_b32 v41, v1 :: v_dual_mov_b32 v40, v0
+; GCN-NEXT: v_dual_mov_b32 v42, v2 :: v_dual_mov_b32 v41, v1
+; GCN-NEXT: s_waitcnt lgkmcnt(6)
+; GCN-NEXT: v_dual_mov_b32 v40, v0 :: v_dual_mov_b32 v55, v15
; GCN-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v53, v13
; GCN-NEXT: v_dual_mov_b32 v52, v12 :: v_dual_mov_b32 v51, v11
; GCN-NEXT: v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v49, v9
-; GCN-NEXT: v_mov_b32_e32 v48, v8
+; GCN-NEXT: s_waitcnt lgkmcnt(4)
+; GCN-NEXT: v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v63, v23
; GCN-NEXT: v_dual_mov_b32 v62, v22 :: v_dual_mov_b32 v61, v21
; GCN-NEXT: v_dual_mov_b32 v60, v20 :: v_dual_mov_b32 v59, v19
; GCN-NEXT: v_dual_mov_b32 v58, v18 :: v_dual_mov_b32 v57, v17
-; GCN-NEXT: v_mov_b32_e32 v56, v16
+; GCN-NEXT: s_waitcnt lgkmcnt(2)
+; GCN-NEXT: v_dual_mov_b32 v56, v16 :: v_dual_mov_b32 v71, v31
; GCN-NEXT: v_dual_mov_b32 v70, v30 :: v_dual_mov_b32 v69, v29
; GCN-NEXT: v_dual_mov_b32 v68, v28 :: v_dual_mov_b32 v67, v27
; GCN-NEXT: v_dual_mov_b32 v66, v26 :: v_dual_mov_b32 v65, v25
-; GCN-NEXT: v_mov_b32_e32 v64, v24
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_dual_mov_b32 v64, v24 :: v_dual_mov_b32 v79, v39
; GCN-NEXT: v_dual_mov_b32 v78, v38 :: v_dual_mov_b32 v77, v37
; GCN-NEXT: v_dual_mov_b32 v76, v36 :: v_dual_mov_b32 v75, v35
; GCN-NEXT: v_dual_mov_b32 v74, v34 :: v_dual_mov_b32 v73, v33
@@ -80,42 +77,39 @@ define amdgpu_kernel void @test_sched_group_barrier_pipeline_WMMA_cluster(ptr ad
; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(0)
; EXACTCUTOFF-NEXT: v_add_nc_u32_e32 v32, s0, v40
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v81, s1 :: v_dual_add_nc_u32 v80, s1, v40
+; EXACTCUTOFF-NEXT: ds_load_b128 v[0:3], v32
; EXACTCUTOFF-NEXT: ds_load_b128 v[4:7], v32 offset:16
; EXACTCUTOFF-NEXT: ds_load_b128 v[12:15], v32 offset:2064
-; EXACTCUTOFF-NEXT: ds_load_b128 v[20:23], v32 offset:6160
-; EXACTCUTOFF-NEXT: ds_load_b128 v[28:31], v32 offset:12304
-; EXACTCUTOFF-NEXT: ds_load_b128 v[36:39], v32 offset:20496
-; EXACTCUTOFF-NEXT: ds_load_b128 v[0:3], v32
; EXACTCUTOFF-NEXT: ds_load_b128 v[8:11], v32 offset:2048
+; EXACTCUTOFF-NEXT: ds_load_b128 v[20:23], v32 offset:6160
; EXACTCUTOFF-NEXT: ds_load_b128 v[16:19], v32 offset:6144
+; EXACTCUTOFF-NEXT: ds_load_b128 v[28:31], v32 offset:12304
; EXACTCUTOFF-NEXT: ds_load_b128 v[24:27], v32 offset:12288
+; EXACTCUTOFF-NEXT: ds_load_b128 v[36:39], v32 offset:20496
; EXACTCUTOFF-NEXT: ds_load_b128 v[32:35], v32 offset:20480
; EXACTCUTOFF-NEXT: ; sched_group_barrier mask(0x00000100) size(10) SyncID(0)
-; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(4)
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v47, v7
-; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(3)
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v55, v15
-; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(2)
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v63, v23
-; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(1)
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v71, v31
-; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(0)
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v79, v39 :: v_dual_mov_b32 v46, v6
+; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(8)
+; EXACTCUTOFF-NEXT: v_mov_b32_e32 v43, v3
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v47, v7 :: v_dual_mov_b32 v46, v6
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v45, v5 :: v_dual_mov_b32 v44, v4
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v43, v3 :: v_dual_mov_b32 v42, v2
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v41, v1 :: v_dual_mov_b32 v40, v0
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v42, v2 :: v_dual_mov_b32 v41, v1
+; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(6)
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v40, v0 :: v_dual_mov_b32 v55, v15
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v53, v13
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v52, v12 :: v_dual_mov_b32 v51, v11
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v49, v9
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v48, v8
+; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(4)
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v63, v23
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v62, v22 :: v_dual_mov_b32 v61, v21
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v60, v20 :: v_dual_mov_b32 v59, v19
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v58, v18 :: v_dual_mov_b32 v57, v17
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v56, v16
+; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(2)
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v56, v16 :: v_dual_mov_b32 v71, v31
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v70, v30 :: v_dual_mov_b32 v69, v29
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v68, v28 :: v_dual_mov_b32 v67, v27
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v66, v26 :: v_dual_mov_b32 v65, v25
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v64, v24
+; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(0)
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v64, v24 :: v_dual_mov_b32 v79, v39
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v78, v38 :: v_dual_mov_b32 v77, v37
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v76, v36 :: v_dual_mov_b32 v75, v35
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v74, v34 :: v_dual_mov_b32 v73, v33
@@ -184,14 +178,15 @@ define amdgpu_kernel void @test_sched_group_barrier_pipeline_WMMA_interleave(ptr
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_add_nc_u32_e32 v17, s0, v16
; GCN-NEXT: v_add_nc_u32_e32 v16, s1, v16
-; GCN-NEXT: ds_load_b128 v[4:7], v17 offset:16
; GCN-NEXT: ds_load_b128 v[0:3], v17
+; GCN-NEXT: ds_load_b128 v[4:7], v17 offset:16
; GCN-NEXT: ; sched_group_barrier mask(0x00000100) size(2) SyncID(0)
; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v11, v3
; GCN-NEXT: v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
; GCN-NEXT: v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
-; GCN-NEXT: v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
-; GCN-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GCN-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v9, v1
+; GCN-NEXT: v_mov_b32_e32 v8, v0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_wmma_f16_16x16x16_f16 v[8:15], v[0:7], v[0:7], v[8:15]
; GCN-NEXT: ; sched_group_barrier mask(0x00000008) size(1) SyncID(0)
@@ -266,14 +261,15 @@ define amdgpu_kernel void @test_sched_group_barrier_pipeline_WMMA_interleave(ptr
; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(0)
; EXACTCUTOFF-NEXT: v_add_nc_u32_e32 v17, s0, v16
; EXACTCUTOFF-NEXT: v_add_nc_u32_e32 v16, s1, v16
-; EXACTCUTOFF-NEXT: ds_load_b128 v[4:7], v17 offset:16
; EXACTCUTOFF-NEXT: ds_load_b128 v[0:3], v17
+; EXACTCUTOFF-NEXT: ds_load_b128 v[4:7], v17 offset:16
; EXACTCUTOFF-NEXT: ; sched_group_barrier mask(0x00000100) size(2) SyncID(0)
; EXACTCUTOFF-NEXT: s_waitcnt lgkmcnt(0)
+; EXACTCUTOFF-NEXT: v_mov_b32_e32 v11, v3
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
; EXACTCUTOFF-NEXT: v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v9, v1
+; EXACTCUTOFF-NEXT: v_mov_b32_e32 v8, v0
; EXACTCUTOFF-NEXT: s_delay_alu instid0(VALU_DEP_1)
; EXACTCUTOFF-NEXT: v_wmma_f16_16x16x16_f16 v[8:15], v[0:7], v[0:7], v[8:15]
; EXACTCUTOFF-NEXT: ; sched_group_barrier mask(0x00000008) size(1) SyncID(0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
index c2f79076fca91..9616f17f25c81 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
@@ -25,24 +25,20 @@ define amdgpu_kernel void @test_sched_group_barrier_pipeline_SWMMAC_cluster(ptr
; GCN-NEXT: ds_load_b128 v[0:3], v0 offset:11264
; GCN-NEXT: ; sched_group_barrier mask(0x00000100) size(7) SyncID(0)
; GCN-NEXT: s_wait_dscnt 0x6
-; GCN-NEXT: v_mov_b32_e32 v31, v11
+; GCN-NEXT: v_dual_mov_b32 v31, v11 :: v_dual_mov_b32 v30, v10
+; GCN-NEXT: v_dual_mov_b32 v29, v9 :: v_dual_mov_b32 v28, v8
; GCN-NEXT: s_wait_dscnt 0x5
-; GCN-NEXT: v_mov_b32_e32 v35, v15
+; GCN-NEXT: v_dual_mov_b32 v35, v15 :: v_dual_mov_b32 v34, v14
+; GCN-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v32, v12
; GCN-NEXT: s_wait_dscnt 0x4
-; GCN-NEXT: v_mov_b32_e32 v39, v19
+; GCN-NEXT: v_dual_mov_b32 v39, v19 :: v_dual_mov_b32 v38, v18
+; GCN-NEXT: v_dual_mov_b32 v37, v17 :: v_dual_mov_b32 v36, v16
; GCN-NEXT: s_wait_dscnt 0x3
-; GCN-NEXT: v_mov_b32_e32 v43, v23
+; GCN-NEXT: v_dual_mov_b32 v43, v23 :: v_dual_mov_b32 v42, v22
+; GCN-NEXT: v_dual_mov_b32 v41, v21 :: v_dual_mov_b32 v40, v20
; GCN-NEXT: s_wait_dscnt 0x2
-; GCN-NEXT: v_dual_mov_b32 v47, v27 :: v_dual_mov_b32 v30, v10
-; GCN-NEXT: v_dual_mov_b32 v29, v9 :: v_dual_mov_b32 v28, v8
-; GCN-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13
-; GCN-NEXT: v_mov_b32_e32 v32, v12
-; GCN-NEXT: v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v37, v17
-; GCN-NEXT: v_mov_b32_e32 v36, v16
-; GCN-NEXT: v_dual_mov_b32 v42, v22 :: v_dual_mov_b32 v41, v21
-; GCN-NEXT: v_mov_b32_e32 v40, v20
-; GCN-NEXT: v_dual_mov_b32 v46, v26 :: v_dual_mov_b32 v45, v25
-; GCN-NEXT: v_mov_b32_e32 v44, v24
+; GCN-NEXT: v_dual_mov_b32 v47, v27 :: v_dual_mov_b32 v46, v26
+; GCN-NEXT: v_dual_mov_b32 v45, v25 :: v_dual_mov_b32 v44, v24
; GCN-NEXT: s_wait_dscnt 0x0
; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[28:31], v[8:11], v[0:7], v48
; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[32:35], v[12:15], v[0:7], v48
@@ -77,24 +73,20 @@ define amdgpu_kernel void @test_sched_group_barrier_pipeline_SWMMAC_cluster(ptr
; EXACTCUTOFF-NEXT: ds_load_b128 v[0:3], v0 offset:11264
; EXACTCUTOFF-NEXT: ; sched_group_barrier mask(0x00000100) size(7) SyncID(0)
; EXACTCUTOFF-NEXT: s_wait_dscnt 0x6
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v31, v11
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v31, v11 :: v_dual_mov_b32 v30, v10
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v29, v9 :: v_dual_mov_b32 v28, v8
; EXACTCUTOFF-NEXT: s_wait_dscnt 0x5
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v35, v15
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v35, v15 :: v_dual_mov_b32 v34, v14
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v32, v12
; EXACTCUTOFF-NEXT: s_wait_dscnt 0x4
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v39, v19
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v39, v19 :: v_dual_mov_b32 v38, v18
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v37, v17 :: v_dual_mov_b32 v36, v16
; EXACTCUTOFF-NEXT: s_wait_dscnt 0x3
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v43, v23
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v43, v23 :: v_dual_mov_b32 v42, v22
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v41, v21 :: v_dual_mov_b32 v40, v20
; EXACTCUTOFF-NEXT: s_wait_dscnt 0x2
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v47, v27 :: v_dual_mov_b32 v30, v10
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v29, v9 :: v_dual_mov_b32 v28, v8
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v32, v12
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v37, v17
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v36, v16
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v42, v22 :: v_dual_mov_b32 v41, v21
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v40, v20
-; EXACTCUTOFF-NEXT: v_dual_mov_b32 v46, v26 :: v_dual_mov_b32 v45, v25
-; EXACTCUTOFF-NEXT: v_mov_b32_e32 v44, v24
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v47, v27 :: v_dual_mov_b32 v46, v26
+; EXACTCUTOFF-NEXT: v_dual_mov_b32 v45, v25 :: v_dual_mov_b32 v44, v24
; EXACTCUTOFF-NEXT: s_wait_dscnt 0x0
; EXACTCUTOFF-NEXT: v_swmmac_f16_16x16x32_f16 v[28:31], v[8:11], v[0:7], v48
; EXACTCUTOFF-NEXT: v_swmmac_f16_16x16x32_f16 v[32:35], v[12:15], v[0:7], v48
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
index 373afad8842a4..b8fb7cc43179b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
@@ -91,15 +91,25 @@ define amdgpu_kernel void @test_get_ddid(ptr addrspace(1) %out) {
}
define amdgpu_kernel void @test_get_tma(ptr addrspace(1) %out) {
-; GFX11-LABEL: test_get_tma:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TMA)
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: test_get_tma:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TMA)
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: test_get_tma:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TMA)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: test_get_tma:
; GFX1250: ; %bb.0:
@@ -117,15 +127,25 @@ define amdgpu_kernel void @test_get_tma(ptr addrspace(1) %out) {
}
define amdgpu_kernel void @test_get_realtime(ptr addrspace(1) %out) {
-; GFX11-LABEL: test_get_realtime:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: test_get_realtime:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: test_get_realtime:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: test_get_realtime:
; GFX1250: ; %bb.0:
@@ -186,15 +206,25 @@ define amdgpu_kernel void @test_savewave(ptr addrspace(1) %out) {
}
define amdgpu_kernel void @test_get_tba(ptr addrspace(1) %out) {
-; GFX11-LABEL: test_get_tba:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TBA)
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: test_get_tba:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TBA)
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: test_get_tba:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_TBA)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: test_get_tba:
; GFX1250: ; %bb.0:
@@ -255,15 +285,25 @@ define amdgpu_kernel void @test_get_0_i32(ptr addrspace(1) %out) {
}
define amdgpu_kernel void @test_get_99999_i64(ptr addrspace(1) %out) {
-; GFX11-LABEL: test_get_99999_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], 99999
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: test_get_99999_i64:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: s_sendmsg_rtn_b64 s[2:3], 99999
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: test_get_99999_i64:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_sendmsg_rtn_b64 s[2:3], 99999
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: test_get_99999_i64:
; GFX1250: ; %bb.0:
@@ -281,15 +321,25 @@ define amdgpu_kernel void @test_get_99999_i64(ptr addrspace(1) %out) {
}
define amdgpu_kernel void @test_get_136_i64(ptr addrspace(1) %out) {
-; GFX11-LABEL: test_get_136_i64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(136, 0, 0)
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
+; GFX11-SDAG-LABEL: test_get_136_i64:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(136, 0, 0)
+; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-SDAG-NEXT: s_endpgm
+;
+; GFX11-GISEL-LABEL: test_get_136_i64:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_sendmsg_rtn_b64 s[2:3], sendmsg(136, 0, 0)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: test_get_136_i64:
; GFX1250: ; %bb.0:
@@ -308,3 +358,5 @@ define amdgpu_kernel void @test_get_136_i64(ptr addrspace(1) %out) {
declare i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32)
declare i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
index 4cb8eb820fcf1..bb842c4af9f8c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
@@ -301,10 +301,10 @@ define <4 x float> @test_smfmac_f32_16x16x64_f16__sgpr(<8 x half> inreg %arg0, <
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[14:15], s[2:3]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[0:1]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[8:9], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[10:11], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[26:27]
; GISEL-VGPR-NEXT: v_mov_b32_e32 v16, s28
; GISEL-VGPR-NEXT: s_nop 1
@@ -820,10 +820,10 @@ define <16 x float> @test_smfmac_f32_32x32x32_f16__sgpr(<8 x half> inreg %arg0,
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s51, v9
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s0, v10
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[16:17], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[20:21], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[22:23], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -1678,10 +1678,10 @@ define <4 x i32> @test_smfmac_i32_16x16x128_i8__sgpr(<4 x i32> inreg %arg0, <8 x
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[14:15], s[2:3]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[0:1]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[8:9], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[10:11], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[26:27]
; GISEL-VGPR-NEXT: v_mov_b32_e32 v16, s28
; GISEL-VGPR-NEXT: s_nop 1
@@ -2209,10 +2209,10 @@ define <16 x i32> @test_smfmac_i32_32x32x64_i8__sgpr(<4 x i32> inreg %arg0, <8 x
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s51, v9
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s0, v10
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[16:17], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[20:21], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[22:23], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -2547,10 +2547,10 @@ define <4 x float> @test_smfmac_f32_16x16x128_bf8_bf8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[14:15], s[2:3]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[0:1]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[8:9], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[10:11], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[26:27]
; GISEL-VGPR-NEXT: v_mov_b32_e32 v16, s28
; GISEL-VGPR-NEXT: s_nop 1
@@ -2868,10 +2868,10 @@ define <4 x float> @test_smfmac_f32_16x16x128_bf8_fp8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[14:15], s[2:3]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[0:1]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[8:9], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[10:11], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[26:27]
; GISEL-VGPR-NEXT: v_mov_b32_e32 v16, s28
; GISEL-VGPR-NEXT: s_nop 1
@@ -3189,10 +3189,10 @@ define <4 x float> @test_smfmac_f32_16x16x128_fp8_bf8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[14:15], s[2:3]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[0:1]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[8:9], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[10:11], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[26:27]
; GISEL-VGPR-NEXT: v_mov_b32_e32 v16, s28
; GISEL-VGPR-NEXT: s_nop 1
@@ -3510,10 +3510,10 @@ define <4 x float> @test_smfmac_f32_16x16x128_fp8_fp8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[14:15], s[2:3]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[12:13], s[0:1]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[8:9], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[10:11], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[26:27]
; GISEL-VGPR-NEXT: v_mov_b32_e32 v16, s28
; GISEL-VGPR-NEXT: s_nop 1
@@ -4041,10 +4041,10 @@ define <16 x float> @test_smfmac_f32_32x32x64_bf8_bf8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s51, v9
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s0, v10
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[16:17], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[20:21], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[22:23], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -4589,10 +4589,10 @@ define <16 x float> @test_smfmac_f32_32x32x64_bf8_fp8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s51, v9
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s0, v10
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[16:17], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[20:21], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[22:23], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -5137,10 +5137,10 @@ define <16 x float> @test_smfmac_f32_32x32x64_fp8_bf8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s51, v9
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s0, v10
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[16:17], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[20:21], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[22:23], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
@@ -5685,10 +5685,10 @@ define <16 x float> @test_smfmac_f32_32x32x64_fp8_fp8__sgpr(<4 x i32> inreg %arg
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s51, v9
; GISEL-VGPR-NEXT: v_readfirstlane_b32 s0, v10
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[16:17], s[16:17]
-; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[18:19], s[18:19]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[20:21], s[20:21]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[22:23], s[22:23]
+; GISEL-VGPR-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[2:3], s[38:39]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[4:5], s[40:41]
; GISEL-VGPR-NEXT: v_mov_b64_e32 v[6:7], s[42:43]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
index ec4572c464dcd..0c0275b1324a7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
@@ -891,13 +891,13 @@ define amdgpu_cs float @buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2
; GFX12-GISEL-NEXT: buffer_load_format_xyzw v[2:6], v7, s[0:3], null idxen tfe
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v6
; GFX12-GISEL-NEXT: ; return to shader part epilog
@@ -985,13 +985,13 @@ define amdgpu_cs float @buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2
; GFX12-GISEL-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], null idxen tfe
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
; GFX12-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v6
; GFX12-GISEL-NEXT: ; return to shader part epilog
@@ -1077,12 +1077,12 @@ define amdgpu_cs float @buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
; GFX12-GISEL-NEXT: v_mov_b32_e32 v5, v2
; GFX12-GISEL-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s2
; GFX12-GISEL-NEXT: global_store_b96 v[0:1], v[2:4], off
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v5
; GFX12-GISEL-NEXT: ; return to shader part epilog
@@ -1168,12 +1168,12 @@ define amdgpu_cs float @buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
; GFX12-GISEL-NEXT: v_mov_b32_e32 v5, v2
; GFX12-GISEL-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s2
; GFX12-GISEL-NEXT: global_store_b96 v[0:1], v[2:4], off
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v5
; GFX12-GISEL-NEXT: ; return to shader part epilog
@@ -1256,7 +1256,7 @@ define amdgpu_cs float @buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v4
; GFX12-GISEL-NEXT: ; return to shader part epilog
@@ -1339,7 +1339,7 @@ define amdgpu_cs float @buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX12-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v4
; GFX12-GISEL-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
index e9ed5f59b1006..2299ece622c24 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
@@ -46,14 +46,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x4_f32_non_splat(<2 x float> %A, <2 x
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -89,15 +89,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x4_f32_non_inlineable(<2 x float> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[10:11], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[12:13], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[8:9], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -406,14 +406,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_fp8_fp8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -449,15 +449,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_fp8_fp8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -516,14 +516,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_fp8_bf8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -559,15 +559,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_fp8_bf8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -626,14 +626,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_bf8_fp8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -669,15 +669,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_bf8_fp8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -736,14 +736,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_bf8_bf8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -779,15 +779,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x64_bf8_bf8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -841,9 +841,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_fp8_fp8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x64_fp8_fp8 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -870,11 +870,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_fp8_fp8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x64_fp8_fp8 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -923,9 +923,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_fp8_bf8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x64_fp8_bf8 v[18:21], v[0:7], v[8:15], v[18:21] neg_hi:[0,0,1]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -952,11 +952,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_fp8_bf8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x64_fp8_bf8 v[18:21], v[0:7], v[8:15], v[18:21] neg_hi:[0,0,1]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -1005,9 +1005,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_bf8_fp8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x64_bf8_fp8 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -1034,11 +1034,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_bf8_fp8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x64_bf8_fp8 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -1087,9 +1087,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_bf8_bf8_non_splat(<8 x i32> %A, <8
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x64_bf8_bf8 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -1116,11 +1116,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x64_bf8_bf8_non_inlineable(<8 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x64_bf8_bf8 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -1174,14 +1174,14 @@ define amdgpu_ps void @test_wmma_i32_16x16x64_iu8_non_splat(<8 x i32> %A, <8 x i
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1
; GISEL-NEXT: s_mov_b32 s2, 2
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1217,15 +1217,15 @@ define amdgpu_ps void @test_wmma_i32_16x16x64_iu8_non_inlineable(<8 x i32> %A, <
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_movk_i32 s0, 0x80
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1284,14 +1284,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x32_f16_non_splat(<16 x half> %A, <16
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1327,15 +1327,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x32_f16_non_inlineable(<16 x half> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1389,9 +1389,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x32_f16_non_splat(<16 x half> %A, <16
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x32_f16 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -1418,11 +1418,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x32_f16_non_inlineable(<16 x half> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x32_f16 v[18:21], v[0:7], v[8:15], v[18:21]
; GISEL-NEXT: global_store_b128 v[16:17], v[18:21], off
; GISEL-NEXT: s_endpgm
@@ -1476,14 +1476,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_f8f6f4_non_splat(<16 x i32> %A, <
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s1, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1519,15 +1519,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_f8f6f4_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1586,14 +1586,14 @@ define amdgpu_ps void @test_wmma_scale_f32_16x16x128_f8f6f4_non_splat(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s1, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1630,15 +1630,15 @@ define amdgpu_ps void @test_wmma_scale_f32_16x16x128_f8f6f4_non_inlineable(<16 x
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: v_mov_b32_e32 v42, 0x64
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: v_mov_b32_e32 v43, 0x65
@@ -1698,14 +1698,14 @@ define amdgpu_ps void @test_wmma_scale16_f32_16x16x128_f8f6f4_non_splat(<16 x i3
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s1, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -1743,15 +1743,15 @@ define amdgpu_ps void @test_wmma_scale16_f32_16x16x128_f8f6f4_non_inlineable(<16
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: v_mov_b64_e32 v[42:43], 0x64
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[44:45], 0x65
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
@@ -1806,9 +1806,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_fp8_fp8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x128_fp8_fp8 v[34:37], v[0:15], v[16:31], v[34:37]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -1835,11 +1835,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_fp8_fp8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x128_fp8_fp8 v[34:37], v[0:15], v[16:31], v[34:37]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -1888,9 +1888,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_fp8_bf8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x128_fp8_bf8 v[34:37], v[0:15], v[16:31], v[34:37] neg_hi:[0,0,1]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -1917,11 +1917,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_fp8_bf8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x128_fp8_bf8 v[34:37], v[0:15], v[16:31], v[34:37] neg_hi:[0,0,1]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -1970,9 +1970,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_bf8_fp8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x128_bf8_fp8 v[34:37], v[0:15], v[16:31], v[34:37]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -1999,11 +1999,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_bf8_fp8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x128_bf8_fp8 v[34:37], v[0:15], v[16:31], v[34:37]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -2052,9 +2052,9 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_bf8_bf8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_mov_b32 s1, 0x3c004000
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_wmma_f16_16x16x128_bf8_bf8 v[34:37], v[0:15], v[16:31], v[34:37]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -2081,11 +2081,11 @@ define amdgpu_ps void @test_wmma_f16_16x16x128_bf8_bf8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x42004200
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
-; GISEL-NEXT: s_mov_b32 s1, s0
-; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
+; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_wmma_f16_16x16x128_bf8_bf8 v[34:37], v[0:15], v[16:31], v[34:37]
; GISEL-NEXT: global_store_b128 v[32:33], v[34:37], off
; GISEL-NEXT: s_endpgm
@@ -2139,14 +2139,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_fp8_fp8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2182,15 +2182,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_fp8_fp8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2249,14 +2249,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_fp8_bf8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2292,15 +2292,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_fp8_bf8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2359,14 +2359,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_bf8_fp8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2402,15 +2402,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_bf8_fp8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2469,14 +2469,14 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_bf8_bf8_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2512,15 +2512,15 @@ define amdgpu_ps void @test_wmma_f32_16x16x128_bf8_bf8_non_inlineable(<16 x i32>
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s6, s0
-; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
; GISEL-NEXT: s_mov_b32 s5, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
+; GISEL-NEXT: s_mov_b32 s6, s0
+; GISEL-NEXT: s_mov_b32 s7, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[6:7]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2590,8 +2590,6 @@ define amdgpu_ps void @test_wmma_f32_32x16x128_f4_non_splat(<16 x i32> %A, <8 x
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s2, 2.0
-; GISEL-NEXT: s_mov_b32 s14, s0
-; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
@@ -2604,8 +2602,10 @@ define amdgpu_ps void @test_wmma_f32_32x16x128_f4_non_splat(<16 x i32> %A, <8 x
; GISEL-NEXT: s_mov_b32 s11, s0
; GISEL-NEXT: s_mov_b32 s12, s0
; GISEL-NEXT: s_mov_b32 s13, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
+; GISEL-NEXT: s_mov_b32 s14, s0
+; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[6:7]
@@ -2654,8 +2654,6 @@ define amdgpu_ps void @test_wmma_f32_32x16x128_f4_non_inlineable(<16 x i32> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b32 s14, s0
-; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
@@ -2669,8 +2667,10 @@ define amdgpu_ps void @test_wmma_f32_32x16x128_f4_non_inlineable(<16 x i32> %A,
; GISEL-NEXT: s_mov_b32 s11, s0
; GISEL-NEXT: s_mov_b32 s12, s0
; GISEL-NEXT: s_mov_b32 s13, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
+; GISEL-NEXT: s_mov_b32 s14, s0
+; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[6:7]
@@ -2746,8 +2746,6 @@ define amdgpu_ps void @test_wmma_scale_f32_32x16x128_f4_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s1, 2.0
-; GISEL-NEXT: s_mov_b32 s14, s0
-; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
@@ -2760,8 +2758,10 @@ define amdgpu_ps void @test_wmma_scale_f32_32x16x128_f4_non_splat(<16 x i32> %A,
; GISEL-NEXT: s_mov_b32 s11, s0
; GISEL-NEXT: s_mov_b32 s12, s0
; GISEL-NEXT: s_mov_b32 s13, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
+; GISEL-NEXT: s_mov_b32 s14, s0
+; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[6:7]
@@ -2811,8 +2811,6 @@ define amdgpu_ps void @test_wmma_scale_f32_32x16x128_f4_non_inlineable(<16 x i32
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: v_mov_b32_e32 v42, 0x64
-; GISEL-NEXT: s_mov_b32 s14, s0
-; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
@@ -2826,8 +2824,10 @@ define amdgpu_ps void @test_wmma_scale_f32_32x16x128_f4_non_inlineable(<16 x i32
; GISEL-NEXT: s_mov_b32 s11, s0
; GISEL-NEXT: s_mov_b32 s12, s0
; GISEL-NEXT: s_mov_b32 s13, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
+; GISEL-NEXT: s_mov_b32 s14, s0
+; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[6:7]
@@ -2904,8 +2904,6 @@ define amdgpu_ps void @test_wmma_scale16_f32_32x16x128_f4_non_splat(<16 x i32> %
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 1.0
; GISEL-NEXT: s_mov_b32 s1, 2.0
-; GISEL-NEXT: s_mov_b32 s14, s0
-; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
; GISEL-NEXT: s_mov_b32 s4, s0
@@ -2918,8 +2916,10 @@ define amdgpu_ps void @test_wmma_scale16_f32_32x16x128_f4_non_splat(<16 x i32> %
; GISEL-NEXT: s_mov_b32 s11, s0
; GISEL-NEXT: s_mov_b32 s12, s0
; GISEL-NEXT: s_mov_b32 s13, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
+; GISEL-NEXT: s_mov_b32 s14, s0
+; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[6:7]
@@ -2970,8 +2970,6 @@ define amdgpu_ps void @test_wmma_scale16_f32_32x16x128_f4_non_inlineable(<16 x i
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b32 s0, 0x40400000
; GISEL-NEXT: v_mov_b64_e32 v[42:43], 0x64
-; GISEL-NEXT: s_mov_b32 s14, s0
-; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: s_mov_b32 s1, s0
; GISEL-NEXT: s_mov_b32 s2, s0
; GISEL-NEXT: s_mov_b32 s3, s0
@@ -2985,8 +2983,10 @@ define amdgpu_ps void @test_wmma_scale16_f32_32x16x128_f4_non_inlineable(<16 x i
; GISEL-NEXT: s_mov_b32 s11, s0
; GISEL-NEXT: s_mov_b32 s12, s0
; GISEL-NEXT: s_mov_b32 s13, s0
-; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
+; GISEL-NEXT: s_mov_b32 s14, s0
+; GISEL-NEXT: s_mov_b32 s15, s0
; GISEL-NEXT: v_mov_b64_e32 v[38:39], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[40:41], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[36:37], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[34:35], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[32:33], s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
index f654d63b70a63..44820e8841586 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
@@ -57,14 +57,14 @@ define amdgpu_ps void @test_wmma_f64_16x16x4_f64_non_splat(<2 x double> %A, <2 x
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b64 s[0:1], 1.0
; GISEL-NEXT: s_mov_b64 s[4:5], 2.0
-; GISEL-NEXT: s_mov_b64 s[14:15], s[0:1]
; GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
; GISEL-NEXT: s_mov_b64 s[8:9], s[0:1]
; GISEL-NEXT: s_mov_b64 s[10:11], s[0:1]
; GISEL-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[14:15]
+; GISEL-NEXT: s_mov_b64 s[14:15], s[0:1]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[6:7]
@@ -112,15 +112,15 @@ define amdgpu_ps void @test_wmma_f64_16x16x4_f64_non_inlineable(<2 x double> %A,
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT: s_mov_b64 s[0:1], 0x4008000000000000
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_mov_b64 s[14:15], s[0:1]
; GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
; GISEL-NEXT: s_mov_b64 s[4:5], s[0:1]
; GISEL-NEXT: s_mov_b64 s[6:7], s[0:1]
; GISEL-NEXT: s_mov_b64 s[8:9], s[0:1]
; GISEL-NEXT: s_mov_b64 s[10:11], s[0:1]
; GISEL-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[14:15]
+; GISEL-NEXT: s_mov_b64 s[14:15], s[0:1]
; GISEL-NEXT: v_mov_b64_e32 v[22:23], s[12:13]
+; GISEL-NEXT: v_mov_b64_e32 v[24:25], s[14:15]
; GISEL-NEXT: v_mov_b64_e32 v[20:21], s[10:11]
; GISEL-NEXT: v_mov_b64_e32 v[18:19], s[8:9]
; GISEL-NEXT: v_mov_b64_e32 v[16:17], s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
index 588232df486b7..4ed450ad4024f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
@@ -534,8 +534,8 @@ define amdgpu_kernel void @test_writelane_imm_sreg_f64(ptr addrspace(1) %out, i3
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX802-SDAG-NEXT: s_mov_b32 m0, s4
-; GFX802-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX802-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX802-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX802-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: v_mov_b32_e32 v1, s3
@@ -590,8 +590,8 @@ define amdgpu_kernel void @test_writelane_imm_sreg_f64(ptr addrspace(1) %out, i3
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX802-GISEL-NEXT: s_mov_b32 m0, s4
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX802-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s2
@@ -656,13 +656,13 @@ define amdgpu_kernel void @test_writelane_vreg_lane_i32(ptr addrspace(1) %out, p
; GFX802-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX802-SDAG-NEXT: flat_load_dword v0, v[0:1]
; GFX802-SDAG-NEXT: s_load_dword s2, s[0:1], 0x0
+; GFX802-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: v_mov_b32_e32 v2, s2
; GFX802-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX802-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; GFX802-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; GFX802-SDAG-NEXT: s_nop 1
+; GFX802-SDAG-NEXT: s_nop 2
; GFX802-SDAG-NEXT: v_writelane_b32 v2, 12, s2
; GFX802-SDAG-NEXT: flat_store_dword v[0:1], v2
; GFX802-SDAG-NEXT: s_endpgm
@@ -719,13 +719,13 @@ define amdgpu_kernel void @test_writelane_vreg_lane_i32(ptr addrspace(1) %out, p
; GFX802-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX802-GISEL-NEXT: flat_load_dword v0, v[0:1]
; GFX802-GISEL-NEXT: s_load_dword s2, s[0:1], 0x0
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX802-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX802-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX802-GISEL-NEXT: s_nop 1
+; GFX802-GISEL-NEXT: s_nop 2
; GFX802-GISEL-NEXT: v_writelane_b32 v2, 12, s2
; GFX802-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX802-GISEL-NEXT: s_endpgm
@@ -791,14 +791,14 @@ define amdgpu_kernel void @test_writelane_vreg_lane_i64(ptr addrspace(1) %out, p
; GFX802-SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX802-SDAG-NEXT: flat_load_dword v2, v[0:1]
; GFX802-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX802-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX802-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX802-SDAG-NEXT: v_readfirstlane_b32 s2, v2
-; GFX802-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX802-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX802-SDAG-NEXT: s_nop 1
+; GFX802-SDAG-NEXT: s_nop 2
; GFX802-SDAG-NEXT: v_writelane_b32 v1, 0, s2
; GFX802-SDAG-NEXT: v_writelane_b32 v0, 12, s2
; GFX802-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -937,15 +937,16 @@ define amdgpu_kernel void @test_writelane_vreg_lane_f64(ptr addrspace(1) %out, p
; GFX802-SDAG-NEXT: flat_load_dword v2, v[0:1]
; GFX802-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX802-SDAG-NEXT: s_mov_b32 s4, 0x40280000
+; GFX802-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX802-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX802-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX802-SDAG-NEXT: v_readfirstlane_b32 s2, v2
; GFX802-SDAG-NEXT: s_mov_b32 m0, s2
-; GFX802-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX802-SDAG-NEXT: v_writelane_b32 v1, s4, m0
; GFX802-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX802-SDAG-NEXT: s_nop 0
; GFX802-SDAG-NEXT: v_writelane_b32 v0, 0, s2
; GFX802-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX802-SDAG-NEXT: s_endpgm
@@ -1086,9 +1087,9 @@ define amdgpu_kernel void @test_writelane_m0_sreg_i32(ptr addrspace(1) %out, i32
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: s_load_dword s3, s[0:1], 0x0
; GFX802-SDAG-NEXT: s_mov_b32 m0, s2
-; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX802-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX802-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: v_mov_b32_e32 v2, s3
; GFX802-SDAG-NEXT: v_writelane_b32 v2, s4, m0
@@ -1142,9 +1143,9 @@ define amdgpu_kernel void @test_writelane_m0_sreg_i32(ptr addrspace(1) %out, i32
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: s_load_dword s3, s[0:1], 0x0
; GFX802-GISEL-NEXT: s_mov_b32 m0, s2
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX802-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s3
; GFX802-GISEL-NEXT: v_writelane_b32 v2, s4, m0
@@ -1495,8 +1496,8 @@ define amdgpu_kernel void @test_writelane_sreg_oldval_i32(i32 %oldval, ptr addrs
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: v_mov_b32_e32 v2, s4
; GFX802-SDAG-NEXT: s_mov_b32 m0, s3
-; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX802-SDAG-NEXT: v_writelane_b32 v2, s2, m0
+; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX802-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX802-SDAG-NEXT: flat_store_dword v[0:1], v2
; GFX802-SDAG-NEXT: s_endpgm
@@ -1535,8 +1536,8 @@ define amdgpu_kernel void @test_writelane_sreg_oldval_i32(i32 %oldval, ptr addrs
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s4
; GFX802-GISEL-NEXT: s_mov_b32 m0, s3
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: v_writelane_b32 v2, s2, m0
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX802-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX802-GISEL-NEXT: s_endpgm
@@ -1630,10 +1631,10 @@ define amdgpu_kernel void @test_writelane_sreg_oldval_i64(i64 %oldval, ptr addrs
; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX802-GISEL-NEXT: s_mov_b32 m0, s6
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX802-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX802-GISEL-NEXT: v_writelane_b32 v0, s4, m0
; GFX802-GISEL-NEXT: v_writelane_b32 v1, s5, m0
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX802-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX802-GISEL-NEXT: s_endpgm
@@ -1733,10 +1734,10 @@ define amdgpu_kernel void @test_writelane_sreg_oldval_f64(double %oldval, ptr ad
; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX802-GISEL-NEXT: s_mov_b32 m0, s6
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX802-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX802-GISEL-NEXT: v_writelane_b32 v0, s4, m0
; GFX802-GISEL-NEXT: v_writelane_b32 v1, s5, m0
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s3
; GFX802-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX802-GISEL-NEXT: s_endpgm
@@ -1785,8 +1786,8 @@ define amdgpu_kernel void @test_writelane_imm_oldval_i32(ptr addrspace(1) %out,
; GFX802-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX802-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-SDAG-NEXT: s_mov_b32 m0, s3
-; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX802-SDAG-NEXT: v_writelane_b32 v2, s2, m0
+; GFX802-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX802-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX802-SDAG-NEXT: flat_store_dword v[0:1], v2
; GFX802-SDAG-NEXT: s_endpgm
@@ -1820,8 +1821,8 @@ define amdgpu_kernel void @test_writelane_imm_oldval_i32(ptr addrspace(1) %out,
; GFX802-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: s_mov_b32 m0, s3
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: v_writelane_b32 v2, s2, m0
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX802-GISEL-NEXT: flat_store_dword v[0:1], v2
; GFX802-GISEL-NEXT: s_endpgm
@@ -1906,11 +1907,11 @@ define amdgpu_kernel void @test_writelane_imm_oldval_i64(ptr addrspace(1) %out,
; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: s_mov_b32 m0, s4
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX802-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX802-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX802-GISEL-NEXT: v_writelane_b32 v0, s2, m0
; GFX802-GISEL-NEXT: v_writelane_b32 v1, s3, m0
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX802-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX802-GISEL-NEXT: s_endpgm
@@ -2003,11 +2004,11 @@ define amdgpu_kernel void @test_writelane_imm_oldval_f64(ptr addrspace(1) %out,
; GFX802-GISEL-NEXT: v_mov_b32_e32 v1, 0x40450000
; GFX802-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX802-GISEL-NEXT: s_mov_b32 m0, s4
-; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX802-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX802-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX802-GISEL-NEXT: v_writelane_b32 v0, s2, m0
; GFX802-GISEL-NEXT: v_writelane_b32 v1, s3, m0
+; GFX802-GISEL-NEXT: v_mov_b32_e32 v3, s1
; GFX802-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX802-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX802-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
index a0a983f1c977b..5cfde136295a8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
@@ -414,11 +414,11 @@ define <2 x double> @v_exp_v2f64(<2 x double> %in) #0 {
; SI-SDAG-NEXT: v_add_f64 v[6:7], v[16:17], -v[6:7]
; SI-SDAG-NEXT: s_mov_b32 s12, 0xfca7ab0c
; SI-SDAG-NEXT: s_mov_b32 s13, 0x3e928af3
-; SI-SDAG-NEXT: v_mov_b32_e32 v10, s12
; SI-SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc
; SI-SDAG-NEXT: s_mov_b32 s14, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s15, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v10, s12
; SI-SDAG-NEXT: v_mov_b32_e32 v11, s13
; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[8:9], v[2:3]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[8:9], s[14:15], v[10:11]
@@ -589,8 +589,8 @@ define <2 x double> @v_exp_v2f64(<2 x double> %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[6:7], v[2:3], s[4:5]
; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
-; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: v_mov_b32_e32 v13, s7
; VI-SDAG-NEXT: v_mov_b32_e32 v12, s6
; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
@@ -755,8 +755,8 @@ define <2 x double> @v_exp_v2f64(<2 x double> %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], v[2:3], s[4:5]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, s6
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
@@ -938,12 +938,12 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[11:12], s[10:11], v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s12, 0x3b39803f
; SI-SDAG-NEXT: s_mov_b32 s13, 0xbc7abc9e
-; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[11:12], s[12:13], v[7:8]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v9, s5
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s14, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s15, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v9, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v8, s4
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[13:14], s[14:15], v[8:9]
; SI-SDAG-NEXT: s_mov_b32 s16, 0x623fde64
@@ -1180,13 +1180,13 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[8:9], v[2:3], s[4:5]
; VI-SDAG-NEXT: s_mov_b32 s8, 0x3b39803f
; VI-SDAG-NEXT: s_mov_b32 s9, 0xbc7abc9e
-; VI-SDAG-NEXT: s_mov_b32 s11, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s10, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s11, 0x3e928af3
; VI-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; VI-SDAG-NEXT: v_mov_b32_e32 v13, s11
; VI-SDAG-NEXT: s_mov_b32 s12, 0x6a5dcb37
-; VI-SDAG-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; VI-SDAG-NEXT: s_mov_b32 s13, 0x3e5ade15
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; VI-SDAG-NEXT: v_mov_b32_e32 v13, s11
; VI-SDAG-NEXT: v_mov_b32_e32 v12, s10
; VI-SDAG-NEXT: s_mov_b32 s10, 0x623fde64
; VI-SDAG-NEXT: s_mov_b32 s11, 0x3ec71dee
@@ -1392,13 +1392,13 @@ define <3 x double> @v_exp_v3f64(<3 x double> %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[8:9], v[2:3], s[4:5]
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x3b39803f
; GFX900-SDAG-NEXT: s_mov_b32 s9, 0xbc7abc9e
-; GFX900-SDAG-NEXT: s_mov_b32 s11, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s10, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s11, 0x3e928af3
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s11
; GFX900-SDAG-NEXT: s_mov_b32 s12, 0x6a5dcb37
-; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX900-SDAG-NEXT: s_mov_b32 s13, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s11
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, s10
; GFX900-SDAG-NEXT: s_mov_b32 s10, 0x623fde64
; GFX900-SDAG-NEXT: s_mov_b32 s11, 0x3ec71dee
@@ -1633,12 +1633,12 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_cndmask_b32_e32 v14, v16, v14, vcc
; SI-SDAG-NEXT: v_fma_f64 v[16:17], v[10:11], s[10:11], v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s13, 0xbc7abc9e
-; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[19:20], v[10:11], s[12:13], v[16:17]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v17, s5
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s16, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s17, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v17, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v16, s4
; SI-SDAG-NEXT: v_fma_f64 v[21:22], v[19:20], s[16:17], v[16:17]
; SI-SDAG-NEXT: s_mov_b32 s14, 0x623fde64
@@ -1917,8 +1917,8 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s19, 0xbfe62e42
; VI-SDAG-NEXT: s_mov_b32 s20, 0x3b39803f
; VI-SDAG-NEXT: s_mov_b32 s21, 0xbc7abc9e
-; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s22, 0x6a5dcb37
; VI-SDAG-NEXT: v_rndne_f64_e32 v[10:11], v[8:9]
; VI-SDAG-NEXT: s_mov_b32 s23, 0x3e5ade15
@@ -2175,8 +2175,8 @@ define <4 x double> @v_exp_v4f64(<4 x double> %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s19, 0xbfe62e42
; GFX900-SDAG-NEXT: s_mov_b32 s20, 0x3b39803f
; GFX900-SDAG-NEXT: s_mov_b32 s21, 0xbc7abc9e
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s22, 0x6a5dcb37
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[10:11], v[8:9]
; GFX900-SDAG-NEXT: s_mov_b32 s23, 0x3e5ade15
@@ -2444,8 +2444,8 @@ define amdgpu_ps <2 x i32> @s_exp_f64(double inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s2, 0xfefa39ef
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; SI-SDAG-NEXT: s_mov_b32 s3, 0xbfe62e42
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; SI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[0:1], s[2:3], v[2:3]
; SI-SDAG-NEXT: s_mov_b32 s2, 0x3b39803f
@@ -2521,9 +2521,9 @@ define amdgpu_ps <2 x i32> @s_exp_f64(double inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
; SI-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xfefa39ef
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fe62e42
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
; SI-GISEL-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3b39803f
@@ -2583,9 +2583,9 @@ define amdgpu_ps <2 x i32> @s_exp_f64(double inreg %in) #0 {
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x652b82fe
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x3ff71547
; VI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: s_mov_b32 s2, 0xfefa39ef
; VI-SDAG-NEXT: s_mov_b32 s3, 0xbfe62e42
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0xfca7ab0c
; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x3e928af3
@@ -2706,9 +2706,9 @@ define amdgpu_ps <2 x i32> @s_exp_f64(double inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x652b82fe
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x3ff71547
; GFX900-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX900-SDAG-NEXT: s_mov_b32 s2, 0xfefa39ef
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0xbfe62e42
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0xfca7ab0c
; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0x3e928af3
@@ -2848,8 +2848,8 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s6, 0xfefa39ef
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v6, s3
; SI-SDAG-NEXT: s_mov_b32 s7, 0xbfe62e42
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s3
; SI-SDAG-NEXT: v_mov_b32_e32 v5, s2
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], s[6:7], v[5:6]
; SI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
@@ -2867,9 +2867,9 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mov_b32_e32 v4, s0
; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[6:7], v[4:5]
; SI-SDAG-NEXT: s_mov_b32 s11, 0x3e928af3
-; SI-SDAG-NEXT: v_mov_b32_e32 v8, s10
; SI-SDAG-NEXT: s_mov_b32 s12, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s13, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v8, s10
; SI-SDAG-NEXT: v_mov_b32_e32 v9, s11
; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[8:9], v[4:5]
; SI-SDAG-NEXT: v_fma_f64 v[10:11], v[6:7], s[12:13], v[8:9]
@@ -2959,9 +2959,9 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s11, v5
; SI-GISEL-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
; SI-GISEL-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xfefa39ef
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3fe62e42
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; SI-GISEL-NEXT: v_mov_b32_e32 v5, s5
; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x3b39803f
@@ -3061,16 +3061,16 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s5
; VI-SDAG-NEXT: v_mul_f64 v[2:3], s[2:3], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; VI-SDAG-NEXT: v_mov_b32_e32 v7, s1
; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s3
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s2
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v6, s0
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
-; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: v_mov_b32_e32 v9, s7
; VI-SDAG-NEXT: v_mov_b32_e32 v8, s6
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
@@ -3240,16 +3240,16 @@ define amdgpu_ps <4 x i32> @s_exp_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s5
; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], s[2:3], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, s3
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, s2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s0
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s6
; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
@@ -3435,18 +3435,18 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s8, 0xfefa39ef
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v6, s5
; SI-SDAG-NEXT: s_mov_b32 s9, 0xbfe62e42
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v5, s4
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], s[8:9], v[5:6]
; SI-SDAG-NEXT: s_mov_b32 s12, 0x3b39803f
; SI-SDAG-NEXT: s_mov_b32 s13, 0xbc7abc9e
-; SI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], s[12:13], v[5:6]
; SI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v8, s7
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s14, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s15, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v8, s7
; SI-SDAG-NEXT: v_mov_b32_e32 v7, s6
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[5:6], s[14:15], v[7:8]
; SI-SDAG-NEXT: s_mov_b32 s16, 0x623fde64
@@ -3499,9 +3499,9 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_add_f64 v[3:4], v[15:16], -v[4:5]
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, s[10:11]
; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[13:14], s[14:15], v[7:8]
-; SI-SDAG-NEXT: v_mov_b32_e32 v16, s1
; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[6:7]
; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[6:7]
+; SI-SDAG-NEXT: v_mov_b32_e32 v16, s1
; SI-SDAG-NEXT: v_mov_b32_e32 v15, s0
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[13:14], v[17:18], s[16:17]
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[0:1], s[8:9], v[15:16]
@@ -3578,9 +3578,9 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s13, v5
; SI-GISEL-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
; SI-GISEL-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, s10
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xfefa39ef
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3fe62e42
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s10
; SI-GISEL-NEXT: v_mov_b32_e32 v5, s11
; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x3b39803f
@@ -3718,19 +3718,19 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[2:3], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, s3
; VI-SDAG-NEXT: s_mov_b32 s6, 0xfefa39ef
; VI-SDAG-NEXT: s_mov_b32 s7, 0xbfe62e42
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, s5
; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v9, s3
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
; VI-SDAG-NEXT: v_mov_b32_e32 v8, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v11, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v10, s0
-; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[2:3], s[6:7], v[6:7]
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[4:5], s[6:7], v[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[0:1], s[6:7], v[10:11]
@@ -3949,19 +3949,19 @@ define amdgpu_ps <6 x i32> @s_exp_v3f64(<3 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], s[4:5], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0xfefa39ef
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xbfe62e42
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s5
; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s3
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
; GFX900-SDAG-NEXT: v_mov_b32_e32 v11, s1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v10, s0
-; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[2:3], s[6:7], v[6:7]
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[4:5], s[6:7], v[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[0:1], s[6:7], v[10:11]
@@ -4195,8 +4195,8 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s8, 0xfefa39ef
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v5, s6
; SI-SDAG-NEXT: s_mov_b32 s9, 0xbfe62e42
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, s6
; SI-SDAG-NEXT: v_mov_b32_e32 v6, s7
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], s[8:9], v[5:6]
; SI-SDAG-NEXT: v_mul_f64 v[8:9], s[4:5], v[0:1]
@@ -4214,11 +4214,11 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_bfi_b32 v5, s33, v19, v12
; SI-SDAG-NEXT: v_add_f64 v[13:14], v[11:12], v[4:5]
; SI-SDAG-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v15, s16
; SI-SDAG-NEXT: v_add_f64 v[13:14], v[13:14], -v[4:5]
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[11:12]|, s[12:13]
; SI-SDAG-NEXT: s_mov_b32 s14, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s15, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v15, s16
; SI-SDAG-NEXT: v_mov_b32_e32 v16, s17
; SI-SDAG-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc
@@ -4241,26 +4241,26 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s26, 0x555502a1
; SI-SDAG-NEXT: s_mov_b32 s27, 0x3fa55555
; SI-SDAG-NEXT: v_mov_b32_e32 v18, s5
-; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[6:7], v[13:14], s[26:27]
; SI-SDAG-NEXT: v_mov_b32_e32 v17, s4
+; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[6:7], v[13:14], s[26:27]
+; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[8:9], s[8:9], v[17:18]
; SI-SDAG-NEXT: s_mov_b32 s28, 0x55555511
; SI-SDAG-NEXT: s_mov_b32 s29, 0x3fc55555
-; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[8:9], s[8:9], v[17:18]
; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[6:7], v[13:14], s[28:29]
+; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[8:9], s[10:11], v[17:18]
; SI-SDAG-NEXT: s_mov_b32 s30, 11
; SI-SDAG-NEXT: s_mov_b32 s31, 0x3fe00000
-; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[8:9], s[10:11], v[17:18]
; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[6:7], v[13:14], s[30:31]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[17:18], s[14:15], v[15:16]
; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[6:7], v[13:14], 1.0
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[17:18], v[2:3], s[16:17]
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[6:7], v[13:14], 1.0
-; SI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[17:18], v[2:3], s[18:19]
+; SI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
; SI-SDAG-NEXT: v_ldexp_f64 v[6:7], v[5:6], v10
-; SI-SDAG-NEXT: v_bfi_b32 v5, s33, v19, v1
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[17:18], v[2:3], s[20:21]
+; SI-SDAG-NEXT: v_bfi_b32 v5, s33, v19, v1
; SI-SDAG-NEXT: v_add_f64 v[19:20], v[0:1], v[4:5]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[17:18], v[2:3], s[22:23]
; SI-SDAG-NEXT: v_add_f64 v[4:5], v[19:20], -v[4:5]
@@ -4280,10 +4280,10 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[19:20], v[4:5], v[19:20], s[16:17]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[17:18], v[2:3], 1.0
; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[4:5], v[19:20], s[18:19]
-; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v10, v[8:9]
-; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[4:5], v[17:18], s[20:21]
; SI-SDAG-NEXT: v_mov_b32_e32 v13, 0
+; SI-SDAG-NEXT: v_fma_f64 v[17:18], v[4:5], v[17:18], s[20:21]
; SI-SDAG-NEXT: v_mov_b32_e32 v14, 0x40900000
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v10, v[8:9]
; SI-SDAG-NEXT: v_fma_f64 v[8:9], v[4:5], v[17:18], s[22:23]
; SI-SDAG-NEXT: v_cmp_ngt_f64_e32 vcc, s[6:7], v[13:14]
; SI-SDAG-NEXT: v_mov_b32_e32 v19, 0x7ff00000
@@ -4370,9 +4370,9 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s15, v5
; SI-GISEL-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17]
; SI-GISEL-NEXT: s_cselect_b64 s[12:13], s[12:13], s[14:15]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, s12
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xfefa39ef
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3fe62e42
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s12
; SI-GISEL-NEXT: v_mov_b32_e32 v5, s13
; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x3b39803f
@@ -4545,9 +4545,9 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s8
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s9
; VI-SDAG-NEXT: v_mul_f64 v[2:3], s[6:7], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v6, s6
; VI-SDAG-NEXT: s_mov_b32 s8, 0xfefa39ef
; VI-SDAG-NEXT: s_mov_b32 s9, 0xbfe62e42
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s6
; VI-SDAG-NEXT: v_mov_b32_e32 v7, s7
; VI-SDAG-NEXT: v_mul_f64 v[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: s_mov_b32 s10, 0x3b39803f
@@ -4555,10 +4555,10 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: s_mov_b32 s14, 0xfca7ab0c
; VI-SDAG-NEXT: s_mov_b32 s15, 0x3e928af3
-; VI-SDAG-NEXT: v_mov_b32_e32 v10, s14
; VI-SDAG-NEXT: s_mov_b32 s12, 0x6a5dcb37
-; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; VI-SDAG-NEXT: s_mov_b32 s13, 0x3e5ade15
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v10, s14
; VI-SDAG-NEXT: v_mov_b32_e32 v11, s15
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[2:3], s[8:9], v[6:7]
; VI-SDAG-NEXT: v_mov_b32_e32 v9, s5
@@ -4828,9 +4828,9 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, s8
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s9
; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], s[6:7], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s6
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0xfefa39ef
; GFX900-SDAG-NEXT: s_mov_b32 s9, 0xbfe62e42
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s6
; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s7
; GFX900-SDAG-NEXT: v_mul_f64 v[4:5], s[4:5], v[0:1]
; GFX900-SDAG-NEXT: s_mov_b32 s10, 0x3b39803f
@@ -4838,10 +4838,10 @@ define amdgpu_ps <8 x i32> @s_exp_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: s_mov_b32 s14, 0xfca7ab0c
; GFX900-SDAG-NEXT: s_mov_b32 s15, 0x3e928af3
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v10, s14
; GFX900-SDAG-NEXT: s_mov_b32 s12, 0x6a5dcb37
-; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; GFX900-SDAG-NEXT: s_mov_b32 s13, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v10, s14
; GFX900-SDAG-NEXT: v_mov_b32_e32 v11, s15
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[2:3], s[8:9], v[6:7]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s5
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
index 7758ac482e638..389563c72c1be 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
@@ -76,9 +76,9 @@ define amdgpu_kernel void @s_exp_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
@@ -391,8 +391,8 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-SDAG-NEXT: s_endpgm
@@ -450,8 +450,8 @@ define amdgpu_kernel void @s_exp_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -946,8 +946,8 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v5
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5
; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-SDAG-NEXT: s_endpgm
@@ -1028,9 +1028,9 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
@@ -1263,8 +1263,8 @@ define amdgpu_kernel void @s_exp_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s3
; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
@@ -1734,8 +1734,8 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v5
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v6
-; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-SDAG-NEXT: s_endpgm
@@ -1838,10 +1838,10 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s6
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
index 4df967768e19a..bf9af5b89fec5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
@@ -460,9 +460,9 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[8:9], v[2:3]
; SI-SDAG-NEXT: s_mov_b32 s17, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[10:11], v[14:15]
-; SI-SDAG-NEXT: v_mov_b32_e32 v10, s16
; SI-SDAG-NEXT: s_mov_b32 s18, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s19, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v10, s16
; SI-SDAG-NEXT: v_mov_b32_e32 v11, s17
; SI-SDAG-NEXT: v_mul_f64 v[16:17], v[14:15], s[12:13]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[8:9], s[18:19], v[10:11]
@@ -641,8 +641,8 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[6:7], v[2:3], s[4:5]
; VI-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
-; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s8, 0
; VI-SDAG-NEXT: s_mov_b32 s9, 0xc090cc00
; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
@@ -663,9 +663,9 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[4:5], v[12:13]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[4:5], v[14:15]
-; VI-SDAG-NEXT: v_mov_b32_e32 v13, s7
; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_mov_b32_e32 v13, s7
; VI-SDAG-NEXT: v_mov_b32_e32 v12, s6
; VI-SDAG-NEXT: s_mov_b32 s6, 0
; VI-SDAG-NEXT: s_mov_b32 s7, 0x40900000
@@ -823,8 +823,8 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], v[2:3], s[4:5]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0
; GFX900-SDAG-NEXT: s_mov_b32 s9, 0xc090cc00
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
@@ -845,9 +845,9 @@ define <2 x double> @v_exp10_v2f64(<2 x double> %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[4:5], v[12:13]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[4:5], v[14:15]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s7
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, s6
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x40900000
@@ -1028,12 +1028,12 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[13:14], v[7:8], s[16:17]
; SI-SDAG-NEXT: s_mov_b32 s18, 0xbbb55516
; SI-SDAG-NEXT: s_mov_b32 s19, 0x40026bb1
-; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[7:8], s[18:19], v[13:14]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v9, s5
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s20, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s21, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v9, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v8, s4
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[13:14], s[20:21], v[8:9]
; SI-SDAG-NEXT: s_mov_b32 s22, 0x623fde64
@@ -1307,8 +1307,8 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s17, 0x3fa55555
; VI-SDAG-NEXT: s_mov_b32 s18, 0x55555511
; VI-SDAG-NEXT: v_fma_f64 v[18:19], v[12:13], s[4:5], v[18:19]
-; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s19, 0x3fc55555
; VI-SDAG-NEXT: v_mul_f64 v[16:17], v[10:11], s[8:9]
; VI-SDAG-NEXT: s_mov_b32 s20, 11
@@ -1539,8 +1539,8 @@ define <3 x double> @v_exp10_v3f64(<3 x double> %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s17, 0x3fa55555
; GFX900-SDAG-NEXT: s_mov_b32 s18, 0x55555511
; GFX900-SDAG-NEXT: v_fma_f64 v[18:19], v[12:13], s[4:5], v[18:19]
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s19, 0x3fc55555
; GFX900-SDAG-NEXT: v_mul_f64 v[16:17], v[10:11], s[8:9]
; GFX900-SDAG-NEXT: s_mov_b32 s20, 11
@@ -1790,12 +1790,12 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[16:17], v[8:9], s[14:15], v[16:17]
; SI-SDAG-NEXT: s_mov_b32 s23, 0x40026bb1
; SI-SDAG-NEXT: v_mul_f64 v[18:19], v[16:17], s[20:21]
-; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
-; SI-SDAG-NEXT: v_fma_f64 v[18:19], v[16:17], s[22:23], v[18:19]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v17, s5
+; SI-SDAG-NEXT: v_fma_f64 v[18:19], v[16:17], s[22:23], v[18:19]
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s10, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s11, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v17, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v16, s4
; SI-SDAG-NEXT: v_fma_f64 v[20:21], v[18:19], s[10:11], v[16:17]
; SI-SDAG-NEXT: s_mov_b32 s12, 0x623fde64
@@ -2090,8 +2090,8 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s72, 0xbbb55516
; VI-SDAG-NEXT: v_rndne_f64_e32 v[10:11], v[8:9]
; VI-SDAG-NEXT: s_mov_b32 s73, 0x40026bb1
-; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s16, 0x6a5dcb37
; VI-SDAG-NEXT: s_mov_b32 s17, 0x3e5ade15
; VI-SDAG-NEXT: s_mov_b32 s18, 0x623fde64
@@ -2372,8 +2372,8 @@ define <4 x double> @v_exp10_v4f64(<4 x double> %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s72, 0xbbb55516
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[10:11], v[8:9]
; GFX900-SDAG-NEXT: s_mov_b32 s73, 0x40026bb1
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s16, 0x6a5dcb37
; GFX900-SDAG-NEXT: s_mov_b32 s17, 0x3e5ade15
; GFX900-SDAG-NEXT: s_mov_b32 s18, 0x623fde64
@@ -2660,8 +2660,8 @@ define amdgpu_ps <2 x i32> @s_exp10_f64(double inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s2, 0x509f79ff
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; SI-SDAG-NEXT: s_mov_b32 s3, 0xbfd34413
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; SI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[0:1], s[2:3], v[2:3]
; SI-SDAG-NEXT: s_mov_b32 s2, 0xa994fd21
@@ -2743,9 +2743,9 @@ define amdgpu_ps <2 x i32> @s_exp10_f64(double inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v3
; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
; SI-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x509f79ff
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fd34413
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
; SI-GISEL-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xa994fd21
@@ -2811,9 +2811,9 @@ define amdgpu_ps <2 x i32> @s_exp10_f64(double inreg %in) #0 {
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x979a371
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x400a934f
; VI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: s_mov_b32 s2, 0x509f79ff
; VI-SDAG-NEXT: s_mov_b32 s3, 0xbfd34413
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; VI-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
@@ -2946,9 +2946,9 @@ define amdgpu_ps <2 x i32> @s_exp10_f64(double inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x979a371
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x400a934f
; GFX900-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x509f79ff
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0xbfd34413
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
@@ -3100,8 +3100,8 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s6, 0x509f79ff
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v6, s3
; SI-SDAG-NEXT: s_mov_b32 s7, 0xbfd34413
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s3
; SI-SDAG-NEXT: v_mov_b32_e32 v5, s2
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], s[6:7], v[5:6]
; SI-SDAG-NEXT: s_mov_b32 s8, 0xa994fd21
@@ -3126,10 +3126,10 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[6:7], v[4:5]
; SI-SDAG-NEXT: s_mov_b32 s15, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[8:9], v[4:5]
-; SI-SDAG-NEXT: v_mov_b32_e32 v8, s14
-; SI-SDAG-NEXT: v_mul_f64 v[12:13], v[4:5], s[10:11]
; SI-SDAG-NEXT: s_mov_b32 s16, 0x6a5dcb37
+; SI-SDAG-NEXT: v_mul_f64 v[12:13], v[4:5], s[10:11]
; SI-SDAG-NEXT: s_mov_b32 s17, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v8, s14
; SI-SDAG-NEXT: v_mov_b32_e32 v9, s15
; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[12:13], v[12:13]
; SI-SDAG-NEXT: v_fma_f64 v[10:11], v[6:7], s[16:17], v[8:9]
@@ -3219,9 +3219,9 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s11, v5
; SI-GISEL-NEXT: s_or_b64 s[12:13], s[12:13], s[12:13]
; SI-GISEL-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x509f79ff
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3fd34413
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; SI-GISEL-NEXT: v_mov_b32_e32 v5, s5
; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xa994fd21
@@ -3329,16 +3329,16 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s5
; VI-SDAG-NEXT: v_mul_f64 v[2:3], s[2:3], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; VI-SDAG-NEXT: v_mov_b32_e32 v7, s1
; VI-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s3
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s2
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v6, s0
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
-; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[0:1], s[4:5], v[6:7]
; VI-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
@@ -3355,9 +3355,9 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[4:5], v[10:11]
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, s7
; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_mov_b32_e32 v9, s7
; VI-SDAG-NEXT: v_mov_b32_e32 v8, s6
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[4:5], s[4:5], v[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[6:7], s[4:5], v[8:9]
@@ -3524,16 +3524,16 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s5
; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], s[2:3], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, s3
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, s2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s0
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[0:1], s[4:5], v[6:7]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
@@ -3550,9 +3550,9 @@ define amdgpu_ps <4 x i32> @s_exp10_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[4:5], v[10:11]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s7
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s6
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[4:5], s[4:5], v[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[6:7], s[4:5], v[8:9]
@@ -3735,8 +3735,8 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s8, 0x509f79ff
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v6, s5
; SI-SDAG-NEXT: s_mov_b32 s9, 0xbfd34413
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v5, s4
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], s[8:9], v[5:6]
; SI-SDAG-NEXT: s_mov_b32 s10, 0xa994fd21
@@ -3747,12 +3747,12 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[7:8], v[5:6], s[12:13]
; SI-SDAG-NEXT: s_mov_b32 s14, 0xbbb55516
; SI-SDAG-NEXT: s_mov_b32 s15, 0x40026bb1
-; SI-SDAG-NEXT: s_mov_b32 s18, 0xfca7ab0c
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[5:6], s[14:15], v[7:8]
+; SI-SDAG-NEXT: s_mov_b32 s18, 0xfca7ab0c
; SI-SDAG-NEXT: s_mov_b32 s19, 0x3e928af3
-; SI-SDAG-NEXT: v_mov_b32_e32 v7, s18
; SI-SDAG-NEXT: s_mov_b32 s16, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s17, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, s18
; SI-SDAG-NEXT: v_mov_b32_e32 v8, s19
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[5:6], s[16:17], v[7:8]
; SI-SDAG-NEXT: s_mov_b32 s18, 0x623fde64
@@ -3888,9 +3888,9 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s13, v5
; SI-GISEL-NEXT: s_or_b64 s[14:15], s[14:15], s[14:15]
; SI-GISEL-NEXT: s_cselect_b64 s[10:11], s[10:11], s[12:13]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, s10
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x509f79ff
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3fd34413
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s10
; SI-GISEL-NEXT: v_mov_b32_e32 v5, s11
; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xa994fd21
@@ -4038,19 +4038,19 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[2:3], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, s3
; VI-SDAG-NEXT: s_mov_b32 s6, 0x509f79ff
; VI-SDAG-NEXT: s_mov_b32 s7, 0xbfd34413
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, s5
; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v9, s3
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
; VI-SDAG-NEXT: v_mov_b32_e32 v8, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v11, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v10, s0
-; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[2:3], s[6:7], v[6:7]
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[4:5], s[6:7], v[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[0:1], s[6:7], v[10:11]
@@ -4070,9 +4070,9 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[6:7], v[12:13]
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[6:7], v[14:15]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[6:7], v[16:17]
-; VI-SDAG-NEXT: v_mov_b32_e32 v13, s9
; VI-SDAG-NEXT: s_mov_b32 s6, 0x6a5dcb37
; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e5ade15
+; VI-SDAG-NEXT: v_mov_b32_e32 v13, s9
; VI-SDAG-NEXT: v_mov_b32_e32 v12, s8
; VI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[6:7], v[12:13]
; VI-SDAG-NEXT: v_fma_f64 v[16:17], v[8:9], s[6:7], v[12:13]
@@ -4289,19 +4289,19 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], s[4:5], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x509f79ff
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xbfd34413
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s5
; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s3
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
; GFX900-SDAG-NEXT: v_mov_b32_e32 v11, s1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v10, s0
-; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[2:3], s[6:7], v[6:7]
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[4:5], s[6:7], v[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[0:1], s[6:7], v[10:11]
@@ -4321,9 +4321,9 @@ define amdgpu_ps <6 x i32> @s_exp10_v3f64(<3 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[6:7], v[12:13]
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[6:7], v[14:15]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[6:7], v[16:17]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s9
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x6a5dcb37
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s9
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, s8
; GFX900-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[6:7], v[12:13]
; GFX900-SDAG-NEXT: v_fma_f64 v[16:17], v[8:9], s[6:7], v[12:13]
@@ -4555,8 +4555,8 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: s_mov_b32 s10, 0x509f79ff
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-SDAG-NEXT: v_mov_b32_e32 v5, s6
; SI-SDAG-NEXT: s_mov_b32 s11, 0xbfd34413
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, s6
; SI-SDAG-NEXT: v_mov_b32_e32 v6, s7
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[2:3], s[10:11], v[5:6]
; SI-SDAG-NEXT: s_mov_b32 s12, 0xa994fd21
@@ -4589,9 +4589,9 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_cndmask_b32_e32 v13, v15, v13, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc
; SI-SDAG-NEXT: v_mul_f64 v[14:15], v[10:11], s[14:15]
-; SI-SDAG-NEXT: v_mov_b32_e32 v16, s20
; SI-SDAG-NEXT: s_mov_b32 s18, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s19, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v16, s20
; SI-SDAG-NEXT: v_mov_b32_e32 v17, s21
; SI-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[16:17], v[14:15]
; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[18:19], v[16:17]
@@ -4603,33 +4603,33 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[22:23]
; SI-SDAG-NEXT: s_mov_b32 s24, 0x14761f6e
; SI-SDAG-NEXT: s_mov_b32 s25, 0x3f2a01a0
-; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[24:25]
; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v19, v[2:3]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], s[18:19], v[16:17]
+; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[24:25]
; SI-SDAG-NEXT: s_mov_b32 s26, 0x1852b7b0
; SI-SDAG-NEXT: s_mov_b32 s27, 0x3f56c16c
-; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[26:27]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[20:21]
+; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[26:27]
; SI-SDAG-NEXT: s_mov_b32 s28, 0x11122322
; SI-SDAG-NEXT: s_mov_b32 s29, 0x3f811111
-; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[28:29]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[22:23]
+; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[28:29]
; SI-SDAG-NEXT: s_mov_b32 s30, 0x555502a1
; SI-SDAG-NEXT: s_mov_b32 s31, 0x3fa55555
-; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[30:31]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[24:25]
+; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[30:31]
; SI-SDAG-NEXT: s_mov_b32 s34, 0x55555511
; SI-SDAG-NEXT: s_mov_b32 s35, 0x3fc55555
-; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[34:35]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[26:27]
+; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[34:35]
; SI-SDAG-NEXT: s_mov_b32 s36, 11
; SI-SDAG-NEXT: s_mov_b32 s37, 0x3fe00000
-; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[36:37]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[28:29]
-; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], 1.0
+; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], s[36:37]
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[30:31]
-; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[6:7], v[14:15], 1.0
+; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], v[14:15], 1.0
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[34:35]
+; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[6:7], v[14:15], 1.0
; SI-SDAG-NEXT: v_mov_b32_e32 v15, s3
; SI-SDAG-NEXT: v_mov_b32_e32 v14, s2
; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[10:11], v[2:3], s[36:37]
@@ -4742,9 +4742,9 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; SI-GISEL-NEXT: v_readfirstlane_b32 s15, v5
; SI-GISEL-NEXT: s_or_b64 s[16:17], s[16:17], s[16:17]
; SI-GISEL-NEXT: s_cselect_b64 s[12:13], s[12:13], s[14:15]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, s12
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x509f79ff
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3fd34413
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, s12
; SI-GISEL-NEXT: v_mov_b32_e32 v5, s13
; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], s[0:1]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xa994fd21
@@ -4932,21 +4932,21 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[4:5], s[4:5], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[6:7], s[2:3], v[0:1]
; VI-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, s7
; VI-SDAG-NEXT: s_mov_b32 s8, 0x509f79ff
; VI-SDAG-NEXT: s_mov_b32 s9, 0xbfd34413
+; VI-SDAG-NEXT: v_mov_b32_e32 v9, s7
; VI-SDAG-NEXT: v_mov_b32_e32 v8, s6
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; VI-SDAG-NEXT: v_mov_b32_e32 v11, s5
-; VI-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; VI-SDAG-NEXT: v_mov_b32_e32 v10, s4
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; VI-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v13, s3
; VI-SDAG-NEXT: s_mov_b32 s10, 0xa994fd21
+; VI-SDAG-NEXT: s_mov_b32 s11, 0x3c49dc1d
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[2:3], s[8:9], v[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[4:5], s[8:9], v[10:11]
-; VI-SDAG-NEXT: s_mov_b32 s11, 0x3c49dc1d
+; VI-SDAG-NEXT: v_mov_b32_e32 v13, s3
; VI-SDAG-NEXT: v_mov_b32_e32 v12, s2
; VI-SDAG-NEXT: v_fma_f64 v[12:13], v[6:7], s[8:9], v[12:13]
; VI-SDAG-NEXT: v_mov_b32_e32 v15, s1
@@ -4972,8 +4972,8 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[16:17], v[12:13], s[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[10:11], v[18:19]
; VI-SDAG-NEXT: v_mul_f64 v[18:19], v[14:15], s[8:9]
-; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s18, 0x11122322
; VI-SDAG-NEXT: s_mov_b32 s19, 0x3f811111
; VI-SDAG-NEXT: s_mov_b32 s20, 0x555502a1
@@ -5239,21 +5239,21 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[4:5], s[4:5], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], s[2:3], v[0:1]
; GFX900-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s7
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x509f79ff
; GFX900-SDAG-NEXT: s_mov_b32 s9, 0xbfd34413
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s6
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], v[4:5]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v11, s5
-; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v10, s4
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s3
; GFX900-SDAG-NEXT: s_mov_b32 s10, 0xa994fd21
+; GFX900-SDAG-NEXT: s_mov_b32 s11, 0x3c49dc1d
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[2:3], s[8:9], v[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[4:5], s[8:9], v[10:11]
-; GFX900-SDAG-NEXT: s_mov_b32 s11, 0x3c49dc1d
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s3
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, s2
; GFX900-SDAG-NEXT: v_fma_f64 v[12:13], v[6:7], s[8:9], v[12:13]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v15, s1
@@ -5279,8 +5279,8 @@ define amdgpu_ps <8 x i32> @s_exp10_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[16:17], v[12:13], s[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[10:11], v[18:19]
; GFX900-SDAG-NEXT: v_mul_f64 v[18:19], v[14:15], s[8:9]
-; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s18, 0x11122322
; GFX900-SDAG-NEXT: s_mov_b32 s19, 0x3f811111
; GFX900-SDAG-NEXT: s_mov_b32 s20, 0x555502a1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
index 30fdbeaa448ca..560584f78f88c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
@@ -78,9 +78,9 @@ define amdgpu_kernel void @s_exp10_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: s_cselect_b32 s3, 0, s3
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
@@ -393,8 +393,8 @@ define amdgpu_kernel void @s_exp10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-SDAG-NEXT: s_endpgm
@@ -452,8 +452,8 @@ define amdgpu_kernel void @s_exp10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -948,8 +948,8 @@ define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v5
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5
; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-SDAG-NEXT: s_endpgm
@@ -1030,9 +1030,9 @@ define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s3
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
@@ -1265,8 +1265,8 @@ define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v2
; SI-GISEL-NEXT: s_cselect_b32 s6, 0, s3
; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; SI-GISEL-NEXT: s_cselect_b32 s2, 0x7f800000, s6
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; SI-GISEL-NEXT: s_mov_b32 s6, -1
; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
@@ -1736,8 +1736,8 @@ define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v5
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v6
-; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-SDAG-NEXT: s_endpgm
@@ -1840,10 +1840,10 @@ define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7f800000, s6
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
index 7441f4645d2e6..be27531d8e53c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
@@ -398,13 +398,13 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
; SI-SDAG-NEXT: s_mov_b32 s8, 0xfefa39ef
; SI-SDAG-NEXT: s_mov_b32 s9, 0x3fe62e42
-; SI-SDAG-NEXT: s_mov_b32 s10, 0xfca7ab0c
; SI-SDAG-NEXT: v_add_f64 v[14:15], v[2:3], -v[4:5]
; SI-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[8:9], v[10:11]
+; SI-SDAG-NEXT: s_mov_b32 s10, 0xfca7ab0c
; SI-SDAG-NEXT: s_mov_b32 s11, 0x3e928af3
-; SI-SDAG-NEXT: v_mov_b32_e32 v10, s10
; SI-SDAG-NEXT: s_mov_b32 s12, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s13, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v10, s10
; SI-SDAG-NEXT: v_mov_b32_e32 v11, s11
; SI-SDAG-NEXT: v_mul_f64 v[16:17], v[14:15], s[6:7]
; SI-SDAG-NEXT: v_fma_f64 v[12:13], v[8:9], s[12:13], v[10:11]
@@ -571,8 +571,8 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; VI-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[2:3]
; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s8, 0
; VI-SDAG-NEXT: s_mov_b32 s9, 0xc090cc00
; VI-SDAG-NEXT: v_add_f64 v[8:9], v[0:1], -v[4:5]
@@ -585,9 +585,9 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[4:5], v[12:13]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[4:5], v[14:15]
-; VI-SDAG-NEXT: v_mov_b32_e32 v13, s7
; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_mov_b32_e32 v13, s7
; VI-SDAG-NEXT: v_mov_b32_e32 v12, s6
; VI-SDAG-NEXT: s_mov_b32 s6, 0
; VI-SDAG-NEXT: s_mov_b32 s7, 0x40900000
@@ -733,8 +733,8 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[6:7], v[2:3]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0
; GFX900-SDAG-NEXT: s_mov_b32 s9, 0xc090cc00
; GFX900-SDAG-NEXT: v_add_f64 v[8:9], v[0:1], -v[4:5]
@@ -747,9 +747,9 @@ define <2 x double> @v_exp2_v2f64(<2 x double> %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[4:5], v[12:13]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[4:5], v[14:15]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s7
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, s6
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x40900000
@@ -912,12 +912,12 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[13:14], v[7:8], s[10:11]
; SI-SDAG-NEXT: s_mov_b32 s12, 0xfefa39ef
; SI-SDAG-NEXT: s_mov_b32 s13, 0x3fe62e42
-; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[13:14], v[7:8], s[12:13], v[13:14]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v9, s5
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s14, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s15, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v9, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v8, s4
; SI-SDAG-NEXT: v_fma_f64 v[15:16], v[13:14], s[14:15], v[8:9]
; SI-SDAG-NEXT: s_mov_b32 s16, 0x623fde64
@@ -1173,8 +1173,8 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; VI-SDAG-NEXT: v_fma_f64 v[12:13], v[12:13], s[6:7], v[18:19]
; VI-SDAG-NEXT: s_mov_b32 s21, 0x3fe00000
; VI-SDAG-NEXT: v_mul_f64 v[18:19], v[14:15], s[4:5]
-; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: v_fma_f64 v[14:15], v[14:15], s[6:7], v[18:19]
; VI-SDAG-NEXT: v_mov_b32_e32 v19, s5
; VI-SDAG-NEXT: v_mov_b32_e32 v18, s4
@@ -1381,8 +1381,8 @@ define <3 x double> @v_exp2_v3f64(<3 x double> %in) #0 {
; GFX900-SDAG-NEXT: v_fma_f64 v[12:13], v[12:13], s[6:7], v[18:19]
; GFX900-SDAG-NEXT: s_mov_b32 s21, 0x3fe00000
; GFX900-SDAG-NEXT: v_mul_f64 v[18:19], v[14:15], s[4:5]
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: v_fma_f64 v[14:15], v[14:15], s[6:7], v[18:19]
; GFX900-SDAG-NEXT: v_mov_b32_e32 v19, s5
; GFX900-SDAG-NEXT: v_mov_b32_e32 v18, s4
@@ -1581,12 +1581,12 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[13:14], v[11:12], s[18:19]
; SI-SDAG-NEXT: s_mov_b32 s20, 0xfefa39ef
; SI-SDAG-NEXT: s_mov_b32 s21, 0x3fe62e42
-; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[14:15], v[11:12], s[20:21], v[13:14]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v13, s5
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s22, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s23, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v13, s5
; SI-SDAG-NEXT: v_mov_b32_e32 v12, s4
; SI-SDAG-NEXT: v_fma_f64 v[18:19], v[14:15], s[22:23], v[12:13]
; SI-SDAG-NEXT: s_mov_b32 s24, 0x623fde64
@@ -1875,8 +1875,8 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s57, 0x3c7abc9e
; VI-SDAG-NEXT: s_mov_b32 s58, 0xfefa39ef
; VI-SDAG-NEXT: s_mov_b32 s59, 0x3fe62e42
-; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s16, 0x6a5dcb37
; VI-SDAG-NEXT: v_add_f64 v[8:9], v[0:1], -v[10:11]
; VI-SDAG-NEXT: s_mov_b32 s17, 0x3e5ade15
@@ -2129,8 +2129,8 @@ define <4 x double> @v_exp2_v4f64(<4 x double> %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s57, 0x3c7abc9e
; GFX900-SDAG-NEXT: s_mov_b32 s58, 0xfefa39ef
; GFX900-SDAG-NEXT: s_mov_b32 s59, 0x3fe62e42
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s16, 0x6a5dcb37
; GFX900-SDAG-NEXT: v_add_f64 v[8:9], v[0:1], -v[10:11]
; GFX900-SDAG-NEXT: s_mov_b32 s17, 0x3e5ade15
@@ -2775,8 +2775,8 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0
; SI-SDAG-NEXT: v_add_f64 v[2:3], s[2:3], v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s4, -1
-; SI-SDAG-NEXT: v_add_f64 v[1:2], v[2:3], -v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s5, 0x432fffff
+; SI-SDAG-NEXT: v_add_f64 v[1:2], v[2:3], -v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; SI-SDAG-NEXT: v_mov_b32_e32 v4, s5
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[3:4]
@@ -2789,12 +2789,12 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[7:8], v[1:2], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s6, 0xfefa39ef
; SI-SDAG-NEXT: s_mov_b32 s7, 0x3fe62e42
-; SI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[1:2], s[6:7], v[7:8]
; SI-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v10, s9
+; SI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s10, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s11, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v10, s9
; SI-SDAG-NEXT: v_mov_b32_e32 v9, s8
; SI-SDAG-NEXT: v_fma_f64 v[1:2], v[7:8], s[10:11], v[9:10]
; SI-SDAG-NEXT: s_mov_b32 s8, 0x623fde64
@@ -2992,8 +2992,8 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], s[0:1]
; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; VI-SDAG-NEXT: v_add_f64 v[4:5], s[2:3], -v[0:1]
; VI-SDAG-NEXT: v_add_f64 v[6:7], s[0:1], -v[2:3]
; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
@@ -3004,9 +3004,9 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[4:5], v[10:11]
-; VI-SDAG-NEXT: v_mov_b32_e32 v9, s7
; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_mov_b32_e32 v9, s7
; VI-SDAG-NEXT: v_mov_b32_e32 v8, s6
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[4:5], s[4:5], v[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[6:7], s[4:5], v[8:9]
@@ -3161,8 +3161,8 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], s[0:1]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; GFX900-SDAG-NEXT: v_add_f64 v[4:5], s[2:3], -v[0:1]
; GFX900-SDAG-NEXT: v_add_f64 v[6:7], s[0:1], -v[2:3]
; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
@@ -3173,9 +3173,9 @@ define amdgpu_ps <4 x i32> @s_exp2_v2f64(<2 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[4:5], v[10:11]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s7
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, s7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s6
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[4:5], s[4:5], v[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[6:7], s[4:5], v[8:9]
@@ -3338,8 +3338,8 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0
; SI-SDAG-NEXT: v_add_f64 v[2:3], s[4:5], v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s6, -1
-; SI-SDAG-NEXT: v_add_f64 v[1:2], v[2:3], -v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-SDAG-NEXT: v_add_f64 v[1:2], v[2:3], -v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v3, s6
; SI-SDAG-NEXT: v_mov_b32_e32 v4, s7
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, v[3:4]
@@ -3352,12 +3352,12 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[7:8], v[5:6], s[8:9]
; SI-SDAG-NEXT: s_mov_b32 s10, 0xfefa39ef
; SI-SDAG-NEXT: s_mov_b32 s11, 0x3fe62e42
-; SI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[5:6], s[10:11], v[7:8]
; SI-SDAG-NEXT: s_mov_b32 s6, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v8, s7
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s12, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s13, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v8, s7
; SI-SDAG-NEXT: v_mov_b32_e32 v7, s6
; SI-SDAG-NEXT: v_fma_f64 v[9:10], v[5:6], s[12:13], v[7:8]
; SI-SDAG-NEXT: s_mov_b32 s14, 0x623fde64
@@ -3625,8 +3625,8 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_rndne_f64_e32 v[4:5], s[0:1]
; VI-SDAG-NEXT: s_mov_b32 s6, 0x3b39803f
; VI-SDAG-NEXT: s_mov_b32 s7, 0x3c7abc9e
-; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: v_add_f64 v[6:7], s[4:5], -v[0:1]
; VI-SDAG-NEXT: v_add_f64 v[8:9], s[2:3], -v[2:3]
; VI-SDAG-NEXT: v_add_f64 v[10:11], s[0:1], -v[4:5]
@@ -3638,9 +3638,9 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[6:7], v[12:13]
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[6:7], v[14:15]
; VI-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[6:7], v[16:17]
-; VI-SDAG-NEXT: v_mov_b32_e32 v13, s9
; VI-SDAG-NEXT: s_mov_b32 s6, 0x6a5dcb37
; VI-SDAG-NEXT: s_mov_b32 s7, 0x3e5ade15
+; VI-SDAG-NEXT: v_mov_b32_e32 v13, s9
; VI-SDAG-NEXT: v_mov_b32_e32 v12, s8
; VI-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[6:7], v[12:13]
; VI-SDAG-NEXT: v_fma_f64 v[16:17], v[8:9], s[6:7], v[12:13]
@@ -3844,8 +3844,8 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[4:5], s[0:1]
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x3b39803f
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3c7abc9e
-; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: v_add_f64 v[6:7], s[4:5], -v[0:1]
; GFX900-SDAG-NEXT: v_add_f64 v[8:9], s[2:3], -v[2:3]
; GFX900-SDAG-NEXT: v_add_f64 v[10:11], s[0:1], -v[4:5]
@@ -3857,9 +3857,9 @@ define amdgpu_ps <6 x i32> @s_exp2_v3f64(<3 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[6:7], s[6:7], v[12:13]
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[6:7], v[14:15]
; GFX900-SDAG-NEXT: v_fma_f64 v[10:11], v[10:11], s[6:7], v[16:17]
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s9
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x6a5dcb37
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v13, s9
; GFX900-SDAG-NEXT: v_mov_b32_e32 v12, s8
; GFX900-SDAG-NEXT: v_fma_f64 v[14:15], v[6:7], s[6:7], v[12:13]
; GFX900-SDAG-NEXT: v_fma_f64 v[16:17], v[8:9], s[6:7], v[12:13]
@@ -4070,8 +4070,8 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0
; SI-SDAG-NEXT: v_add_f64 v[2:3], s[6:7], v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s8, -1
-; SI-SDAG-NEXT: v_add_f64 v[1:2], v[2:3], -v[0:1]
; SI-SDAG-NEXT: s_mov_b32 s9, 0x432fffff
+; SI-SDAG-NEXT: v_add_f64 v[1:2], v[2:3], -v[0:1]
; SI-SDAG-NEXT: v_mov_b32_e32 v3, s8
; SI-SDAG-NEXT: v_mov_b32_e32 v4, s9
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, v[3:4]
@@ -4084,12 +4084,12 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; SI-SDAG-NEXT: v_mul_f64 v[7:8], v[1:2], s[10:11]
; SI-SDAG-NEXT: s_mov_b32 s12, 0xfefa39ef
; SI-SDAG-NEXT: s_mov_b32 s13, 0x3fe62e42
-; SI-SDAG-NEXT: s_mov_b32 s14, 0xfca7ab0c
; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[1:2], s[12:13], v[7:8]
+; SI-SDAG-NEXT: s_mov_b32 s14, 0xfca7ab0c
; SI-SDAG-NEXT: s_mov_b32 s15, 0x3e928af3
-; SI-SDAG-NEXT: v_mov_b32_e32 v9, s14
; SI-SDAG-NEXT: s_mov_b32 s8, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s9, 0x3e5ade15
+; SI-SDAG-NEXT: v_mov_b32_e32 v9, s14
; SI-SDAG-NEXT: v_mov_b32_e32 v10, s15
; SI-SDAG-NEXT: v_fma_f64 v[1:2], v[7:8], s[8:9], v[9:10]
; SI-SDAG-NEXT: s_mov_b32 s14, 0x623fde64
@@ -4449,8 +4449,8 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; VI-SDAG-NEXT: v_mul_f64 v[12:13], v[14:15], s[8:9]
; VI-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[10:11], v[16:17]
; VI-SDAG-NEXT: v_mul_f64 v[16:17], v[18:19], s[8:9]
-; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; VI-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s22, 0x55555511
; VI-SDAG-NEXT: s_mov_b32 s23, 0x3fc55555
; VI-SDAG-NEXT: s_mov_b32 s24, 11
@@ -4718,8 +4718,8 @@ define amdgpu_ps <8 x i32> @s_exp2_v4f64(<4 x double> inreg %in) #0 {
; GFX900-SDAG-NEXT: v_mul_f64 v[12:13], v[14:15], s[8:9]
; GFX900-SDAG-NEXT: v_fma_f64 v[8:9], v[8:9], s[10:11], v[16:17]
; GFX900-SDAG-NEXT: v_mul_f64 v[16:17], v[18:19], s[8:9]
-; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s8, 0xfca7ab0c
+; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s22, 0x55555511
; GFX900-SDAG-NEXT: s_mov_b32 s23, 0x3fc55555
; GFX900-SDAG-NEXT: s_mov_b32 s24, 11
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
index 7911c5383d0c1..c16d32187978c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
@@ -62,9 +62,9 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; VI-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
; VI-SDAG-NEXT: v_ldexp_f32 v2, v0, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
; VI-SDAG-NEXT: s_endpgm
;
@@ -81,9 +81,9 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_ldexp_f32 v2, v0, s2
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -243,8 +243,8 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-SDAG-NEXT: v_ldexp_f32 v1, v2, s3
; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; VI-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, s2
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-SDAG-NEXT: s_endpgm
@@ -476,18 +476,18 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-SDAG-NEXT: v_add_f32_e32 v3, s1, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-SDAG-NEXT: v_exp_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, s1, v3
; VI-SDAG-NEXT: v_add_f32_e32 v0, s0, v0
+; VI-SDAG-NEXT: v_exp_f32_e32 v3, v3
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-SDAG-NEXT: v_ldexp_f32 v1, v3, s4
; VI-SDAG-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v3, s4
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, s0
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s3
-; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, s0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s2
; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-SDAG-NEXT: s_endpgm
@@ -788,17 +788,17 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-SDAG-NEXT: v_add_f32_e32 v4, s1, v4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v4, s1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v0, s0, v0
+; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-SDAG-NEXT: v_ldexp_f32 v1, v4, s2
; VI-SDAG-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v4, s2
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-SDAG-NEXT: s_endpgm
@@ -829,19 +829,19 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: s_cselect_b32 s4, 0x42800000, 0
; VI-GISEL-NEXT: v_add_f32_e32 v2, s9, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2
; VI-GISEL-NEXT: v_add_f32_e32 v3, s10, v3
; VI-GISEL-NEXT: v_add_f32_e32 v1, s11, v1
-; VI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_exp_f32_e32 v3, v3
; VI-GISEL-NEXT: v_exp_f32_e32 v4, v1
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_ldexp_f32 v1, v2, s0
; VI-GISEL-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, s5
; VI-GISEL-NEXT: v_ldexp_f32 v2, v3, s1
; VI-GISEL-NEXT: v_ldexp_f32 v3, v4, s0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, s5
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index 62f3c06e5b523..7a5ff1833f80f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -67,8 +67,8 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[2:3], s2, 3
; GFX8GLISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GLISEL-NEXT: s_cselect_b32 s2, -1, 0
-; GFX8GLISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GLISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GLISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GLISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GLISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GLISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
index 70108a090ee29..b8925662f0321 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
@@ -64,8 +64,8 @@ define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) {
; GFX8GLISEL-NEXT: v_cmp_class_f32_e64 s[2:3], s2, 3
; GFX8GLISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GLISEL-NEXT: s_cselect_b32 s2, -1, 0
-; GFX8GLISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GLISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8GLISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GLISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX8GLISEL-NEXT: flat_store_dword v[0:1], v2
; GFX8GLISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 9357b373c3d13..dbfd6fa6350db 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -889,8 +889,8 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -1486,9 +1486,9 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
@@ -2281,9 +2281,9 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 97d706c38020f..22f7fa7ce5745 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -889,8 +889,8 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-GISEL-NEXT: s_endpgm
@@ -1486,9 +1486,9 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1
-; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0
; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-GISEL-NEXT: s_endpgm
@@ -2281,9 +2281,9 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1
-; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index 7ef457c70b789..41106ec77ddc9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -92,9 +92,9 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
; VI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -304,12 +304,12 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
-; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_log_f32_e32 v4, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v1, v3, v2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-SDAG-NEXT: s_endpgm
@@ -626,14 +626,14 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_log_f32_e32 v5, v5
-; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v6, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
; VI-SDAG-NEXT: v_sub_f32_e32 v1, v5, v4
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v6, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5
; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-SDAG-NEXT: s_endpgm
@@ -1051,16 +1051,16 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_log_f32_e32 v5, v5
-; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v7, v7
; VI-SDAG-NEXT: v_log_f32_e32 v8, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v5, v4
-; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
; VI-SDAG-NEXT: v_sub_f32_e32 v1, v7, v6
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v8, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-SDAG-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
index 76b97e843d777..37250ca94f42a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
@@ -19,8 +19,8 @@ define amdgpu_kernel void @round_f64(ptr addrspace(1) %out, double %x) #0 {
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s8, s5
; SI-NEXT: s_cmp_gt_i32 s7, 51
-; SI-NEXT: s_cselect_b32 s8, s2, s4
; SI-NEXT: s_cselect_b32 s9, s3, s5
+; SI-NEXT: s_cselect_b32 s8, s2, s4
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_add_f64 v[0:1], s[2:3], -v[0:1]
@@ -150,8 +150,8 @@ define amdgpu_kernel void @round_v2f64(ptr addrspace(1) %out, <2 x double> %in)
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s12, 51
-; SI-NEXT: s_cselect_b32 s12, s10, s0
; SI-NEXT: s_cselect_b32 s13, s11, s1
+; SI-NEXT: s_cselect_b32 s12, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_mov_b32_e32 v1, s13
; SI-NEXT: v_add_f64 v[0:1], s[10:11], -v[0:1]
@@ -170,8 +170,8 @@ define amdgpu_kernel void @round_v2f64(ptr addrspace(1) %out, <2 x double> %in)
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s6, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: s_cselect_b32 s5, s9, s5
+; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_add_f64 v[2:3], s[8:9], -v[2:3]
@@ -243,8 +243,8 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s16, 51
-; SI-NEXT: s_cselect_b32 s16, s10, s0
; SI-NEXT: s_cselect_b32 s17, s11, s1
+; SI-NEXT: s_cselect_b32 s16, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_add_f64 v[0:1], s[10:11], -v[0:1]
@@ -264,9 +264,9 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_brev_b32 s18, -2
+; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_bfi_b32 v5, s18, v0, v1
-; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_add_f64 v[0:1], s[8:9], -v[0:1]
@@ -285,8 +285,8 @@ define amdgpu_kernel void @round_v4f64(ptr addrspace(1) %out, <4 x double> %in)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: s_cselect_b32 s9, s15, s9
+; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_add_f64 v[0:1], s[14:15], -v[0:1]
@@ -397,8 +397,8 @@ define amdgpu_kernel void @round_v8f64(ptr addrspace(1) %out, <8 x double> %in)
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s24, 51
-; SI-NEXT: s_cselect_b32 s24, s10, s0
; SI-NEXT: s_cselect_b32 s25, s11, s1
+; SI-NEXT: s_cselect_b32 s24, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s24
; SI-NEXT: v_mov_b32_e32 v1, s25
; SI-NEXT: v_add_f64 v[0:1], s[10:11], -v[0:1]
@@ -418,9 +418,9 @@ define amdgpu_kernel void @round_v8f64(ptr addrspace(1) %out, <8 x double> %in)
; SI-NEXT: s_cselect_b32 s5, s11, s5
; SI-NEXT: s_cmp_gt_i32 s10, 51
; SI-NEXT: s_brev_b32 s3, -2
+; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_bfi_b32 v9, s3, v0, v1
-; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_add_f64 v[0:1], s[8:9], -v[0:1]
@@ -439,8 +439,8 @@ define amdgpu_kernel void @round_v8f64(ptr addrspace(1) %out, <8 x double> %in)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s11, s9
; SI-NEXT: s_cmp_gt_i32 s10, 51
-; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: s_cselect_b32 s9, s15, s9
+; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_add_f64 v[0:1], s[14:15], -v[0:1]
@@ -459,8 +459,8 @@ define amdgpu_kernel void @round_v8f64(ptr addrspace(1) %out, <8 x double> %in)
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s11, s5
; SI-NEXT: s_cmp_gt_i32 s10, 51
-; SI-NEXT: s_cselect_b32 s4, s12, s4
; SI-NEXT: s_cselect_b32 s5, s13, s5
+; SI-NEXT: s_cselect_b32 s4, s12, s4
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_mov_b32_e32 v5, s5
; SI-NEXT: v_add_f64 v[4:5], s[12:13], -v[4:5]
@@ -480,8 +480,8 @@ define amdgpu_kernel void @round_v8f64(ptr addrspace(1) %out, <8 x double> %in)
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s11, s9
; SI-NEXT: s_cmp_gt_i32 s10, 51
-; SI-NEXT: s_cselect_b32 s8, s18, s8
; SI-NEXT: s_cselect_b32 s9, s19, s9
+; SI-NEXT: s_cselect_b32 s8, s18, s8
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_mov_b32_e32 v5, s9
; SI-NEXT: v_add_f64 v[4:5], s[18:19], -v[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll b/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
index 90a0e43fb27d0..b83bbc02f1525 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
@@ -53,9 +53,9 @@ define amdgpu_kernel void @constant_load_f64(ptr addrspace(1) %out, ptr addrspac
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
%ld = load double, ptr addrspace(4) %in
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 589ea74948d2a..d4363157e1238 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -672,9 +672,9 @@ define amdgpu_kernel void @constant_load_v64i1(ptr addrspace(1) %out, ptr addrsp
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
;
@@ -1654,13 +1654,13 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX8-NEXT: s_bfe_u32 s7, s2, 0x10002
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x10004
; GFX8-NEXT: s_add_u32 s0, s0, 16
-; GFX8-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: v_mov_b32_e32 v11, s1
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 7, v0
; GFX8-NEXT: v_bfe_u32 v2, v0, 6, 1
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v11, s1
; GFX8-NEXT: v_mov_b32_e32 v10, s0
; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v5, s4
@@ -1822,8 +1822,8 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX8-NEXT: s_add_u32 s2, s0, 16
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v11, s3
-; GFX8-NEXT: v_mov_b32_e32 v9, s1
; GFX8-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NEXT: v_mov_b32_e32 v9, s1
; GFX8-NEXT: v_mov_b32_e32 v8, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_bfe_i32 v3, v4, 3, 1
@@ -2001,27 +2001,27 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v15, s3
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v19, s3
-; GFX8-NEXT: v_mov_b32_e32 v1, s8
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s13
; GFX8-NEXT: v_mov_b32_e32 v18, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32
-; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s8
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s13
+; GFX8-NEXT: s_add_u32 s0, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: v_mov_b32_e32 v6, s10
; GFX8-NEXT: v_mov_b32_e32 v4, s17
; GFX8-NEXT: v_mov_b32_e32 v7, s12
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: s_add_u32 s0, s0, 16
-; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_mov_b32_e32 v11, s5
; GFX8-NEXT: v_mov_b32_e32 v8, s16
; GFX8-NEXT: v_mov_b32_e32 v9, s11
; GFX8-NEXT: v_mov_b32_e32 v10, s15
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v12, s9
; GFX8-NEXT: v_mov_b32_e32 v13, s4
@@ -2214,13 +2214,13 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v9, s3
; GFX8-NEXT: v_mov_b32_e32 v8, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32
-; GFX8-NEXT: v_mov_b32_e32 v13, s1
; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v13, s1
; GFX8-NEXT: v_mov_b32_e32 v12, s0
; GFX8-NEXT: s_add_u32 s0, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v15, s3
-; GFX8-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v17, s1
; GFX8-NEXT: v_mov_b32_e32 v16, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -3514,93 +3514,93 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v0, s27
; GFX8-NEXT: s_addc_u32 s27, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s26
-; GFX8-NEXT: v_mov_b32_e32 v1, s44
-; GFX8-NEXT: v_mov_b32_e32 v3, s43
; GFX8-NEXT: v_mov_b32_e32 v5, s27
; GFX8-NEXT: s_add_u32 s26, s0, 0xe0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v1, s44
+; GFX8-NEXT: v_mov_b32_e32 v3, s43
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xd0
; GFX8-NEXT: v_mov_b32_e32 v0, s66
; GFX8-NEXT: v_mov_b32_e32 v1, s42
; GFX8-NEXT: v_mov_b32_e32 v2, s65
; GFX8-NEXT: v_mov_b32_e32 v3, s41
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xd0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xc0
; GFX8-NEXT: v_mov_b32_e32 v0, s64
; GFX8-NEXT: v_mov_b32_e32 v1, s63
; GFX8-NEXT: v_mov_b32_e32 v2, s62
; GFX8-NEXT: v_mov_b32_e32 v3, s40
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xc0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xb0
; GFX8-NEXT: v_mov_b32_e32 v0, s61
; GFX8-NEXT: v_mov_b32_e32 v1, s39
; GFX8-NEXT: v_mov_b32_e32 v2, s60
; GFX8-NEXT: v_mov_b32_e32 v3, s38
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xb0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xa0
; GFX8-NEXT: v_mov_b32_e32 v0, s59
; GFX8-NEXT: v_mov_b32_e32 v1, s37
; GFX8-NEXT: v_mov_b32_e32 v2, s58
; GFX8-NEXT: v_mov_b32_e32 v3, s36
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xa0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x90
; GFX8-NEXT: v_mov_b32_e32 v0, s57
; GFX8-NEXT: v_mov_b32_e32 v1, s35
; GFX8-NEXT: v_mov_b32_e32 v2, s56
; GFX8-NEXT: v_mov_b32_e32 v3, s34
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x90
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x80
; GFX8-NEXT: v_mov_b32_e32 v0, s55
; GFX8-NEXT: v_mov_b32_e32 v1, s33
; GFX8-NEXT: v_mov_b32_e32 v2, s54
; GFX8-NEXT: v_mov_b32_e32 v3, s31
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x80
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x70
; GFX8-NEXT: v_mov_b32_e32 v0, s52
; GFX8-NEXT: v_mov_b32_e32 v1, s30
; GFX8-NEXT: v_mov_b32_e32 v2, s53
; GFX8-NEXT: v_mov_b32_e32 v3, s29
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x70
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x60
; GFX8-NEXT: v_mov_b32_e32 v0, s51
; GFX8-NEXT: v_mov_b32_e32 v1, s28
; GFX8-NEXT: v_mov_b32_e32 v2, s50
; GFX8-NEXT: v_mov_b32_e32 v3, s25
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x60
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x50
; GFX8-NEXT: v_mov_b32_e32 v0, s49
; GFX8-NEXT: v_mov_b32_e32 v1, s23
; GFX8-NEXT: v_mov_b32_e32 v2, s48
; GFX8-NEXT: v_mov_b32_e32 v3, s21
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x50
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NEXT: v_mov_b32_e32 v0, s47
; GFX8-NEXT: v_mov_b32_e32 v1, s46
@@ -3612,30 +3612,30 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NEXT: s_add_u32 s22, s0, 64
; GFX8-NEXT: s_addc_u32 s23, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: v_mov_b32_e32 v5, s23
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NEXT: s_add_u32 s18, s0, 48
; GFX8-NEXT: s_addc_u32 s19, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v0, s20
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: v_mov_b32_e32 v3, s11
+; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v5, s19
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NEXT: s_add_u32 s14, s0, 32
; GFX8-NEXT: s_addc_u32 s15, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: v_mov_b32_e32 v3, s6
+; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: v_mov_b32_e32 v5, s15
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -3643,9 +3643,9 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s4, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s5, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v2, s10
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
@@ -4319,84 +4319,84 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v0, s27
; GFX8-NEXT: s_addc_u32 s27, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s26
-; GFX8-NEXT: v_mov_b32_e32 v1, s66
-; GFX8-NEXT: v_mov_b32_e32 v2, s65
; GFX8-NEXT: v_mov_b32_e32 v5, s27
; GFX8-NEXT: s_add_u32 s26, s0, 0xe0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v1, s66
+; GFX8-NEXT: v_mov_b32_e32 v2, s65
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xd0
; GFX8-NEXT: v_mov_b32_e32 v0, s64
; GFX8-NEXT: v_mov_b32_e32 v1, s63
; GFX8-NEXT: v_mov_b32_e32 v2, s62
; GFX8-NEXT: v_mov_b32_e32 v3, s61
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xd0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xc0
; GFX8-NEXT: v_mov_b32_e32 v0, s60
; GFX8-NEXT: v_mov_b32_e32 v1, s59
; GFX8-NEXT: v_mov_b32_e32 v2, s58
; GFX8-NEXT: v_mov_b32_e32 v3, s57
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xc0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xb0
; GFX8-NEXT: v_mov_b32_e32 v0, s56
; GFX8-NEXT: v_mov_b32_e32 v1, s55
; GFX8-NEXT: v_mov_b32_e32 v2, s54
; GFX8-NEXT: v_mov_b32_e32 v3, s53
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xb0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0xa0
; GFX8-NEXT: v_mov_b32_e32 v0, s52
; GFX8-NEXT: v_mov_b32_e32 v1, s51
; GFX8-NEXT: v_mov_b32_e32 v2, s50
; GFX8-NEXT: v_mov_b32_e32 v3, s49
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0xa0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x90
; GFX8-NEXT: v_mov_b32_e32 v0, s48
; GFX8-NEXT: v_mov_b32_e32 v1, s47
; GFX8-NEXT: v_mov_b32_e32 v2, s46
; GFX8-NEXT: v_mov_b32_e32 v3, s45
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x90
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x80
; GFX8-NEXT: v_mov_b32_e32 v0, s44
; GFX8-NEXT: v_mov_b32_e32 v1, s43
; GFX8-NEXT: v_mov_b32_e32 v2, s42
; GFX8-NEXT: v_mov_b32_e32 v3, s41
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x80
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x70
; GFX8-NEXT: v_mov_b32_e32 v0, s40
; GFX8-NEXT: v_mov_b32_e32 v1, s39
; GFX8-NEXT: v_mov_b32_e32 v2, s38
; GFX8-NEXT: v_mov_b32_e32 v3, s37
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x70
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NEXT: s_add_u32 s26, s0, 0x60
; GFX8-NEXT: v_mov_b32_e32 v0, s36
; GFX8-NEXT: v_mov_b32_e32 v1, s35
; GFX8-NEXT: v_mov_b32_e32 v2, s34
; GFX8-NEXT: v_mov_b32_e32 v3, s33
-; GFX8-NEXT: v_mov_b32_e32 v5, s27
-; GFX8-NEXT: s_add_u32 s26, s0, 0x60
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s27, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NEXT: v_mov_b32_e32 v0, s31
; GFX8-NEXT: v_mov_b32_e32 v1, s30
@@ -4409,9 +4409,9 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s22, s0, 0x50
; GFX8-NEXT: v_mov_b32_e32 v2, s23
; GFX8-NEXT: s_addc_u32 s23, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: v_mov_b32_e32 v0, s25
; GFX8-NEXT: v_mov_b32_e32 v1, s24
+; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: v_mov_b32_e32 v5, s23
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -4419,9 +4419,9 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s18, s0, 64
; GFX8-NEXT: v_mov_b32_e32 v2, s19
; GFX8-NEXT: s_addc_u32 s19, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v0, s21
; GFX8-NEXT: v_mov_b32_e32 v1, s20
+; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v5, s19
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -4429,9 +4429,9 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s14, s0, 48
; GFX8-NEXT: v_mov_b32_e32 v2, s15
; GFX8-NEXT: s_addc_u32 s15, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: v_mov_b32_e32 v0, s17
; GFX8-NEXT: v_mov_b32_e32 v1, s16
+; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: v_mov_b32_e32 v5, s15
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -4439,9 +4439,9 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s10, s0, 32
; GFX8-NEXT: v_mov_b32_e32 v2, s11
; GFX8-NEXT: s_addc_u32 s11, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NEXT: v_mov_b32_e32 v0, s13
; GFX8-NEXT: v_mov_b32_e32 v1, s12
+; GFX8-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -4449,9 +4449,9 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s6, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NEXT: s_addc_u32 s7, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v0, s9
; GFX8-NEXT: v_mov_b32_e32 v1, s8
+; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
@@ -5091,8 +5091,9 @@ define amdgpu_kernel void @constant_sextload_i1_to_i64(ptr addrspace(1) %out, pt
; GFX12-NEXT: s_load_u8 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
;
@@ -5257,8 +5258,9 @@ define amdgpu_kernel void @constant_sextload_v1i1_to_v1i64(ptr addrspace(1) %out
; GFX12-NEXT: s_load_u8 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
;
@@ -5544,9 +5546,9 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX8-NEXT: s_add_u32 s2, s0, 16
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v9, s3
-; GFX8-NEXT: v_mov_b32_e32 v7, s1
; GFX8-NEXT: v_mov_b32_e32 v8, s2
; GFX8-NEXT: v_mov_b32_e32 v1, v5
+; GFX8-NEXT: v_mov_b32_e32 v7, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v4
@@ -5695,8 +5697,8 @@ define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX8-NEXT: s_add_u32 s2, s0, 16
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v7, s3
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 2, v0
@@ -5823,14 +5825,14 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
; GFX8-NEXT: s_add_u32 s2, s0, 16
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v3, v1
-; GFX8-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NEXT: v_mov_b32_e32 v11, s3
; GFX8-NEXT: v_mov_b32_e32 v10, s2
; GFX8-NEXT: v_mov_b32_e32 v5, v1
; GFX8-NEXT: v_mov_b32_e32 v7, v1
+; GFX8-NEXT: v_mov_b32_e32 v9, s1
; GFX8-NEXT: v_mov_b32_e32 v8, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v4, 1, v0
@@ -5999,8 +6001,8 @@ define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX8-NEXT: s_add_u32 s2, s0, 16
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v11, s3
-; GFX8-NEXT: v_mov_b32_e32 v9, s1
; GFX8-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NEXT: v_mov_b32_e32 v9, s1
; GFX8-NEXT: v_mov_b32_e32 v8, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 2, v0
@@ -6153,11 +6155,11 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX8-NEXT: s_add_u32 s2, s0, 48
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: s_add_u32 s4, s0, 32
-; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: v_mov_b32_e32 v16, s5
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v5, v1
; GFX8-NEXT: v_mov_b32_e32 v7, v1
+; GFX8-NEXT: v_mov_b32_e32 v16, s5
; GFX8-NEXT: v_mov_b32_e32 v15, s4
; GFX8-NEXT: v_mov_b32_e32 v8, v1
; GFX8-NEXT: v_mov_b32_e32 v10, v1
@@ -6168,7 +6170,7 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX8-NEXT: v_bfe_u32 v6, v0, 5, 1
; GFX8-NEXT: v_bfe_u32 v4, v0, 4, 1
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
-; GFX8-NEXT: v_mov_b32_e32 v16, s3
+; GFX8-NEXT: v_bfe_u32 v9, v0, 3, 1
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: s_add_u32 s0, s0, 16
@@ -6176,8 +6178,8 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX8-NEXT: v_mov_b32_e32 v18, s1
; GFX8-NEXT: v_mov_b32_e32 v17, s0
; GFX8-NEXT: v_and_b32_e32 v6, 0xffff, v0
-; GFX8-NEXT: v_bfe_u32 v9, v0, 3, 1
; GFX8-NEXT: v_bfe_u32 v7, v0, 2, 1
+; GFX8-NEXT: v_mov_b32_e32 v16, s3
; GFX8-NEXT: v_mov_b32_e32 v15, s2
; GFX8-NEXT: v_bfe_u32 v13, v0, 1, 1
; GFX8-NEXT: v_and_b32_e32 v11, 1, v0
@@ -6372,25 +6374,25 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX8-NEXT: v_mov_b32_e32 v19, s3
; GFX8-NEXT: v_mov_b32_e32 v18, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v6, s4
; GFX8-NEXT: v_mov_b32_e32 v7, s5
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GFX8-NEXT: s_add_u32 s0, s0, 16
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v8, s6
; GFX8-NEXT: v_mov_b32_e32 v9, s7
; GFX8-NEXT: v_mov_b32_e32 v10, s8
; GFX8-NEXT: v_mov_b32_e32 v11, s9
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v12, s10
; GFX8-NEXT: v_mov_b32_e32 v13, s11
; GFX8-NEXT: v_mov_b32_e32 v14, s12
; GFX8-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v2, s14
@@ -6640,37 +6642,37 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[2:5]
; GFX8-NEXT: v_mov_b32_e32 v11, s3
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v10, s2
; GFX8-NEXT: s_add_u32 s2, s0, 0x70
-; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s5
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_add_u32 s2, s0, 0x60
-; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_mov_b32_e32 v4, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s13
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_add_u32 s2, s0, 48
-; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
+; GFX8-NEXT: v_mov_b32_e32 v2, s13
; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_mov_b32_e32 v2, s12
-; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_add_u32 s2, s0, 32
-; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
+; GFX8-NEXT: v_mov_b32_e32 v2, s12
+; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_mov_b32_e32 v2, s11
-; GFX8-NEXT: v_mov_b32_e32 v4, v12
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_add_u32 s2, s0, 16
-; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
+; GFX8-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NEXT: v_mov_b32_e32 v4, v12
; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NEXT: v_mov_b32_e32 v4, s7
@@ -7082,26 +7084,26 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v7, s19
; GFX8-NEXT: v_mov_b32_e32 v8, s20
; GFX8-NEXT: v_mov_b32_e32 v9, s21
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[6:9]
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: s_add_u32 s0, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v10, s22
; GFX8-NEXT: v_mov_b32_e32 v11, s23
; GFX8-NEXT: v_mov_b32_e32 v12, s24
; GFX8-NEXT: v_mov_b32_e32 v13, s25
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[6:9]
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[10:13]
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v14, s26
; GFX8-NEXT: v_mov_b32_e32 v15, s27
; GFX8-NEXT: v_mov_b32_e32 v16, s28
; GFX8-NEXT: v_mov_b32_e32 v17, s29
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[10:13]
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v2, s30
@@ -7500,92 +7502,92 @@ define amdgpu_kernel void @constant_zextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0xe0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s34
-; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0xd0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s34
+; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s33
-; GFX8-NEXT: v_mov_b32_e32 v2, s9
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0xc0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s33
+; GFX8-NEXT: v_mov_b32_e32 v2, s9
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s31
-; GFX8-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0xb0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s31
+; GFX8-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s30
-; GFX8-NEXT: v_mov_b32_e32 v2, s11
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0xa0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s30
+; GFX8-NEXT: v_mov_b32_e32 v2, s11
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s28
-; GFX8-NEXT: v_mov_b32_e32 v2, s29
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x90
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s28
+; GFX8-NEXT: v_mov_b32_e32 v2, s29
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s27
-; GFX8-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x80
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s27
+; GFX8-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s26
-; GFX8-NEXT: v_mov_b32_e32 v2, s13
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x70
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s26
+; GFX8-NEXT: v_mov_b32_e32 v2, s13
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s25
-; GFX8-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x60
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s25
+; GFX8-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s24
-; GFX8-NEXT: v_mov_b32_e32 v2, s15
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x50
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s24
+; GFX8-NEXT: v_mov_b32_e32 v2, s15
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s23
-; GFX8-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 64
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s23
+; GFX8-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s22
-; GFX8-NEXT: v_mov_b32_e32 v2, s17
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 48
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s22
+; GFX8-NEXT: v_mov_b32_e32 v2, s17
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s21
-; GFX8-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s6, s0, 32
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s21
+; GFX8-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v0, s20
; GFX8-NEXT: v_mov_b32_e32 v2, s19
@@ -8180,48 +8182,48 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v1, s45
; GFX8-NEXT: s_addc_u32 s45, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s44
-; GFX8-NEXT: v_mov_b32_e32 v2, s46
-; GFX8-NEXT: v_mov_b32_e32 v3, s47
; GFX8-NEXT: v_mov_b32_e32 v5, s45
; GFX8-NEXT: s_add_u32 s44, s0, 0xe0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v2, s46
+; GFX8-NEXT: v_mov_b32_e32 v3, s47
; GFX8-NEXT: s_addc_u32 s45, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NEXT: v_mov_b32_e32 v5, s45
+; GFX8-NEXT: s_add_u32 s44, s0, 0xd0
; GFX8-NEXT: v_mov_b32_e32 v0, s48
; GFX8-NEXT: v_mov_b32_e32 v1, s49
; GFX8-NEXT: v_mov_b32_e32 v2, s50
; GFX8-NEXT: v_mov_b32_e32 v3, s51
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xd0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s45, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NEXT: v_mov_b32_e32 v5, s45
+; GFX8-NEXT: s_add_u32 s44, s0, 0xc0
; GFX8-NEXT: v_mov_b32_e32 v0, s52
; GFX8-NEXT: v_mov_b32_e32 v1, s53
; GFX8-NEXT: v_mov_b32_e32 v2, s54
; GFX8-NEXT: v_mov_b32_e32 v3, s55
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xc0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s45, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NEXT: v_mov_b32_e32 v5, s45
+; GFX8-NEXT: s_add_u32 s44, s0, 0xb0
; GFX8-NEXT: v_mov_b32_e32 v0, s56
; GFX8-NEXT: v_mov_b32_e32 v1, s57
; GFX8-NEXT: v_mov_b32_e32 v2, s58
; GFX8-NEXT: v_mov_b32_e32 v3, s59
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xb0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s45, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NEXT: v_mov_b32_e32 v5, s45
+; GFX8-NEXT: s_add_u32 s44, s0, 0xa0
; GFX8-NEXT: v_mov_b32_e32 v0, s60
; GFX8-NEXT: v_mov_b32_e32 v1, s61
; GFX8-NEXT: v_mov_b32_e32 v2, s62
; GFX8-NEXT: v_mov_b32_e32 v3, s63
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xa0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s45, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s44
; GFX8-NEXT: v_mov_b32_e32 v0, s64
; GFX8-NEXT: v_mov_b32_e32 v1, s65
@@ -8234,9 +8236,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s40, s0, 0x90
; GFX8-NEXT: v_mov_b32_e32 v3, s41
; GFX8-NEXT: s_addc_u32 s41, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s40
; GFX8-NEXT: v_mov_b32_e32 v0, s42
; GFX8-NEXT: v_mov_b32_e32 v1, s43
+; GFX8-NEXT: v_mov_b32_e32 v4, s40
; GFX8-NEXT: v_mov_b32_e32 v5, s41
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8244,9 +8246,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s36, s0, 0x80
; GFX8-NEXT: v_mov_b32_e32 v3, s37
; GFX8-NEXT: s_addc_u32 s37, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s36
; GFX8-NEXT: v_mov_b32_e32 v0, s38
; GFX8-NEXT: v_mov_b32_e32 v1, s39
+; GFX8-NEXT: v_mov_b32_e32 v4, s36
; GFX8-NEXT: v_mov_b32_e32 v5, s37
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8254,9 +8256,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s30, s0, 0x70
; GFX8-NEXT: v_mov_b32_e32 v3, s31
; GFX8-NEXT: s_addc_u32 s31, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v0, s34
; GFX8-NEXT: v_mov_b32_e32 v1, s35
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v5, s31
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8264,9 +8266,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s26, s0, 0x60
; GFX8-NEXT: v_mov_b32_e32 v3, s27
; GFX8-NEXT: s_addc_u32 s27, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NEXT: v_mov_b32_e32 v0, s28
; GFX8-NEXT: v_mov_b32_e32 v1, s29
+; GFX8-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NEXT: v_mov_b32_e32 v5, s27
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8274,9 +8276,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s22, s0, 0x50
; GFX8-NEXT: v_mov_b32_e32 v3, s23
; GFX8-NEXT: s_addc_u32 s23, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NEXT: v_mov_b32_e32 v1, s25
+; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: v_mov_b32_e32 v5, s23
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8284,9 +8286,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s18, s0, 64
; GFX8-NEXT: v_mov_b32_e32 v3, s19
; GFX8-NEXT: s_addc_u32 s19, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v0, s20
; GFX8-NEXT: v_mov_b32_e32 v1, s21
+; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v5, s19
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8294,9 +8296,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s14, s0, 48
; GFX8-NEXT: v_mov_b32_e32 v3, s15
; GFX8-NEXT: s_addc_u32 s15, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: v_mov_b32_e32 v1, s17
+; GFX8-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NEXT: v_mov_b32_e32 v5, s15
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8304,9 +8306,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s10, s0, 32
; GFX8-NEXT: v_mov_b32_e32 v3, s11
; GFX8-NEXT: s_addc_u32 s11, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8314,9 +8316,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s6, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NEXT: s_addc_u32 s7, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
@@ -9046,92 +9048,92 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v4, s42
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x1f0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s66
-; GFX8-NEXT: v_mov_b32_e32 v2, s44
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x1e0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s66
+; GFX8-NEXT: v_mov_b32_e32 v2, s44
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s65
-; GFX8-NEXT: v_mov_b32_e32 v2, s45
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x1d0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s65
+; GFX8-NEXT: v_mov_b32_e32 v2, s45
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s64
-; GFX8-NEXT: v_mov_b32_e32 v2, s46
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x1c0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s64
+; GFX8-NEXT: v_mov_b32_e32 v2, s46
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s63
-; GFX8-NEXT: v_mov_b32_e32 v2, s47
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x1b0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s63
+; GFX8-NEXT: v_mov_b32_e32 v2, s47
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s62
-; GFX8-NEXT: v_mov_b32_e32 v2, s48
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x190
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s62
+; GFX8-NEXT: v_mov_b32_e32 v2, s48
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s61
-; GFX8-NEXT: v_mov_b32_e32 v2, s49
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x180
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s61
+; GFX8-NEXT: v_mov_b32_e32 v2, s49
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s60
-; GFX8-NEXT: v_mov_b32_e32 v2, s50
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x170
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s60
+; GFX8-NEXT: v_mov_b32_e32 v2, s50
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s59
-; GFX8-NEXT: v_mov_b32_e32 v2, s51
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x160
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s59
+; GFX8-NEXT: v_mov_b32_e32 v2, s51
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s58
-; GFX8-NEXT: v_mov_b32_e32 v2, s52
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x150
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s58
+; GFX8-NEXT: v_mov_b32_e32 v2, s52
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s57
-; GFX8-NEXT: v_mov_b32_e32 v2, s53
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x140
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s57
+; GFX8-NEXT: v_mov_b32_e32 v2, s53
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s56
-; GFX8-NEXT: v_mov_b32_e32 v2, s40
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x130
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s56
+; GFX8-NEXT: v_mov_b32_e32 v2, s40
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
-; GFX8-NEXT: v_mov_b32_e32 v0, s55
-; GFX8-NEXT: v_mov_b32_e32 v2, s38
; GFX8-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NEXT: s_add_u32 s42, s0, 0x120
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s55
+; GFX8-NEXT: v_mov_b32_e32 v2, s38
; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s42
; GFX8-NEXT: v_mov_b32_e32 v0, s54
; GFX8-NEXT: v_mov_b32_e32 v2, s37
@@ -9141,56 +9143,56 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s41
; GFX8-NEXT: s_addc_u32 s41, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s40
; GFX8-NEXT: v_mov_b32_e32 v2, s35
+; GFX8-NEXT: v_mov_b32_e32 v4, s40
; GFX8-NEXT: v_mov_b32_e32 v5, s41
; GFX8-NEXT: s_add_u32 s38, s0, 0x100
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s39
; GFX8-NEXT: s_addc_u32 s39, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s38
; GFX8-NEXT: v_mov_b32_e32 v2, s33
+; GFX8-NEXT: v_mov_b32_e32 v4, s38
; GFX8-NEXT: v_mov_b32_e32 v5, s39
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s36
; GFX8-NEXT: s_add_u32 s36, s0, 0xf0
; GFX8-NEXT: s_addc_u32 s37, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s36
; GFX8-NEXT: v_mov_b32_e32 v2, s30
+; GFX8-NEXT: v_mov_b32_e32 v4, s36
; GFX8-NEXT: v_mov_b32_e32 v5, s37
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s34
; GFX8-NEXT: s_add_u32 s34, s0, 0xe0
; GFX8-NEXT: s_addc_u32 s35, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s34
; GFX8-NEXT: v_mov_b32_e32 v2, s28
+; GFX8-NEXT: v_mov_b32_e32 v4, s34
; GFX8-NEXT: v_mov_b32_e32 v5, s35
; GFX8-NEXT: s_add_u32 s30, s0, 0xd0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s31
; GFX8-NEXT: s_addc_u32 s31, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v2, s26
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v5, s31
; GFX8-NEXT: s_add_u32 s28, s0, 0xc0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s29
; GFX8-NEXT: s_addc_u32 s29, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s28
; GFX8-NEXT: v_mov_b32_e32 v2, s25
+; GFX8-NEXT: v_mov_b32_e32 v4, s28
; GFX8-NEXT: v_mov_b32_e32 v5, s29
; GFX8-NEXT: s_add_u32 s26, s0, 0xb0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s27
; GFX8-NEXT: s_addc_u32 s27, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NEXT: v_mov_b32_e32 v2, s22
+; GFX8-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NEXT: v_mov_b32_e32 v5, s27
; GFX8-NEXT: s_add_u32 s22, s0, 0xa0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -9198,11 +9200,11 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v0, s23
; GFX8-NEXT: s_addc_u32 s23, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s22
-; GFX8-NEXT: v_mov_b32_e32 v2, s24
; GFX8-NEXT: v_mov_b32_e32 v5, s23
; GFX8-NEXT: s_add_u32 s22, s0, 0x90
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v2, s24
; GFX8-NEXT: s_addc_u32 s23, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: v_mov_b32_e32 v0, s21
; GFX8-NEXT: v_mov_b32_e32 v2, s19
@@ -9212,32 +9214,32 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v0, s20
; GFX8-NEXT: s_add_u32 s20, s0, 0x80
; GFX8-NEXT: s_addc_u32 s21, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v2, s17
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v5, s21
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s18
; GFX8-NEXT: s_add_u32 s18, s0, 0x70
; GFX8-NEXT: s_addc_u32 s19, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NEXT: v_mov_b32_e32 v5, s19
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: s_add_u32 s16, s0, 0x60
; GFX8-NEXT: s_addc_u32 s17, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NEXT: v_mov_b32_e32 v2, s13
+; GFX8-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NEXT: v_mov_b32_e32 v5, s17
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NEXT: s_add_u32 s12, s0, 0x50
; GFX8-NEXT: s_addc_u32 s13, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NEXT: v_mov_b32_e32 v5, s13
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -10506,8 +10508,9 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v56, s86
; GFX8-NEXT: v_mov_b32_e32 v57, s87
; GFX8-NEXT: s_add_u32 s86, s0, 0x190
-; GFX8-NEXT: flat_store_dwordx4 v[46:47], v[12:15]
; GFX8-NEXT: s_addc_u32 s87, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[46:47], v[12:15]
+; GFX8-NEXT: flat_store_dwordx4 v[48:49], v[4:7]
; GFX8-NEXT: v_mov_b32_e32 v12, s86
; GFX8-NEXT: v_mov_b32_e32 v13, s87
; GFX8-NEXT: s_add_u32 s86, s0, 0x180
@@ -10519,7 +10522,6 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v58, s86
; GFX8-NEXT: v_mov_b32_e32 v59, s87
; GFX8-NEXT: s_add_u32 s86, s0, 0x160
-; GFX8-NEXT: flat_store_dwordx4 v[48:49], v[4:7]
; GFX8-NEXT: s_addc_u32 s87, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v6, s86
; GFX8-NEXT: v_mov_b32_e32 v7, s87
@@ -10543,11 +10545,12 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s4, s0, 0x120
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v11, s5
-; GFX8-NEXT: v_mov_b32_e32 v60, s86
-; GFX8-NEXT: v_mov_b32_e32 v4, s10
-; GFX8-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NEXT: v_mov_b32_e32 v10, s4
; GFX8-NEXT: s_add_u32 s4, s0, 0x110
+; GFX8-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v60, s86
; GFX8-NEXT: v_mov_b32_e32 v61, s87
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
@@ -10560,151 +10563,150 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: flat_store_dwordx4 v[60:61], v[44:47]
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
-; GFX8-NEXT: s_addc_u32 s5, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x100
; GFX8-NEXT: v_mov_b32_e32 v1, s15
; GFX8-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NEXT: v_mov_b32_e32 v3, s17
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0x100
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xf0
; GFX8-NEXT: v_mov_b32_e32 v0, s22
; GFX8-NEXT: v_mov_b32_e32 v1, s23
; GFX8-NEXT: v_mov_b32_e32 v2, s20
; GFX8-NEXT: v_mov_b32_e32 v3, s21
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0xf0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xe0
; GFX8-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NEXT: v_mov_b32_e32 v1, s25
; GFX8-NEXT: v_mov_b32_e32 v2, s26
; GFX8-NEXT: v_mov_b32_e32 v3, s27
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0xe0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xd0
; GFX8-NEXT: v_mov_b32_e32 v0, s30
; GFX8-NEXT: v_mov_b32_e32 v1, s31
; GFX8-NEXT: v_mov_b32_e32 v2, s82
; GFX8-NEXT: v_mov_b32_e32 v3, s83
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0xd0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xc0
; GFX8-NEXT: v_mov_b32_e32 v0, s84
; GFX8-NEXT: v_mov_b32_e32 v1, s85
; GFX8-NEXT: v_mov_b32_e32 v2, s80
; GFX8-NEXT: v_mov_b32_e32 v3, s81
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0xc0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xb0
; GFX8-NEXT: v_mov_b32_e32 v0, s78
; GFX8-NEXT: v_mov_b32_e32 v1, s79
; GFX8-NEXT: v_mov_b32_e32 v2, s76
; GFX8-NEXT: v_mov_b32_e32 v3, s77
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0xb0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xa0
; GFX8-NEXT: v_mov_b32_e32 v0, s74
; GFX8-NEXT: v_mov_b32_e32 v1, s75
; GFX8-NEXT: v_mov_b32_e32 v2, s72
; GFX8-NEXT: v_mov_b32_e32 v3, s73
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0xa0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x90
; GFX8-NEXT: v_mov_b32_e32 v0, s70
; GFX8-NEXT: v_mov_b32_e32 v1, s71
; GFX8-NEXT: v_mov_b32_e32 v2, s68
; GFX8-NEXT: v_mov_b32_e32 v3, s69
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0x90
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x80
; GFX8-NEXT: v_mov_b32_e32 v0, s66
; GFX8-NEXT: v_mov_b32_e32 v1, s67
; GFX8-NEXT: v_mov_b32_e32 v2, s64
; GFX8-NEXT: v_mov_b32_e32 v3, s65
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0x80
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x70
; GFX8-NEXT: v_mov_b32_e32 v0, s62
; GFX8-NEXT: v_mov_b32_e32 v1, s63
; GFX8-NEXT: v_mov_b32_e32 v2, s60
; GFX8-NEXT: v_mov_b32_e32 v3, s61
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0x70
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x60
; GFX8-NEXT: v_mov_b32_e32 v0, s58
; GFX8-NEXT: v_mov_b32_e32 v1, s59
; GFX8-NEXT: v_mov_b32_e32 v2, s56
; GFX8-NEXT: v_mov_b32_e32 v3, s57
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0x60
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x50
; GFX8-NEXT: v_mov_b32_e32 v0, s54
; GFX8-NEXT: v_mov_b32_e32 v1, s55
; GFX8-NEXT: v_mov_b32_e32 v2, s52
; GFX8-NEXT: v_mov_b32_e32 v3, s53
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 0x50
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 64
; GFX8-NEXT: v_mov_b32_e32 v0, s50
; GFX8-NEXT: v_mov_b32_e32 v1, s51
; GFX8-NEXT: v_mov_b32_e32 v2, s48
; GFX8-NEXT: v_mov_b32_e32 v3, s49
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 64
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 48
; GFX8-NEXT: v_mov_b32_e32 v0, s46
; GFX8-NEXT: v_mov_b32_e32 v1, s47
; GFX8-NEXT: v_mov_b32_e32 v2, s44
; GFX8-NEXT: v_mov_b32_e32 v3, s45
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 48
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 32
; GFX8-NEXT: v_mov_b32_e32 v0, s42
; GFX8-NEXT: v_mov_b32_e32 v1, s43
; GFX8-NEXT: v_mov_b32_e32 v2, s40
; GFX8-NEXT: v_mov_b32_e32 v3, s41
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 32
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v0, s38
; GFX8-NEXT: v_mov_b32_e32 v1, s39
; GFX8-NEXT: v_mov_b32_e32 v2, s36
; GFX8-NEXT: v_mov_b32_e32 v3, s37
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NEXT: s_add_u32 s4, s0, 16
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s34
; GFX8-NEXT: v_mov_b32_e32 v1, s35
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 0021af9381335..5494bcf0c64f2 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -201,10 +201,10 @@ define amdgpu_kernel void @constant_load_v3i16(ptr addrspace(1) %out, ptr addrsp
; GCN-HSA-NEXT: s_add_u32 s4, s0, 4
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s2
; GCN-HSA-NEXT: flat_store_short v[2:3], v4
@@ -219,10 +219,10 @@ define amdgpu_kernel void @constant_load_v3i16(ptr addrspace(1) %out, ptr addrsp
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s0, 4
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s1, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s2
; GCN-NOHSA-VI-NEXT: flat_store_short v[2:3], v4
@@ -347,9 +347,9 @@ define amdgpu_kernel void @constant_load_v4i16(ptr addrspace(1) %out, ptr addrsp
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -428,10 +428,10 @@ define amdgpu_kernel void @constant_load_v8i16(ptr addrspace(1) %out, ptr addrsp
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -478,12 +478,12 @@ define amdgpu_kernel void @constant_load_v16i16(ptr addrspace(1) %out, ptr addrs
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s7
-; GCN-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GCN-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-HSA-NEXT: s_endpgm
@@ -502,12 +502,12 @@ define amdgpu_kernel void @constant_load_v16i16(ptr addrspace(1) %out, ptr addrs
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-NOHSA-VI-NEXT: s_endpgm
@@ -620,8 +620,8 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -668,6 +668,7 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s2
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 26
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
; GCN-NOHSA-VI-NEXT: flat_load_ushort v16, v[0:1]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v17, v[2:3]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v18, v[4:5]
@@ -676,7 +677,6 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-NOHSA-VI-NEXT: flat_load_ushort v9, v[10:11]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v10, v[12:13]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v11, v[14:15]
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 24
@@ -692,11 +692,11 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s2
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 18
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
; GCN-NOHSA-VI-NEXT: flat_load_ushort v12, v[0:1]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v13, v[2:3]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v14, v[4:5]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v15, v[6:7]
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
@@ -706,8 +706,8 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 2
; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s0
; GCN-NOHSA-VI-NEXT: flat_load_ushort v0, v[0:1]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v20, v[2:3]
@@ -1802,9 +1802,9 @@ define amdgpu_kernel void @constant_zextload_v8i16_to_v8i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -1834,9 +1834,9 @@ define amdgpu_kernel void @constant_zextload_v8i16_to_v8i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
@@ -1955,16 +1955,16 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_ashr_i32 s3, s6, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
; GCN-HSA-NEXT: s_sext_i32_i16 s6, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
+; GCN-HSA-NEXT: s_sext_i32_i16 s4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
-; GCN-HSA-NEXT: s_sext_i32_i16 s4, s4
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
@@ -1987,16 +1987,16 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s3, s6, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s2
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
@@ -2401,27 +2401,29 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: s_sext_i32_i16 s11, s11
; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: s_sext_i32_i16 s9, s9
; GCN-HSA-NEXT: s_sext_i32_i16 s8, s8
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
+; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
+; GCN-HSA-NEXT: s_sext_i32_i16 s6, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s17
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
-; GCN-HSA-NEXT: s_sext_i32_i16 s6, s6
+; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
+; GCN-HSA-NEXT: s_sext_i32_i16 s4, s4
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
@@ -2429,8 +2431,6 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
-; GCN-HSA-NEXT: s_sext_i32_i16 s4, s4
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
@@ -2459,27 +2459,29 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s16
; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
@@ -2487,8 +2489,6 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s14
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
@@ -2740,17 +2740,17 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s0
+; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s34
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s33
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
-; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s31
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s30
@@ -2758,14 +2758,14 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s29
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s28
-; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s28
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s27
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s9
+; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s26
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
@@ -3203,18 +3203,20 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_sext_i32_i16 s14, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s0
+; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
-; GCN-HSA-NEXT: s_add_u32 s0, s16, 64
-; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: s_sext_i32_i16 s13, s13
; GCN-HSA-NEXT: s_sext_i32_i16 s12, s12
+; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GCN-HSA-NEXT: s_sext_i32_i16 s9, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: s_add_u32 s0, s16, 48
+; GCN-HSA-NEXT: s_sext_i32_i16 s8, s8
; GCN-HSA-NEXT: s_sext_i32_i16 s11, s11
; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
@@ -3222,21 +3224,19 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s33
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: s_sext_i32_i16 s9, s9
-; GCN-HSA-NEXT: s_sext_i32_i16 s8, s8
+; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
+; GCN-HSA-NEXT: s_sext_i32_i16 s6, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s31
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s30
-; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
-; GCN-HSA-NEXT: s_sext_i32_i16 s6, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s30
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s29
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s9
+; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s28
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
@@ -3245,19 +3245,19 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s26
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
; GCN-HSA-NEXT: s_sext_i32_i16 s4, s4
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: s_add_u32 s0, s16, 16
+; GCN-HSA-NEXT: s_sext_i32_i16 s3, s3
+; GCN-HSA-NEXT: s_sext_i32_i16 s2, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s24
; GCN-HSA-NEXT: s_addc_u32 s1, s17, 0
-; GCN-HSA-NEXT: s_sext_i32_i16 s3, s3
-; GCN-HSA-NEXT: s_sext_i32_i16 s2, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
@@ -3303,18 +3303,18 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x70
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s15, s15
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s14, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s13, s13
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s12, s12
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x50
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
@@ -3322,10 +3322,10 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s33
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 64
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
@@ -3333,10 +3333,10 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s30
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
@@ -3344,10 +3344,10 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s28
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
@@ -3355,19 +3355,19 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s26
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s24
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
@@ -3857,29 +3857,29 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s20
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s56
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s18
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s21
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s55
-; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
-; GCN-HSA-NEXT: s_addc_u32 s13, s37, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s54
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s19
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s15
-; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s68
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GCN-HSA-NEXT: s_addc_u32 s13, s37, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s17
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s67
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s52
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s51
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s14
+; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s12
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
@@ -3890,9 +3890,9 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s10, s36, 0x50
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
; GCN-HSA-NEXT: s_addc_u32 s11, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s48
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -3900,9 +3900,9 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s8, s36, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s9
; GCN-HSA-NEXT: s_addc_u32 s9, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s46
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s45
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -3910,9 +3910,9 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s6, s36, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
; GCN-HSA-NEXT: s_addc_u32 s7, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s44
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -3920,9 +3920,9 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s4, s36, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s42
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -3930,9 +3930,9 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s2, s36, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
@@ -4683,9 +4683,9 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s18
; GCN-HSA-NEXT: s_add_u32 s18, s36, 0xa0
; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s19
; GCN-HSA-NEXT: s_sext_i32_i16 s27, s27
; GCN-HSA-NEXT: s_sext_i32_i16 s26, s26
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s19
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s18
; GCN-HSA-NEXT: s_add_u32 s18, s36, 0x90
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s26
@@ -4693,10 +4693,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s27
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s63
; GCN-HSA-NEXT: s_addc_u32 s19, s37, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s19
; GCN-HSA-NEXT: s_sext_i32_i16 s25, s25
; GCN-HSA-NEXT: s_sext_i32_i16 s24, s24
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s19
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s18
; GCN-HSA-NEXT: s_add_u32 s18, s36, 0x80
; GCN-HSA-NEXT: s_sext_i32_i16 s14, s14
@@ -4735,37 +4735,37 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s29
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s65
; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s20
+; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
; GCN-HSA-NEXT: s_add_u32 s12, s36, 0x60
+; GCN-HSA-NEXT: s_sext_i32_i16 s17, s17
+; GCN-HSA-NEXT: s_sext_i32_i16 s16, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s20
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s58
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s56
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s21
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
-; GCN-HSA-NEXT: s_addc_u32 s13, s37, 0
-; GCN-HSA-NEXT: s_sext_i32_i16 s10, s10
-; GCN-HSA-NEXT: s_sext_i32_i16 s17, s17
-; GCN-HSA-NEXT: s_sext_i32_i16 s16, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s56
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s54
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s55
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s15
-; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GCN-HSA-NEXT: s_addc_u32 s13, s37, 0
; GCN-HSA-NEXT: s_sext_i32_i16 s11, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s19
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s18
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s17
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s51
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s39
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s38
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s14
+; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s12
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
@@ -4776,9 +4776,9 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s10, s36, 0x50
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
; GCN-HSA-NEXT: s_addc_u32 s11, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s48
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: s_sext_i32_i16 s9, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -4787,9 +4787,9 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s8, s36, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s9
; GCN-HSA-NEXT: s_addc_u32 s9, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s46
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s45
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: s_sext_i32_i16 s7, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -4798,9 +4798,9 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s6, s36, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
; GCN-HSA-NEXT: s_addc_u32 s7, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s44
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: s_sext_i32_i16 s5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -4809,9 +4809,9 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s4, s36, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s42
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: s_sext_i32_i16 s3, s3
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -4820,11 +4820,11 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s2, s36, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s37, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: s_sext_i32_i16 s0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_sext_i32_i16 s0, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
@@ -4880,18 +4880,18 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xf0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s15, s15
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s14, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xe0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s13, s13
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s12, s12
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xd0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
@@ -4899,10 +4899,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s65
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xc0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
@@ -4910,10 +4910,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s63
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xb0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
@@ -4921,10 +4921,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s61
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xa0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
@@ -4932,10 +4932,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s59
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x90
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
@@ -4943,10 +4943,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s57
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x80
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
@@ -4963,10 +4963,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s53
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s51
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s31, s31
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s30, s30
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
@@ -4974,10 +4974,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s49
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s29, s29
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s28, s28
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x50
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
@@ -4985,10 +4985,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s47
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s27, s27
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s26, s26
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 64
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
@@ -4996,10 +4996,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s45
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s25, s25
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s24, s24
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
@@ -5007,10 +5007,10 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s25
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s43
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s23, s23
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s22, s22
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
@@ -5018,19 +5018,21 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s23
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s41
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s21, s21
; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s20, s20
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s19, s19
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s18, s18
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s40
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s39
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s19, s19
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s18, s18
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s17, s17
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s16, s16
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
@@ -5038,8 +5040,6 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s19
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s17, s17
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s16, s16
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s36
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
@@ -6001,8 +6001,8 @@ define amdgpu_kernel void @constant_zextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -6145,9 +6145,9 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s4, s0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -6176,9 +6176,9 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
@@ -6588,21 +6588,21 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 32
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
-; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 16
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
@@ -7200,25 +7200,25 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s14
; GCN-HSA-NEXT: s_add_u32 s14, s8, 48
; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s22
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s14
+; GCN-HSA-NEXT: s_add_u32 s14, s8, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
-; GCN-HSA-NEXT: s_add_u32 s14, s8, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s34
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s33
-; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s17
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s31
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s30
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s18
+; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s19
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s15
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
@@ -7229,12 +7229,12 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
; GCN-HSA-NEXT: s_addc_u32 s7, s9, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: s_add_u32 s6, s8, 64
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
; GCN-HSA-NEXT: s_addc_u32 s7, s9, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
@@ -7247,9 +7247,9 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s4, s8, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
@@ -7300,30 +7300,30 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s34
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s35
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 64
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s34
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s35
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x70
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s31
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
-; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x70
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
-; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x60
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s23
@@ -7688,20 +7688,20 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x50
; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s8
; GCN-HSA-NEXT: s_add_u32 s8, s16, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
-; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s9
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s29
; GCN-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s11
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s28
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s8
; GCN-HSA-NEXT: s_add_u32 s8, s16, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
@@ -7711,40 +7711,40 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s8
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xe0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s25
; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
-; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xe0
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s23
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xc0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s31
-; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xc0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s33
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: s_add_u32 s8, s16, 0xa0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s33
; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x80
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s35
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
@@ -7754,24 +7754,24 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: s_add_u32 s6, s16, 0x60
; GCN-HSA-NEXT: s_addc_u32 s7, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: s_add_u32 s4, s16, 64
; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_add_u32 s2, s16, 32
; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
@@ -7828,85 +7828,85 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xe0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s35
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xd0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s35
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s13
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s34
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xc0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s34
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s33
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xb0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s33
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xa0
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s11
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x90
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s9
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x80
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x70
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s28
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x60
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s26
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x50
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s26
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s25
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 64
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s25
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s24
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s23
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 48
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s23
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s22
; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
@@ -8429,26 +8429,26 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x70
; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s52
; GCN-HSA-NEXT: v_mov_b32_e32 v27, s43
; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s73
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s72
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s71
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s70
; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s73
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s72
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[6:9]
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s36
+; GCN-HSA-NEXT: s_add_u32 s36, s16, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s45
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[2:5]
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s69
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s68
-; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[6:9]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[10:13]
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s36
-; GCN-HSA-NEXT: s_add_u32 s36, s16, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s37
; GCN-HSA-NEXT: s_addc_u32 s37, s17, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[10:13]
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s37
; GCN-HSA-NEXT: s_add_u32 s36, s16, 16
@@ -8466,33 +8466,34 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s61
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s31
; GCN-HSA-NEXT: s_addc_u32 s31, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s42
; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s50
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
; GCN-HSA-NEXT: s_add_u32 s14, s16, 0xc0
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s51
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s59
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v29, s43
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
-; GCN-HSA-NEXT: s_addc_u32 s15, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v29, s43
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s55
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GCN-HSA-NEXT: s_addc_u32 s15, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s30
-; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[18:21]
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s37
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s33
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s34
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s35
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s30
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s31
+; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[18:21]
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s14
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
@@ -8503,9 +8504,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s12, s16, 0xa0
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
; GCN-HSA-NEXT: s_addc_u32 s13, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s26
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s13
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8513,9 +8514,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s10, s16, 0x80
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s11
; GCN-HSA-NEXT: s_addc_u32 s11, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8523,9 +8524,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x60
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s9
; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8533,9 +8534,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s6, s16, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s7
; GCN-HSA-NEXT: s_addc_u32 s7, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s20
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8543,9 +8544,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_add_u32 s4, s16, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s18
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
@@ -8623,9 +8624,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s60, s16, 0xf0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s61
; GCN-NOHSA-VI-NEXT: s_addc_u32 s61, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s62
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s63
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s61
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
@@ -8633,9 +8634,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s58, s16, 0xe0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s59
; GCN-NOHSA-VI-NEXT: s_addc_u32 s59, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s58
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s72
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s73
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s58
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s59
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
@@ -8643,9 +8644,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s54, s16, 0xd0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s55
; GCN-NOHSA-VI-NEXT: s_addc_u32 s55, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s54
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s56
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s57
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s54
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s55
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
@@ -8653,9 +8654,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s52, s16, 0xc0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s53
; GCN-NOHSA-VI-NEXT: s_addc_u32 s53, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s52
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s64
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s65
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s52
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s53
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
@@ -8663,9 +8664,9 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_add_u32 s48, s16, 0xb0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s49
; GCN-NOHSA-VI-NEXT: s_addc_u32 s49, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s50
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s51
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s49
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
@@ -8674,12 +8675,12 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s39
; GCN-NOHSA-VI-NEXT: s_addc_u32 s39, s17, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s38
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s46
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s47
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s39
; GCN-NOHSA-VI-NEXT: s_add_u32 s38, s16, 0x90
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s46
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s47
; GCN-NOHSA-VI-NEXT: s_addc_u32 s39, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s38
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s44
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s45
@@ -8693,12 +8694,12 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
; GCN-NOHSA-VI-NEXT: s_addc_u32 s25, s17, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s24
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s40
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s41
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s25
; GCN-NOHSA-VI-NEXT: s_add_u32 s24, s16, 0x70
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s40
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s41
; GCN-NOHSA-VI-NEXT: s_addc_u32 s25, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s37
@@ -8712,12 +8713,12 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
; GCN-NOHSA-VI-NEXT: s_addc_u32 s21, s17, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s20
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s31
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s21
; GCN-NOHSA-VI-NEXT: s_add_u32 s20, s16, 0x50
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s31
; GCN-NOHSA-VI-NEXT: s_addc_u32 s21, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s20
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s29
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
index 2e862cee733f4..7770149c5cde9 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
@@ -177,9 +177,9 @@ define amdgpu_kernel void @constant_load_v2i32(ptr addrspace(1) %out, ptr addrsp
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
;
@@ -391,10 +391,10 @@ define amdgpu_kernel void @constant_load_v4i32(ptr addrspace(1) %out, ptr addrsp
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
;
@@ -454,12 +454,12 @@ define amdgpu_kernel void @constant_load_v8i32(ptr addrspace(1) %out, ptr addrsp
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-HSA-NEXT: s_endpgm
@@ -478,12 +478,12 @@ define amdgpu_kernel void @constant_load_v8i32(ptr addrspace(1) %out, ptr addrsp
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NOHSA-NEXT: s_endpgm
@@ -606,15 +606,15 @@ define amdgpu_kernel void @constant_load_v9i32(ptr addrspace(1) %out, ptr addrsp
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GFX7-HSA-NEXT: flat_store_dword v[4:5], v6
; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: flat_store_dword v[4:5], v6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
@@ -637,15 +637,15 @@ define amdgpu_kernel void @constant_load_v9i32(ptr addrspace(1) %out, ptr addrsp
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NOHSA-NEXT: flat_store_dword v[4:5], v6
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: flat_store_dword v[4:5], v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
@@ -787,18 +787,18 @@ define amdgpu_kernel void @constant_load_v10i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: s_add_u32 s10, s8, 32
; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
-; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GFX7-HSA-NEXT: flat_store_dwordx2 v[4:5], v[6:7]
; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[4:5], v[6:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
@@ -819,18 +819,18 @@ define amdgpu_kernel void @constant_load_v10i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: s_add_u32 s10, s8, 32
; GFX8-NOHSA-NEXT: s_addc_u32 s11, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
-; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s13
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[4:5], v[6:7]
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[4:5], v[6:7]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
@@ -895,13 +895,13 @@ define amdgpu_kernel void @constant_load_v10i32(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b64 s[12:13], s[10:11], 0x20
; GFX12-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v10, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, s13
; GFX12-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v1, s5
-; GFX12-NEXT: v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v0, s4
-; GFX12-NEXT: v_dual_mov_b32 v3, s7 :: v_dual_mov_b32 v2, s6
-; GFX12-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
-; GFX12-NEXT: v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
+; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
+; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v5, s1
+; GFX12-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v7, s3
+; GFX12-NEXT: v_mov_b32_e32 v6, s2
; GFX12-NEXT: s_clause 0x2
; GFX12-NEXT: global_store_b64 v10, v[8:9], s[8:9] offset:32
; GFX12-NEXT: global_store_b128 v10, v[0:3], s[8:9] offset:16
@@ -984,19 +984,19 @@ define amdgpu_kernel void @constant_load_v11i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX7-HSA-NEXT: s_add_u32 s0, s8, 32
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
; GFX7-HSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; GFX7-HSA-NEXT: s_endpgm
@@ -1027,9 +1027,9 @@ define amdgpu_kernel void @constant_load_v11i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; GFX8-NOHSA-NEXT: s_endpgm
@@ -1172,27 +1172,28 @@ define amdgpu_kernel void @constant_load_v12i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: s_add_u32 s10, s8, 32
; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s11
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm
@@ -1206,27 +1207,28 @@ define amdgpu_kernel void @constant_load_v12i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: s_add_u32 s10, s8, 32
; GFX8-NOHSA-NEXT: s_addc_u32 s11, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s11
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s11
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_endpgm
@@ -1287,14 +1289,14 @@ define amdgpu_kernel void @constant_load_v12i32(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_b128 s[12:15], s[10:11], 0x20
; GFX12-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v12, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v1, s13
; GFX12-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v3, s15
-; GFX12-NEXT: v_dual_mov_b32 v1, s13 :: v_dual_mov_b32 v2, s14
-; GFX12-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
-; GFX12-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
-; GFX12-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
-; GFX12-NEXT: v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
+; GFX12-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v5, s5
+; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
+; GFX12-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s1
+; GFX12-NEXT: v_dual_mov_b32 v8, s0 :: v_dual_mov_b32 v11, s3
+; GFX12-NEXT: v_mov_b32_e32 v10, s2
; GFX12-NEXT: s_clause 0x2
; GFX12-NEXT: global_store_b128 v12, v[0:3], s[8:9] offset:32
; GFX12-NEXT: global_store_b128 v12, v[4:7], s[8:9] offset:16
@@ -1374,27 +1376,27 @@ define amdgpu_kernel void @constant_load_v16i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s19
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GFX7-HSA-NEXT: s_add_u32 s8, s16, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
; GFX7-HSA-NEXT: s_add_u32 s4, s16, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
@@ -1416,27 +1418,27 @@ define amdgpu_kernel void @constant_load_v16i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s19
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
-; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
@@ -2240,8 +2242,8 @@ define amdgpu_kernel void @constant_zextload_v4i32_to_v4i64(ptr addrspace(1) %ou
; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
@@ -2398,16 +2400,16 @@ define amdgpu_kernel void @constant_sextload_v4i32_to_v4i64(ptr addrspace(1) %ou
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s2
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-HSA-NEXT: s_endpgm
@@ -2426,16 +2428,16 @@ define amdgpu_kernel void @constant_sextload_v4i32_to_v4i64(ptr addrspace(1) %ou
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s2
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NOHSA-NEXT: s_endpgm
@@ -2821,9 +2823,9 @@ define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %ou
; GFX7-HSA-NEXT: s_add_u32 s6, s8, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
; GFX7-HSA-NEXT: s_addc_u32 s7, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -2831,9 +2833,9 @@ define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %ou
; GFX7-HSA-NEXT: s_add_u32 s4, s8, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -2841,9 +2843,9 @@ define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %ou
; GFX7-HSA-NEXT: s_add_u32 s2, s8, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
; GFX7-HSA-NEXT: s_addc_u32 s3, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
@@ -2873,9 +2875,9 @@ define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %ou
; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -2883,9 +2885,9 @@ define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %ou
; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s15
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -2893,9 +2895,9 @@ define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %ou
; GFX8-NOHSA-NEXT: s_add_u32 s2, s8, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
@@ -3175,19 +3177,21 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_add_u32 s18, s16, 48
; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s19
-; GFX7-HSA-NEXT: s_add_u32 s18, s16, 32
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s34
; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s33
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
-; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s29
; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[3:6]
@@ -3197,33 +3201,31 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s28
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s19
-; GFX7-HSA-NEXT: s_add_u32 s18, s16, 16
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s27
; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[6:9]
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s26
-; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s19
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s23
; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[3:6]
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s19
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s23
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s22
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s21
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[9:12]
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s0
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
; GFX7-HSA-NEXT: s_endpgm
@@ -3254,9 +3256,9 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s14, s16, 0x70
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
; GFX8-NOHSA-NEXT: s_addc_u32 s15, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s34
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s15
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -3264,9 +3266,9 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0x60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s31
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -3274,9 +3276,9 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s10, s16, 0x50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
; GFX8-NOHSA-NEXT: s_addc_u32 s11, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s29
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -3284,9 +3286,9 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s27
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -3294,9 +3296,9 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s25
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -3304,9 +3306,9 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s23
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -3314,9 +3316,9 @@ define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s2, s16, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s21
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
@@ -4160,9 +4162,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xd0
; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s48
; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s24
; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xc0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s48
; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[25:26], v[18:21]
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s26
@@ -4175,9 +4177,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xa0
; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s47
; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s24
; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x90
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s47
; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[27:28], v[7:10]
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s46
@@ -4193,8 +4195,8 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s24
; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x60
; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v34, s25
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v34, s25
; GFX7-HSA-NEXT: v_mov_b32_e32 v33, s24
; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x50
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s44
@@ -4207,7 +4209,6 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s42
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s41
-; GFX7-HSA-NEXT: v_mov_b32_e32 v36, s25
; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[31:32], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s49
@@ -4215,6 +4216,7 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_add_u32 s14, s36, 64
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v36, s25
; GFX7-HSA-NEXT: v_mov_b32_e32 v35, s24
; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s40
; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s35
@@ -4223,12 +4225,12 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s38
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s31
; GFX7-HSA-NEXT: s_addc_u32 s15, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
; GFX7-HSA-NEXT: flat_store_dwordx4 v[33:34], v[3:6]
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s29
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
; GFX7-HSA-NEXT: flat_store_dwordx4 v[35:36], v[6:9]
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s9
@@ -4238,9 +4240,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_add_u32 s6, s36, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
; GFX7-HSA-NEXT: s_addc_u32 s7, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s34
@@ -4248,9 +4250,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_add_u32 s4, s36, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
; GFX7-HSA-NEXT: s_addc_u32 s5, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s33
@@ -4258,9 +4260,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: s_add_u32 s2, s36, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
; GFX7-HSA-NEXT: s_addc_u32 s3, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s36
@@ -4316,9 +4318,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s30, s36, 0xf0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s31
; GFX8-NOHSA-NEXT: s_addc_u32 s31, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s66
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s65
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s31
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4326,9 +4328,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s28, s36, 0xe0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s29
; GFX8-NOHSA-NEXT: s_addc_u32 s29, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s63
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s29
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4336,9 +4338,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s26, s36, 0xd0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s27
; GFX8-NOHSA-NEXT: s_addc_u32 s27, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s62
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s61
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s26
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s27
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4346,9 +4348,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s24, s36, 0xc0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s25
; GFX8-NOHSA-NEXT: s_addc_u32 s25, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s59
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s25
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4356,9 +4358,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s22, s36, 0xb0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s23
; GFX8-NOHSA-NEXT: s_addc_u32 s23, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s58
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s57
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s23
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4366,9 +4368,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s20, s36, 0xa0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s21
; GFX8-NOHSA-NEXT: s_addc_u32 s21, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s56
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s55
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s21
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4376,9 +4378,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s18, s36, 0x90
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
; GFX8-NOHSA-NEXT: s_addc_u32 s19, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s54
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s53
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s19
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4386,9 +4388,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s16, s36, 0x80
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s17
; GFX8-NOHSA-NEXT: s_addc_u32 s17, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s52
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s51
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4396,9 +4398,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s14, s36, 0x70
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
; GFX8-NOHSA-NEXT: s_addc_u32 s15, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s49
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s15
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4406,9 +4408,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s12, s36, 0x60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
; GFX8-NOHSA-NEXT: s_addc_u32 s13, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s47
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4416,9 +4418,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s10, s36, 0x50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
; GFX8-NOHSA-NEXT: s_addc_u32 s11, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s46
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s45
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4426,9 +4428,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s8, s36, 64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
; GFX8-NOHSA-NEXT: s_addc_u32 s9, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s44
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s43
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4436,9 +4438,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s6, s36, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s42
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s41
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4446,9 +4448,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s4, s36, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s40
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s39
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -4456,9 +4458,9 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX8-NOHSA-NEXT: s_add_u32 s2, s36, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s38
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
@@ -5047,20 +5049,20 @@ define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s0
; GFX7-HSA-NEXT: s_add_u32 s0, s36, 0xb0
+; GFX7-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
; GFX7-HSA-NEXT: s_addc_u32 s1, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s1
-; GFX7-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s0
; GFX7-HSA-NEXT: s_add_u32 s0, s36, 0xa0
; GFX7-HSA-NEXT: s_addc_u32 s1, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s0
; GFX7-HSA-NEXT: s_add_u32 s0, s36, 0x90
-; GFX7-HSA-NEXT: s_addc_u32 s1, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX7-HSA-NEXT: s_addc_u32 s1, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s0
; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
@@ -5123,26 +5125,26 @@ define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s16
+; GFX7-HSA-NEXT: s_addc_u32 s15, s37, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
-; GFX7-HSA-NEXT: s_addc_u32 s15, s37, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s17
; GFX7-HSA-NEXT: s_add_u32 s12, s36, 16
; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
; GFX7-HSA-NEXT: s_addc_u32 s13, s37, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
@@ -5703,18 +5705,19 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s19
; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x60
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x50
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
; GFX7-HSA-NEXT: s_add_u32 s18, s16, 64
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
@@ -5723,9 +5726,9 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: s_add_u32 s12, s16, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
; GFX7-HSA-NEXT: s_addc_u32 s13, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -5733,9 +5736,9 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -5743,9 +5746,9 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX7-HSA-NEXT: s_add_u32 s4, s16, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
@@ -5777,18 +5780,18 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s25
; GFX8-NOHSA-NEXT: s_addc_u32 s25, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s26
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s27
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s25
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
; GFX8-NOHSA-NEXT: s_add_u32 s20, s36, 0x50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s21
; GFX8-NOHSA-NEXT: s_addc_u32 s21, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s21
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -5796,9 +5799,9 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: s_add_u32 s16, s36, 64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NOHSA-NEXT: s_addc_u32 s17, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -5806,9 +5809,9 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: s_add_u32 s12, s36, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NOHSA-NEXT: s_addc_u32 s13, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -5816,9 +5819,9 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: s_add_u32 s8, s36, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NOHSA-NEXT: s_addc_u32 s9, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -5826,9 +5829,9 @@ define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrs
; GFX8-NOHSA-NEXT: s_add_u32 s4, s36, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s37, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
index bc666066a7acd..b40a2a4b7a7be 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
@@ -69,9 +69,9 @@ define amdgpu_kernel void @constant_load_i64(ptr addrspace(1) %out, ptr addrspac
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
%ld = load i64, ptr addrspace(4) %in
@@ -149,10 +149,10 @@ define amdgpu_kernel void @constant_load_v2i64(ptr addrspace(1) %out, ptr addrsp
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -198,12 +198,12 @@ define amdgpu_kernel void @constant_load_v3i64(ptr addrspace(1) %out, ptr addrsp
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v5, s8
; GFX7-NEXT: v_mov_b32_e32 v6, s9
-; GFX7-NEXT: flat_store_dwordx2 v[3:4], v[5:6]
-; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-NEXT: flat_store_dwordx2 v[3:4], v[5:6]
; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s0
; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-NEXT: s_endpgm
@@ -221,12 +221,12 @@ define amdgpu_kernel void @constant_load_v3i64(ptr addrspace(1) %out, ptr addrsp
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v5, s8
; GFX8-NEXT: v_mov_b32_e32 v6, s9
-; GFX8-NEXT: flat_store_dwordx2 v[3:4], v[5:6]
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: flat_store_dwordx2 v[3:4], v[5:6]
; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
@@ -310,12 +310,12 @@ define amdgpu_kernel void @constant_load_v4i64(ptr addrspace(1) %out, ptr addrsp
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: v_mov_b32_e32 v2, s6
; GFX7-NEXT: v_mov_b32_e32 v3, s7
-; GFX7-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-NEXT: v_mov_b32_e32 v4, s0
-; GFX7-NEXT: v_mov_b32_e32 v0, s8
; GFX7-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-NEXT: v_mov_b32_e32 v6, s2
; GFX7-NEXT: v_mov_b32_e32 v7, s3
+; GFX7-NEXT: v_mov_b32_e32 v0, s8
; GFX7-NEXT: v_mov_b32_e32 v1, s9
; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-NEXT: s_endpgm
@@ -334,12 +334,12 @@ define amdgpu_kernel void @constant_load_v4i64(ptr addrspace(1) %out, ptr addrsp
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s0
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v6, s2
; GFX8-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: s_endpgm
@@ -430,27 +430,27 @@ define amdgpu_kernel void @constant_load_v8i64(ptr addrspace(1) %out, ptr addrsp
; GFX7-NEXT: v_mov_b32_e32 v6, s18
; GFX7-NEXT: v_mov_b32_e32 v7, s19
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-NEXT: s_add_u32 s8, s16, 32
; GFX7-NEXT: v_mov_b32_e32 v0, s12
; GFX7-NEXT: v_mov_b32_e32 v1, s13
; GFX7-NEXT: v_mov_b32_e32 v2, s14
; GFX7-NEXT: v_mov_b32_e32 v3, s15
-; GFX7-NEXT: v_mov_b32_e32 v4, s8
-; GFX7-NEXT: s_add_u32 s8, s16, 32
; GFX7-NEXT: v_mov_b32_e32 v5, s9
-; GFX7-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX7-NEXT: v_mov_b32_e32 v6, s10
; GFX7-NEXT: v_mov_b32_e32 v7, s11
+; GFX7-NEXT: v_mov_b32_e32 v0, s8
; GFX7-NEXT: v_mov_b32_e32 v1, s9
; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_add_u32 s4, s16, 16
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s5, s17, 0
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v2, s6
; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-NEXT: v_mov_b32_e32 v4, s16
@@ -472,27 +472,27 @@ define amdgpu_kernel void @constant_load_v8i64(ptr addrspace(1) %out, ptr addrsp
; GFX8-NEXT: v_mov_b32_e32 v6, s18
; GFX8-NEXT: v_mov_b32_e32 v7, s19
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: s_add_u32 s8, s16, 32
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NEXT: v_mov_b32_e32 v3, s15
-; GFX8-NEXT: v_mov_b32_e32 v4, s8
-; GFX8-NEXT: s_add_u32 s8, s16, 32
; GFX8-NEXT: v_mov_b32_e32 v5, s9
-; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NEXT: s_addc_u32 s9, s17, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v6, s10
; GFX8-NEXT: v_mov_b32_e32 v7, s11
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s4, s16, 16
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s5, s17, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s16
@@ -649,18 +649,19 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX7-NEXT: v_mov_b32_e32 v16, s18
; GFX7-NEXT: v_mov_b32_e32 v17, s19
; GFX7-NEXT: s_add_u32 s18, s16, 0x60
-; GFX7-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX7-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX7-NEXT: s_nop 0
; GFX7-NEXT: v_mov_b32_e32 v0, s18
; GFX7-NEXT: v_mov_b32_e32 v1, s19
; GFX7-NEXT: s_add_u32 s18, s16, 0x50
-; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX7-NEXT: v_mov_b32_e32 v0, s18
; GFX7-NEXT: v_mov_b32_e32 v1, s19
; GFX7-NEXT: s_add_u32 s18, s16, 64
-; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX7-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX7-NEXT: v_mov_b32_e32 v0, s18
; GFX7-NEXT: v_mov_b32_e32 v1, s19
; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
@@ -669,9 +670,9 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX7-NEXT: s_add_u32 s12, s16, 48
; GFX7-NEXT: v_mov_b32_e32 v1, s13
; GFX7-NEXT: s_addc_u32 s13, s17, 0
-; GFX7-NEXT: v_mov_b32_e32 v4, s12
; GFX7-NEXT: v_mov_b32_e32 v2, s14
; GFX7-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-NEXT: v_mov_b32_e32 v4, s12
; GFX7-NEXT: v_mov_b32_e32 v5, s13
; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-NEXT: s_nop 0
@@ -679,9 +680,9 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX7-NEXT: s_add_u32 s8, s16, 32
; GFX7-NEXT: v_mov_b32_e32 v1, s9
; GFX7-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-NEXT: v_mov_b32_e32 v4, s8
; GFX7-NEXT: v_mov_b32_e32 v2, s10
; GFX7-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-NEXT: v_mov_b32_e32 v4, s8
; GFX7-NEXT: v_mov_b32_e32 v5, s9
; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-NEXT: s_nop 0
@@ -689,9 +690,9 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX7-NEXT: s_add_u32 s4, s16, 16
; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: s_addc_u32 s5, s17, 0
-; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v2, s6
; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
; GFX7-NEXT: v_mov_b32_e32 v5, s5
; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-NEXT: v_mov_b32_e32 v4, s16
@@ -723,18 +724,18 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s25
; GFX8-NEXT: s_addc_u32 s25, s37, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NEXT: v_mov_b32_e32 v6, s26
; GFX8-NEXT: v_mov_b32_e32 v7, s27
+; GFX8-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NEXT: v_mov_b32_e32 v1, s25
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: v_mov_b32_e32 v0, s20
; GFX8-NEXT: s_add_u32 s20, s36, 0x50
; GFX8-NEXT: v_mov_b32_e32 v1, s21
; GFX8-NEXT: s_addc_u32 s21, s37, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NEXT: v_mov_b32_e32 v3, s23
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v5, s21
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -742,9 +743,9 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX8-NEXT: s_add_u32 s16, s36, 64
; GFX8-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NEXT: s_addc_u32 s17, s37, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NEXT: v_mov_b32_e32 v5, s17
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -752,9 +753,9 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX8-NEXT: s_add_u32 s12, s36, 48
; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: s_addc_u32 s13, s37, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NEXT: v_mov_b32_e32 v4, s12
; GFX8-NEXT: v_mov_b32_e32 v5, s13
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -762,9 +763,9 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX8-NEXT: s_add_u32 s8, s36, 32
; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: s_addc_u32 s9, s37, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NEXT: v_mov_b32_e32 v3, s11
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
; GFX8-NEXT: v_mov_b32_e32 v5, s9
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -772,9 +773,9 @@ define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrs
; GFX8-NEXT: s_add_u32 s4, s36, 16
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s5, s37, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v4, s36
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 14c1e04776561..4de1ba478d397 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -454,9 +454,9 @@ define amdgpu_kernel void @constant_load_v8i8(ptr addrspace(1) %out, ptr addrspa
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -535,10 +535,10 @@ define amdgpu_kernel void @constant_load_v16i8(ptr addrspace(1) %out, ptr addrsp
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
entry:
@@ -1551,9 +1551,9 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i32(ptr addrspace(1) %out
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -1583,9 +1583,9 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i32(ptr addrspace(1) %out
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
@@ -1710,9 +1710,9 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i32(ptr addrspace(1) %out
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -1742,9 +1742,9 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i32(ptr addrspace(1) %out
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
@@ -2160,24 +2160,25 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
@@ -2185,7 +2186,6 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
@@ -2218,24 +2218,25 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s7
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s6, s6
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s6, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s14
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s5
@@ -2243,7 +2244,6 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s11
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
@@ -2499,17 +2499,17 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s27
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s26
-; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s25
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s24
@@ -2517,14 +2517,14 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s34
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s23
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s22
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s22
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s21
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s8
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
@@ -2966,15 +2966,16 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_sext_i32_i8 s11, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s34
-; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX7-HSA-NEXT: s_sext_i32_i8 s10, s10
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GFX7-HSA-NEXT: s_sext_i32_i8 s8, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
; GFX7-HSA-NEXT: s_sext_i32_i8 s9, s9
@@ -2983,19 +2984,18 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s30
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: s_sext_i32_i8 s8, s8
+; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s29
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s27
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s27
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s26
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s25
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
@@ -3004,17 +3004,18 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s20
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s19
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
@@ -3022,7 +3023,6 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
@@ -3067,16 +3067,16 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 0x70
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s11, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 0x60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s11
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s34
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s10, s10
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s10, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 0x50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
@@ -3084,9 +3084,9 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s31
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s30
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s9, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s9, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s9
@@ -3094,9 +3094,9 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s27
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s8, s8
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s8, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
@@ -3104,9 +3104,9 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s25
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s24
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s7, s7
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s7, s7
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 32
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s7
@@ -3114,17 +3114,18 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s21
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s6, s6
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s6, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s20
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s18
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s5
@@ -3132,7 +3133,6 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
@@ -3606,12 +3606,12 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s50
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s68
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s57
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s56
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x70
; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
@@ -3637,28 +3637,28 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s61
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x50
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s45
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s62
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s44
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
-; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s59
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s43
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s60
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s58
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s41
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s42
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s39
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s38
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s35
; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s40
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s33
@@ -3671,13 +3671,13 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s4, s16, 64
; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX7-HSA-NEXT: s_add_u32 s4, s16, 48
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s26
@@ -3788,93 +3788,93 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s54
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s53
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xe0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s54
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s53
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xd0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s67
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s52
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s51
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xd0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xc0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s66
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s49
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xc0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xb0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s65
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s47
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xb0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xa0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s46
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s45
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xa0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x90
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s63
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s44
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s43
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x90
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x80
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s62
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s42
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s41
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x80
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x70
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s61
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s40
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s39
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x70
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s59
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s38
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s37
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x60
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s57
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s36
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s58
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s35
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x50
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s56
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s33
@@ -3887,13 +3887,13 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 64
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s55
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s29
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s28
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 48
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s34
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s26
@@ -4476,8 +4476,8 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0xa0
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s9
; GFX7-HSA-NEXT: s_sext_i32_i8 s13, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x90
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s13
@@ -4485,9 +4485,9 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s61
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s60
; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s12, s12
; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s9
-; GFX7-HSA-NEXT: s_sext_i32_i8 s12, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s8
; GFX7-HSA-NEXT: s_add_u32 s8, s16, 0x80
; GFX7-HSA-NEXT: s_sext_i32_i8 s15, s15
@@ -4503,23 +4503,23 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s67
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s66
; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[12:15]
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX7-HSA-NEXT: s_sext_i32_i8 s14, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s6
; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x70
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s11
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s56
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s55
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s54
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s7
; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
-; GFX7-HSA-NEXT: s_sext_i32_i8 s14, s14
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s7
; GFX7-HSA-NEXT: s_sext_i32_i8 s10, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s65
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s64
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s63
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s7
; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s6
; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x60
; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s10
@@ -4529,33 +4529,33 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s51
; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s50
+; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s50
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s49
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s48
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s47
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
-; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x50
-; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s40
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s37
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s46
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s44
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s43
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s40
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s42
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s41
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s39
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s38
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s37
; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s35
@@ -4567,15 +4567,15 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s4, s16, 64
; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 48
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s33
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s30
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX7-HSA-NEXT: s_add_u32 s4, s16, 48
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
@@ -4593,6 +4593,7 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s0, s0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s1
@@ -4600,7 +4601,6 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT: s_sext_i32_i8 s0, s0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
@@ -4669,107 +4669,107 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_bfe_i32 s66, s15, 0x80008
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s6
; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xf0
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s15, s15
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s15, s15
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s15
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s66
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xe0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s66
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s14, s14
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xd0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s65
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s63
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xd0
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s13, s13
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xc0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s62
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s61
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s60
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xc0
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s12, s12
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xb0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s59
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s58
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s57
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xb0
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s11, s11
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xa0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s11
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s56
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s55
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s54
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0xa0
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s10, s10
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x90
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s53
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s52
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s51
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x90
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s9, s9
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x80
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s49
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s48
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x80
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s8, s8
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x70
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s47
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s46
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s45
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x70
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s44
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s43
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s42
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s41
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x60
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x50
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s40
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s39
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s38
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s37
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x50
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s36
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s35
@@ -4781,15 +4781,15 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 64
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s33
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s31
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s30
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 48
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s29
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s28
@@ -4807,6 +4807,7 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s25
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s24
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s0, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s1
@@ -4814,7 +4815,6 @@ define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s21
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NOHSA-NEXT: s_sext_i32_i8 s0, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
@@ -5987,9 +5987,9 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(ptr addrspace(1) %out
; GFX7-HSA-NEXT: s_add_u32 s4, s0, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -6018,9 +6018,9 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(ptr addrspace(1) %out
; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
@@ -7085,24 +7085,25 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x60
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s11
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s26
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s10
+; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s26
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s27
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s10
-; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x50
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s11
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 64
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s34
@@ -7114,16 +7115,15 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[4:7]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[2:3], v[12:15]
-; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: s_add_u32 s10, s0, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s20
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s29
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
-; GFX7-HSA-NEXT: s_add_u32 s10, s0, 32
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
@@ -7136,9 +7136,9 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s6, s0, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -7193,30 +7193,30 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s36
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s30
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x60
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s30
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s25
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s23
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x50
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 64
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s26
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s27
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s29
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 64
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s34
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s35
@@ -7230,21 +7230,21 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s33
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s31
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 32
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s33
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s31
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s15
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s17
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
-; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 16
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
@@ -7596,20 +7596,20 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s13
; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0x50
; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s26
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s12
; GFX7-HSA-NEXT: s_add_u32 s12, s0, 48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s19
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s26
-; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s17
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s12
; GFX7-HSA-NEXT: s_add_u32 s12, s0, 16
; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
@@ -7619,33 +7619,33 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s15
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s12
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xe0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s21
; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
-; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xe0
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xc0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s27
-; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xc0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s33
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0xa0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s29
@@ -7655,8 +7655,8 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x80
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -7737,92 +7737,92 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0xb0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s13
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x70
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s11
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s17
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 48
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s17
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s9
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0xe0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s35
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0xd0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s35
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s20
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0xc0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s20
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s34
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s21
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0xa0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s21
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s33
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x90
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s33
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s23
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x80
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s23
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s31
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x60
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s24
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s30
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s25
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x50
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s25
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s26
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 64
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s26
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s29
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s27
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 32
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s29
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s27
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s28
@@ -8385,50 +8385,52 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s29
; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s29
+; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x80
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s67
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s54
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s55
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s29
-; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x80
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s62
; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s62
; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s63
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s69
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s68
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s28
; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s29
; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x70
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s61
; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s56
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s57
; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s65
; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s51
; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s61
; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s48
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s24
; GFX7-HSA-NEXT: s_add_u32 s24, s8, 0x60
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s49
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s46
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s37
; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s25
; GFX7-HSA-NEXT: s_addc_u32 s25, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX7-HSA-NEXT: s_add_u32 s20, s8, 0x50
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s45
; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s42
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s43
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s28
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s34
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GFX7-HSA-NEXT: s_add_u32 s20, s8, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX7-HSA-NEXT: s_addc_u32 s21, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s34
; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s30
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s31
@@ -8436,17 +8438,15 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s50
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s41
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s28
; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s29
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[8:11]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[12:15]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
-; GFX7-HSA-NEXT: s_addc_u32 s21, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s22
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s21
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -8455,12 +8455,12 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
; GFX7-HSA-NEXT: s_addc_u32 s15, s9, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s19
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
; GFX7-HSA-NEXT: s_add_u32 s14, s8, 48
-; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s19
; GFX7-HSA-NEXT: s_addc_u32 s15, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
@@ -8473,9 +8473,9 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s10, s8, 32
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -8483,9 +8483,9 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s5
; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
@@ -8572,21 +8572,21 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s47
; GFX8-NOHSA-NEXT: s_addc_u32 s47, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s46
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s65
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s47
; GFX8-NOHSA-NEXT: s_add_u32 s46, s8, 0xe0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s65
; GFX8-NOHSA-NEXT: s_addc_u32 s47, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s46
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s47
+; GFX8-NOHSA-NEXT: s_add_u32 s46, s8, 0xd0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s56
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s57
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s54
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s55
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s47
-; GFX8-NOHSA-NEXT: s_add_u32 s46, s8, 0xd0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s47, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s46
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s58
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s59
@@ -8600,21 +8600,21 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s45
; GFX8-NOHSA-NEXT: s_addc_u32 s45, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s44
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s62
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s63
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s45
; GFX8-NOHSA-NEXT: s_add_u32 s44, s8, 0xb0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s62
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s63
; GFX8-NOHSA-NEXT: s_addc_u32 s45, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s45
+; GFX8-NOHSA-NEXT: s_add_u32 s44, s8, 0xa0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s52
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s53
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s64
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NOHSA-NEXT: s_add_u32 s44, s8, 0xa0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s45, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s44
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s49
@@ -8627,9 +8627,9 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s40, s8, 0x90
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s41
; GFX8-NOHSA-NEXT: s_addc_u32 s41, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s40
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s42
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s43
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s40
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s41
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -8637,9 +8637,9 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s36, s8, 0x80
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s37
; GFX8-NOHSA-NEXT: s_addc_u32 s37, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s38
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s39
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s37
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -10497,10 +10497,10 @@ define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s2
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -10553,10 +10553,10 @@ define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s13
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
@@ -10870,9 +10870,9 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i16(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -10943,9 +10943,9 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i16(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-f32.ll b/llvm/test/CodeGen/AMDGPU/load-global-f32.ll
index 35f1f3b7bc16b..a6e484a29001f 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-f32.ll
@@ -260,10 +260,10 @@ define amdgpu_kernel void @global_load_v8f32(ptr addrspace(1) %out, ptr addrspac
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_add_u32 s4, s2, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -336,27 +336,27 @@ define amdgpu_kernel void @global_load_v9f32(ptr addrspace(1) %out, ptr addrspac
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_add_u32 s4, s2, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 32
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dword v14, v[6:7]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
@@ -426,27 +426,27 @@ define amdgpu_kernel void @global_load_v10f32(ptr addrspace(1) %out, ptr addrspa
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCN-HSA-NEXT: flat_load_dwordx2 v[8:9], v[8:9]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
@@ -517,27 +517,27 @@ define amdgpu_kernel void @global_load_v11f32(ptr addrspace(1) %out, ptr addrspa
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCN-HSA-NEXT: flat_load_dwordx3 v[8:10], v[8:9]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
; GCN-HSA-NEXT: flat_store_dwordx4 v[11:12], v[0:3]
@@ -607,27 +607,27 @@ define amdgpu_kernel void @global_load_v12f32(ptr addrspace(1) %out, ptr addrspa
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
@@ -702,16 +702,16 @@ define amdgpu_kernel void @global_load_v16f32(ptr addrspace(1) %out, ptr addrspa
; GCN-HSA-NEXT: s_add_u32 s4, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: s_add_u32 s6, s2, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: s_addc_u32 s7, s3, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCN-HSA-NEXT: s_add_u32 s2, s2, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s5
@@ -720,19 +720,19 @@ define amdgpu_kernel void @global_load_v16f32(ptr addrspace(1) %out, ptr addrspa
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_add_u32 s4, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s5
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s4
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
index f8c8be01f2d35..2be5f2b3c84b6 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
@@ -235,8 +235,8 @@ define amdgpu_kernel void @global_load_v3i16(ptr addrspace(1) %out, ptr addrspac
; GCN-HSA-NEXT: s_add_u32 s2, s0, 4
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: flat_store_short v[4:5], v1
@@ -705,8 +705,8 @@ define amdgpu_kernel void @global_load_v16i16_align2(ptr addrspace(1) %in, ptr a
; GCN-HSA-NEXT: s_add_u32 s0, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s1, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
@@ -1883,8 +1883,8 @@ define amdgpu_kernel void @global_zextload_v8i16_to_v8i32(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v3
@@ -2032,8 +2032,8 @@ define amdgpu_kernel void @global_sextload_v8i16_to_v8i32(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 16, v3
@@ -2194,8 +2194,8 @@ define amdgpu_kernel void @global_zextload_v16i16_to_v16i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s4, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -2204,14 +2204,14 @@ define amdgpu_kernel void @global_zextload_v16i16_to_v16i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v1
@@ -2427,8 +2427,8 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
@@ -2436,13 +2436,13 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s3
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s2
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
@@ -2691,16 +2691,16 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 48
-; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
@@ -2727,23 +2727,22 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s0, s0, 48
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v29, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v31, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v28, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v31, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v30, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v5
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v4
; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xffff, v5
; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xffff, v4
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19]
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v13
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v12
; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xffff, v13
; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xffff, v12
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[16:19]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v14
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v7
@@ -2753,6 +2752,7 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v15
; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xffff, v15
; GCN-HSA-NEXT: v_and_b32_e32 v4, 0xffff, v14
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s6
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
; GCN-HSA-NEXT: s_waitcnt vmcnt(4)
@@ -3076,24 +3076,24 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
-; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: s_add_u32 s4, s2, 48
+; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
+; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
-; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
@@ -3108,9 +3108,9 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v27, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
@@ -3123,13 +3123,13 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x50
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v29, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v18, 16, v15
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v16, 16, v14
; GCN-HSA-NEXT: v_bfe_i32 v17, v15, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v15, v14, 0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v29, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[15:18]
; GCN-HSA-NEXT: s_waitcnt vmcnt(4)
@@ -3142,8 +3142,6 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_bfe_i32 v17, v9, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v15, v8, 0, 16
; GCN-HSA-NEXT: s_add_u32 s0, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s3
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[15:18]
; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[11:14]
; GCN-HSA-NEXT: s_waitcnt vmcnt(5)
@@ -3155,16 +3153,18 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v12, 16, v4
; GCN-HSA-NEXT: v_bfe_i32 v13, v5, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v11, v4, 0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v31, s1
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[19:20], v[11:14]
; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[7:10]
-; GCN-HSA-NEXT: v_mov_b32_e32 v30, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v31, s1
; GCN-HSA-NEXT: s_waitcnt vmcnt(6)
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v10, 16, v1
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v8, 16, v0
; GCN-HSA-NEXT: v_bfe_i32 v9, v1, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v7, v0, 0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v30, s0
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v6, 16, v3
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 16, v2
; GCN-HSA-NEXT: v_bfe_i32 v5, v3, 0, 16
@@ -3576,10 +3576,10 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_addc_u32 s7, s3, 0
; GCN-HSA-NEXT: s_add_u32 s8, s2, 48
; GCN-HSA-NEXT: s_addc_u32 s9, s3, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s9
; GCN-HSA-NEXT: s_add_u32 s10, s2, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s8
; GCN-HSA-NEXT: s_addc_u32 s11, s3, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s8
; GCN-HSA-NEXT: flat_load_dwordx4 v[20:23], v[16:17]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
@@ -3591,8 +3591,8 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[4:5]
; GCN-HSA-NEXT: s_addc_u32 s11, s3, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: s_add_u32 s2, s2, 0x70
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -3600,8 +3600,8 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[28:31], v[12:13]
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s6
; GCN-HSA-NEXT: flat_load_dwordx4 v[16:19], v[12:13]
; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[14:15]
@@ -3619,9 +3619,9 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xe0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_add_u32 s4, s0, 0xf0
+; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[36:37], v[32:35]
; GCN-HSA-NEXT: v_mov_b32_e32 v37, s3
-; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v36, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
@@ -3645,21 +3645,21 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v0
; GCN-HSA-NEXT: v_and_b32_e32 v26, 0xffff, v1
; GCN-HSA-NEXT: v_and_b32_e32 v24, 0xffff, v0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: flat_store_dwordx4 v[32:33], v[24:27]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
; GCN-HSA-NEXT: s_waitcnt vmcnt(7)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v27, 16, v9
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v8
; GCN-HSA-NEXT: v_and_b32_e32 v26, 0xffff, v9
; GCN-HSA-NEXT: v_and_b32_e32 v24, 0xffff, v8
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s10
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v27, 16, v11
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v10
; GCN-HSA-NEXT: v_and_b32_e32 v26, 0xffff, v11
; GCN-HSA-NEXT: v_and_b32_e32 v24, 0xffff, v10
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s11
; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[24:27]
; GCN-HSA-NEXT: s_waitcnt vmcnt(8)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v5
@@ -3667,14 +3667,15 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xffff, v5
; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v33, s7
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x90
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v27, 16, v7
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v6
; GCN-HSA-NEXT: v_and_b32_e32 v26, 0xffff, v7
; GCN-HSA-NEXT: v_and_b32_e32 v24, 0xffff, v6
+; GCN-HSA-NEXT: v_mov_b32_e32 v33, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v32, s6
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
; GCN-HSA-NEXT: s_waitcnt vmcnt(8)
@@ -3682,9 +3683,9 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v10, 16, v29
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v8, 16, v28
; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v29
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x90
-; GCN-HSA-NEXT: flat_store_dwordx4 v[32:33], v[24:27]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[32:33], v[24:27]
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v27, 16, v31
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v30
; GCN-HSA-NEXT: v_and_b32_e32 v26, 0xffff, v31
@@ -3694,7 +3695,6 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v3
; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xffff, v2
@@ -3705,10 +3705,10 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v21
; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v21
; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v20
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -3740,18 +3740,19 @@ define amdgpu_kernel void @global_zextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v14
; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xffff, v14
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
; GCN-HSA-NEXT: s_add_u32 s0, s0, 48
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v19
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v19
+; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
@@ -4353,27 +4354,27 @@ define amdgpu_kernel void @global_sextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GCN-HSA-NEXT: flat_load_dwordx4 v[20:23], v[0:1]
; GCN-HSA-NEXT: s_add_u32 s4, s2, 0x60
+; GCN-HSA-NEXT: flat_load_dwordx4 v[20:23], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 0x50
-; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 64
-; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 48
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: s_add_u32 s6, s2, 32
; GCN-HSA-NEXT: s_addc_u32 s7, s3, 0
-; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
@@ -4435,13 +4436,14 @@ define amdgpu_kernel void @global_sextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xb0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v39, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v38, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
; GCN-HSA-NEXT: s_waitcnt vmcnt(9)
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v23, 16, v13
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v21, 16, v12
; GCN-HSA-NEXT: v_bfe_i32 v22, v13, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v20, v12, 0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v38, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v31, 16, v15
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v29, 16, v14
; GCN-HSA-NEXT: v_bfe_i32 v30, v15, 0, 16
@@ -4462,12 +4464,11 @@ define amdgpu_kernel void @global_sextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 16, v0
; GCN-HSA-NEXT: v_bfe_i32 v6, v1, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v4, v0, 0, 16
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x90
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
@@ -4517,20 +4518,20 @@ define amdgpu_kernel void @global_sextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 48
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v15, 16, v25
; GCN-HSA-NEXT: v_bfe_i32 v14, v25, 0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 48
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 16, v27
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 16, v26
; GCN-HSA-NEXT: v_bfe_i32 v6, v27, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v4, v26, 0, 16
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-HSA-NEXT: s_endpgm
@@ -5687,14 +5688,14 @@ define amdgpu_kernel void @global_zextload_v4i16_to_v4i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx2 v[8:9], v[0:1]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v5, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v7, v1
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 16, v9
@@ -5836,17 +5837,18 @@ define amdgpu_kernel void @global_sextload_v4i16_to_v4i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_bfe_i32 v4, v1, 0, 16
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GCN-HSA-NEXT: v_bfe_i32 v4, v1, 0, 16
+; GCN-HSA-NEXT: v_bfe_i32 v0, v0, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v1
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v6, 16, v1
-; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GCN-HSA-NEXT: v_bfe_i32 v0, v0, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GCN-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
@@ -5997,21 +5999,21 @@ define amdgpu_kernel void @global_zextload_v8i16_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v6, v4
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s1
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v8, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v10, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v12, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v14, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v16, v4
; GCN-HSA-NEXT: v_mov_b32_e32 v18, v4
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v3
@@ -6247,29 +6249,29 @@ define amdgpu_kernel void @global_sextload_v8i16_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_u32 s6, s0, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
; GCN-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s7
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s18
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s6
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s6
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s11
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s17
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s5
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s15
@@ -6527,21 +6529,17 @@ define amdgpu_kernel void @global_zextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s3
-; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xffff, v3
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
+; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xffff, v3
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[7:10]
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s0
; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x60
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v11, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v13, v8
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v16, 16, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xffff, v4
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s1
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xffff, v2
; GCN-HSA-NEXT: v_mov_b32_e32 v21, v8
@@ -6549,9 +6547,13 @@ define amdgpu_kernel void @global_zextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v17, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v7, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v9, v8
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v16, 16, v4
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v8, 16, v6
; GCN-HSA-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xffff, v4
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v22, 16, v0
; GCN-HSA-NEXT: v_and_b32_e32 v20, 0xffff, v0
@@ -6883,8 +6885,8 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
@@ -6980,19 +6982,19 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s5
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[22:25]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[22:25]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
@@ -7343,8 +7345,8 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GCN-HSA-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
+; GCN-HSA-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
@@ -7352,8 +7354,8 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s2, 48
-; GCN-HSA-NEXT: flat_load_dwordx4 v[10:13], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[10:13], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[14:17], v[0:1]
@@ -7371,8 +7373,8 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_addc_u32 s13, s1, 0
; GCN-HSA-NEXT: s_add_u32 s14, s0, 0x70
; GCN-HSA-NEXT: s_addc_u32 s15, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s14
; GCN-HSA-NEXT: s_add_u32 s14, s0, 0x50
; GCN-HSA-NEXT: v_mov_b32_e32 v19, v1
@@ -7412,9 +7414,9 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_waitcnt vmcnt(5)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v17
; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GCN-HSA-NEXT: s_add_u32 s4, s0, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[17:20]
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s9
-; GCN-HSA-NEXT: s_add_u32 s4, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s8
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v15
; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xffff, v15
@@ -7424,19 +7426,19 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s4
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v12
; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xffff, v12
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCN-HSA-NEXT: s_add_u32 s4, s0, 0xe0
; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[17:20]
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 16, v10
; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xffff, v10
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[11:12], v[17:20]
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, v1
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, v1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 16, v16
; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v16
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, v1
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s4
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[9:12]
; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xffff, v13
@@ -7444,47 +7446,47 @@ define amdgpu_kernel void @global_zextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xffff, v2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 16, v13
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v23, 16, v14
-; GCN-HSA-NEXT: v_and_b32_e32 v21, 0xffff, v14
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, v1
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xa0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[21:24]
+; GCN-HSA-NEXT: v_and_b32_e32 v21, 0xffff, v14
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, v1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[21:24]
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v20, 16, v8
; GCN-HSA-NEXT: v_and_b32_e32 v18, 0xffff, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v19, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v21, v1
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
-; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[18:21]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[18:21]
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v6
; GCN-HSA-NEXT: v_and_b32_e32 v15, 0xffff, v6
; GCN-HSA-NEXT: v_mov_b32_e32 v16, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v18, v1
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v4
; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[15:18]
; GCN-HSA-NEXT: v_mov_b32_e32 v6, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v8, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, v1
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GCN-HSA-NEXT: v_and_b32_e32 v5, 0xffff, v4
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[5:8]
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[9:12]
@@ -8081,21 +8083,21 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-HSA-NEXT: s_add_u32 s4, s2, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s4, s2, 48
-; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: flat_load_dwordx4 v[16:19], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[16:19], v[0:1]
+; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
-; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
+; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
@@ -8199,27 +8201,26 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v30, s41
; GCN-HSA-NEXT: s_add_u32 s40, s0, 0xb0
; GCN-HSA-NEXT: s_addc_u32 s41, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s38
; GCN-HSA-NEXT: s_add_u32 s38, s0, 0x90
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s39
; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v27, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s39
; GCN-HSA-NEXT: s_add_u32 s38, s0, 0x70
; GCN-HSA-NEXT: v_mov_b32_e32 v28, s47
-; GCN-HSA-NEXT: v_mov_b32_e32 v31, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s48
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s33
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s54
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s53
; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s42
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v31, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v32, s41
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s52
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
@@ -8236,6 +8237,7 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s45
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s62
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s61
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s39
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8243,9 +8245,9 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s36, s0, 0x50
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s37
; GCN-HSA-NEXT: s_addc_u32 s37, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s60
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s59
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s37
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8253,9 +8255,9 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s4, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -8297,14 +8299,14 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll
index 9b0218f5bcba4..1796824595b0d 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll
@@ -475,27 +475,27 @@ define amdgpu_kernel void @global_load_v9i32(ptr addrspace(1) %out, ptr addrspac
; GCNX3-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCNX3-HSA-NEXT: flat_load_dword v14, v[8:9]
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s0
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
@@ -606,27 +606,27 @@ define amdgpu_kernel void @global_load_v10i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCNX3-HSA-NEXT: flat_load_dwordx2 v[8:9], v[8:9]
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
@@ -736,27 +736,27 @@ define amdgpu_kernel void @global_load_v11i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCNX3-HSA-NEXT: flat_load_dwordx3 v[8:10], v[8:9]
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s0
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[11:12], v[0:3]
@@ -869,27 +869,27 @@ define amdgpu_kernel void @global_load_v12i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s0
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v15, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(2)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
@@ -1006,14 +1006,14 @@ define amdgpu_kernel void @global_load_v16i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s4
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 48
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 32
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -1024,14 +1024,14 @@ define amdgpu_kernel void @global_load_v16i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 48
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 16
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
@@ -1709,8 +1709,8 @@ define amdgpu_kernel void @global_zextload_v4i32_to_v4i64(ptr addrspace(1) %out,
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v7, v5
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0)
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v2
@@ -1837,8 +1837,8 @@ define amdgpu_kernel void @global_sextload_v4i32_to_v4i64(ptr addrspace(1) %out,
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(0)
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v3
@@ -1978,8 +1978,8 @@ define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(ptr addrspace(1) %out,
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
-; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -1989,11 +1989,11 @@ define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(ptr addrspace(1) %out,
; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 48
; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, v9
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v12, s0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s3
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s2
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(1)
@@ -2170,8 +2170,8 @@ define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(ptr addrspace(1) %out,
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 16
@@ -2179,13 +2179,13 @@ define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(ptr addrspace(1) %out,
; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 48
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 32
; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3
-; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2
+; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(1)
@@ -2398,24 +2398,24 @@ define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(ptr addrspace(1) %ou
; GCNX3-HSA: ; %bb.0:
; GCNX3-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCNX3-HSA-NEXT: s_add_i32 s12, s12, s17
-; GCNX3-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCNX3-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCNX3-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCNX3-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 48
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
@@ -2430,9 +2430,9 @@ define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v27, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 64
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s0
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3)
@@ -2445,13 +2445,13 @@ define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x50
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s2
-; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v19, 31, v11
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v10
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v10
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v11
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s3
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s2
+; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19]
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(4)
@@ -2464,8 +2464,6 @@ define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v14
; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v15
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s3
-; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[24:25], v[16:19]
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(5)
@@ -2477,16 +2475,18 @@ define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v14, v5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v6
; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v7
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v23, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v22, s2
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s1
+; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[12:15]
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[8:11]
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s1
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(6)
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v1
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, v0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v10, v1
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s0
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v2
@@ -2758,12 +2758,12 @@ define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 32
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 48
-; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -2784,43 +2784,43 @@ define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v27, s3
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 64
; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, v17
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s0
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(3)
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v1
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x50
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v3
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19]
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(4)
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v4
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v5
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[24:25], v[16:19]
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v6
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v7
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3
+; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(5)
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v8
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v9
-; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, v10
; GCNX3-HSA-NEXT: v_mov_b32_e32 v18, v11
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s2
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[2:3], v[16:19]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0
@@ -3137,28 +3137,28 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 0x50
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[20:23], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[20:23], v[0:1]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 64
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 48
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
+; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 32
; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[16:19], v[8:9]
-; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 32
; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[16:19], v[8:9]
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s7
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s7
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s6
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
@@ -3289,25 +3289,25 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32
+; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v14, 31, v1
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v12, 31, v0
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v11
; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, v11
; GCNX3-HSA-NEXT: v_mov_b32_e32 v11, v0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v13, v1
-; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48
-; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[11:14]
; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v22, 31, v3
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v20, 31, v2
; GCNX3-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v10
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, v10
+; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[11:14]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v19, v2
; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, v3
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[0:1], v[19:22]
@@ -3571,7 +3571,6 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCN-GFX900-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-GFX900-HSA-NEXT: v_mov_b32_e32 v12, 0
; GCN-GFX900-HSA-NEXT: s_add_u32 s20, s20, s17
-; GCN-GFX900-HSA-NEXT: s_addc_u32 s21, s21, 0
; GCN-GFX900-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[4:7], v12, s[2:3] offset:96
; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[8:11], v12, s[2:3] offset:112
@@ -3580,6 +3579,7 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[17:20], v12, s[2:3] offset:48
; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[21:24], v12, s[2:3] offset:32
; GCN-GFX900-HSA-NEXT: global_load_dwordx4 v[0:3], v12, s[2:3] offset:16
+; GCN-GFX900-HSA-NEXT: s_addc_u32 s21, s21, 0
; GCN-GFX900-HSA-NEXT: s_waitcnt vmcnt(6)
; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v32, 31, v7
; GCN-GFX900-HSA-NEXT: v_ashrrev_i32_e32 v30, 31, v6
@@ -3741,13 +3741,10 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v19, v24
; GCN-GFX908-HSA-NEXT: global_load_dwordx4 v[21:24], v12, s[2:3]
; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a0, v29
-; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a3, v32
; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a1, v30
; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a2, v31
-; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v12, v[37:40], s[0:1] offset:224
-; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v12, v[33:36], s[0:1] offset:240
+; GCN-GFX908-HSA-NEXT: v_accvgpr_write_b32 a3, v32
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v32, 31, v28
-; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v36, a3
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v30, 31, v27
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v44, 31, v26
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v42, 31, v25
@@ -3755,7 +3752,7 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v43, v26
; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v29, v27
; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v31, v28
-; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(3)
+; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v60, 31, v3
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v58, 31, v2
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v28, 31, v1
@@ -3764,10 +3761,13 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v27, v1
; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v57, v2
; GCN-GFX908-HSA-NEXT: v_mov_b32_e32 v59, v3
+; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v12, v[37:40], s[0:1] offset:224
+; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v12, v[33:36], s[0:1] offset:240
+; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v12, v[8:11], s[0:1] offset:192
+; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v36, a3
; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v35, a2
; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v34, a1
; GCN-GFX908-HSA-NEXT: v_accvgpr_read_b32 v33, a0
-; GCN-GFX908-HSA-NEXT: global_store_dwordx4 v12, v[8:11], s[0:1] offset:192
; GCN-GFX908-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v24
; GCN-GFX908-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v23
@@ -3896,15 +3896,15 @@ define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 16
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 32
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s8, s2, 48
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[28:31], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s9, s3, 0
; GCNX3-HSA-NEXT: s_add_u32 s10, s2, 64
; GCNX3-HSA-NEXT: s_addc_u32 s11, s3, 0
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCNX3-HSA-NEXT: s_add_u32 s12, s2, 0x50
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[28:31], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s13, s3, 0
; GCNX3-HSA-NEXT: s_add_u32 s14, s2, 0x60
; GCNX3-HSA-NEXT: s_addc_u32 s15, s3, 0
@@ -3926,8 +3926,8 @@ define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s9
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s7
; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s7
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s6
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
@@ -3985,24 +3985,23 @@ define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x90
-; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[30:31], v[0:3]
-; GCNX3-HSA-NEXT: s_nop 0
+; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v26
; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v27
; GCNX3-HSA-NEXT: v_mov_b32_e32 v27, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v26, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x60
-; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[32:33], v[0:3]
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s3
+; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(10)
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v20
; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v21
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[34:35], v[0:3]
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v31, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v22
; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v23
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v30, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[28:29], v[0:3]
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
@@ -4036,16 +4035,16 @@ define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(ptr addrspace(1) %ou
; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s2
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 32
+; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v10
; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v11
-; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GCNX3-HSA-NEXT: s_add_u32 s0, s0, 48
+; GCNX3-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v4
; GCNX3-HSA-NEXT: v_mov_b32_e32 v2, v5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCNX3-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, v6
@@ -4399,12 +4398,12 @@ define amdgpu_kernel void @global_load_v32i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCNX3-HSA-NEXT: s_add_u32 s6, s2, 48
; GCNX3-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s5
-; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCNX3-HSA-NEXT: s_addc_u32 s7, s3, 0
+; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v29, s5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v28, s4
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCNX3-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s4
@@ -4417,16 +4416,16 @@ define amdgpu_kernel void @global_load_v32i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: v_mov_b32_e32 v17, s5
; GCNX3-HSA-NEXT: v_mov_b32_e32 v16, s4
; GCNX3-HSA-NEXT: s_add_u32 s4, s2, 0x70
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCNX3-HSA-NEXT: s_addc_u32 s5, s3, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCNX3-HSA-NEXT: s_add_u32 s2, s2, 0x60
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
-; GCNX3-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCNX3-HSA-NEXT: v_mov_b32_e32 v21, s5
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v20, s4
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v25, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v24, s2
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[12:15], v[12:13]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[16:19], v[16:17]
@@ -4434,10 +4433,10 @@ define amdgpu_kernel void @global_load_v32i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[24:27], v[24:25]
; GCNX3-HSA-NEXT: flat_load_dwordx4 v[28:31], v[28:29]
; GCNX3-HSA-NEXT: s_add_u32 s2, s0, 0x60
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v33, s1
; GCNX3-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, s0
; GCNX3-HSA-NEXT: s_add_u32 s4, s0, 0x70
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v33, s1
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v32, s0
; GCNX3-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[32:33], v[0:3]
@@ -4464,11 +4463,11 @@ define amdgpu_kernel void @global_load_v32i32(ptr addrspace(1) %out, ptr addrspa
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[6:7], v[8:11]
; GCNX3-HSA-NEXT: v_mov_b32_e32 v6, s6
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v7, s7
-; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v3, s5
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCNX3-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCNX3-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCNX3-HSA-NEXT: v_mov_b32_e32 v8, s0
; GCNX3-HSA-NEXT: s_waitcnt vmcnt(7)
; GCNX3-HSA-NEXT: flat_store_dwordx4 v[6:7], v[12:15]
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
index f074770ad6e92..88b10f9327575 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
@@ -257,9 +257,9 @@ define amdgpu_kernel void @global_load_v3i8(ptr addrspace(1) %out, ptr addrspace
; GCN-HSA-NEXT: s_add_u32 s0, s0, 2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-HSA-NEXT: flat_store_short v[0:1], v2
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_byte v[0:1], v3
; GCN-HSA-NEXT: s_endpgm
@@ -1751,8 +1751,8 @@ define amdgpu_kernel void @global_zextload_v8i8_to_v8i32(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 24, v9
@@ -1903,8 +1903,8 @@ define amdgpu_kernel void @global_sextload_v8i8_to_v8i32(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 24, v7
@@ -2075,11 +2075,11 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
@@ -2087,19 +2087,19 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_u32 v8, v3, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff, v3
; GCN-HSA-NEXT: v_bfe_u32 v9, v3, 16, 8
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 24, v0
-; GCN-HSA-NEXT: v_bfe_u32 v4, v0, 8, 8
; GCN-HSA-NEXT: flat_store_dwordx4 v[11:12], v[7:10]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v14, 24, v2
+; GCN-HSA-NEXT: v_bfe_u32 v12, v2, 8, 8
+; GCN-HSA-NEXT: v_and_b32_e32 v11, 0xff, v2
+; GCN-HSA-NEXT: v_bfe_u32 v13, v2, 16, 8
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 24, v0
+; GCN-HSA-NEXT: v_bfe_u32 v4, v0, 8, 8
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v10, 24, v1
; GCN-HSA-NEXT: v_bfe_u32 v8, v1, 8, 8
-; GCN-HSA-NEXT: v_bfe_u32 v12, v2, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xff, v0
; GCN-HSA-NEXT: v_bfe_u32 v5, v0, 16, 8
; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff, v1
; GCN-HSA-NEXT: v_bfe_u32 v9, v1, 16, 8
-; GCN-HSA-NEXT: v_and_b32_e32 v11, 0xff, v2
-; GCN-HSA-NEXT: v_bfe_u32 v13, v2, 16, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[11:14]
@@ -2301,11 +2301,11 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
@@ -2313,19 +2313,19 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_i32 v10, v3, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v9, v3, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v8, v3, 0, 8
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GCN-HSA-NEXT: v_ashrrev_i32_e32 v15, 24, v2
+; GCN-HSA-NEXT: v_bfe_i32 v14, v2, 16, 8
+; GCN-HSA-NEXT: v_bfe_i32 v13, v2, 8, 8
+; GCN-HSA-NEXT: v_bfe_i32 v12, v2, 0, 8
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 24, v0
; GCN-HSA-NEXT: v_bfe_i32 v6, v0, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v5, v0, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v4, v0, 0, 8
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
-; GCN-HSA-NEXT: v_ashrrev_i32_e32 v15, 24, v2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 24, v1
; GCN-HSA-NEXT: v_bfe_i32 v10, v1, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v9, v1, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v8, v1, 0, 8
-; GCN-HSA-NEXT: v_bfe_i32 v14, v2, 16, 8
-; GCN-HSA-NEXT: v_bfe_i32 v13, v2, 8, 8
-; GCN-HSA-NEXT: v_bfe_i32 v12, v2, 0, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
@@ -2618,23 +2618,23 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 24, v3
; GCN-HSA-NEXT: v_bfe_u32 v5, v3, 8, 8
; GCN-HSA-NEXT: v_bfe_u32 v6, v3, 16, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 24, v0
-; GCN-HSA-NEXT: v_bfe_u32 v9, v0, 8, 8
; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v15, 24, v2
+; GCN-HSA-NEXT: v_bfe_u32 v13, v2, 8, 8
+; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xff, v2
+; GCN-HSA-NEXT: v_bfe_u32 v14, v2, 16, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
+; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 24, v0
+; GCN-HSA-NEXT: v_bfe_u32 v9, v0, 8, 8
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 24, v1
; GCN-HSA-NEXT: v_bfe_u32 v4, v1, 8, 8
-; GCN-HSA-NEXT: v_bfe_u32 v13, v2, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xff, v0
; GCN-HSA-NEXT: v_bfe_u32 v10, v0, 16, 8
; GCN-HSA-NEXT: v_and_b32_e32 v3, 0xff, v1
; GCN-HSA-NEXT: v_bfe_u32 v5, v1, 16, 8
-; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xff, v2
-; GCN-HSA-NEXT: v_bfe_u32 v14, v2, 16, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[3:6]
@@ -2980,8 +2980,8 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_i32 v8, v6, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v7, v6, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s3
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[6:9]
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x50
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v8, 24, v5
@@ -3001,23 +3001,23 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_i32 v10, v3, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v9, v3, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v8, v3, 0, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s3
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[8:11]
+; GCN-HSA-NEXT: v_ashrrev_i32_e32 v15, 24, v2
+; GCN-HSA-NEXT: v_bfe_i32 v14, v2, 16, 8
+; GCN-HSA-NEXT: v_bfe_i32 v13, v2, 8, 8
+; GCN-HSA-NEXT: v_bfe_i32 v12, v2, 0, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 24, v0
; GCN-HSA-NEXT: v_bfe_i32 v6, v0, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v5, v0, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v4, v0, 0, 8
-; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[8:11]
-; GCN-HSA-NEXT: v_ashrrev_i32_e32 v15, 24, v2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 24, v1
; GCN-HSA-NEXT: v_bfe_i32 v10, v1, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v9, v1, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v8, v1, 0, 8
-; GCN-HSA-NEXT: v_bfe_i32 v14, v2, 16, 8
-; GCN-HSA-NEXT: v_bfe_i32 v13, v2, 8, 8
-; GCN-HSA-NEXT: v_bfe_i32 v12, v2, 0, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[19:20], v[12:15]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
@@ -3482,43 +3482,43 @@ define amdgpu_kernel void @global_zextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_u32 v18, v14, 16, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xb0
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s4
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v19, 24, v15
; GCN-HSA-NEXT: v_bfe_u32 v17, v15, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v16, 0xff, v15
; GCN-HSA-NEXT: v_bfe_u32 v18, v15, 16, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s4
; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[16:19]
; GCN-HSA-NEXT: v_bfe_u32 v15, v12, 8, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 24, v12
; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xff, v12
; GCN-HSA-NEXT: v_bfe_u32 v16, v12, 16, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[14:17]
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s6
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 24, v13
; GCN-HSA-NEXT: v_bfe_u32 v15, v13, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xff, v13
; GCN-HSA-NEXT: v_bfe_u32 v16, v13, 16, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s7
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s8
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[14:17]
; GCN-HSA-NEXT: s_waitcnt vmcnt(6)
; GCN-HSA-NEXT: v_bfe_u32 v13, v10, 8, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s11
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v15, 24, v10
; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xff, v10
; GCN-HSA-NEXT: v_bfe_u32 v14, v10, 16, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s11
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s10
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s13
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xb0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v15, 24, v11
; GCN-HSA-NEXT: v_bfe_u32 v13, v11, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v12, 0xff, v11
; GCN-HSA-NEXT: v_bfe_u32 v14, v11, 16, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s12
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
@@ -3526,25 +3526,26 @@ define amdgpu_kernel void @global_zextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_u32 v11, v8, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xff, v8
; GCN-HSA-NEXT: v_bfe_u32 v12, v8, 16, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s15
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[10:13]
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s14
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v13, 24, v9
; GCN-HSA-NEXT: v_bfe_u32 v11, v9, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xff, v9
; GCN-HSA-NEXT: v_bfe_u32 v12, v9, 16, 8
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[10:13]
; GCN-HSA-NEXT: v_bfe_u32 v9, v3, 8, 8
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 24, v3
; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xff, v3
; GCN-HSA-NEXT: v_bfe_u32 v10, v3, 16, 8
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x90
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v20, 24, v1
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v11, 24, v0
@@ -3554,7 +3555,6 @@ define amdgpu_kernel void @global_zextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_u32 v18, v1, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v17, 0xff, v1
; GCN-HSA-NEXT: v_bfe_u32 v19, v1, 16, 8
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
@@ -3580,19 +3580,19 @@ define amdgpu_kernel void @global_zextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_u32 v19, v6, 16, 8
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[17:20]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 24, v7
; GCN-HSA-NEXT: v_bfe_u32 v1, v7, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v0, 0xff, v7
; GCN-HSA-NEXT: v_bfe_u32 v2, v7, 16, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x50
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x50
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[13:16]
@@ -4207,13 +4207,13 @@ define amdgpu_kernel void @global_sextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_i32 v16, v15, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v15, v15, 0, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s2
-; GCN-HSA-NEXT: flat_store_dwordx4 v[19:20], v[15:18]
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
+; GCN-HSA-NEXT: flat_store_dwordx4 v[19:20], v[15:18]
+; GCN-HSA-NEXT: v_bfe_i32 v14, v12, 0, 8
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 24, v12
; GCN-HSA-NEXT: v_bfe_i32 v16, v12, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v15, v12, 8, 8
-; GCN-HSA-NEXT: v_bfe_i32 v14, v12, 0, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[14:17]
@@ -4257,8 +4257,8 @@ define amdgpu_kernel void @global_sextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_i32 v12, v8, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v11, v8, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v10, v8, 0, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s3
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[10:13]
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v12, 24, v9
; GCN-HSA-NEXT: v_bfe_i32 v11, v9, 16, 8
@@ -4283,33 +4283,35 @@ define amdgpu_kernel void @global_sextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[7:10]
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x90
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 24, v4
; GCN-HSA-NEXT: v_bfe_i32 v8, v4, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v7, v4, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v6, v4, 0, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x90
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(10)
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v14, 24, v1
; GCN-HSA-NEXT: v_bfe_i32 v13, v1, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v12, v1, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v11, v1, 0, 8
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[6:9]
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 24, v0
; GCN-HSA-NEXT: v_bfe_i32 v8, v0, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v7, v0, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v6, v0, 0, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v18, 24, v5
; GCN-HSA-NEXT: v_bfe_i32 v17, v5, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v16, v5, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v15, v5, 0, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x70
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v18, 24, v3
; GCN-HSA-NEXT: v_bfe_i32 v17, v3, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v16, v3, 8, 8
@@ -4318,20 +4320,18 @@ define amdgpu_kernel void @global_sextload_v64i8_to_v64i32(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_bfe_i32 v4, v2, 16, 8
; GCN-HSA-NEXT: v_bfe_i32 v3, v2, 8, 8
; GCN-HSA-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x70
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x50
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x50
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[11:14]
@@ -5561,14 +5561,14 @@ define amdgpu_kernel void @global_zextload_v4i8_to_v4i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dword v0, v[0:1]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v5, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v7, v1
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_bfe_u32 v6, v0, 8, 8
@@ -5715,8 +5715,8 @@ define amdgpu_kernel void @global_sextload_v4i8_to_v4i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v0
@@ -5884,16 +5884,16 @@ define amdgpu_kernel void @global_zextload_v8i8_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v6, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v8, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v14, v1
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 24, v16
; GCN-HSA-NEXT: v_bfe_u32 v0, v16, 16, 8
@@ -5902,11 +5902,11 @@ define amdgpu_kernel void @global_zextload_v8i8_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
-; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s1
+; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 24, v15
; GCN-HSA-NEXT: v_bfe_u32 v3, v15, 16, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s0
; GCN-HSA-NEXT: v_bfe_u32 v9, v16, 8, 8
; GCN-HSA-NEXT: v_bfe_u32 v13, v15, 8, 8
@@ -6148,26 +6148,26 @@ define amdgpu_kernel void @global_sextload_v8i8_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s11
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s13
+; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
@@ -6440,19 +6440,20 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v16, 24, v1
; GCN-HSA-NEXT: v_bfe_u32 v14, v1, 16, 8
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[14:17]
; GCN-HSA-NEXT: v_mov_b32_e32 v9, v5
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v11, v5
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s4
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[14:17]
; GCN-HSA-NEXT: v_bfe_u32 v10, v2, 8, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s4
; GCN-HSA-NEXT: v_and_b32_e32 v8, 0xff, v2
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[8:11]
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 24, v2
; GCN-HSA-NEXT: v_bfe_u32 v4, v2, 16, 8
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v12, v5
; GCN-HSA-NEXT: v_mov_b32_e32 v14, v5
; GCN-HSA-NEXT: v_mov_b32_e32 v8, v5
@@ -6460,18 +6461,17 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v16, v5
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_bfe_u32 v13, v3, 8, 8
+; GCN-HSA-NEXT: v_and_b32_e32 v11, 0xff, v3
; GCN-HSA-NEXT: v_bfe_u32 v9, v0, 8, 8
; GCN-HSA-NEXT: v_bfe_u32 v17, v1, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v15, 0xff, v1
; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff, v0
-; GCN-HSA-NEXT: v_and_b32_e32 v11, 0xff, v3
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[19:20], v[11:14]
@@ -6871,11 +6871,11 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x50
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[2:5]
@@ -6893,27 +6893,27 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s22
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[12:15]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s11
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -7319,8 +7319,8 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_add_u32 s4, s0, 0x50
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s4
; GCN-HSA-NEXT: s_add_u32 s4, s0, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v11, v1
@@ -7392,14 +7392,14 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s4
; GCN-HSA-NEXT: v_bfe_u32 v12, v3, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xff, v3
-; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
; GCN-HSA-NEXT: s_add_u32 s4, s0, 0xe0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
; GCN-HSA-NEXT: v_bfe_u32 v12, v2, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v10, 0xff, v2
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[10:13]
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[10:13]
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
; GCN-HSA-NEXT: v_bfe_u32 v11, v9, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v9, 0xff, v9
@@ -7410,30 +7410,30 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v2, 24, v5
; GCN-HSA-NEXT: v_bfe_u32 v0, v5, 16, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, v1
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: v_bfe_u32 v16, v8, 8, 8
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xa0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: v_bfe_u32 v16, v8, 8, 8
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x80
; GCN-HSA-NEXT: v_and_b32_e32 v14, 0xff, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v15, v1
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x80
-; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[14:17]
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, v1
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, v1
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_bfe_u32 v9, v7, 8, 8
; GCN-HSA-NEXT: v_bfe_u32 v13, v6, 8, 8
; GCN-HSA-NEXT: v_and_b32_e32 v11, 0xff, v6
; GCN-HSA-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[14:17]
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, v1
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, v1
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[2:3], v[7:10]
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[11:14]
@@ -8154,53 +8154,54 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s36
; GCN-HSA-NEXT: s_add_u32 s36, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s59
-; GCN-HSA-NEXT: v_mov_b32_e32 v30, s42
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s37
; GCN-HSA-NEXT: s_addc_u32 s37, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s20
+; GCN-HSA-NEXT: s_add_u32 s20, s0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
+; GCN-HSA-NEXT: v_mov_b32_e32 v30, s42
; GCN-HSA-NEXT: v_mov_b32_e32 v31, s43
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s58
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s45
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s20
-; GCN-HSA-NEXT: s_add_u32 s20, s0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s21
; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[30:31], v[16:19]
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s20
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s21
; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xf0
; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s40
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s21
+; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xe0
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s36
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s37
+; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s21
-; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xe0
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s46
; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[20:23]
-; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s20
-; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s56
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s21
+; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xd0
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s57
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s54
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s55
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s48
; GCN-HSA-NEXT: v_mov_b32_e32 v27, s49
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s52
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s46
; GCN-HSA-NEXT: v_mov_b32_e32 v29, s47
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s28
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s21
+; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
-; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xd0
; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s30
@@ -8214,12 +8215,11 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[12:15]
-; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s20
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s20
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s21
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8227,9 +8227,9 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_add_u32 s16, s0, 0xc0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s17
; GCN-HSA-NEXT: s_addc_u32 s17, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s18
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8237,9 +8237,9 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_add_u32 s14, s0, 0xb0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s15
; GCN-HSA-NEXT: s_addc_u32 s15, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s44
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8247,9 +8247,9 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_add_u32 s10, s0, 0xa0
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s11
; GCN-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8257,10 +8257,10 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_add_u32 s6, s0, 0x90
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s7
; GCN-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: s_add_u32 s0, s0, 0x80
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -10537,11 +10537,11 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i16(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_and_b32 s2, s2, 0xff00ff
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s6
@@ -11028,11 +11028,11 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i16(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_or_b32 s2, s2, s17
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
@@ -11666,20 +11666,21 @@ define amdgpu_kernel void @global_zextload_v32i8_to_v32i16(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s8
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GCN-HSA-NEXT: s_endpgm
@@ -12567,21 +12568,21 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i16(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s6
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
diff --git a/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll b/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
index 3fedd68edaea2..e6bd487ac4eed 100644
--- a/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
@@ -21,16 +21,16 @@ define amdgpu_kernel void @select_ptr_crash_i64_flat(i32 %tmp, [8 x i32], ptr %p
; GCN-NEXT: s_cselect_b32 s2, s4, s5
; GCN-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: s_add_u32 s2, s2, 4
-; GCN-NEXT: flat_load_dword v0, v[0:1]
; GCN-NEXT: s_addc_u32 s3, s3, 0
+; GCN-NEXT: flat_load_dword v0, v[0:1]
; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: v_mov_b32_e32 v2, s3
; GCN-NEXT: flat_load_dword v1, v[1:2]
-; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mov_b32_e32 v2, s0
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -62,8 +62,8 @@ define amdgpu_kernel void @select_ptr_crash_i64_global(i32 %tmp, [8 x i32], ptr
; GCN-NEXT: s_cselect_b32 s3, s3, s6
; GCN-NEXT: s_cselect_b32 s2, s4, s5
; GCN-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
@@ -93,8 +93,8 @@ define amdgpu_kernel void @select_ptr_crash_i64_local(i32 %tmp, ptr addrspace(3)
; GCN-NEXT: s_cselect_b32 s0, s1, s2
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: ds_read_b64 v[0:1], v0
-; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_mov_b32_e32 v3, s5
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
@@ -125,8 +125,8 @@ define amdgpu_kernel void @select_ptr_crash_i64_local_offsets(i32 %tmp, ptr addr
; GCN-NEXT: s_cselect_b32 s0, s1, s2
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: ds_read_b64 v[0:1], v0
-; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_mov_b32_e32 v3, s5
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
index 88204849afee8..688d20309745c 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
@@ -516,9 +516,9 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) #1 {
; FLATSCR-NEXT: scratch_store_dword off, v2, s0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_mov_b32 s0, 0
-; FLATSCR-NEXT: s_mov_b32 s3, s0
; FLATSCR-NEXT: s_mov_b32 s1, s0
; FLATSCR-NEXT: s_mov_b32 s2, s0
+; FLATSCR-NEXT: s_mov_b32 s3, s0
; FLATSCR-NEXT: v_mov_b32_e32 v5, s3
; FLATSCR-NEXT: v_mov_b32_e32 v4, s2
; FLATSCR-NEXT: v_mov_b32_e32 v3, s1
@@ -566,11 +566,11 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) #1 {
; FLATSCR-NEXT: s_movk_i32 s0, 0x2000
; FLATSCR-NEXT: s_add_i32 s4, s33, s0
; FLATSCR-NEXT: s_mov_b32 s0, 0
-; FLATSCR-NEXT: s_mov_b32 s3, s0
; FLATSCR-NEXT: s_mov_b32 s1, s0
; FLATSCR-NEXT: s_mov_b32 s2, s0
-; FLATSCR-NEXT: v_mov_b32_e32 v5, s3
+; FLATSCR-NEXT: s_mov_b32 s3, s0
; FLATSCR-NEXT: s_addk_i32 s4, 0x3000
+; FLATSCR-NEXT: v_mov_b32_e32 v5, s3
; FLATSCR-NEXT: v_mov_b32_e32 v4, s2
; FLATSCR-NEXT: v_mov_b32_e32 v3, s1
; FLATSCR-NEXT: v_mov_b32_e32 v2, s0
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
index 09225709a1acf..11bade44eb909 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
@@ -81,13 +81,13 @@ define amdgpu_kernel void @caller() {
; GFX9-SDAG-NEXT: s_add_u32 s4, s4, callee at gotpcrel32@lo+4
; GFX9-SDAG-NEXT: s_addc_u32 s5, s5, callee at gotpcrel32@hi+12
; GFX9-SDAG-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x0
-; GFX9-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s12
; GFX9-SDAG-NEXT: s_mov_b32 s32, 0
@@ -111,13 +111,13 @@ define amdgpu_kernel void @caller() {
; GFX9-GISEL-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
; GFX9-GISEL-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x0
-; GFX9-GISEL-NEXT: s_mov_b64 s[10:11], s[6:7]
-; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX9-GISEL-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-GISEL-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s14
+; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], s[12:13]
; GFX9-GISEL-NEXT: s_mov_b32 s12, s14
@@ -140,13 +140,13 @@ define amdgpu_kernel void @caller() {
; GFX9ARCH-SDAG-NEXT: s_add_u32 s4, s4, callee at gotpcrel32@lo+4
; GFX9ARCH-SDAG-NEXT: s_addc_u32 s5, s5, callee at gotpcrel32@hi+12
; GFX9ARCH-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0
-; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9ARCH-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9ARCH-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9ARCH-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX9ARCH-SDAG-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9ARCH-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9
; GFX9ARCH-SDAG-NEXT: s_mov_b32 s32, 0
@@ -169,13 +169,13 @@ define amdgpu_kernel void @caller() {
; GFX9ARCH-GISEL-NEXT: s_add_u32 s0, s0, callee at gotpcrel32@lo+4
; GFX9ARCH-GISEL-NEXT: s_addc_u32 s1, s1, callee at gotpcrel32@hi+12
; GFX9ARCH-GISEL-NEXT: s_load_dwordx2 s[14:15], s[0:1], 0x0
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[10:11], s[6:7]
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9ARCH-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9ARCH-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9ARCH-GISEL-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9
+; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX9ARCH-GISEL-NEXT: s_mov_b64 s[4:5], s[12:13]
; GFX9ARCH-GISEL-NEXT: s_mov_b32 s32, 0
diff --git a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
index 4e24b02a9b15e..567f80f9f576b 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
@@ -1092,8 +1092,9 @@ define amdgpu_kernel void @mad_i64_i32_uniform(ptr addrspace(1) %out, i32 %arg0,
; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3
; GFX11-NEXT: s_add_u32 s2, s6, s4
; GFX11-NEXT: s_addc_u32 s3, s3, s5
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
;
@@ -1110,8 +1111,9 @@ define amdgpu_kernel void @mad_i64_i32_uniform(ptr addrspace(1) %out, i32 %arg0,
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: s_mul_u64 s[2:3], s[6:7], s[2:3]
; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll b/llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
index af713179a888d..607c3cbfce616 100644
--- a/llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
+++ b/llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
@@ -93,12 +93,12 @@ define amdgpu_kernel void @long_store_chain(ptr addrspace(1) %p) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-NEXT: s_mov_b32 s0, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_mov_b32 s1, s0
; GFX11-NEXT: s_mov_b32 s2, s0
; GFX11-NEXT: s_mov_b32 s3, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1f
@@ -176,12 +176,12 @@ define amdgpu_kernel void @long_store_chain(ptr addrspace(1) %p) {
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX12-NEXT: s_mov_b32 s0, 0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: s_mov_b32 s1, s0
; GFX12-NEXT: s_mov_b32 s2, s0
; GFX12-NEXT: s_mov_b32 s3, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_clause 0x1f
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll b/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
index dd826623c7d3f..69b9a1fa47d83 100644
--- a/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
+++ b/llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
@@ -185,9 +185,9 @@ define void @issue63986_reduced_expanded(i64 %idxprom) {
; CHECK-NEXT: s_cmp_lg_u32 s6, 1
; CHECK-NEXT: s_cbranch_scc1 .LBB1_8
; CHECK-NEXT: .LBB1_5: ; %loop-memcpy-residual.preheader
-; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_mov_b64 s[8:9], 0
; CHECK-NEXT: s_mov_b32 s7, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: .LBB1_6: ; %loop-memcpy-residual
; CHECK-NEXT: s_add_i32 s6, s8, 1
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll b/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
index 073f682f222e9..41d3ba9353cfc 100644
--- a/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
+++ b/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
@@ -99,7 +99,6 @@ define amdgpu_kernel void @memcpy_p5_p4_minsize(ptr addrspace(5) %local, ptr add
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v24, 0
-; CHECK-NEXT: s_add_u32 s20, s20, s17
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: global_load_dwordx4 v[0:3], v24, s[0:1] offset:112
; CHECK-NEXT: global_load_dwordx4 v[4:7], v24, s[0:1] offset:96
@@ -107,6 +106,7 @@ define amdgpu_kernel void @memcpy_p5_p4_minsize(ptr addrspace(5) %local, ptr add
; CHECK-NEXT: global_load_dwordx4 v[12:15], v24, s[0:1] offset:64
; CHECK-NEXT: global_load_dwordx4 v[16:19], v24, s[0:1] offset:48
; CHECK-NEXT: global_load_dwordx4 v[20:23], v24, s[0:1] offset:32
+; CHECK-NEXT: s_add_u32 s20, s20, s17
; CHECK-NEXT: s_addc_u32 s21, s21, 0
; CHECK-NEXT: v_mov_b32_e32 v25, s2
; CHECK-NEXT: s_waitcnt vmcnt(5)
@@ -387,7 +387,6 @@ define amdgpu_kernel void @memcpy_p5_p4_optsize(ptr addrspace(5) %local, ptr add
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; CHECK-NEXT: s_load_dword s2, s[8:9], 0x0
; CHECK-NEXT: v_mov_b32_e32 v24, 0
-; CHECK-NEXT: s_add_u32 s20, s20, s17
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: global_load_dwordx4 v[0:3], v24, s[0:1] offset:112
; CHECK-NEXT: global_load_dwordx4 v[4:7], v24, s[0:1] offset:96
@@ -395,6 +394,7 @@ define amdgpu_kernel void @memcpy_p5_p4_optsize(ptr addrspace(5) %local, ptr add
; CHECK-NEXT: global_load_dwordx4 v[12:15], v24, s[0:1] offset:64
; CHECK-NEXT: global_load_dwordx4 v[16:19], v24, s[0:1] offset:48
; CHECK-NEXT: global_load_dwordx4 v[20:23], v24, s[0:1] offset:32
+; CHECK-NEXT: s_add_u32 s20, s20, s17
; CHECK-NEXT: s_addc_u32 s21, s21, 0
; CHECK-NEXT: v_mov_b32_e32 v25, s2
; CHECK-NEXT: s_waitcnt vmcnt(5)
diff --git a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
index a64db94eae5be..e122859bd57e4 100644
--- a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+++ b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
@@ -6851,8 +6851,8 @@ define void @memmove_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0
; UNROLL3-NEXT: s_cbranch_execz .LBB5_4
; UNROLL3-NEXT: ; %bb.1: ; %memmove_fwd_loop.preheader
; UNROLL3-NEXT: v_mov_b32_e32 v5, v3
-; UNROLL3-NEXT: v_mov_b32_e32 v7, v1
; UNROLL3-NEXT: v_mov_b32_e32 v4, v2
+; UNROLL3-NEXT: v_mov_b32_e32 v7, v1
; UNROLL3-NEXT: v_mov_b32_e32 v6, v0
; UNROLL3-NEXT: s_mov_b64 s[4:5], 0x7e0
; UNROLL3-NEXT: .p2align 6
@@ -8367,8 +8367,8 @@ define void @memmove_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1
; UNROLL3-NEXT: s_cbranch_execz .LBB6_4
; UNROLL3-NEXT: ; %bb.1: ; %memmove_fwd_loop.preheader
; UNROLL3-NEXT: v_mov_b32_e32 v5, v3
-; UNROLL3-NEXT: v_mov_b32_e32 v7, v1
; UNROLL3-NEXT: v_mov_b32_e32 v4, v2
+; UNROLL3-NEXT: v_mov_b32_e32 v7, v1
; UNROLL3-NEXT: v_mov_b32_e32 v6, v0
; UNROLL3-NEXT: s_mov_b64 s[4:5], 0x7e0
; UNROLL3-NEXT: .p2align 6
@@ -9609,8 +9609,8 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; UNROLL3-NEXT: s_cbranch_execz .LBB7_4
; UNROLL3-NEXT: ; %bb.1: ; %memmove_fwd_loop.preheader
; UNROLL3-NEXT: v_mov_b32_e32 v5, v3
-; UNROLL3-NEXT: v_mov_b32_e32 v7, v1
; UNROLL3-NEXT: v_mov_b32_e32 v4, v2
+; UNROLL3-NEXT: v_mov_b32_e32 v7, v1
; UNROLL3-NEXT: v_mov_b32_e32 v6, v0
; UNROLL3-NEXT: s_mov_b64 s[4:5], 0x7e0
; UNROLL3-NEXT: .p2align 6
diff --git a/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll b/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
index 7786d47810b28..f1e6739d46a79 100644
--- a/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
@@ -32,10 +32,10 @@ define void @memmove_p0_p0(ptr addrspace(0) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: s_cbranch_execz .LBB0_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v5, v3
-; CHECK-NEXT: v_mov_b32_e32 v11, v1
-; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v4, v2
+; CHECK-NEXT: v_mov_b32_e32 v11, v1
; CHECK-NEXT: v_mov_b32_e32 v10, v0
+; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: s_mov_b32 s9, 0
; CHECK-NEXT: .p2align 6
@@ -129,8 +129,8 @@ define void @memmove_p0_p0(ptr addrspace(0) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB0_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_mov_b32_e32 v10, v8
+; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_add_co_u32 v4, vcc_lo, v2, v10
; CHECK-NEXT: v_add_co_ci_u32_e64 v5, null, v3, v11, vcc_lo
; CHECK-NEXT: v_add_co_u32 v8, vcc_lo, v10, -16
@@ -180,10 +180,10 @@ define void @memmove_p0_p1(ptr addrspace(0) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: s_cbranch_execz .LBB1_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v5, v3
-; CHECK-NEXT: v_mov_b32_e32 v11, v1
-; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v4, v2
+; CHECK-NEXT: v_mov_b32_e32 v11, v1
; CHECK-NEXT: v_mov_b32_e32 v10, v0
+; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: s_mov_b32 s9, 0
; CHECK-NEXT: .p2align 6
@@ -277,8 +277,8 @@ define void @memmove_p0_p1(ptr addrspace(0) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB1_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_mov_b32_e32 v10, v8
+; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_add_co_u32 v4, vcc_lo, v2, v10
; CHECK-NEXT: v_add_co_ci_u32_e64 v5, null, v3, v11, vcc_lo
; CHECK-NEXT: v_add_co_u32 v8, vcc_lo, v10, -16
@@ -330,8 +330,8 @@ define void @memmove_p0_p3(ptr addrspace(0) align 1 %dst, ptr addrspace(3) align
; CHECK-NEXT: s_cbranch_execz .LBB2_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v10, v1
-; CHECK-NEXT: v_mov_b32_e32 v12, v6
; CHECK-NEXT: v_mov_b32_e32 v9, v0
+; CHECK-NEXT: v_mov_b32_e32 v12, v6
; CHECK-NEXT: v_mov_b32_e32 v11, v5
; CHECK-NEXT: v_mov_b32_e32 v4, v2
; CHECK-NEXT: s_mov_b32 s9, 0
@@ -472,10 +472,10 @@ define void @memmove_p0_p4(ptr addrspace(0) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: s_cbranch_execz .LBB3_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v5, v3
-; CHECK-NEXT: v_mov_b32_e32 v11, v1
-; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v4, v2
+; CHECK-NEXT: v_mov_b32_e32 v11, v1
; CHECK-NEXT: v_mov_b32_e32 v10, v0
+; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: s_mov_b32 s9, 0
; CHECK-NEXT: .p2align 6
@@ -569,8 +569,8 @@ define void @memmove_p0_p4(ptr addrspace(0) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB3_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_mov_b32_e32 v10, v8
+; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_add_co_u32 v4, vcc_lo, v2, v10
; CHECK-NEXT: v_add_co_ci_u32_e64 v5, null, v3, v11, vcc_lo
; CHECK-NEXT: v_add_co_u32 v8, vcc_lo, v10, -16
@@ -622,8 +622,8 @@ define void @memmove_p0_p5(ptr addrspace(0) align 1 %dst, ptr addrspace(5) align
; CHECK-NEXT: s_cbranch_execz .LBB4_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v10, v1
-; CHECK-NEXT: v_mov_b32_e32 v12, v6
; CHECK-NEXT: v_mov_b32_e32 v9, v0
+; CHECK-NEXT: v_mov_b32_e32 v12, v6
; CHECK-NEXT: v_mov_b32_e32 v11, v5
; CHECK-NEXT: v_mov_b32_e32 v4, v2
; CHECK-NEXT: s_mov_b32 s9, 0
@@ -772,10 +772,10 @@ define void @memmove_p1_p0(ptr addrspace(1) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: s_cbranch_execz .LBB5_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v5, v3
-; CHECK-NEXT: v_mov_b32_e32 v11, v1
-; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v4, v2
+; CHECK-NEXT: v_mov_b32_e32 v11, v1
; CHECK-NEXT: v_mov_b32_e32 v10, v0
+; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: s_mov_b32 s9, 0
; CHECK-NEXT: .p2align 6
@@ -869,8 +869,8 @@ define void @memmove_p1_p0(ptr addrspace(1) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB5_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_mov_b32_e32 v10, v8
+; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_add_co_u32 v4, vcc_lo, v2, v10
; CHECK-NEXT: v_add_co_ci_u32_e64 v5, null, v3, v11, vcc_lo
; CHECK-NEXT: v_add_co_u32 v8, vcc_lo, v10, -16
@@ -918,10 +918,10 @@ define void @memmove_p1_p1(ptr addrspace(1) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: s_cbranch_execz .LBB6_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v5, v3
-; CHECK-NEXT: v_mov_b32_e32 v11, v1
-; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v4, v2
+; CHECK-NEXT: v_mov_b32_e32 v11, v1
; CHECK-NEXT: v_mov_b32_e32 v10, v0
+; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: s_mov_b32 s9, 0
; CHECK-NEXT: .p2align 6
@@ -1015,8 +1015,8 @@ define void @memmove_p1_p1(ptr addrspace(1) align 1 %dst, ptr addrspace(1) align
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB6_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_mov_b32_e32 v10, v8
+; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_add_co_u32 v4, vcc_lo, v2, v10
; CHECK-NEXT: v_add_co_ci_u32_e64 v5, null, v3, v11, vcc_lo
; CHECK-NEXT: v_add_co_u32 v8, vcc_lo, v10, -16
@@ -1127,10 +1127,10 @@ define void @memmove_p1_p4(ptr addrspace(1) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: s_cbranch_execz .LBB8_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v5, v3
-; CHECK-NEXT: v_mov_b32_e32 v11, v1
-; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v4, v2
+; CHECK-NEXT: v_mov_b32_e32 v11, v1
; CHECK-NEXT: v_mov_b32_e32 v10, v0
+; CHECK-NEXT: v_mov_b32_e32 v13, v9
; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: s_mov_b32 s9, 0
; CHECK-NEXT: .p2align 6
@@ -1224,8 +1224,8 @@ define void @memmove_p1_p4(ptr addrspace(1) align 1 %dst, ptr addrspace(4) align
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB8_15: ; %memmove_bwd_main_loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_mov_b32_e32 v10, v8
+; CHECK-NEXT: v_mov_b32_e32 v11, v9
; CHECK-NEXT: v_add_co_u32 v4, vcc_lo, v2, v10
; CHECK-NEXT: v_add_co_ci_u32_e64 v5, null, v3, v11, vcc_lo
; CHECK-NEXT: v_add_co_u32 v8, vcc_lo, v10, -16
@@ -1347,8 +1347,8 @@ define void @memmove_p3_p0(ptr addrspace(3) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: s_cbranch_execz .LBB10_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v10, v2
-; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: v_mov_b32_e32 v9, v1
+; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: v_mov_b32_e32 v11, v7
; CHECK-NEXT: v_mov_b32_e32 v4, v0
; CHECK-NEXT: s_mov_b32 s9, 0
@@ -1813,8 +1813,8 @@ define void @memmove_p5_p0(ptr addrspace(5) align 1 %dst, ptr addrspace(0) align
; CHECK-NEXT: s_cbranch_execz .LBB15_6
; CHECK-NEXT: ; %bb.4: ; %memmove_fwd_main_loop.preheader
; CHECK-NEXT: v_mov_b32_e32 v10, v2
-; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: v_mov_b32_e32 v9, v1
+; CHECK-NEXT: v_mov_b32_e32 v12, v8
; CHECK-NEXT: v_mov_b32_e32 v11, v7
; CHECK-NEXT: v_mov_b32_e32 v4, v0
; CHECK-NEXT: s_mov_b32 s8, 0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
index fcbbdb6afa146..0ad16159badf1 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
@@ -2590,7 +2590,7 @@ define amdgpu_kernel void @flat_wg_ld_acquire_single64(ptr addrspace(0) %p) #1 {
; GFX9-NEXT: liveins: $sgpr4_sgpr5
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: early-clobber renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM_ec killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64) from %ir.p.kernarg.offset, align 4, addrspace 4)
- ; GFX9-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ ; GFX9-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX9-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX9-NEXT: dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load syncscope("workgroup") acquire (s32) from %ir.p.load)
; GFX9-NEXT: S_ENDPGM 0
@@ -2609,7 +2609,7 @@ define amdgpu_kernel void @flat_wg_ld_acquire_single64(ptr addrspace(0) %p) #1 {
; GFX10-W32-NEXT: liveins: $sgpr4_sgpr5
; GFX10-W32-NEXT: {{ $}}
; GFX10-W32-NEXT: early-clobber renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM_ec killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64) from %ir.p.kernarg.offset, align 4, addrspace 4)
- ; GFX10-W32-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ ; GFX10-W32-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX10-W32-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX10-W32-NEXT: dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 1, implicit $exec, implicit $flat_scr :: (load syncscope("workgroup") acquire (s32) from %ir.p.load)
; GFX10-W32-NEXT: S_WAITCNT_soft .Vmcnt_0_Lgkmcnt_0
@@ -2621,7 +2621,7 @@ define amdgpu_kernel void @flat_wg_ld_acquire_single64(ptr addrspace(0) %p) #1 {
; GFX10-W64-NEXT: liveins: $sgpr4_sgpr5
; GFX10-W64-NEXT: {{ $}}
; GFX10-W64-NEXT: early-clobber renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM_ec killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64) from %ir.p.kernarg.offset, align 4, addrspace 4)
- ; GFX10-W64-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ ; GFX10-W64-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX10-W64-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX10-W64-NEXT: dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load syncscope("workgroup") acquire (s32) from %ir.p.load)
; GFX10-W64-NEXT: S_ENDPGM 0
@@ -2631,7 +2631,7 @@ define amdgpu_kernel void @flat_wg_ld_acquire_single64(ptr addrspace(0) %p) #1 {
; GFX12-W32-NEXT: liveins: $sgpr4_sgpr5
; GFX12-W32-NEXT: {{ $}}
; GFX12-W32-NEXT: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64) from %ir.p.kernarg.offset, align 4, addrspace 4)
- ; GFX12-W32-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 $sgpr0, killed $sgpr1, implicit $exec, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
+ ; GFX12-W32-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 $sgpr0, killed $sgpr1, implicit $exec, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX12-W32-NEXT: dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 8, implicit $exec, implicit $flat_scr :: (load syncscope("workgroup") acquire (s32) from %ir.p.load)
; GFX12-W32-NEXT: S_WAIT_LOADCNT_soft 0
; GFX12-W32-NEXT: S_WAIT_DSCNT_soft 0
@@ -2643,7 +2643,7 @@ define amdgpu_kernel void @flat_wg_ld_acquire_single64(ptr addrspace(0) %p) #1 {
; GFX12-W64-NEXT: liveins: $sgpr4_sgpr5
; GFX12-W64-NEXT: {{ $}}
; GFX12-W64-NEXT: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64) from %ir.p.kernarg.offset, align 4, addrspace 4)
- ; GFX12-W64-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ ; GFX12-W64-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX12-W64-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX12-W64-NEXT: dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load syncscope("workgroup") acquire (s32) from %ir.p.load)
; GFX12-W64-NEXT: S_ENDPGM 0
@@ -2670,7 +2670,7 @@ define amdgpu_kernel void @flat_wg_st_seq_cst_multi(ptr addrspace(0) %p, i32 %x)
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: early-clobber renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM_ec renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64) from %ir.p.kernarg.offset, align 4, addrspace 4)
; GFX9-NEXT: renamable $sgpr2 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 44, 0 :: (dereferenceable invariant load (s32) from %ir.x.kernarg.offset, addrspace 4)
- ; GFX9-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ ; GFX9-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX9-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX9-NEXT: $vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
; GFX9-NEXT: S_WAITCNT_soft .Lgkmcnt_0
@@ -2697,7 +2697,7 @@ define amdgpu_kernel void @flat_wg_st_seq_cst_multi(ptr addrspace(0) %p, i32 %x)
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: early-clobber renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM_ec renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64) from %ir.p.kernarg.offset, align 4, addrspace 4)
; GFX10-NEXT: renamable $sgpr2 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 44, 0 :: (dereferenceable invariant load (s32) from %ir.x.kernarg.offset, addrspace 4)
- ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ ; GFX10-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX10-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX10-NEXT: $vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
; GFX10-NEXT: S_WAITCNT_soft .Vmcnt_0_Lgkmcnt_0
@@ -2711,7 +2711,7 @@ define amdgpu_kernel void @flat_wg_st_seq_cst_multi(ptr addrspace(0) %p, i32 %x)
; GFX12-W32-NEXT: liveins: $sgpr4_sgpr5
; GFX12-W32-NEXT: {{ $}}
; GFX12-W32-NEXT: renamable $sgpr0_sgpr1_sgpr2 = S_LOAD_DWORDX3_IMM killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s96) from %ir.p.kernarg.offset, align 4, addrspace 4)
- ; GFX12-W32-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 $sgpr0, killed $sgpr1, implicit $exec, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
+ ; GFX12-W32-NEXT: $vgpr0, $vgpr1 = V_DUAL_MOV_B32_e32_X_MOV_B32_e32_gfx12 $sgpr0, killed $sgpr1, implicit $exec, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX12-W32-NEXT: $vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
; GFX12-W32-NEXT: S_WAIT_BVHCNT_soft 0
; GFX12-W32-NEXT: S_WAIT_SAMPLECNT_soft 0
@@ -2726,7 +2726,7 @@ define amdgpu_kernel void @flat_wg_st_seq_cst_multi(ptr addrspace(0) %p, i32 %x)
; GFX12-W64-NEXT: liveins: $sgpr4_sgpr5
; GFX12-W64-NEXT: {{ $}}
; GFX12-W64-NEXT: renamable $sgpr0_sgpr1_sgpr2 = S_LOAD_DWORDX3_IMM killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s96) from %ir.p.kernarg.offset, align 4, addrspace 4)
- ; GFX12-W64-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ ; GFX12-W64-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1
; GFX12-W64-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
; GFX12-W64-NEXT: $vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
; GFX12-W64-NEXT: S_WAIT_BVHCNT_soft 0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
index 9b9aa709a9c07..a718b6630846c 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
@@ -16,14 +16,14 @@ define amdgpu_kernel void @_Z6brokenPd(ptr %arg) {
; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: s_add_u32 s4, s4, 4
-; GCN-NEXT: flat_store_dword v[0:1], v2
+; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_addc_u32 s5, s5, 0
-; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: flat_store_dword v[0:1], v2
; GCN-NEXT: v_mov_b32_e32 v2, 0x7ff80000
+; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: flat_store_dword v[0:1], v2
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/memory_clause.ll b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
index 4d3920a9459dd..59feadb5ba01a 100644
--- a/llvm/test/CodeGen/AMDGPU/memory_clause.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
@@ -388,14 +388,14 @@ define amdgpu_kernel void @flat_scratch_load(float %a, float %b, <8 x i32> %desc
; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x44
; GCN-NEXT: s_addc_u32 s17, s17, 0
; GCN-NEXT: v_mov_b32_e32 v0, 0x40b00000
+; GCN-NEXT: s_brev_b32 s0, 1
; GCN-NEXT: buffer_store_dword v0, off, s[16:19], 0
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_brev_b32 s0, 1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: s_mov_b32 s3, 0
; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_mov_b32 s2, s0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: v_mov_b32_e32 v1, s7
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/memset-pattern.ll b/llvm/test/CodeGen/AMDGPU/memset-pattern.ll
index f2e7192df56ea..37bdd5c6535df 100644
--- a/llvm/test/CodeGen/AMDGPU/memset-pattern.ll
+++ b/llvm/test/CodeGen/AMDGPU/memset-pattern.ll
@@ -37,10 +37,10 @@ define void @memset_pattern_i128_len1(ptr addrspace(1) align 16 %a) {
; GFX942-GISEL-LABEL: memset_pattern_i128_len1:
; GFX942-GISEL: ; %bb.0: ; %memset.pattern-expansion-residual-body
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-GISEL-NEXT: s_mov_b32 s2, 0xbbbbbbbb
-; GFX942-GISEL-NEXT: s_mov_b32 s3, 0xaaaaaaaa
; GFX942-GISEL-NEXT: s_mov_b32 s0, 0xdddddddd
; GFX942-GISEL-NEXT: s_mov_b32 s1, 0xcccccccc
+; GFX942-GISEL-NEXT: s_mov_b32 s2, 0xbbbbbbbb
+; GFX942-GISEL-NEXT: s_mov_b32 s3, 0xaaaaaaaa
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX942-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
@@ -54,12 +54,12 @@ define void @memset_pattern_i128_constlen_mainloop_and_residual_taken(ptr addrsp
; GFX942-SDAG-LABEL: memset_pattern_i128_constlen_mainloop_and_residual_taken:
; GFX942-SDAG: ; %bb.0:
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-SDAG-NEXT: s_mov_b32 s5, 0xcccccccc
-; GFX942-SDAG-NEXT: s_mov_b32 s4, 0xdddddddd
; GFX942-SDAG-NEXT: s_mov_b32 s7, 0xaaaaaaaa
; GFX942-SDAG-NEXT: s_mov_b32 s6, 0xbbbbbbbb
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
+; GFX942-SDAG-NEXT: s_mov_b32 s5, 0xcccccccc
+; GFX942-SDAG-NEXT: s_mov_b32 s4, 0xdddddddd
; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
; GFX942-SDAG-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], v[0:1]
@@ -114,8 +114,8 @@ define void @memset_pattern_i128_constlen_mainloop_and_residual_taken(ptr addrsp
; GFX942-GISEL-NEXT: s_mov_b32 s5, 0xcccccccc
; GFX942-GISEL-NEXT: s_mov_b32 s6, 0xbbbbbbbb
; GFX942-GISEL-NEXT: s_mov_b32 s7, 0xaaaaaaaa
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[6:7]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], v[0:1]
; GFX942-GISEL-NEXT: .LBB3_1: ; %memset.pattern-expansion-main-body
@@ -150,11 +150,11 @@ define void @memset_pattern_i128_constlen_mainloop_and_residual_taken(ptr addrsp
; GFX942-GISEL-NEXT: v_add_co_u32_e32 v4, vcc, 0x100, v0
; GFX942-GISEL-NEXT: s_mov_b32 s4, 0xdddddddd
; GFX942-GISEL-NEXT: s_mov_b32 s5, 0xcccccccc
-; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
; GFX942-GISEL-NEXT: s_mov_b32 s6, 0xbbbbbbbb
; GFX942-GISEL-NEXT: s_mov_b32 s7, 0xaaaaaaaa
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
; GFX942-GISEL-NEXT: s_mov_b32 s0, 1
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
; GFX942-GISEL-NEXT: s_mov_b32 s1, 0
; GFX942-GISEL-NEXT: .LBB3_3: ; %memset.pattern-expansion-residual-body
@@ -190,10 +190,10 @@ define void @memset_pattern_i128_len1_lds(ptr addrspace(3) align 16 %a) {
; GFX942-GISEL-LABEL: memset_pattern_i128_len1_lds:
; GFX942-GISEL: ; %bb.0: ; %memset.pattern-expansion-residual-body
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-GISEL-NEXT: s_mov_b32 s2, 0xbbbbbbbb
-; GFX942-GISEL-NEXT: s_mov_b32 s3, 0xaaaaaaaa
; GFX942-GISEL-NEXT: s_mov_b32 s0, 0xdddddddd
; GFX942-GISEL-NEXT: s_mov_b32 s1, 0xcccccccc
+; GFX942-GISEL-NEXT: s_mov_b32 s2, 0xbbbbbbbb
+; GFX942-GISEL-NEXT: s_mov_b32 s3, 0xaaaaaaaa
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX942-GISEL-NEXT: ds_write_b128 v0, v[2:5]
@@ -218,10 +218,10 @@ define void @memset_pattern_i128_len1_no_align(ptr addrspace(1) %a) {
; GFX942-GISEL-LABEL: memset_pattern_i128_len1_no_align:
; GFX942-GISEL: ; %bb.0: ; %memset.pattern-expansion-residual-body
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-GISEL-NEXT: s_mov_b32 s2, 0xbbbbbbbb
-; GFX942-GISEL-NEXT: s_mov_b32 s3, 0xaaaaaaaa
; GFX942-GISEL-NEXT: s_mov_b32 s0, 0xdddddddd
; GFX942-GISEL-NEXT: s_mov_b32 s1, 0xcccccccc
+; GFX942-GISEL-NEXT: s_mov_b32 s2, 0xbbbbbbbb
+; GFX942-GISEL-NEXT: s_mov_b32 s3, 0xaaaaaaaa
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX942-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
@@ -235,12 +235,12 @@ define void @memset_pattern_i128_len16(ptr addrspace(1) align 16 %a) {
; GFX942-SDAG-LABEL: memset_pattern_i128_len16:
; GFX942-SDAG: ; %bb.0:
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-SDAG-NEXT: s_mov_b32 s5, 0xcccccccc
-; GFX942-SDAG-NEXT: s_mov_b32 s4, 0xdddddddd
; GFX942-SDAG-NEXT: s_mov_b32 s7, 0xaaaaaaaa
; GFX942-SDAG-NEXT: s_mov_b32 s6, 0xbbbbbbbb
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX942-SDAG-NEXT: s_mov_b32 s5, 0xcccccccc
+; GFX942-SDAG-NEXT: s_mov_b32 s4, 0xdddddddd
; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX942-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[6:7]
; GFX942-SDAG-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX942-SDAG-NEXT: .LBB6_1: ; %memset.pattern-expansion-main-body
@@ -278,8 +278,8 @@ define void @memset_pattern_i128_len16(ptr addrspace(1) align 16 %a) {
; GFX942-GISEL-NEXT: s_mov_b32 s5, 0xcccccccc
; GFX942-GISEL-NEXT: s_mov_b32 s6, 0xbbbbbbbb
; GFX942-GISEL-NEXT: s_mov_b32 s7, 0xaaaaaaaa
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[6:7]
; GFX942-GISEL-NEXT: .LBB6_1: ; %memset.pattern-expansion-main-body
; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -814,8 +814,8 @@ define void @memset_pattern_i64_as7_dynlen(ptr addrspace(7) inreg align 16 %a, i
; GFX942-GISEL-NEXT: s_mov_b32 s8, 0xccccdddd
; GFX942-GISEL-NEXT: s_mov_b32 s9, 0xaaaabbbb
; GFX942-GISEL-NEXT: s_mov_b64 s[10:11], s[8:9]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[8:9]
; GFX942-GISEL-NEXT: v_add_u32_e32 v1, s16, v0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[8:9]
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[10:11]
; GFX942-GISEL-NEXT: s_mov_b64 s[8:9], 0
; GFX942-GISEL-NEXT: .LBB12_2: ; %memset.pattern-expansion-main-body
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll b/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
index 263298d1cd1c8..2d4888c465594 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
@@ -628,14 +628,14 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_call(ptr addrspace(1) %arg)
; GFX908-NEXT: s_add_u32 s4, s4, foo at gotpcrel32@lo+4
; GFX908-NEXT: s_addc_u32 s5, s5, foo at gotpcrel32@hi+12
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX908-NEXT: s_mov_b32 s14, s10
-; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: s_mov_b32 s14, s10
+; GFX908-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[36:37]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX908-NEXT: s_mov_b32 s32, 0
; GFX908-NEXT: v_mov_b32_e32 v40, 0
@@ -899,10 +899,10 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_call_multi_bb(ptr addrspace(
; GFX908-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GFX908-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX908-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX908-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_mov_b64 s[0:1], s[52:53]
-; GFX908-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX908-NEXT: s_mov_b64 s[2:3], s[54:55]
; GFX908-NEXT: ; implicit-def: $sgpr15
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
index 059527cea7c01..795de7ccb8932 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
@@ -55,12 +55,12 @@ define amdgpu_kernel void @test_mfma_loop_zeroinit(ptr addrspace(1) %arg) #0 {
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -286,12 +286,12 @@ define amdgpu_kernel void @test_mfma_loop_unfoldable_splat(ptr addrspace(1) %arg
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -511,12 +511,12 @@ define amdgpu_kernel void @test_mfma_loop_non_splat(ptr addrspace(1) %arg) #0 {
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -773,12 +773,12 @@ define amdgpu_kernel void @test_mfma_loop_unfoldable_seq(ptr addrspace(1) %arg)
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -998,12 +998,12 @@ define amdgpu_kernel void @test_mfma_loop_vgpr_init(ptr addrspace(1) %arg) #0 {
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -1262,12 +1262,12 @@ define amdgpu_kernel void @test_mfma_loop_sgpr_init(ptr addrspace(1) %arg, float
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -1527,12 +1527,12 @@ define amdgpu_kernel void @test_mfma_loop_mixed_init(ptr addrspace(1) %arg, floa
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -1762,12 +1762,12 @@ define amdgpu_kernel void @test_mfma_loop_mfma_forward_init(ptr addrspace(1) %ar
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -1967,12 +1967,12 @@ define amdgpu_kernel void @test_mfma_loop_agpr_init(ptr addrspace(1) %arg) #0 {
; GFX908-NEXT: ; %bb.2: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 13
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
@@ -2246,12 +2246,12 @@ define amdgpu_kernel void @test_mfma_nested_loop_zeroinit(ptr addrspace(1) %arg)
; GFX908-NEXT: ; %bb.4: ; %exit
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX908-NEXT: s_nop 10
-; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v28, a28
; GFX908-NEXT: v_accvgpr_read_b32 v29, a29
; GFX908-NEXT: v_accvgpr_read_b32 v30, a30
; GFX908-NEXT: v_accvgpr_read_b32 v31, a31
; GFX908-NEXT: v_mov_b32_e32 v32, 0
+; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index 7e241bf2dbdb6..e24b465ff99ff 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -357,11 +357,11 @@ define amdgpu_kernel void @s_test_imin_sle_v4i32(ptr addrspace(1) %out, <4 x i32
; CI-NEXT: s_min_i32 s2, s2, s6
; CI-NEXT: s_min_i32 s1, s1, s5
; CI-NEXT: s_min_i32 s0, s0, s4
-; CI-NEXT: v_mov_b32_e32 v4, s8
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
+; CI-NEXT: v_mov_b32_e32 v4, s8
; CI-NEXT: v_mov_b32_e32 v5, s9
; CI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; CI-NEXT: s_endpgm
@@ -378,11 +378,11 @@ define amdgpu_kernel void @s_test_imin_sle_v4i32(ptr addrspace(1) %out, <4 x i32
; VI-NEXT: s_min_i32 s2, s2, s6
; VI-NEXT: s_min_i32 s1, s1, s5
; VI-NEXT: s_min_i32 s0, s0, s4
-; VI-NEXT: v_mov_b32_e32 v4, s8
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
+; VI-NEXT: v_mov_b32_e32 v4, s8
; VI-NEXT: v_mov_b32_e32 v5, s9
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -506,8 +506,8 @@ define amdgpu_kernel void @s_test_imin_sle_i8(ptr addrspace(1) %out, [8 x i32],
; CI-NEXT: s_sext_i32_i8 s2, s2
; CI-NEXT: s_sext_i32_i8 s3, s3
; CI-NEXT: s_min_i32 s2, s2, s3
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: flat_store_byte v[0:1], v2
@@ -524,8 +524,8 @@ define amdgpu_kernel void @s_test_imin_sle_i8(ptr addrspace(1) %out, [8 x i32],
; VI-NEXT: s_sext_i32_i8 s2, s2
; VI-NEXT: s_sext_i32_i8 s3, s3
; VI-NEXT: s_min_i32 s2, s3, s2
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_byte v[0:1], v2
@@ -682,8 +682,8 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
; CI-NEXT: s_or_b32 s3, s4, s3
; CI-NEXT: s_and_b32 s3, s3, 0xffff
; CI-NEXT: s_or_b32 s2, s3, s2
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: flat_store_dword v[0:1], v2
@@ -720,8 +720,8 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
; VI-NEXT: s_lshl_b32 s4, s4, 16
; VI-NEXT: s_and_b32 s2, s2, 0xffff
; VI-NEXT: s_or_b32 s2, s2, s4
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
@@ -1098,9 +1098,9 @@ define amdgpu_kernel void @s_test_imin_sle_v4i16(ptr addrspace(1) %out, <4 x i16
; CI-NEXT: s_and_b32 s0, s0, 0xffff
; CI-NEXT: s_or_b32 s1, s1, s7
; CI-NEXT: s_or_b32 s0, s0, s3
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -1131,9 +1131,9 @@ define amdgpu_kernel void @s_test_imin_sle_v4i16(ptr addrspace(1) %out, <4 x i16
; VI-NEXT: s_lshl_b32 s3, s3, 16
; VI-NEXT: s_and_b32 s0, s0, 0xffff
; VI-NEXT: s_or_b32 s0, s0, s3
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -1644,9 +1644,9 @@ define amdgpu_kernel void @s_test_imin_slt_v2i32(ptr addrspace(1) %out, <2 x i32
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_min_i32 s1, s1, s3
; CI-NEXT: s_min_i32 s0, s0, s2
-; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
+; CI-NEXT: v_mov_b32_e32 v2, s4
; CI-NEXT: v_mov_b32_e32 v3, s5
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -1661,9 +1661,9 @@ define amdgpu_kernel void @s_test_imin_slt_v2i32(ptr addrspace(1) %out, <2 x i32
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_min_i32 s1, s1, s3
; VI-NEXT: s_min_i32 s0, s0, s2
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -3418,9 +3418,9 @@ define amdgpu_kernel void @s_test_umin_ult_v8i32(ptr addrspace(1) %out, <8 x i32
; CI-NEXT: s_add_u32 s2, s0, 16
; CI-NEXT: v_mov_b32_e32 v2, s3
; CI-NEXT: s_addc_u32 s3, s1, 0
-; CI-NEXT: v_mov_b32_e32 v5, s3
; CI-NEXT: v_mov_b32_e32 v0, s9
; CI-NEXT: v_mov_b32_e32 v1, s8
+; CI-NEXT: v_mov_b32_e32 v5, s3
; CI-NEXT: v_mov_b32_e32 v4, s2
; CI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; CI-NEXT: v_mov_b32_e32 v5, s1
@@ -3452,9 +3452,9 @@ define amdgpu_kernel void @s_test_umin_ult_v8i32(ptr addrspace(1) %out, <8 x i32
; VI-NEXT: s_add_u32 s2, s0, 16
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: s_addc_u32 s3, s1, 0
-; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v0, s9
; VI-NEXT: v_mov_b32_e32 v1, s8
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_mov_b32_e32 v5, s1
@@ -3762,11 +3762,11 @@ define amdgpu_kernel void @s_test_umin_ult_v8i16(ptr addrspace(1) %out, <8 x i16
; CI-NEXT: s_or_b32 s2, s2, s6
; CI-NEXT: s_or_b32 s1, s1, s5
; CI-NEXT: s_or_b32 s0, s0, s4
-; CI-NEXT: v_mov_b32_e32 v4, s8
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
+; CI-NEXT: v_mov_b32_e32 v4, s8
; CI-NEXT: v_mov_b32_e32 v5, s9
; CI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; CI-NEXT: s_endpgm
@@ -3811,11 +3811,11 @@ define amdgpu_kernel void @s_test_umin_ult_v8i16(ptr addrspace(1) %out, <8 x i16
; VI-NEXT: s_min_u32 s1, s5, s1
; VI-NEXT: s_lshl_b32 s0, s0, 16
; VI-NEXT: s_or_b32 s1, s1, s0
-; VI-NEXT: v_mov_b32_e32 v4, s8
; VI-NEXT: v_mov_b32_e32 v0, s1
; VI-NEXT: v_mov_b32_e32 v1, s2
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: v_mov_b32_e32 v3, s10
+; VI-NEXT: v_mov_b32_e32 v4, s8
; VI-NEXT: v_mov_b32_e32 v5, s9
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
@@ -3920,8 +3920,8 @@ define amdgpu_kernel void @simplify_demanded_bits_test_umin_ult_i16(ptr addrspac
; CI-NEXT: s_and_b32 s2, s2, 0xffff
; CI-NEXT: s_and_b32 s3, s3, 0xffff
; CI-NEXT: s_min_u32 s2, s2, s3
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: flat_store_dword v[0:1], v2
@@ -3938,8 +3938,8 @@ define amdgpu_kernel void @simplify_demanded_bits_test_umin_ult_i16(ptr addrspac
; VI-NEXT: s_and_b32 s2, s2, 0xffff
; VI-NEXT: s_and_b32 s3, s3, 0xffff
; VI-NEXT: s_min_u32 s2, s2, s3
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
@@ -4050,8 +4050,8 @@ define amdgpu_kernel void @simplify_demanded_bits_test_min_slt_i16(ptr addrspace
; CI-NEXT: s_sext_i32_i16 s2, s2
; CI-NEXT: s_sext_i32_i16 s3, s3
; CI-NEXT: s_min_i32 s2, s2, s3
-; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: flat_store_dword v[0:1], v2
@@ -4068,8 +4068,8 @@ define amdgpu_kernel void @simplify_demanded_bits_test_min_slt_i16(ptr addrspace
; VI-NEXT: s_sext_i32_i16 s2, s2
; VI-NEXT: s_sext_i32_i16 s3, s3
; VI-NEXT: s_min_i32 s2, s2, s3
-; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index 05ff5c8bb0b3a..8adfed45e2514 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -91,15 +91,15 @@ define amdgpu_kernel void @withcall() {
; GFX9-NEXT: s_add_u32 s4, s4, nonkernel at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, nonkernel at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX9-NEXT: s_mov_b32 s14, s10
-; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GFX9-NEXT: s_mov_b32 s14, s10
+; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-NEXT: s_mov_b64 s[0:1], s[20:21]
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b64 s[2:3], s[22:23]
; GFX9-NEXT: s_mov_b32 s32, 0
; GFX9-NEXT: ds_write_b32 v3, v3 offset:8
@@ -156,15 +156,15 @@ define amdgpu_kernel void @withcall() {
; G_GFX9-NEXT: s_add_u32 s0, s0, nonkernel at gotpcrel32@lo+4
; G_GFX9-NEXT: s_addc_u32 s1, s1, nonkernel at gotpcrel32@hi+12
; G_GFX9-NEXT: s_load_dwordx2 s[18:19], s[0:1], 0x0
+; G_GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; G_GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; G_GFX9-NEXT: s_mov_b32 s14, s10
; G_GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]
; G_GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]
-; G_GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; G_GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; G_GFX9-NEXT: s_mov_b64 s[0:1], s[20:21]
; G_GFX9-NEXT: v_mov_b32_e32 v3, 0
; G_GFX9-NEXT: v_mov_b32_e32 v4, 8
; G_GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
+; G_GFX9-NEXT: s_mov_b64 s[0:1], s[20:21]
; G_GFX9-NEXT: s_mov_b64 s[2:3], s[22:23]
; G_GFX9-NEXT: s_mov_b64 s[4:5], s[12:13]
; G_GFX9-NEXT: s_mov_b32 s12, s16
diff --git a/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll b/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
index aff07787a2fb7..79414e52eed9c 100644
--- a/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
@@ -10,9 +10,9 @@ define protected amdgpu_kernel void @no_folding_imm_to_inst_with_fi(<4 x i64> %v
; CHECK-NEXT: s_load_b512 s[0:15], s[4:5], 0xa4
; CHECK-NEXT: s_mov_b64 s[34:35], src_private_base
; CHECK-NEXT: s_movk_i32 s34, 0x80
-; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-NEXT: v_dual_mov_b32 v27, s35 :: v_dual_mov_b32 v26, s34
; CHECK-NEXT: s_add_nc_u64 s[44:45], s[34:35], 0x70
-; CHECK-NEXT: v_dual_mov_b32 v26, s34 :: v_dual_mov_b32 v27, s35
; CHECK-NEXT: v_dual_mov_b32 v20, s44 :: v_dual_mov_b32 v21, s45
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v1, s41
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
index 95f716541b149..f9678b966d805 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
@@ -63,8 +63,8 @@ define amdgpu_kernel void @negated_cond(ptr addrspace(1) %arg1) {
; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2
; GCN-NEXT: s_ashr_i32 s13, s12, 31
; GCN-NEXT: s_lshl_b64 s[14:15], s[12:13], 2
-; GCN-NEXT: v_mov_b32_e32 v1, s14
; GCN-NEXT: s_cmp_eq_u32 s12, 32
+; GCN-NEXT: v_mov_b32_e32 v1, s14
; GCN-NEXT: v_mov_b32_e32 v2, s15
; GCN-NEXT: s_mov_b64 s[14:15], 0
; GCN-NEXT: s_cselect_b64 s[16:17], -1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/or.ll b/llvm/test/CodeGen/AMDGPU/or.ll
index df1f300c84553..10a9d1221392b 100644
--- a/llvm/test/CodeGen/AMDGPU/or.ll
+++ b/llvm/test/CodeGen/AMDGPU/or.ll
@@ -278,8 +278,8 @@ define amdgpu_kernel void @scalar_or_literal_multi_use_i64(ptr addrspace(1) %out
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_add_u32 s0, s4, 0x3039
@@ -300,9 +300,9 @@ define amdgpu_kernel void @scalar_or_literal_multi_use_i64(ptr addrspace(1) %out
; GFX8-NEXT: s_mov_b32 s9, 0xf237b
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_mov_b32 s3, 0xf000
; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX8-NEXT: s_add_u32 s0, s4, 0x3039
@@ -361,12 +361,12 @@ define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(ptr addrspace(1) %
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_or_b32 s0, s2, 63
-; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_add_u32 s0, s8, 63
-; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_addc_u32 s1, s9, 0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
@@ -383,12 +383,12 @@ define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(ptr addrspace(1) %
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, s0
; GFX8-NEXT: s_or_b32 s0, s2, 63
-; GFX8-NEXT: s_mov_b32 s5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_add_u32 s0, s8, 63
-; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
index ff0c3edc9dcf0..4bb6979092be8 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll
@@ -73,8 +73,8 @@ define amdgpu_kernel void @fadd_v2_ss(ptr addrspace(1) %a, <2 x double> %x, <2 x
; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
@@ -299,79 +299,72 @@ define amdgpu_kernel void @fadd_v32_vs(ptr addrspace(1) %a, <32 x double> %x) {
; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[4:7], v[4:7], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[8:11], v[8:11], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[12:15], v[12:15], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[16:19], v[16:19], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[20:23], v[20:23], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[24:27], v[24:27], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[28:31], v[28:31], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[32:35], v[32:35], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[36:39], v[36:39], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[40:43], v[40:43], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[44:47], v[44:47], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[48:51], v[48:51], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[52:55], v[52:55], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[56:59], v[56:59], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[60:63], v[60:63], v[68:71]
; GFX1251-GISEL-NEXT: s_clause 0xf
; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
@@ -655,9 +648,9 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, double %x) {
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s5, v5
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
@@ -751,9 +744,9 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo2(ptr addrspace(1) %a, double %x, do
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s5, v5
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[0:3], v[0:3], v[4:7]
; GFX1251-GISEL-NEXT: global_store_b128 v8, v[0:3], s[0:1] scale_offset
@@ -890,8 +883,8 @@ define amdgpu_kernel void @fmul_v2_ss(ptr addrspace(1) %a, <2 x double> %x, <2 x
; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[4:7]
@@ -1116,79 +1109,72 @@ define amdgpu_kernel void @fmul_v32_vs(ptr addrspace(1) %a, <32 x double> %x) {
; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[0:3], v[0:3], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[4:7], v[4:7], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[8:11], v[8:11], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[12:15], v[12:15], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[16:19], v[16:19], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[20:23], v[20:23], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[24:27], v[24:27], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[28:31], v[28:31], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[32:35], v[32:35], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[36:39], v[36:39], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[40:43], v[40:43], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[44:47], v[44:47], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[48:51], v[48:51], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[52:55], v[52:55], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[56:59], v[56:59], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[60:63], v[60:63], v[68:71]
; GFX1251-GISEL-NEXT: s_clause 0xf
; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
@@ -1443,10 +1429,10 @@ define amdgpu_kernel void @fma_v2_ss(ptr addrspace(1) %a, <2 x double> %x, <2 x
; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[2:3]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[0:3], v[0:3], v[4:7], v[8:11]
@@ -1645,79 +1631,72 @@ define amdgpu_kernel void @fma_v32_vs(ptr addrspace(1) %a, <32 x double> %x) {
; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[0:3], v[0:3], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[4:7], v[4:7], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[8:11], v[8:11], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[12:15], v[12:15], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[16:19], v[16:19], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[20:23], v[20:23], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[24:27], v[24:27], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[28:31], v[28:31], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[32:35], v[32:35], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[36:39], v[36:39], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[40:43], v[40:43], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[44:47], v[44:47], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[48:51], v[48:51], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[52:55], v[52:55], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[56:59], v[56:59], v[64:67], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[60:63], v[60:63], v[68:71], v[68:71]
; GFX1251-GISEL-NEXT: s_clause 0xf
; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
@@ -1768,10 +1747,10 @@ define amdgpu_kernel void @fma_v2_v_imm(ptr addrspace(1) %a) {
; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: v_and_b32_e32 v8, 0x3ff, v0
; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 0x4069000000000000
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], s[0:1]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v8, s[6:7] scale_offset
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -1856,13 +1835,13 @@ define amdgpu_kernel void @fma_v2_v_unfoldable_lit(ptr addrspace(1) %a) {
; GFX1251-GISEL-NEXT: s_load_b64 s[8:9], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: v_and_b32_e32 v12, 0x3ff, v0
; GFX1251-GISEL-NEXT: s_mov_b64 s[2:3], 0x4008000000000000
-; GFX1251-GISEL-NEXT: s_mov_b64 s[6:7], 2.0
; GFX1251-GISEL-NEXT: s_mov_b64 s[0:1], 4.0
+; GFX1251-GISEL-NEXT: s_mov_b64 s[6:7], 2.0
; GFX1251-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1251-GISEL-NEXT: s_mov_b64 s[4:5], 1.0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[6:7]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[6:7]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[4:5]
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: global_load_b128 v[0:3], v12, s[8:9] scale_offset
@@ -1990,10 +1969,10 @@ define amdgpu_kernel void @fma_vector_vector_neg_scalar_lo_scalar_hi(ptr addrspa
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s14, v2
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s13, v1
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
-; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s15, v3
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s15, v3
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[14:15]
@@ -2377,20 +2356,20 @@ define void @strict_fadd_v2_ss(<2 x double> inreg %x, <2 x double> inreg %y, ptr
; GFX1251-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[18:19]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_add_f64 v[2:5], v[2:5], v[6:9]
-; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1251-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1251-GISEL-NEXT: s_set_pc_i64 s[30:31]
%add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -2430,20 +2409,20 @@ define void @strict_fmul_v2_ss(<2 x double> inreg %x, <2 x double> inreg %y, ptr
; GFX1251-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[18:19]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_mul_f64 v[2:5], v[2:5], v[6:9]
-; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1251-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1251-GISEL-NEXT: s_set_pc_i64 s[30:31]
%mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double> %x, <2 x double> %y, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -2485,22 +2464,22 @@ define void @strict_fma_v2_ss(<2 x double> inreg %x, <2 x double> inreg %y, <2 x
; GFX1251-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[20:21]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[20:21]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[22:23]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1251-GISEL-NEXT: v_pk_fma_f64 v[2:5], v[2:5], v[6:9], v[10:13]
-; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1251-GISEL-NEXT: v_readfirstlane_b32 s3, v5
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
; GFX1251-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1251-GISEL-NEXT: s_set_pc_i64 s[30:31]
%fma = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %x, <2 x double> %y, <2 x double> %z, metadata !"round.dynamic", metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/AMDGPU/packed-u64.ll b/llvm/test/CodeGen/AMDGPU/packed-u64.ll
index 77e45fb1560e3..13d6b0b9e93ce 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-u64.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-u64.ll
@@ -73,8 +73,8 @@ define amdgpu_kernel void @add_v2_ss(ptr addrspace(1) %a, <2 x i64> %x, <2 x i64
; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[4:7]
@@ -299,79 +299,72 @@ define amdgpu_kernel void @add_v32_vs(ptr addrspace(1) %a, <32 x i64> %x) {
; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[0:3], v[0:3], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[4:7], v[4:7], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[8:11], v[8:11], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[12:15], v[12:15], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[16:19], v[16:19], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[20:23], v[20:23], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[24:27], v[24:27], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[28:31], v[28:31], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[32:35], v[32:35], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[36:39], v[36:39], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[40:43], v[40:43], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[44:47], v[44:47], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[48:51], v[48:51], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[52:55], v[52:55], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[56:59], v[56:59], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_add_nc_u64 v[60:63], v[60:63], v[68:71]
; GFX1251-GISEL-NEXT: s_clause 0xf
; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
@@ -656,8 +649,8 @@ define amdgpu_kernel void @sub_v2_ss(ptr addrspace(1) %a, <2 x i64> %x, <2 x i64
; GFX1251-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[12:13]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[14:15]
; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[4:7]
@@ -882,79 +875,72 @@ define amdgpu_kernel void @sub_v32_vs(ptr addrspace(1) %a, <32 x i64> %x) {
; GFX1251-GISEL-NEXT: global_load_b128 v[56:59], v72, s[0:1] offset:224
; GFX1251-GISEL-NEXT: global_load_b128 v[60:63], v72, s[0:1] offset:240
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_load_b512 s[8:23], s[4:5], 0x1a4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xf
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[0:3], v[0:3], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[26:27]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xe
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[4:7], v[4:7], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[30:31]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[24:25]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[28:29]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xd
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[8:11], v[8:11], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xc
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[12:15], v[12:15], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_load_b512 s[36:51], s[4:5], 0x1e4 nv
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xb
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[16:19], v[16:19], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[54:55]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0xa
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[20:23], v[20:23], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[58:59]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[52:53]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[56:57]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x9
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[24:27], v[24:27], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[10:11]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x8
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[28:31], v[28:31], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[14:15]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[8:9]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[12:13]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x7
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[32:35], v[32:35], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[18:19]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x6
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[36:39], v[36:39], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[22:23]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[16:17]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[20:21]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x5
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[40:43], v[40:43], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[38:39]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x4
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[44:47], v[44:47], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[42:43]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[36:37]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[40:41]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x3
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[48:51], v[48:51], v[64:67]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[66:67], s[46:47]
+; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x2
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[52:55], v[52:55], v[68:71]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[70:71], s[50:51]
-; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[64:65], s[44:45]
; GFX1251-GISEL-NEXT: v_mov_b64_e32 v[68:69], s[48:49]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x1
-; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[56:59], v[56:59], v[64:67]
; GFX1251-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1251-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1251-GISEL-NEXT: v_pk_sub_nc_u64 v[60:63], v[60:63], v[68:71]
; GFX1251-GISEL-NEXT: s_clause 0xf
; GFX1251-GISEL-NEXT: global_store_b128 v72, v[0:3], s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
index 4ecb54f8aba2a..e75639a2dc261 100644
--- a/llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Check that no attributes are added to graphics functions
; RUN: opt -S -mtriple=amdgcn-amd-amdpal -passes=amdgpu-attributor %s | FileCheck -check-prefixes=ATTRIBUTOR_GCN %s
@@ -29,6 +29,7 @@ define amdgpu_cs void @test_simple_indirect_call() {
; GFX9-NEXT: s_mov_b64 s[2:3], s[10:11]
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: s_endpgm
+;
; GFX10-LABEL: test_simple_indirect_call:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_getpc_b64 s[8:9]
@@ -40,8 +41,8 @@ define amdgpu_cs void @test_simple_indirect_call() {
; GFX10-NEXT: s_bitset0_b32 s11, 21
; GFX10-NEXT: s_add_u32 s8, s8, s0
; GFX10-NEXT: s_addc_u32 s9, s9, 0
-; GFX10-NEXT: s_mov_b64 s[0:1], s[8:9]
; GFX10-NEXT: s_mov_b64 s[2:3], s[10:11]
+; GFX10-NEXT: s_mov_b64 s[0:1], s[8:9]
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
index ab6597363825e..03afc774398bf 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
@@ -6,9 +6,9 @@
define amdgpu_kernel void @test_bitcast_llc_v128i8_v16i8(ptr addrspace(1) %out, i32 %idx) {
; GFX9-LABEL: test_bitcast_llc_v128i8_v16i8:
; GFX9: ; %bb.0: ; %entry
-; GFX9-NEXT: s_lshl_b32 s0, s0, 8
; GFX9-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s33, s[4:5], 0x8
+; GFX9-NEXT: s_lshl_b32 s0, s0, 8
; GFX9-NEXT: s_and_b32 s1, s0, 0xff
; GFX9-NEXT: s_or_b32 s0, s1, s0
; GFX9-NEXT: s_and_b32 s1, s0, 0xffff
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
index fa1d34da9376e..c99a32356da7a 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -22,8 +22,8 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
@@ -361,8 +361,8 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
@@ -390,8 +390,8 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX8-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX8-NEXT: ; =>This Loop Header: Depth=1
; GFX8-NEXT: ; Child Loop BB1_2 Depth 2
-; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: s_mov_b32 s5, 0
+; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: .LBB1_2: ; %for.body
; GFX8-NEXT: ; Parent Loop BB1_1 Depth=1
@@ -1040,8 +1040,8 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
@@ -1361,8 +1361,8 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
@@ -1587,8 +1587,8 @@ define amdgpu_kernel void @p32Offset64(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
@@ -1796,8 +1796,8 @@ define amdgpu_kernel void @DiffBase(ptr addrspace(1) %buffer1,
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[48:49]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[48:49]
; GFX8-NEXT: s_mov_b64 s[2:3], s[50:51]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
@@ -2072,8 +2072,8 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
@@ -2414,8 +2414,8 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX8-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
-; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: v_mov_b32_e32 v31, v0
+; GFX8-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0
diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
index 2e15c37bc19fb..5a0ab4ef7b42b 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
@@ -89,8 +89,8 @@ define amdgpu_kernel void @gep_as0_uniform(ptr %p, i64 %offset, ptr %ret) {
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: s_addc_u32 s1, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: flat_store_dword v[2:3], v5
; GFX8-NEXT: flat_store_dword v[0:1], v4
@@ -140,7 +140,7 @@ define amdgpu_kernel void @gep_as0_uniform(ptr %p, i64 %offset, ptr %ret) {
; GFX11-NEXT: s_add_u32 s0, s0, s2
; GFX11-NEXT: s_addc_u32 s1, s1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: flat_store_b64 v[0:1], v[2:3]
; GFX11-NEXT: s_endpgm
;
@@ -246,8 +246,8 @@ define amdgpu_kernel void @multi_gep_as0_uniform(ptr %p, i64 %offset, ptr %ret)
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: s_addc_u32 s1, s5, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: flat_store_dword v[2:3], v5
; GFX8-NEXT: flat_store_dword v[0:1], v4
@@ -303,7 +303,7 @@ define amdgpu_kernel void @multi_gep_as0_uniform(ptr %p, i64 %offset, ptr %ret)
; GFX11-NEXT: s_add_u32 s0, s0, 5
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: flat_store_b64 v[0:1], v[2:3]
; GFX11-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
index 163a64ce24fd3..23b379edae8b1 100644
--- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
@@ -178,9 +178,9 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19]
; GFX9-NEXT: v_or3_b32 v6, v6, v10, v12
; GFX9-NEXT: v_and_b32_e32 v10, 1, v32
-; GFX9-NEXT: v_mov_b32_e32 v19, v11
; GFX9-NEXT: v_or3_b32 v7, v7, 0, v13
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v19, v11
; GFX9-NEXT: v_mov_b32_e32 v18, v10
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB0_3
@@ -1604,9 +1604,9 @@ define i128 @v_urem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[20:21]
; GFX9-NEXT: v_or3_b32 v8, v8, v12, v14
; GFX9-NEXT: v_and_b32_e32 v12, 1, v30
-; GFX9-NEXT: v_mov_b32_e32 v21, v13
; GFX9-NEXT: v_or3_b32 v9, v9, 0, v15
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v21, v13
; GFX9-NEXT: v_mov_b32_e32 v20, v12
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB1_3
diff --git a/llvm/test/CodeGen/AMDGPU/rotl.ll b/llvm/test/CodeGen/AMDGPU/rotl.ll
index 3d2c268416f30..0d7df428c72d8 100644
--- a/llvm/test/CodeGen/AMDGPU/rotl.ll
+++ b/llvm/test/CodeGen/AMDGPU/rotl.ll
@@ -137,9 +137,9 @@ define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX8-NEXT: s_and_b32 s3, s6, 31
; GFX8-NEXT: s_mov_b32 s1, s0
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -272,11 +272,11 @@ define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX8-NEXT: s_and_b32 s3, s12, 31
; GFX8-NEXT: s_mov_b32 s9, s8
; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], s3
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s6
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/rotr.ll b/llvm/test/CodeGen/AMDGPU/rotr.ll
index 7df102fd9c856..daaa8778eb3a2 100644
--- a/llvm/test/CodeGen/AMDGPU/rotr.ll
+++ b/llvm/test/CodeGen/AMDGPU/rotr.ll
@@ -122,9 +122,9 @@ define amdgpu_kernel void @rotr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX8-NEXT: s_mov_b32 s1, s0
; GFX8-NEXT: s_lshr_b64 s[2:3], s[6:7], s3
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s8
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
@@ -237,11 +237,11 @@ define amdgpu_kernel void @rotr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX8-NEXT: s_mov_b32 s9, s8
; GFX8-NEXT: s_lshr_b64 s[4:5], s[10:11], s5
; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], s3
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s6
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
@@ -414,10 +414,10 @@ define amdgpu_kernel void @rotr_v8i32(ptr addrspace(1) %in, <8 x i32> %x, <8 x i
; GFX8-NEXT: v_mov_b32_e32 v3, s10
; GFX8-NEXT: s_add_u32 s10, s0, 16
; GFX8-NEXT: s_addc_u32 s11, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v1, s16
; GFX8-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
diff --git a/llvm/test/CodeGen/AMDGPU/sad.ll b/llvm/test/CodeGen/AMDGPU/sad.ll
index 15fc987d1e7c6..67a9224cab685 100644
--- a/llvm/test/CodeGen/AMDGPU/sad.ll
+++ b/llvm/test/CodeGen/AMDGPU/sad.ll
@@ -35,13 +35,13 @@ define amdgpu_kernel void @v_sad_u32_constant_pat1(ptr addrspace(1) %out, i32 %a
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s2, s[8:9], 0x2
; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
-; GCN-NEXT: v_mov_b32_e32 v0, 0x5a
; GCN-NEXT: s_add_i32 s12, s12, s17
+; GCN-NEXT: v_mov_b32_e32 v0, 0x5a
; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_sad_u32 v2, s2, v0, 20
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: flat_store_dword v[0:1], v2
; GCN-NEXT: s_endpgm
@@ -137,9 +137,9 @@ define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(ptr addrspace(1) %out, i
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: v_mov_b32_e32 v3, s2
-; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: s_addc_u32 s21, s21, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: v_sad_u32 v2, s0, v2, v3
; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen
@@ -175,11 +175,11 @@ define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(ptr addrspace(1) %out, i
; GCN-NEXT: v_mov_b32_e32 v0, s1
; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: v_sad_u32 v3, s0, v0, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: flat_store_dword v[0:1], v3
; GCN-NEXT: s_endpgm
@@ -213,11 +213,11 @@ define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(ptr addrspace(1) %out, i
; GCN-NEXT: v_mov_b32_e32 v0, s1
; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: v_sad_u32 v3, s0, v0, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: flat_store_dword v[0:1], v3
; GCN-NEXT: s_endpgm
@@ -252,11 +252,11 @@ define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(ptr addrspace(1) %out, i
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: v_sad_u32 v3, s1, v0, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: flat_store_dword v[0:1], v3
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/saddo.ll b/llvm/test/CodeGen/AMDGPU/saddo.ll
index b1e2da0accfa5..8c5c10d434e43 100644
--- a/llvm/test/CodeGen/AMDGPU/saddo.ll
+++ b/llvm/test/CodeGen/AMDGPU/saddo.ll
@@ -22,9 +22,9 @@ define amdgpu_kernel void @saddo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b)
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_add_u32 s0, s2, s8
-; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_addc_u32 s1, s3, s9
+; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; SI-NEXT: s_cmp_lt_i32 s9, 0
@@ -46,8 +46,8 @@ define amdgpu_kernel void @saddo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b)
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_add_u32 s0, s2, s4
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: s_addc_u32 s1, s3, s5
; VI-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[2:3]
@@ -123,11 +123,11 @@ define amdgpu_kernel void @saddo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b)
; GFX11-NEXT: s_xor_b32 s2, s3, s2
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-NEXT: s_cselect_b64 s[2:3], 1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_u32 s2, s6, s2
; GFX11-NEXT: s_addc_u32 s3, s7, s3
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
%sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind
@@ -375,17 +375,17 @@ define amdgpu_kernel void @s_saddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_add_u32 s12, s4, s6
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_addc_u32 s13, s5, s7
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_cmp_lt_i64_e32 vcc, s[12:13], v[0:1]
; SI-NEXT: s_cmp_lt_i32 s7, 0
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
-; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_mov_b32_e32 v1, s13
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_mov_b32 s0, s2
@@ -404,9 +404,9 @@ define amdgpu_kernel void @s_saddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_add_u32 s0, s4, s6
-; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_addc_u32 s1, s5, s7
+; VI-NEXT: v_mov_b32_e32 v4, s4
; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[4:5]
; VI-NEXT: s_cmp_lt_i32 s7, 0
@@ -474,13 +474,12 @@ define amdgpu_kernel void @s_saddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX11-NEXT: s_cmp_lt_i32 s7, 0
; GFX11-NEXT: v_cmp_lt_i64_e64 s4, s[8:9], s[4:5]
; GFX11-NEXT: s_cselect_b32 s5, -1, 0
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s9
; GFX11-NEXT: s_xor_b32 s4, s5, s4
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
; GFX11-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s4
-; GFX11-NEXT: v_mov_b32_e32 v1, s9
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: global_store_b8 v2, v3, s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index b6e133c1b9dc7..9554a03942579 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -243,9 +243,9 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[10:11], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -456,8 +456,8 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v16
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
@@ -948,9 +948,9 @@ define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[10:11], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -1677,9 +1677,9 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -1860,8 +1860,8 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v14
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
@@ -2054,8 +2054,8 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v14
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
@@ -2148,10 +2148,10 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GCN-IR-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
-; GCN-IR-NEXT: v_or_b32_e32 v1, v7, v1
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v7, v3
+; GCN-IR-NEXT: v_or_b32_e32 v1, v7, v1
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v7, v3
; GCN-IR-NEXT: v_mov_b32_e32 v6, v2
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB14_3
@@ -2536,10 +2536,10 @@ define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GCN-IR-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
-; GCN-IR-NEXT: v_or_b32_e32 v1, v7, v1
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v7, v3
+; GCN-IR-NEXT: v_or_b32_e32 v1, v7, v1
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v7, v3
; GCN-IR-NEXT: v_mov_b32_e32 v6, v2
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB19_3
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index 31ea6efb6907f..d643fdfafbbb5 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -2112,8 +2112,8 @@ define void @crash_lshlrevb16_not_reg_op() {
; NOSDWA-NEXT: .LBB22_1: ; %bb1
; NOSDWA-NEXT: ; =>This Inner Loop Header: Depth=1
; NOSDWA-NEXT: s_lshl_b32 s7, s4, 3
-; NOSDWA-NEXT: v_mov_b32_e32 v0, s4
; NOSDWA-NEXT: s_lshr_b32 s7, s6, s7
+; NOSDWA-NEXT: v_mov_b32_e32 v0, s4
; NOSDWA-NEXT: v_mov_b32_e32 v1, s5
; NOSDWA-NEXT: s_mov_b64 s[4:5], 1
; NOSDWA-NEXT: v_mov_b32_e32 v2, s7
@@ -2134,8 +2134,8 @@ define void @crash_lshlrevb16_not_reg_op() {
; GFX89-NEXT: .LBB22_1: ; %bb1
; GFX89-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX89-NEXT: s_lshl_b32 s7, s4, 3
-; GFX89-NEXT: v_mov_b32_e32 v0, s4
; GFX89-NEXT: s_lshr_b32 s7, s6, s7
+; GFX89-NEXT: v_mov_b32_e32 v0, s4
; GFX89-NEXT: v_mov_b32_e32 v1, s5
; GFX89-NEXT: s_mov_b64 s[4:5], 1
; GFX89-NEXT: v_mov_b32_e32 v2, s7
@@ -2156,8 +2156,8 @@ define void @crash_lshlrevb16_not_reg_op() {
; GFX9-NEXT: .LBB22_1: ; %bb1
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_lshl_b32 s7, s4, 3
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_lshr_b32 s7, s6, s7
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_mov_b64 s[4:5], 1
; GFX9-NEXT: v_mov_b32_e32 v2, s7
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
index f11fe4aa6e00e..e1439be3a906e 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
@@ -75,7 +75,7 @@ body: |
; GFX9-LABEL: name: sgpr96_aligned_src_dst
; GFX9: liveins: $sgpr0_sgpr1_sgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr6 = S_MOV_B32 $sgpr2, implicit $sgpr0_sgpr1_sgpr2, implicit-def $sgpr4_sgpr5_sgpr6
+ ; GFX9-NEXT: $sgpr6 = S_MOV_B32 $sgpr2, implicit $sgpr0_sgpr1_sgpr2
; GFX9-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2
$sgpr4_sgpr5_sgpr6 = COPY $sgpr0_sgpr1_sgpr2
...
@@ -88,7 +88,7 @@ body: |
; GFX9-LABEL: name: sgpr96_killed
; GFX9: liveins: $sgpr4_sgpr5_sgpr6
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr10 = S_MOV_B32 $sgpr6, implicit $sgpr4_sgpr5_sgpr6, implicit-def $sgpr8_sgpr9_sgpr10
+ ; GFX9-NEXT: $sgpr10 = S_MOV_B32 $sgpr6, implicit $sgpr4_sgpr5_sgpr6
; GFX9-NEXT: $sgpr8_sgpr9 = S_MOV_B64 $sgpr4_sgpr5, implicit killed $sgpr4_sgpr5_sgpr6
$sgpr8_sgpr9_sgpr10 = COPY killed $sgpr4_sgpr5_sgpr6
...
@@ -101,7 +101,7 @@ body: |
; GFX9-LABEL: name: sgpr128_forward
; GFX9: liveins: $sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6_sgpr7, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr6_sgpr7, implicit $sgpr4_sgpr5_sgpr6_sgpr7
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
...
@@ -114,7 +114,7 @@ body: |
; GFX9-LABEL: name: sgpr128_backward
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX9-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; GFX9-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3
$sgpr4_sgpr5_sgpr6_sgpr7 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
...
@@ -127,7 +127,7 @@ body: |
; GFX9-LABEL: name: sgpr128_killed
; GFX9: liveins: $sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6_sgpr7, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr6_sgpr7, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY killed $sgpr4_sgpr5_sgpr6_sgpr7
...
@@ -140,7 +140,7 @@ body: |
; GFX9-LABEL: name: sgpr160_forward
; GFX9: liveins: $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
+ ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr10_sgpr11, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
; GFX9-NEXT: $sgpr4 = S_MOV_B32 $sgpr12, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
@@ -154,7 +154,7 @@ body: |
; GFX9-LABEL: name: sgpr160_backward
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr12 = S_MOV_B32 $sgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
+ ; GFX9-NEXT: $sgpr12 = S_MOV_B32 $sgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
; GFX9-NEXT: $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
; GFX9-NEXT: $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
$sgpr8_sgpr9_sgpr10_sgpr11_sgpr12 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
@@ -168,7 +168,7 @@ body: |
; GFX9-LABEL: name: sgpr160_killed
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr12 = S_MOV_B32 $sgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
+ ; GFX9-NEXT: $sgpr12 = S_MOV_B32 $sgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
; GFX9-NEXT: $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
; GFX9-NEXT: $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
$sgpr8_sgpr9_sgpr10_sgpr11_sgpr12 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
@@ -183,7 +183,7 @@ body: |
; GFX9-LABEL: name: sgpr192_forward
; GFX9: liveins: $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
+ ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr10_sgpr11, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
; GFX9-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $sgpr12_sgpr13, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5 = COPY $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
@@ -197,7 +197,7 @@ body: |
; GFX9-LABEL: name: sgpr192_backward
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr12_sgpr13 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
+ ; GFX9-NEXT: $sgpr12_sgpr13 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX9-NEXT: $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX9-NEXT: $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
$sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
@@ -211,7 +211,7 @@ body: |
; GFX9-LABEL: name: sgpr192_killed
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr12_sgpr13 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
+ ; GFX9-NEXT: $sgpr12_sgpr13 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX9-NEXT: $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
; GFX9-NEXT: $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
$sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
@@ -225,7 +225,7 @@ body: |
; GFX9-LABEL: name: sgpr256_forward
; GFX9: liveins: $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
+ ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr10_sgpr11, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $sgpr12_sgpr13, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $sgpr14_sgpr15, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -240,7 +240,7 @@ body: |
; GFX9-LABEL: name: sgpr256_backward
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr14_sgpr15 = S_MOV_B64 $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GFX9-NEXT: $sgpr14_sgpr15 = S_MOV_B64 $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr12_sgpr13 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
@@ -255,7 +255,7 @@ body: |
; GFX9-LABEL: name: sgpr256_killed
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr14_sgpr15 = S_MOV_B64 $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GFX9-NEXT: $sgpr14_sgpr15 = S_MOV_B64 $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr12_sgpr13 = S_MOV_B64 $sgpr4_sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GFX9-NEXT: $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
@@ -270,7 +270,7 @@ body: |
; GFX9-LABEL: name: sgpr512_forward
; GFX9: liveins: $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr16_sgpr17, implicit $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+ ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr16_sgpr17, implicit $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr18_sgpr19, implicit $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $sgpr20_sgpr21, implicit $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $sgpr22_sgpr23, implicit $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
@@ -289,7 +289,7 @@ body: |
; GFX9-LABEL: name: sgpr512_backward
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr30_sgpr31 = S_MOV_B64 $sgpr14_sgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; GFX9-NEXT: $sgpr30_sgpr31 = S_MOV_B64 $sgpr14_sgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr28_sgpr29 = S_MOV_B64 $sgpr12_sgpr13, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr26_sgpr27 = S_MOV_B64 $sgpr10_sgpr11, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr24_sgpr25 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -308,7 +308,7 @@ body: |
; GFX9-LABEL: name: sgpr512_killed
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr30_sgpr31 = S_MOV_B64 $sgpr14_sgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; GFX9-NEXT: $sgpr30_sgpr31 = S_MOV_B64 $sgpr14_sgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr28_sgpr29 = S_MOV_B64 $sgpr12_sgpr13, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr26_sgpr27 = S_MOV_B64 $sgpr10_sgpr11, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GFX9-NEXT: $sgpr24_sgpr25 = S_MOV_B64 $sgpr8_sgpr9, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -327,7 +327,7 @@ body: |
; GFX9-LABEL: name: sgpr1024_forward
; GFX9: liveins: $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr32_sgpr33, implicit $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $sgpr32_sgpr33, implicit $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $sgpr34_sgpr35, implicit $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63
; GFX9-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $sgpr36_sgpr37, implicit $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63
; GFX9-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $sgpr38_sgpr39, implicit $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63
@@ -354,7 +354,7 @@ body: |
; GFX9-LABEL: name: sgpr1024_backward
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr62_sgpr63 = S_MOV_B64 $sgpr30_sgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63
+ ; GFX9-NEXT: $sgpr62_sgpr63 = S_MOV_B64 $sgpr30_sgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr60_sgpr61 = S_MOV_B64 $sgpr28_sgpr29, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr58_sgpr59 = S_MOV_B64 $sgpr26_sgpr27, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr56_sgpr57 = S_MOV_B64 $sgpr24_sgpr25, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
@@ -381,7 +381,7 @@ body: |
; GFX9-LABEL: name: sgpr1024_killed
; GFX9: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: $sgpr62_sgpr63 = S_MOV_B64 $sgpr30_sgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63
+ ; GFX9-NEXT: $sgpr62_sgpr63 = S_MOV_B64 $sgpr30_sgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr60_sgpr61 = S_MOV_B64 $sgpr28_sgpr29, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr58_sgpr59 = S_MOV_B64 $sgpr26_sgpr27, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GFX9-NEXT: $sgpr56_sgpr57 = S_MOV_B64 $sgpr24_sgpr25, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
index 237ac399883dc..110cd903f636d 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
@@ -29,13 +29,13 @@ define amdgpu_kernel void @kernel() {
; GCN-NEXT: s_add_u32 s0, s0, foo at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s1, s1, foo at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x0
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GCN-NEXT: s_mov_b32 s14, s10
; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GCN-NEXT: s_mov_b64 s[0:1], s[36:37]
; GCN-NEXT: v_or3_b32 v31, v0, v1, v2
+; GCN-NEXT: s_mov_b64 s[0:1], s[36:37]
; GCN-NEXT: s_mov_b64 s[2:3], s[38:39]
; GCN-NEXT: s_mov_b32 s32, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll b/llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
index 2b698d3ee4854..8eb09d6884351 100644
--- a/llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
@@ -8,11 +8,11 @@ define amdgpu_kernel void @v_uextract_bit_31_i128(ptr addrspace(1) %out, ptr add
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 4
-; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64
; GCN-NEXT: v_mov_b32_e32 v1, 0
@@ -73,10 +73,10 @@ define amdgpu_kernel void @v_uextract_bit_95_i128(ptr addrspace(1) %out, ptr add
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 4
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, 0
-; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
; GCN-NEXT: s_mov_b64 s[10:11], s[2:3]
+; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v4, s0
; GCN-NEXT: buffer_load_dword v0, v[4:5], s[8:11], 0 addr64 offset:8
; GCN-NEXT: v_mov_b32_e32 v1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll b/llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
index 760a126afa995..f7c8320739ef1 100644
--- a/llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
@@ -11,11 +11,11 @@ define amdgpu_kernel void @v_uextract_bit_31_i64(ptr addrspace(1) %out, ptr addr
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
@@ -69,11 +69,11 @@ define amdgpu_kernel void @v_uextract_bit_1_i64(ptr addrspace(1) %out, ptr addrs
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
@@ -98,11 +98,11 @@ define amdgpu_kernel void @v_uextract_bit_20_i64(ptr addrspace(1) %out, ptr addr
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
@@ -183,11 +183,11 @@ define amdgpu_kernel void @v_uextract_bit_20_21_i64(ptr addrspace(1) %out, ptr a
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
@@ -212,11 +212,11 @@ define amdgpu_kernel void @v_uextract_bit_1_30_i64(ptr addrspace(1) %out, ptr ad
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
@@ -241,11 +241,11 @@ define amdgpu_kernel void @v_uextract_bit_1_31_i64(ptr addrspace(1) %out, ptr ad
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
@@ -272,11 +272,11 @@ define amdgpu_kernel void @v_uextract_bit_31_32_i64(ptr addrspace(1) %out, ptr a
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
-; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64
; GCN-NEXT: s_mov_b64 s[6:7], s[10:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
index a747af428c1b5..d2e999bc7826e 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
@@ -14845,8 +14845,8 @@ define void @s_shuffle_v2i64_v8i64__15_5() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s12, s30
; GFX900-NEXT: s_mov_b32 s13, s31
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -14874,8 +14874,8 @@ define void @s_shuffle_v2i64_v8i64__15_5() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s12, s30
; GFX90A-NEXT: s_mov_b32 s13, s31
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -15129,8 +15129,8 @@ define void @s_shuffle_v2i64_v8i64__15_7() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s12, s30
; GFX942-NEXT: s_mov_b32 s13, s31
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -19205,8 +19205,8 @@ define void @s_shuffle_v2i64_v8i64__12_4() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s26, s12
; GFX900-NEXT: s_mov_b32 s27, s13
-; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -19234,8 +19234,8 @@ define void @s_shuffle_v2i64_v8i64__12_4() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s26, s12
; GFX90A-NEXT: s_mov_b32 s27, s13
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -19883,8 +19883,8 @@ define void @s_shuffle_v2i64_v8i64__9_5() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s12, s18
; GFX900-NEXT: s_mov_b32 s13, s19
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -19912,8 +19912,8 @@ define void @s_shuffle_v2i64_v8i64__9_5() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s12, s18
; GFX90A-NEXT: s_mov_b32 s13, s19
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -20021,8 +20021,8 @@ define void @s_shuffle_v2i64_v8i64__11_5() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s12, s22
; GFX900-NEXT: s_mov_b32 s13, s23
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -20050,8 +20050,8 @@ define void @s_shuffle_v2i64_v8i64__11_5() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s12, s22
; GFX90A-NEXT: s_mov_b32 s13, s23
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -20103,8 +20103,8 @@ define void @s_shuffle_v2i64_v8i64__12_5() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s26, s14
; GFX900-NEXT: s_mov_b32 s27, s15
-; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -20132,8 +20132,8 @@ define void @s_shuffle_v2i64_v8i64__12_5() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s26, s14
; GFX90A-NEXT: s_mov_b32 s27, s15
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -20185,8 +20185,8 @@ define void @s_shuffle_v2i64_v8i64__13_5() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s12, s26
; GFX900-NEXT: s_mov_b32 s13, s27
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -20214,8 +20214,8 @@ define void @s_shuffle_v2i64_v8i64__13_5() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s12, s26
; GFX90A-NEXT: s_mov_b32 s13, s27
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -21076,10 +21076,10 @@ define void @s_shuffle_v2i64_v8i64__12_6() #0 {
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
+; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[36:51]
+; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s46, s16
; GFX900-NEXT: s_mov_b32 s47, s17
@@ -21117,10 +21117,10 @@ define void @s_shuffle_v2i64_v8i64__12_6() #0 {
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
+; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[36:51]
+; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s46, s16
; GFX90A-NEXT: s_mov_b32 s47, s17
@@ -21301,10 +21301,10 @@ define void @s_shuffle_v2i64_v8i64__14_6() #0 {
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
+; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[36:51]
+; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s50, s16
; GFX900-NEXT: s_mov_b32 s51, s17
@@ -21342,10 +21342,10 @@ define void @s_shuffle_v2i64_v8i64__14_6() #0 {
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
+; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[36:51]
+; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s50, s16
; GFX90A-NEXT: s_mov_b32 s51, s17
@@ -21378,10 +21378,10 @@ define void @s_shuffle_v2i64_v8i64__14_6() #0 {
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s30, s12
; GFX942-NEXT: s_mov_b32 s31, s13
@@ -21930,8 +21930,8 @@ define void @s_shuffle_v2i64_v8i64__9_7() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s12, s18
; GFX942-NEXT: s_mov_b32 s13, s19
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -22105,8 +22105,8 @@ define void @s_shuffle_v2i64_v8i64__11_7() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s12, s22
; GFX942-NEXT: s_mov_b32 s13, s23
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -22140,10 +22140,10 @@ define void @s_shuffle_v2i64_v8i64__12_7() #0 {
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
+; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[36:51]
+; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s46, s18
; GFX900-NEXT: s_mov_b32 s47, s19
@@ -22181,10 +22181,10 @@ define void @s_shuffle_v2i64_v8i64__12_7() #0 {
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
+; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[36:51]
+; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s46, s18
; GFX90A-NEXT: s_mov_b32 s47, s19
@@ -22330,8 +22330,8 @@ define void @s_shuffle_v2i64_v8i64__13_7() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s12, s26
; GFX942-NEXT: s_mov_b32 s13, s27
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -22365,10 +22365,10 @@ define void @s_shuffle_v2i64_v8i64__14_7() #0 {
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
+; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[36:51]
+; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s50, s18
; GFX900-NEXT: s_mov_b32 s51, s19
@@ -22406,10 +22406,10 @@ define void @s_shuffle_v2i64_v8i64__14_7() #0 {
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
+; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[36:51]
+; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s50, s18
; GFX90A-NEXT: s_mov_b32 s51, s19
@@ -22442,10 +22442,10 @@ define void @s_shuffle_v2i64_v8i64__14_7() #0 {
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s30, s14
; GFX942-NEXT: s_mov_b32 s31, s15
@@ -23451,8 +23451,8 @@ define void @s_shuffle_v2i64_v8i64__4_9() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s14, s18
; GFX900-NEXT: s_mov_b32 s15, s19
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -23480,8 +23480,8 @@ define void @s_shuffle_v2i64_v8i64__4_9() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s14, s18
; GFX90A-NEXT: s_mov_b32 s15, s19
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -23706,8 +23706,8 @@ define void @s_shuffle_v2i64_v8i64__6_9() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s14, s18
; GFX942-NEXT: s_mov_b32 s15, s19
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -24303,8 +24303,8 @@ define void @s_shuffle_v2i64_v8i64__4_10() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s14, s20
; GFX900-NEXT: s_mov_b32 s15, s21
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -24332,8 +24332,8 @@ define void @s_shuffle_v2i64_v8i64__4_10() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s14, s20
; GFX90A-NEXT: s_mov_b32 s15, s21
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -24551,8 +24551,8 @@ define void @s_shuffle_v2i64_v8i64__6_10() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s14, s20
; GFX942-NEXT: s_mov_b32 s15, s21
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -25349,8 +25349,8 @@ define void @s_shuffle_v2i64_v8i64__4_11() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s14, s22
; GFX900-NEXT: s_mov_b32 s15, s23
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -25378,8 +25378,8 @@ define void @s_shuffle_v2i64_v8i64__4_11() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s14, s22
; GFX90A-NEXT: s_mov_b32 s15, s23
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -25570,8 +25570,8 @@ define void @s_shuffle_v2i64_v8i64__6_11() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s14, s22
; GFX942-NEXT: s_mov_b32 s15, s23
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -26167,8 +26167,8 @@ define void @s_shuffle_v2i64_v8i64__4_12() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s14, s24
; GFX900-NEXT: s_mov_b32 s15, s25
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -26196,8 +26196,8 @@ define void @s_shuffle_v2i64_v8i64__4_12() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s14, s24
; GFX90A-NEXT: s_mov_b32 s15, s25
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -26415,8 +26415,8 @@ define void @s_shuffle_v2i64_v8i64__6_12() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s14, s24
; GFX942-NEXT: s_mov_b32 s15, s25
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -27066,8 +27066,8 @@ define void @s_shuffle_v2i64_v8i64__4_13() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s14, s26
; GFX900-NEXT: s_mov_b32 s15, s27
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -27095,8 +27095,8 @@ define void @s_shuffle_v2i64_v8i64__4_13() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s14, s26
; GFX90A-NEXT: s_mov_b32 s15, s27
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -27148,8 +27148,8 @@ define void @s_shuffle_v2i64_v8i64__5_13() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s24, s14
; GFX900-NEXT: s_mov_b32 s25, s15
-; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -27177,8 +27177,8 @@ define void @s_shuffle_v2i64_v8i64__5_13() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s24, s14
; GFX90A-NEXT: s_mov_b32 s25, s15
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -27313,8 +27313,8 @@ define void @s_shuffle_v2i64_v8i64__6_13() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s14, s26
; GFX942-NEXT: s_mov_b32 s15, s27
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -28024,8 +28024,8 @@ define void @s_shuffle_v2i64_v8i64__4_14() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s14, s28
; GFX900-NEXT: s_mov_b32 s15, s29
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -28053,8 +28053,8 @@ define void @s_shuffle_v2i64_v8i64__4_14() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s14, s28
; GFX90A-NEXT: s_mov_b32 s15, s29
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -28272,8 +28272,8 @@ define void @s_shuffle_v2i64_v8i64__6_14() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s14, s28
; GFX942-NEXT: s_mov_b32 s15, s29
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -29007,8 +29007,8 @@ define void @s_shuffle_v2i64_v8i64__4_15() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s14, s30
; GFX900-NEXT: s_mov_b32 s15, s31
-; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: v_readlane_b32 s30, v0, 0
+; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -29036,8 +29036,8 @@ define void @s_shuffle_v2i64_v8i64__4_15() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s14, s30
; GFX90A-NEXT: s_mov_b32 s15, s31
-; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -29256,8 +29256,8 @@ define void @s_shuffle_v2i64_v8i64__6_15() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s14, s30
; GFX942-NEXT: s_mov_b32 s15, s31
-; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/sign_extend.ll b/llvm/test/CodeGen/AMDGPU/sign_extend.ll
index 0a12a89ddaa01..d312fc78ed7d2 100644
--- a/llvm/test/CodeGen/AMDGPU/sign_extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/sign_extend.ll
@@ -80,9 +80,9 @@ define amdgpu_kernel void @s_sext_i1_to_i64(ptr addrspace(1) %out, i32 %a, i32 %
; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: s_cmp_eq_u32 s4, s5
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
@@ -94,9 +94,9 @@ define amdgpu_kernel void @s_sext_i1_to_i64(ptr addrspace(1) %out, i32 %a, i32 %
; VI-NEXT: s_mov_b64 s[4:5], s[2:3]
; VI-NEXT: s_cmp_eq_u32 s4, s5
; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll b/llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
index e42d62262a203..75214d121e051 100644
--- a/llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
+++ b/llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
@@ -6,8 +6,8 @@ define amdgpu_kernel void @foo(ptr %0) {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CHECK-NEXT: v_mov_b64_e32 v[0:1], 0
-; CHECK-NEXT: v_mov_b32_e32 v6, v1
; CHECK-NEXT: v_mov_b32_e32 v4, 0
+; CHECK-NEXT: v_mov_b32_e32 v6, v1
; CHECK-NEXT: v_mov_b32_e32 v5, v0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
index cb52a639d12bd..c3b76d1094826 100644
--- a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
@@ -29,17 +29,17 @@ define amdgpu_kernel void @test_simple_indirect_call() {
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX9-NEXT: s_add_u32 s0, s0, s17
; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_getpc_b64 s[18:19]
-; GFX9-NEXT: s_add_u32 s18, s18, indirect at rel32@lo+4
-; GFX9-NEXT: s_addc_u32 s19, s19, indirect at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s13, s15
; GFX9-NEXT: s_mov_b32 s12, s14
; GFX9-NEXT: s_mov_b64 s[14:15], src_private_base
-; GFX9-NEXT: v_mov_b32_e32 v5, s18
+; GFX9-NEXT: s_getpc_b64 s[18:19]
+; GFX9-NEXT: s_add_u32 s18, s18, indirect at rel32@lo+4
+; GFX9-NEXT: s_addc_u32 s19, s19, indirect at rel32@hi+12
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_mov_b32_e32 v4, s15
+; GFX9-NEXT: v_mov_b32_e32 v5, s18
; GFX9-NEXT: v_mov_b32_e32 v6, s19
; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
; GFX9-NEXT: s_mov_b32 s14, s16
diff --git a/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
index 101787abf8ea7..f1f0d737b08fc 100644
--- a/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
@@ -61,9 +61,9 @@ define amdgpu_kernel void @sint_to_fp_i1_f64(ptr addrspace(1) %out, i32 %in) {
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_cmp_eq_u32 s2, 0
; CI-NEXT: s_cselect_b32 s2, 0xbff00000, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, s2
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -78,9 +78,9 @@ define amdgpu_kernel void @sint_to_fp_i1_f64(ptr addrspace(1) %out, i32 %in) {
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0xbff00000, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -356,9 +356,9 @@ define amdgpu_kernel void @s_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_cmp_eq_u32 s2, 0
; CI-NEXT: s_cselect_b32 s2, 0xbff00000, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, s2
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -373,9 +373,9 @@ define amdgpu_kernel void @s_select_sint_to_fp_i1_vals_f64(ptr addrspace(1) %out
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0xbff00000, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -437,9 +437,9 @@ define amdgpu_kernel void @s_select_sint_to_fp_i1_vals_i64(ptr addrspace(1) %out
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_cmp_eq_u32 s2, 0
; CI-NEXT: s_cselect_b32 s2, 0xbff00000, 0
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, s2
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -454,9 +454,9 @@ define amdgpu_kernel void @s_select_sint_to_fp_i1_vals_i64(ptr addrspace(1) %out
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0xbff00000, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -549,9 +549,9 @@ define amdgpu_kernel void @s_swap_select_sint_to_fp_i1_vals_f64(ptr addrspace(1)
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_cmp_eq_u32 s2, 0
; CI-NEXT: s_cselect_b32 s2, 0, 0xbff00000
-; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, s2
+; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm
@@ -566,9 +566,9 @@ define amdgpu_kernel void @s_swap_select_sint_to_fp_i1_vals_f64(ptr addrspace(1)
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0, 0xbff00000
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll b/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
index 41ffd01fc7e23..c88557e7d0ea3 100644
--- a/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
@@ -7,9 +7,9 @@ define protected amdgpu_kernel void @test(ptr addrspace(1) %in, ptr addrspace(1)
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX942-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-NEXT: v_mov_b32_e32 v1, v0
; GFX942-NEXT: v_mov_b32_e32 v2, v0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
; GFX942-NEXT: v_mov_b64_e32 v[12:13], v[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index cb9091edb07aa..274588b57e3d1 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -359,9 +359,9 @@ define amdgpu_kernel void @s_abs_v4i16(ptr addrspace(1) %out, <4 x i16> %val) #0
; VI-NEXT: s_or_b32 s2, s4, s2
; VI-NEXT: s_add_i32 s3, s3, 0x20000
; VI-NEXT: s_add_i32 s2, s2, 0x20000
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr.ll b/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
index f2dd473162034..ef9d444a5589c 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr.ll
@@ -31,9 +31,9 @@ define amdgpu_kernel void @max_12regs_13a_used(i32 %cond, ptr addrspace(1) %arg,
; GFX908-NEXT: .LBB0_2: ; %use
; GFX908-NEXT: s_nop 2
; GFX908-NEXT: v_accvgpr_read_b32 v1, a4
-; GFX908-NEXT: v_accvgpr_read_b32 v4, a7
; GFX908-NEXT: v_accvgpr_read_b32 v2, a5
; GFX908-NEXT: v_accvgpr_read_b32 v3, a6
+; GFX908-NEXT: v_accvgpr_read_b32 v4, a7
; GFX908-NEXT: v_accvgpr_write_b32 a4, 4
; GFX908-NEXT: v_accvgpr_write_b32 a8, 5
; GFX908-NEXT: v_accvgpr_write_b32 a9, 1
@@ -83,6 +83,7 @@ define amdgpu_kernel void @max_12regs_13a_used(i32 %cond, ptr addrspace(1) %arg,
; GFX90A-NEXT: v_accvgpr_read_b32 v7, a5
; GFX90A-NEXT: v_accvgpr_read_b32 v6, a4
; GFX90A-NEXT: v_accvgpr_write_b32 a4, 4
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_accvgpr_write_b32 a8, 5
; GFX90A-NEXT: v_accvgpr_write_b32 a9, 1
; GFX90A-NEXT: v_accvgpr_write_b32 a10, 2
@@ -90,7 +91,6 @@ define amdgpu_kernel void @max_12regs_13a_used(i32 %cond, ptr addrspace(1) %arg,
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_accvgpr_write_b32 a4, v6
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_accvgpr_write_b32 a5, v7
; GFX90A-NEXT: v_accvgpr_write_b32 a6, v8
; GFX90A-NEXT: v_accvgpr_write_b32 a7, v9
@@ -128,9 +128,9 @@ define amdgpu_kernel void @max_10_vgprs_used_9a() #1 {
; GFX908-NEXT: ;;#ASMSTART
; GFX908-NEXT: ;;#ASMEND
; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
-; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
+; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
; GFX908-NEXT: ;;#ASMSTART
; GFX908-NEXT: ;;#ASMEND
; GFX908-NEXT: ;;#ASMSTART
@@ -139,8 +139,8 @@ define amdgpu_kernel void @max_10_vgprs_used_9a() #1 {
; GFX908-NEXT: ;;#ASMEND
; GFX908-NEXT: v_accvgpr_read_b32 v5, a2
; GFX908-NEXT: v_accvgpr_read_b32 v4, a1
-; GFX908-NEXT: v_accvgpr_write_b32 a4, v3
; GFX908-NEXT: v_accvgpr_write_b32 a1, v0
+; GFX908-NEXT: v_accvgpr_write_b32 a4, v3
; GFX908-NEXT: v_accvgpr_write_b32 a3, v2
; GFX908-NEXT: v_accvgpr_write_b32 a2, v1
; GFX908-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
index 10b65e26875bb..16ae055fb112d 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
@@ -10375,8 +10375,8 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20e0
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[19:22], s0 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20f0
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v11
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[7:10], s0 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v11
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v12
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v13
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v14
@@ -10521,89 +10521,89 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: ;;#ASMEND
; GFX10-FLATSCR-NEXT: s_movk_i32 s0, 0x2010
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v88, v58
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v92, v62
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v87, v57
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v86, v56
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v85, v55
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v92, v62
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v91, v61
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v90, v60
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v89, v59
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v60, v34
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[63:66], s0 ; 16-byte Folded Spill
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v68, v38
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v59, v33
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v58, v32
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v57, v31
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[63:66], s0 ; 16-byte Folded Spill
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v68, v38
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v67, v37
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v66, v36
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v65, v35
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v36, v10
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v72, v42
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v76, v46
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v80, v50
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v84, v54
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v35, v9
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v34, v8
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, v7
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v72, v42
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v71, v41
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v70, v40
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v69, v39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v40, v14
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v39, v13
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v38, v12
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v37, v11
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v76, v46
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v75, v45
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v74, v44
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v73, v43
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v44, v18
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v43, v17
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v42, v16
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v41, v15
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v80, v50
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v79, v49
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v78, v48
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v77, v47
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v48, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v47, v21
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v46, v20
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v45, v19
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v84, v54
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v83, v53
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v82, v52
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v81, v51
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v52, v26
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v56, v30
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v35, v9
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v34, v8
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v37, v11
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v41, v15
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v45, v19
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v49, v23
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v53, v27
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v39, v13
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v38, v12
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v43, v17
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v42, v16
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v47, v21
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v46, v20
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v51, v25
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v50, v24
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v49, v23
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v56, v30
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v55, v29
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v54, v28
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v53, v27
; GFX10-FLATSCR-NEXT: ;;#ASMSTART
; GFX10-FLATSCR-NEXT: ;;#ASMEND
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, v33
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, v56
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v29, v55
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v28, v54
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v27, v53
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, v49
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v19, v45
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v41
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v11, v37
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v8, v34
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v35
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v36
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v57
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v28, v54
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v29, v55
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, v56
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v50
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v25, v51
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v26, v52
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v19, v45
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v20, v46
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v21, v47
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v22, v48
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v41
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v42
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v17, v43
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v44
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v11, v37
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v12, v38
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v13, v39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, v40
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, v33
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v8, v34
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v35
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v36
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v57
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v58
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, v59
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v34, v60
@@ -10615,26 +10615,26 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v38, v68
; GFX10-FLATSCR-NEXT: scratch_load_dwordx4 v[63:66], off, s0 ; 16-byte Folded Reload
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v59, v89
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v55, v85
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v51, v81
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v47, v77
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v43, v73
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v39, v69
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v60, v90
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v61, v91
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v62, v92
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v55, v85
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v56, v86
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v57, v87
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v58, v88
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v51, v81
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v52, v82
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v53, v83
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v54, v84
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v47, v77
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v48, v78
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v49, v79
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v50, v80
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v43, v73
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v44, v74
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v45, v75
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v46, v76
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v39, v69
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v40, v70
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v41, v71
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v42, v72
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
index f08b68f9b8c38..64a4133e97761 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
@@ -527,13 +527,13 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_cbranch_execz .LBB0_3
; CHECK-NEXT: ; %bb.2: ; %bb2
; CHECK-NEXT: v_accvgpr_write_b32 a10, v42
-; CHECK-NEXT: v_accvgpr_write_b32 a14, v48
-; CHECK-NEXT: v_accvgpr_write_b32 a4, v56
-; CHECK-NEXT: v_accvgpr_write_b32 a2, v50
; CHECK-NEXT: v_accvgpr_write_b32 a11, v43
; CHECK-NEXT: v_accvgpr_write_b32 a8, v40
+; CHECK-NEXT: v_accvgpr_write_b32 a14, v48
; CHECK-NEXT: v_accvgpr_write_b32 a15, v49
+; CHECK-NEXT: v_accvgpr_write_b32 a4, v56
; CHECK-NEXT: v_accvgpr_write_b32 a5, v57
+; CHECK-NEXT: v_accvgpr_write_b32 a2, v50
; CHECK-NEXT: v_accvgpr_write_b32 a3, v51
; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1000 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1004 ; 4-byte Folded Reload
@@ -571,6 +571,7 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_accvgpr_write_b32 a17, v59
; CHECK-NEXT: v_accvgpr_read_b32 v60, a36
; CHECK-NEXT: v_accvgpr_read_b32 v58, a40
+; CHECK-NEXT: v_accvgpr_read_b32 v59, a17
; CHECK-NEXT: s_xor_b64 s[54:55], exec, -1
; CHECK-NEXT: s_waitcnt vmcnt(29)
; CHECK-NEXT: v_xor_b32_e32 v28, v28, v18
@@ -646,14 +647,13 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_xor_b32_e32 v14, v40, v14
; CHECK-NEXT: v_and_b32_e32 v15, 0x7fffffff, v15
; CHECK-NEXT: v_accvgpr_read_b32 v57, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v43, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v49, a15
-; CHECK-NEXT: v_accvgpr_read_b32 v51, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v59, a17
; CHECK-NEXT: v_accvgpr_read_b32 v56, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v43, a11
; CHECK-NEXT: v_accvgpr_read_b32 v42, a10
; CHECK-NEXT: v_accvgpr_read_b32 v40, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v49, a15
; CHECK-NEXT: v_accvgpr_read_b32 v48, a14
+; CHECK-NEXT: v_accvgpr_read_b32 v51, a3
; CHECK-NEXT: v_accvgpr_read_b32 v50, a2
; CHECK-NEXT: v_accvgpr_read_b32 v58, a16
; CHECK-NEXT: s_waitcnt vmcnt(1)
@@ -906,9 +906,11 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:1128 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:1132 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a28
; CHECK-NEXT: v_accvgpr_read_b32 v5, a29
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v5
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a28
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a27
+; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; CHECK-NEXT: v_and_b32_e32 v31, 0x7fffffff, v31
; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v33
; CHECK-NEXT: v_and_b32_e32 v29, 0x7fffffff, v29
@@ -928,11 +930,9 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_alignbit_b32 v2, v5, v4, 15
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v35, vcc
; CHECK-NEXT: flat_store_dword v[0:1], v2
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a26
-; CHECK-NEXT: v_accvgpr_read_b32 v3, a27
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v10
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
-; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a26
; CHECK-NEXT: v_or_b32_e32 v9, v1, v0
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v4
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[2:3]
@@ -1190,59 +1190,59 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1476 ; 4-byte Folded Reload
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v10
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a33
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: v_lshrrev_b64 v[42:43], 1, v[42:43]
+; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v8
; CHECK-NEXT: v_accvgpr_read_b32 v8, a32
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a33
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: v_lshrrev_b64 v[42:43], 1, v[42:43]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[6:7]
; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[8:9]
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a35
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: v_accvgpr_read_b32 v6, a34
-; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a35
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v8
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a24
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_accvgpr_read_b32 v9, a25
-; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[6:7]
+; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v8
+; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[6:7]
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a24
; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[8:9]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a23
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v8
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[58:59]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:64
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v58
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[50:51]
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a20
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a22
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_accvgpr_read_b32 v9, a21
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v50
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[6:7]
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a20
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[8:9]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v8
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[56:57]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:32
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v56
@@ -1331,294 +1331,294 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:1392 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword a31, off, s[0:3], s32 offset:1396 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a30
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a31
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a32
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a28
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a33
; CHECK-NEXT: v_accvgpr_read_b32 v32, a34
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a35
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a36
; CHECK-NEXT: v_accvgpr_read_b32 v36, a38
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a28
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a60
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a21
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a24
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a25
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a26
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a27
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a29
; CHECK-NEXT: v_accvgpr_read_b32 v37, a39
+; CHECK-NEXT: v_accvgpr_read_b32 v48, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v59, a61
+; CHECK-NEXT: v_accvgpr_read_b32 v49, a51
+; CHECK-NEXT: v_accvgpr_read_b32 v53, a55
+; CHECK-NEXT: v_accvgpr_read_b32 v41, a43
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a36
; CHECK-NEXT: v_accvgpr_read_b32 v38, a40
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a35
; CHECK-NEXT: v_accvgpr_read_b32 v39, a41
-; CHECK-NEXT: v_accvgpr_read_b32 v59, a61
-; CHECK-NEXT: v_cndmask_b32_e64 v36, v28, v32, s[44:45]
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a31
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a63
+; CHECK-NEXT: v_accvgpr_read_b32 v52, a54
+; CHECK-NEXT: v_accvgpr_read_b32 v40, a42
+; CHECK-NEXT: v_accvgpr_read_b32 v51, a53
+; CHECK-NEXT: v_accvgpr_read_b32 v50, a52
+; CHECK-NEXT: v_accvgpr_read_b32 v55, a57
+; CHECK-NEXT: v_accvgpr_read_b32 v43, a45
+; CHECK-NEXT: v_accvgpr_read_b32 v54, a56
+; CHECK-NEXT: v_accvgpr_read_b32 v42, a44
+; CHECK-NEXT: v_accvgpr_read_b32 v35, a37
+; CHECK-NEXT: v_accvgpr_read_b32 v44, a46
+; CHECK-NEXT: v_accvgpr_read_b32 v45, a47
+; CHECK-NEXT: v_accvgpr_read_b32 v46, a48
+; CHECK-NEXT: v_accvgpr_read_b32 v47, a49
+; CHECK-NEXT: v_accvgpr_read_b32 v56, a58
+; CHECK-NEXT: v_accvgpr_read_b32 v57, a59
+; CHECK-NEXT: v_accvgpr_read_b32 v58, a60
+; CHECK-NEXT: v_accvgpr_read_b32 v60, a62
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a28
+; CHECK-NEXT: v_accvgpr_read_b32 v61, a63
; CHECK-NEXT: v_accvgpr_read_b32 v34, a30
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
-; CHECK-NEXT: v_cndmask_b32_e64 v37, v59, v29, s[44:45]
-; CHECK-NEXT: v_cndmask_b32_e64 v39, v31, v33, s[40:41]
-; CHECK-NEXT: v_cndmask_b32_e64 v38, v30, v34, s[40:41]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a27
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a21
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a24
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a21
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a28
; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a60
; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v49, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a25
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a24
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a53
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
; CHECK-NEXT: v_accvgpr_read_b32 v24, a56
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a57
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a58
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a59
-; CHECK-NEXT: v_cndmask_b32_e64 v49, v25, v29, s[42:43]
+; CHECK-NEXT: v_accvgpr_read_b32 v17, a17
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a25
+; CHECK-NEXT: v_cndmask_b32_e64 v36, v28, v32, s[44:45]
; CHECK-NEXT: v_accvgpr_read_b32 v28, a24
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a53
; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a30
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a58
-; CHECK-NEXT: v_accvgpr_read_b32 v48, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v50, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v51, a53
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a29
; CHECK-NEXT: v_accvgpr_read_b32 v25, a21
; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a53
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a24
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
; CHECK-NEXT: v_accvgpr_read_b32 v24, a56
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a27
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a59
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a26
+; CHECK-NEXT: v_cndmask_b32_e64 v37, v59, v29, s[44:45]
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a25
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a57
+; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a53
; CHECK-NEXT: v_cndmask_b32_e64 v48, v24, v28, s[42:43]
-; CHECK-NEXT: v_cndmask_b32_e64 v51, v27, v33, s[26:27]
-; CHECK-NEXT: v_cndmask_b32_e64 v50, v26, v34, s[26:27]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v53, a55
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a20
+; CHECK-NEXT: v_cndmask_b32_e64 v49, v25, v29, s[42:43]
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a21
; CHECK-NEXT: v_accvgpr_read_b32 v29, a21
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
+; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
; CHECK-NEXT: v_accvgpr_read_b32 v21, a53
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v13, a13
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a17
; CHECK-NEXT: v_cndmask_b32_e64 v53, v21, v29, s[28:29]
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a17
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a12
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a9
+; CHECK-NEXT: v_cndmask_b32_e64 v41, v17, v29, s[24:25]
+; CHECK-NEXT: v_accvgpr_read_b32 v13, a45
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a13
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a9
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v17, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a41
+; CHECK-NEXT: v_cndmask_b32_e64 v17, v13, v29, s[20:21]
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a9
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
+; CHECK-NEXT: v_cndmask_b32_e64 v21, v9, v29, s[16:17]
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a37
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a2
+; CHECK-NEXT: v_cndmask_b32_e64 v25, v5, v29, s[12:13]
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a32
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a33
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
+; CHECK-NEXT: v_cndmask_b32_e64 v29, v1, v29, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v28, v0, v28, s[4:5]
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a20
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a30
; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a32
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a31
+; CHECK-NEXT: v_cndmask_b32_e64 v38, v30, v34, s[40:41]
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a33
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a59
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
; CHECK-NEXT: v_accvgpr_read_b32 v30, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a31
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a63
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a22
; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a23
; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v52, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v54, a56
-; CHECK-NEXT: v_accvgpr_read_b32 v55, a57
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v12, a12
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
+; CHECK-NEXT: v_cndmask_b32_e64 v39, v31, v33, s[40:41]
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a58
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a59
; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v40, a42
-; CHECK-NEXT: v_accvgpr_read_b32 v41, a43
-; CHECK-NEXT: v_accvgpr_read_b32 v42, a44
-; CHECK-NEXT: v_accvgpr_read_b32 v43, a45
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
; CHECK-NEXT: v_cndmask_b32_e64 v52, v20, v24, s[28:29]
-; CHECK-NEXT: v_cndmask_b32_e64 v55, v23, v33, s[22:23]
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a16
-; CHECK-NEXT: v_cndmask_b32_e64 v54, v22, v34, s[22:23]
; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a14
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
+; CHECK-NEXT: v_cndmask_b32_e64 v51, v27, v33, s[26:27]
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a19
; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a9
-; CHECK-NEXT: v_accvgpr_read_b32 v10, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v11, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v12, a12
-; CHECK-NEXT: v_accvgpr_read_b32 v13, a13
-; CHECK-NEXT: v_accvgpr_read_b32 v14, a14
-; CHECK-NEXT: v_accvgpr_read_b32 v15, a15
-; CHECK-NEXT: v_cndmask_b32_e64 v41, v17, v29, s[24:25]
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
; CHECK-NEXT: v_cndmask_b32_e64 v40, v16, v20, s[24:25]
-; CHECK-NEXT: v_cndmask_b32_e64 v43, v19, v33, s[18:19]
-; CHECK-NEXT: v_cndmask_b32_e64 v42, v18, v34, s[18:19]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a15
-; CHECK-NEXT: v_accvgpr_read_b32 v0, a32
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a14
; CHECK-NEXT: v_accvgpr_read_b32 v12, a44
-; CHECK-NEXT: v_accvgpr_read_b32 v13, a45
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a13
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a12
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a12
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a58
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
; CHECK-NEXT: v_accvgpr_read_b32 v27, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a9
; CHECK-NEXT: v_accvgpr_read_b32 v24, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a5
; CHECK-NEXT: v_accvgpr_read_b32 v20, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a12
-; CHECK-NEXT: v_cndmask_b32_e64 v17, v13, v29, s[20:21]
; CHECK-NEXT: v_cndmask_b32_e64 v16, v12, v30, s[20:21]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a41
; CHECK-NEXT: v_accvgpr_read_b32 v30, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a9
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v15, a15
+; CHECK-NEXT: v_cndmask_b32_e64 v50, v26, v34, s[26:27]
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
+; CHECK-NEXT: v_cndmask_b32_e64 v55, v23, v33, s[22:23]
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a40
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a7
; CHECK-NEXT: v_accvgpr_read_b32 v27, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a5
; CHECK-NEXT: v_accvgpr_read_b32 v24, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a15
-; CHECK-NEXT: v_cndmask_b32_e64 v21, v9, v29, s[16:17]
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a0
; CHECK-NEXT: v_accvgpr_read_b32 v30, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a40
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v11, a11
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a22
; CHECK-NEXT: v_accvgpr_read_b32 v15, a47
+; CHECK-NEXT: v_cndmask_b32_e64 v43, v19, v33, s[18:19]
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a15
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a10
; CHECK-NEXT: v_accvgpr_read_b32 v19, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a14
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a15
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a3
; CHECK-NEXT: v_accvgpr_read_b32 v27, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a3
; CHECK-NEXT: v_accvgpr_read_b32 v24, a2
-; CHECK-NEXT: v_cndmask_b32_e64 v19, v15, v33, s[14:15]
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a11
; CHECK-NEXT: v_cndmask_b32_e64 v20, v8, v30, s[16:17]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v5, a37
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v14, a14
+; CHECK-NEXT: v_cndmask_b32_e64 v54, v22, v34, s[22:23]
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a36
; CHECK-NEXT: v_accvgpr_read_b32 v11, a43
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a6
+; CHECK-NEXT: v_cndmask_b32_e64 v19, v15, v33, s[14:15]
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a11
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a6
; CHECK-NEXT: v_accvgpr_read_b32 v23, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a11
; CHECK-NEXT: v_accvgpr_read_b32 v27, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a1
-; CHECK-NEXT: v_cndmask_b32_e64 v23, v11, v33, s[10:11]
-; CHECK-NEXT: v_cndmask_b32_e64 v25, v5, v29, s[12:13]
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a0
; CHECK-NEXT: v_accvgpr_read_b32 v30, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a36
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v10, a10
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a30
; CHECK-NEXT: v_accvgpr_read_b32 v7, a39
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a6
-; CHECK-NEXT: v_cndmask_b32_e64 v24, v4, v30, s[12:13]
-; CHECK-NEXT: v_cndmask_b32_e64 v27, v7, v33, s[6:7]
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v1, a33
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
-; CHECK-NEXT: v_cndmask_b32_e64 v29, v1, v29, s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e64 v28, v0, v28, s[4:5]
-; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
; CHECK-NEXT: v_accvgpr_read_b32 v14, a46
+; CHECK-NEXT: v_cndmask_b32_e64 v42, v18, v34, s[18:19]
; CHECK-NEXT: v_accvgpr_read_b32 v18, a2
; CHECK-NEXT: v_accvgpr_read_b32 v34, a14
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a4
+; CHECK-NEXT: v_cndmask_b32_e64 v23, v11, v33, s[10:11]
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a7
+; CHECK-NEXT: v_cndmask_b32_e64 v24, v4, v30, s[12:13]
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a26
; CHECK-NEXT: v_accvgpr_read_b32 v2, a34
; CHECK-NEXT: v_accvgpr_read_b32 v3, a35
; CHECK-NEXT: v_accvgpr_read_b32 v10, a42
; CHECK-NEXT: v_cndmask_b32_e64 v18, v14, v34, s[14:15]
; CHECK-NEXT: v_accvgpr_read_b32 v22, a0
; CHECK-NEXT: v_accvgpr_read_b32 v34, a10
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a2
+; CHECK-NEXT: v_cndmask_b32_e64 v27, v7, v33, s[6:7]
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a3
; CHECK-NEXT: v_accvgpr_read_b32 v31, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a22
; CHECK-NEXT: v_accvgpr_read_b32 v6, a38
; CHECK-NEXT: v_cndmask_b32_e64 v22, v10, v34, s[10:11]
; CHECK-NEXT: v_accvgpr_read_b32 v26, a0
; CHECK-NEXT: v_accvgpr_read_b32 v34, a6
; CHECK-NEXT: v_cndmask_b32_e64 v31, v3, v33, s[8:9]
; CHECK-NEXT: v_cndmask_b32_e64 v30, v2, v30, s[8:9]
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a18
; CHECK-NEXT: v_cndmask_b32_e64 v26, v6, v34, s[6:7]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[28:31]
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[24:27] offset:16
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[20:23] offset:32
-; CHECK-NEXT: v_accvgpr_read_b32 v35, a37
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a14
; CHECK-NEXT: v_add_co_u32_e32 v20, vcc, 48, v0
; CHECK-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v1, vcc
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a10
; CHECK-NEXT: v_add_co_u32_e32 v4, vcc, 0x70, v0
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a6
; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; CHECK-NEXT: v_accvgpr_read_b32 v44, a46
-; CHECK-NEXT: v_accvgpr_read_b32 v45, a47
-; CHECK-NEXT: v_accvgpr_read_b32 v46, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v47, a49
-; CHECK-NEXT: v_accvgpr_read_b32 v56, a58
-; CHECK-NEXT: v_accvgpr_read_b32 v57, a59
-; CHECK-NEXT: v_accvgpr_read_b32 v58, a60
-; CHECK-NEXT: v_accvgpr_read_b32 v60, a62
-; CHECK-NEXT: v_accvgpr_read_b32 v61, a63
; CHECK-NEXT: v_accvgpr_read_b32 v32, a2
; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[40:43] offset:64
diff --git a/llvm/test/CodeGen/AMDGPU/srem.ll b/llvm/test/CodeGen/AMDGPU/srem.ll
index fa0a2b61652ed..618dfe78983df 100644
--- a/llvm/test/CodeGen/AMDGPU/srem.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem.ll
@@ -1657,8 +1657,8 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in)
; GCN-NEXT: s_cmp_ge_u32 s3, s2
; GCN-NEXT: s_cselect_b32 s8, s4, s3
; GCN-NEXT: .LBB8_5: ; %.split
-; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: v_mov_b32_e32 v2, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: v_mov_b32_e32 v1, s9
; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GCN-NEXT: s_endpgm
@@ -3367,8 +3367,8 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: s_add_u32 s0, s6, 16
; TONGA-NEXT: s_addc_u32 s1, s7, 0
; TONGA-NEXT: v_mov_b32_e32 v0, s0
-; TONGA-NEXT: v_mov_b32_e32 v4, s6
; TONGA-NEXT: v_mov_b32_e32 v1, s1
+; TONGA-NEXT: v_mov_b32_e32 v4, s6
; TONGA-NEXT: v_mov_b32_e32 v5, s7
; TONGA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; TONGA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
@@ -6205,12 +6205,12 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
; TONGA-NEXT: s_waitcnt lgkmcnt(0)
; TONGA-NEXT: s_add_u32 s0, s6, 48
-; TONGA-NEXT: v_mov_b32_e32 v0, s6
; TONGA-NEXT: s_addc_u32 s1, s7, 0
-; TONGA-NEXT: v_mov_b32_e32 v1, s7
; TONGA-NEXT: s_add_u32 s2, s6, 32
-; TONGA-NEXT: flat_load_dwordx4 v[14:17], v[0:1]
+; TONGA-NEXT: v_mov_b32_e32 v0, s6
+; TONGA-NEXT: v_mov_b32_e32 v1, s7
; TONGA-NEXT: s_addc_u32 s3, s7, 0
+; TONGA-NEXT: flat_load_dwordx4 v[14:17], v[0:1]
; TONGA-NEXT: v_mov_b32_e32 v0, s2
; TONGA-NEXT: v_mov_b32_e32 v1, s3
; TONGA-NEXT: flat_load_dwordx4 v[10:13], v[0:1]
@@ -6800,11 +6800,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; TONGA-NEXT: v_cndmask_b32_e32 v14, v0, v1, vcc
; TONGA-NEXT: .LBB12_21: ; %.split.split.split.split
+; TONGA-NEXT: s_add_u32 s0, s4, 16
; TONGA-NEXT: v_mov_b32_e32 v0, s4
; TONGA-NEXT: v_mov_b32_e32 v1, s5
-; TONGA-NEXT: s_add_u32 s0, s4, 16
-; TONGA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; TONGA-NEXT: s_addc_u32 s1, s5, 0
+; TONGA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; TONGA-NEXT: v_mov_b32_e32 v0, s0
; TONGA-NEXT: v_mov_b32_e32 v1, s1
; TONGA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index e2f7534ce838a..082620a68e1b5 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -437,8 +437,8 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v16
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: v_mov_b32_e32 v10, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
@@ -1129,9 +1129,9 @@ define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -1395,9 +1395,9 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -1889,8 +1889,8 @@ define i64 @v_test_srem_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
@@ -2081,8 +2081,8 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
@@ -2181,10 +2181,10 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
-; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
+; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
@@ -2530,10 +2530,10 @@ define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
-; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
+; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB18_3
diff --git a/llvm/test/CodeGen/AMDGPU/ssubo.ll b/llvm/test/CodeGen/AMDGPU/ssubo.ll
index ccb21c960e3f3..9cce1b5e6e601 100644
--- a/llvm/test/CodeGen/AMDGPU/ssubo.ll
+++ b/llvm/test/CodeGen/AMDGPU/ssubo.ll
@@ -123,8 +123,9 @@ define amdgpu_kernel void @ssubo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b)
; GFX11-NEXT: s_cselect_b64 s[2:3], 1, 0
; GFX11-NEXT: s_add_u32 s2, s4, s2
; GFX11-NEXT: s_addc_u32 s3, s5, s3
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
%ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
@@ -400,9 +401,9 @@ define amdgpu_kernel void @s_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: s_sub_u32 s0, s4, s6
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: s_subb_u32 s1, s5, s7
; VI-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[4:5]
@@ -425,8 +426,8 @@ define amdgpu_kernel void @s_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, s14
; GFX9-NEXT: s_sub_u32 s0, s12, s14
+; GFX9-NEXT: v_mov_b32_e32 v0, s14
; GFX9-NEXT: v_mov_b32_e32 v1, s15
; GFX9-NEXT: s_subb_u32 s1, s13, s15
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[12:13], v[0:1]
@@ -469,16 +470,15 @@ define amdgpu_kernel void @s_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX11-NEXT: v_cmp_lt_i64_e64 s8, s[4:5], s[6:7]
; GFX11-NEXT: s_sub_u32 s4, s4, s6
; GFX11-NEXT: s_subb_u32 s5, s5, s7
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX11-NEXT: s_cmp_lt_i32 s5, 0
; GFX11-NEXT: s_cselect_b32 s6, -1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b32 s6, s8, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
; GFX11-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s6
-; GFX11-NEXT: v_mov_b32_e32 v1, s5
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: global_store_b8 v2, v3, s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll b/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
index db04d8c1c2678..a53d462eae4e0 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
@@ -16,20 +16,20 @@ define amdgpu_kernel void @kernel_background_evaluate(ptr addrspace(5) %kg, ptr
; MUBUF-NEXT: s_mov_b32 s38, -1
; MUBUF-NEXT: s_mov_b32 s39, 0x31c16000
; MUBUF-NEXT: s_add_u32 s36, s36, s11
-; MUBUF-NEXT: s_addc_u32 s37, s37, 0
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x2000
; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
; MUBUF-NEXT: v_mov_b32_e32 v3, 0
; MUBUF-NEXT: v_mov_b32_e32 v4, 0x400000
+; MUBUF-NEXT: s_addc_u32 s37, s37, 0
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, svm_eval_nodes at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes at rel32@hi+12
+; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39]
; MUBUF-NEXT: s_mov_b32 s32, 0xc0000
; MUBUF-NEXT: ; implicit-def: $sgpr15
; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: v_mov_b32_e32 v0, s0
; MUBUF-NEXT: s_mov_b64 s[0:1], s[36:37]
-; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39]
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
; MUBUF-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; MUBUF-NEXT: s_and_saveexec_b32 s0, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
index 92fb6a3e0f03b..8b6af4861dc9a 100644
--- a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
+++ b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
@@ -890,13 +890,13 @@ define amdgpu_kernel void @kernel_stacksave_stackrestore_call_with_stack_objects
; WAVE32-OPT-NEXT: s_load_dwordx4 s[20:23], s[20:21], 0x0
; WAVE32-OPT-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; WAVE32-OPT-NEXT: s_movk_i32 s32, 0x1200
+; WAVE32-OPT-NEXT: v_mov_b32_e32 v3, 42
+; WAVE32-OPT-NEXT: v_mov_b32_e32 v4, 17
; WAVE32-OPT-NEXT: s_mov_b32 s13, s9
+; WAVE32-OPT-NEXT: v_or3_b32 v31, v0, v1, v2
; WAVE32-OPT-NEXT: s_mov_b32 s12, s8
; WAVE32-OPT-NEXT: s_mov_b64 s[8:9], s[4:5]
; WAVE32-OPT-NEXT: s_mov_b32 s4, s32
-; WAVE32-OPT-NEXT: v_mov_b32_e32 v3, 42
-; WAVE32-OPT-NEXT: v_mov_b32_e32 v4, 17
-; WAVE32-OPT-NEXT: v_or3_b32 v31, v0, v1, v2
; WAVE32-OPT-NEXT: s_mov_b32 s14, s10
; WAVE32-OPT-NEXT: s_mov_b32 s17, stack_passed_argument at abs32@hi
; WAVE32-OPT-NEXT: s_mov_b32 s16, stack_passed_argument at abs32@lo
@@ -927,13 +927,13 @@ define amdgpu_kernel void @kernel_stacksave_stackrestore_call_with_stack_objects
; WAVE64-OPT-NEXT: s_load_dwordx4 s[20:23], s[20:21], 0x0
; WAVE64-OPT-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; WAVE64-OPT-NEXT: s_movk_i32 s32, 0x2400
+; WAVE64-OPT-NEXT: v_mov_b32_e32 v3, 42
+; WAVE64-OPT-NEXT: v_mov_b32_e32 v4, 17
; WAVE64-OPT-NEXT: s_mov_b32 s13, s9
+; WAVE64-OPT-NEXT: v_or3_b32 v31, v0, v1, v2
; WAVE64-OPT-NEXT: s_mov_b32 s12, s8
; WAVE64-OPT-NEXT: s_mov_b64 s[8:9], s[4:5]
; WAVE64-OPT-NEXT: s_mov_b32 s4, s32
-; WAVE64-OPT-NEXT: v_mov_b32_e32 v3, 42
-; WAVE64-OPT-NEXT: v_mov_b32_e32 v4, 17
-; WAVE64-OPT-NEXT: v_or3_b32 v31, v0, v1, v2
; WAVE64-OPT-NEXT: s_mov_b32 s14, s10
; WAVE64-OPT-NEXT: s_mov_b32 s17, stack_passed_argument at abs32@hi
; WAVE64-OPT-NEXT: s_mov_b32 s16, stack_passed_argument at abs32@lo
diff --git a/llvm/test/CodeGen/AMDGPU/store-local.128.ll b/llvm/test/CodeGen/AMDGPU/store-local.128.ll
index a4e23ae87614f..b2b9f5bc93365 100644
--- a/llvm/test/CodeGen/AMDGPU/store-local.128.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-local.128.ll
@@ -67,9 +67,9 @@ define amdgpu_kernel void @store_lds_v4i32(ptr addrspace(3) %out, <4 x i32> %x)
; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x0
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v4, s6
+; GFX11-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: ds_store_b128 v4, v[0:3]
; GFX11-NEXT: s_endpgm
store <4 x i32> %x, ptr addrspace(3) %out
@@ -521,8 +521,8 @@ define amdgpu_kernel void @store_lds_v4i32_align8(ptr addrspace(3) %out, <4 x i3
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v4, s6
; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:1
; GFX9-NEXT: s_endpgm
@@ -535,8 +535,8 @@ define amdgpu_kernel void @store_lds_v4i32_align8(ptr addrspace(3) %out, <4 x i3
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v4, s6
; GFX7-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
; GFX7-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:1
; GFX7-NEXT: s_endpgm
@@ -575,10 +575,9 @@ define amdgpu_kernel void @store_lds_v4i32_align8(ptr addrspace(3) %out, <4 x i3
; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x0
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v4, s6
-; GFX11-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: ds_store_2addr_b64 v4, v[0:1], v[2:3] offset1:1
; GFX11-NEXT: s_endpgm
store <4 x i32> %x, ptr addrspace(3) %out, align 8
@@ -647,9 +646,9 @@ define amdgpu_kernel void @store_lds_v4i32_align16(ptr addrspace(3) %out, <4 x i
; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x0
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v4, s6
+; GFX11-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: ds_store_b128 v4, v[0:3]
; GFX11-NEXT: s_endpgm
store <4 x i32> %x, ptr addrspace(3) %out, align 16
diff --git a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
index eee29e20f96b1..0bc21488c5940 100644
--- a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
@@ -55,8 +55,8 @@ define amdgpu_kernel void @local_store_i55(ptr addrspace(3) %ptr, i55 %arg) #0 {
; HAWAII-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; HAWAII-NEXT: s_add_u32 s0, s8, 14
; HAWAII-NEXT: s_addc_u32 s1, s9, 0
-; HAWAII-NEXT: v_mov_b32_e32 v0, s0
; HAWAII-NEXT: s_mov_b32 flat_scratch_lo, s13
+; HAWAII-NEXT: v_mov_b32_e32 v0, s0
; HAWAII-NEXT: v_mov_b32_e32 v1, s1
; HAWAII-NEXT: flat_load_ubyte v0, v[0:1]
; HAWAII-NEXT: s_load_dword s2, s[8:9], 0x0
@@ -290,8 +290,8 @@ define amdgpu_kernel void @local_store_i65(ptr addrspace(3) %ptr, i65 %arg) #0 {
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: v_mov_b32_e32 v2, s3
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: ds_write_b8 v2, v3 offset:8
; GFX9-NEXT: ds_write_b64 v2, v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/structurize-hoist.ll b/llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
index e52df23c29e9c..007f31062789c 100644
--- a/llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
+++ b/llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
@@ -93,8 +93,8 @@ define amdgpu_kernel void @test_loop_with_if( ptr %ptr, i1 %cond) #0 {
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_bitcmp1_b32 s2, 0
; GFX900-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX900-NEXT: v_mov_b32_e32 v1, s6
; GFX900-NEXT: s_xor_b64 s[4:5], s[2:3], -1
+; GFX900-NEXT: v_mov_b32_e32 v1, s6
; GFX900-NEXT: v_mov_b32_e32 v2, s7
; GFX900-NEXT: s_branch .LBB2_2
; GFX900-NEXT: .LBB2_1: ; %latch
diff --git a/llvm/test/CodeGen/AMDGPU/sub.ll b/llvm/test/CodeGen/AMDGPU/sub.ll
index 02c70fbd970f8..515729b630726 100644
--- a/llvm/test/CodeGen/AMDGPU/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub.ll
@@ -694,8 +694,9 @@ define amdgpu_kernel void @s_sub_i64(ptr addrspace(1) noalias %out, i64 %a, i64
; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_sub_nc_u64 s[2:3], s[2:3], s[4:5]
-; GFX12-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
%result = sub i64 %a, %b
@@ -960,8 +961,8 @@ define amdgpu_kernel void @v_test_sub_v4i64(ptr addrspace(1) %out, ptr addrspace
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v10, v14
; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v11, v15, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v8, v12
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v9, v13, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
index 4621be5cab450..93b5cb3428e82 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
@@ -12,18 +12,18 @@ define amdgpu_kernel void @foobar(float %a0, float %a1, ptr addrspace(1) %out) #
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; CHECK-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CHECK-NEXT: s_mov_b32 s2, -1
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v0, s4
-; CHECK-NEXT: v_mov_b32_e32 v1, s5
; CHECK-NEXT: v_mov_b32_e32 v2, s6
+; CHECK-NEXT: v_mov_b32_e32 v1, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v3, s7
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
; CHECK-NEXT: ; %bb.1: ; %ift
; CHECK-NEXT: s_mov_b32 s4, s5
-; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v2, s6
; CHECK-NEXT: v_mov_b32_e32 v3, s7
; CHECK-NEXT: ; %bb.2: ; %ife
diff --git a/llvm/test/CodeGen/AMDGPU/swdev380865.ll b/llvm/test/CodeGen/AMDGPU/swdev380865.ll
index f16f1202c3991..32de73aed7961 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev380865.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev380865.ll
@@ -15,16 +15,16 @@ define amdgpu_kernel void @_Z6kernelILi4000ELi1EEvPd(ptr addrspace(1) %x.coerce)
; CHECK-LABEL: _Z6kernelILi4000ELi1EEvPd:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_mov_b64 s[2:3], 0x100
-; CHECK-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x0
; CHECK-NEXT: s_mov_b64 s[0:1], 0
+; CHECK-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x0
+; CHECK-NEXT: s_mov_b32 s2, 0
; CHECK-NEXT: s_load_dword s0, s[0:1], 0x0
; CHECK-NEXT: s_mov_b32 s1, 0
-; CHECK-NEXT: s_mov_b32 s2, 0
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v0, s6
; CHECK-NEXT: s_mov_b32 s3, 0x40260000
; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: s_mov_b32 s5, 0x40280000
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v0, s6
; CHECK-NEXT: v_mov_b32_e32 v1, s7
; CHECK-NEXT: .LBB0_1: ; %for.cond4.preheader
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/trap-abis.ll b/llvm/test/CodeGen/AMDGPU/trap-abis.ll
index 822f4a2cd8c61..b8a5194ab3ae7 100644
--- a/llvm/test/CodeGen/AMDGPU/trap-abis.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap-abis.ll
@@ -137,8 +137,8 @@ define amdgpu_kernel void @non_entry_trap(ptr addrspace(1) nocapture readonly %a
; HSA-TRAP-GFX803-NEXT: v_cmp_eq_u32_e32 vcc, -1, v0
; HSA-TRAP-GFX803-NEXT: s_cbranch_vccz .LBB1_2
; HSA-TRAP-GFX803-NEXT: ; %bb.1: ; %ret
-; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 3
+; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v0, s0
; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2
; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0)
@@ -431,9 +431,9 @@ define amdgpu_kernel void @debugtrap(ptr addrspace(1) nocapture readonly %arg0)
; HSA-TRAP-GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; HSA-TRAP-GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v3, 2
; HSA-TRAP-GFX803-NEXT: s_waitcnt lgkmcnt(0)
; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v0, s0
-; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v3, 2
; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v1, s1
; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2
; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/trunc.ll b/llvm/test/CodeGen/AMDGPU/trunc.ll
index 76f60f1e5dbfc..a6c126a937e2a 100644
--- a/llvm/test/CodeGen/AMDGPU/trunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/trunc.ll
@@ -99,8 +99,8 @@ define amdgpu_kernel void @trunc_shl_i64(ptr addrspace(1) %out2, ptr addrspace(1
; SI-NEXT: s_mov_b32 s1, s3
; SI-NEXT: s_mov_b32 s2, s6
; SI-NEXT: s_mov_b32 s3, s7
-; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: s_addc_u32 s9, s9, 0
+; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s8
diff --git a/llvm/test/CodeGen/AMDGPU/uaddo.ll b/llvm/test/CodeGen/AMDGPU/uaddo.ll
index 4ef1782323563..d8d8766284b29 100644
--- a/llvm/test/CodeGen/AMDGPU/uaddo.ll
+++ b/llvm/test/CodeGen/AMDGPU/uaddo.ll
@@ -1328,8 +1328,8 @@ define amdgpu_kernel void @uaddo_carry_of_add_carryout_used(ptr addrspace(1) %ou
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: s_and_b64 s[0:1], vcc, exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
-; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v1, s0
+; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 17a579c59eeb3..8dcdf95c0ead7 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -1778,8 +1778,8 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: s_add_u32 s4, s2, 4
; GCN-NEXT: s_addc_u32 s5, s3, 0
; GCN-NEXT: s_add_u32 s6, s2, 2
-; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: s_addc_u32 s7, s3, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: s_add_u32 s4, s2, 6
; GCN-NEXT: s_addc_u32 s5, s3, 0
@@ -1787,8 +1787,8 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mov_b32_e32 v3, s5
; GCN-NEXT: flat_load_ubyte v4, v[2:3]
; GCN-NEXT: flat_load_ushort v5, v[0:1]
-; GCN-NEXT: v_mov_b32_e32 v2, s6
; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: v_mov_b32_e32 v2, s6
; GCN-NEXT: v_mov_b32_e32 v3, s7
; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: flat_load_ubyte v2, v[2:3]
@@ -2024,8 +2024,8 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: s_add_u32 s4, s2, 4
; GCN-NEXT: s_addc_u32 s5, s3, 0
; GCN-NEXT: s_add_u32 s6, s2, 2
-; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: s_addc_u32 s7, s3, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: s_add_u32 s4, s2, 6
; GCN-NEXT: s_addc_u32 s5, s3, 0
@@ -2033,8 +2033,8 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mov_b32_e32 v3, s5
; GCN-NEXT: flat_load_ubyte v4, v[2:3]
; GCN-NEXT: flat_load_ushort v5, v[0:1]
-; GCN-NEXT: v_mov_b32_e32 v2, s6
; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: v_mov_b32_e32 v2, s6
; GCN-NEXT: v_mov_b32_e32 v3, s7
; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: flat_load_ubyte v2, v[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index 2443d511cf199..a37f09722d39d 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -190,9 +190,9 @@ define amdgpu_kernel void @s_test_udiv_i64(ptr addrspace(1) %out, i64 %x, i64 %y
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[2:3]
; GCN-IR-NEXT: .LBB0_5: ; %udiv-end
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -376,8 +376,8 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v7
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v7
; GCN-IR-NEXT: v_mov_b32_e32 v8, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
@@ -1065,9 +1065,9 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3]
; GCN-IR-NEXT: .LBB8_5: ; %udiv-end
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -1237,8 +1237,8 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
@@ -1320,10 +1320,10 @@ define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; GCN-IR-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
-; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v7, v5
+; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v7, v5
; GCN-IR-NEXT: v_mov_b32_e32 v6, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3
@@ -1433,9 +1433,9 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x)
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3]
; GCN-IR-NEXT: .LBB11_5: ; %udiv-end
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -1522,10 +1522,10 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; GCN-IR-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
-; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v7, v5
+; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v7, v5
; GCN-IR-NEXT: v_mov_b32_e32 v6, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
@@ -1858,10 +1858,10 @@ define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GCN-IR-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
-; GCN-IR-NEXT: v_or_b32_e32 v1, v7, v1
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v7, v3
+; GCN-IR-NEXT: v_or_b32_e32 v1, v7, v1
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v7, v3
; GCN-IR-NEXT: v_mov_b32_e32 v6, v2
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB17_3
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem.ll b/llvm/test/CodeGen/AMDGPU/udivrem.ll
index c6aec64d1692e..23205b3f9526a 100644
--- a/llvm/test/CodeGen/AMDGPU/udivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem.ll
@@ -218,6 +218,7 @@ define amdgpu_kernel void @test_udivrem_v2(ptr addrspace(1) %out, <2 x i32> %x,
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX8-NEXT: s_sub_i32 s6, 0, s2
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: v_rcp_f32_e32 v0, v0
; GFX8-NEXT: v_rcp_f32_e32 v2, v2
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -240,7 +241,6 @@ define amdgpu_kernel void @test_udivrem_v2(ptr addrspace(1) %out, <2 x i32> %x,
; GFX8-NEXT: s_cselect_b32 s0, s6, s0
; GFX8-NEXT: s_sub_i32 s2, 0, s3
; GFX8-NEXT: v_mul_lo_u32 v0, s2, v1
-; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
; GFX8-NEXT: v_mul_hi_u32 v1, s1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
index 983acfc2c0699..6f60ce0b64787 100644
--- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
@@ -211,9 +211,9 @@ define amdgpu_kernel void @s_uint_to_fp_v4i64_to_v4f64(ptr addrspace(1) %out, <4
; SI-NEXT: v_ldexp_f64 v[6:7], v[8:9], 32
; SI-NEXT: v_ldexp_f64 v[8:9], v[10:11], 32
; SI-NEXT: s_add_u32 s0, s8, 16
-; SI-NEXT: s_addc_u32 s1, s9, 0
; SI-NEXT: v_add_f64 v[6:7], v[6:7], v[4:5]
; SI-NEXT: v_add_f64 v[4:5], v[8:9], v[12:13]
+; SI-NEXT: s_addc_u32 s1, s9, 0
; SI-NEXT: v_mov_b32_e32 v9, s1
; SI-NEXT: v_mov_b32_e32 v8, s0
; SI-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
@@ -250,8 +250,8 @@ define amdgpu_kernel void @s_uint_to_fp_v4i64_to_v4f64(ptr addrspace(1) %out, <4
; VI-NEXT: s_add_u32 s0, s8, 16
; VI-NEXT: s_addc_u32 s1, s9, 0
; VI-NEXT: v_mov_b32_e32 v11, s1
-; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v10, s0
+; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s9
; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
@@ -368,11 +368,11 @@ define amdgpu_kernel void @s_uint_to_fp_v4i32_to_v4f64(ptr addrspace(1) %out, <4
; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; SI-NEXT: s_mov_b32 flat_scratch_lo, s13
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
; SI-NEXT: v_cvt_f64_u32_e32 v[6:7], s3
; SI-NEXT: v_cvt_f64_u32_e32 v[4:5], s2
-; SI-NEXT: s_add_u32 s0, s4, 16
; SI-NEXT: v_cvt_f64_u32_e32 v[2:3], s1
+; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
+; SI-NEXT: s_add_u32 s0, s4, 16
; SI-NEXT: s_addc_u32 s1, s5, 0
; SI-NEXT: v_mov_b32_e32 v9, s1
; SI-NEXT: v_mov_b32_e32 v8, s0
@@ -391,11 +391,11 @@ define amdgpu_kernel void @s_uint_to_fp_v4i32_to_v4f64(ptr addrspace(1) %out, <4
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], s3
; VI-NEXT: v_cvt_f64_u32_e32 v[4:5], s2
-; VI-NEXT: s_add_u32 s0, s4, 16
; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s1
+; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
+; VI-NEXT: s_add_u32 s0, s4, 16
; VI-NEXT: s_addc_u32 s1, s5, 0
; VI-NEXT: v_mov_b32_e32 v9, s1
; VI-NEXT: v_mov_b32_e32 v8, s0
@@ -437,9 +437,9 @@ define amdgpu_kernel void @uint_to_fp_i1_to_f64(ptr addrspace(1) %out, i32 %in)
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_eq_u32 s2, 0
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
-; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: v_mov_b32_e32 v1, s2
+; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v2, s0
; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SI-NEXT: s_endpgm
@@ -454,9 +454,9 @@ define amdgpu_kernel void @uint_to_fp_i1_to_f64(ptr addrspace(1) %out, i32 %in)
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -615,9 +615,9 @@ define amdgpu_kernel void @s_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_eq_u32 s2, 0
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
-; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: v_mov_b32_e32 v1, s2
+; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v2, s0
; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SI-NEXT: s_endpgm
@@ -632,9 +632,9 @@ define amdgpu_kernel void @s_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -696,9 +696,9 @@ define amdgpu_kernel void @s_select_uint_to_fp_i1_vals_i64(ptr addrspace(1) %out
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_eq_u32 s2, 0
; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
-; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: v_mov_b32_e32 v1, s2
+; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v2, s0
; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SI-NEXT: s_endpgm
@@ -713,9 +713,9 @@ define amdgpu_kernel void @s_select_uint_to_fp_i1_vals_i64(ptr addrspace(1) %out
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -778,9 +778,9 @@ define amdgpu_kernel void @s_swap_select_uint_to_fp_i1_vals_f64(ptr addrspace(1)
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_cmp_eq_u32 s2, 0
; SI-NEXT: s_cselect_b32 s2, 0, 0x3ff00000
-; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: v_mov_b32_e32 v1, s2
+; SI-NEXT: v_mov_b32_e32 v3, s1
; SI-NEXT: v_mov_b32_e32 v2, s0
; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; SI-NEXT: s_endpgm
@@ -795,9 +795,9 @@ define amdgpu_kernel void @s_swap_select_uint_to_fp_i1_vals_f64(ptr addrspace(1)
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b32 s2, 0, 0x3ff00000
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v0, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll b/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
index 22e4a24435f12..ce52b91723371 100644
--- a/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
@@ -209,8 +209,8 @@ define amdgpu_ps i64 @s_underflow_compare_fold_i64(i64 inreg %a, i64 inreg %b) #
; GFX9-LABEL: s_underflow_compare_fold_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s2, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_subb_u32 s3, s1, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
diff --git a/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll b/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
index a82453ee23ee9..75a5c83181820 100644
--- a/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
+++ b/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
@@ -302,8 +302,8 @@ define void @eliminate_spill_after_mfma_rewrite_x2(i32 %x, i32 %y, <4 x i32> %ar
; CHECK-NEXT: v_accvgpr_write_b32 a34, v2
; CHECK-NEXT: v_accvgpr_write_b32 a33, v1
; CHECK-NEXT: v_accvgpr_write_b32 a32, v0
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a3
; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a3
; CHECK-NEXT: v_accvgpr_read_b32 v6, a2
; CHECK-NEXT: v_accvgpr_read_b32 v5, a1
; CHECK-NEXT: v_accvgpr_read_b32 v4, a0
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index 048a87034f048..52235796d7089 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -412,8 +412,8 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v14
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: v_mov_b32_e32 v10, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
@@ -1317,8 +1317,8 @@ define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3
@@ -1406,10 +1406,10 @@ define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
-; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
+; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
@@ -1719,10 +1719,10 @@ define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v1
-; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
+; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB14_3
diff --git a/llvm/test/CodeGen/AMDGPU/usubo.ll b/llvm/test/CodeGen/AMDGPU/usubo.ll
index 3e50534ef12a5..a7781364111a5 100644
--- a/llvm/test/CodeGen/AMDGPU/usubo.ll
+++ b/llvm/test/CodeGen/AMDGPU/usubo.ll
@@ -1265,8 +1265,8 @@ define amdgpu_kernel void @usubo_carry_of_sub_borrowout_used(ptr addrspace(1) %o
; VI-NEXT: v_sub_u32_e32 v1, vcc, s3, v1
; VI-NEXT: s_and_b64 s[0:1], vcc, exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
-; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v4, s5
; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
index a445d1e25d49a..f965dbb0bffd4 100644
--- a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
@@ -49,10 +49,10 @@ define amdgpu_kernel void @v_cnd_nan_nosgpr(ptr addrspace(1) %out, i32 %c, ptr a
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_eq_u32 s2, 0
; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -2362,10 +2362,10 @@ define amdgpu_kernel void @v_cndmask_abs_neg_f32(ptr addrspace(1) %out, i32 %c,
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_lg_u32 s2, 0
; VI-NEXT: s_cselect_b64 s[2:3], -1, 0
+; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e64 v2, -v0, |v0|, s[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -2474,11 +2474,11 @@ define amdgpu_kernel void @v_cndmask_abs_neg_f64(ptr addrspace(1) %out, i32 %c,
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_lg_u32 s2, 0
; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 185f0bb0aa421..c1473f3cf6ab1 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -248,8 +248,8 @@ define amdgpu_kernel void @basic_smax_smin_sgpr(ptr addrspace(1) %out, i32 inreg
; GISEL-VI-NEXT: s_and_b32 s2, 0xffff, s2
; GISEL-VI-NEXT: s_lshl_b32 s3, s3, 16
; GISEL-VI-NEXT: s_or_b32 s2, s2, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1
; GISEL-VI-NEXT: flat_store_dword v[0:1], v2
; GISEL-VI-NEXT: s_endpgm
@@ -749,8 +749,8 @@ define amdgpu_kernel void @vec_smax_smin_sgpr(ptr addrspace(1) %out, <2 x i16> i
; GISEL-VI-NEXT: s_and_b32 s2, 0xffff, s2
; GISEL-VI-NEXT: s_lshl_b32 s3, s3, 16
; GISEL-VI-NEXT: s_or_b32 s2, s2, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
; GISEL-VI-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1
; GISEL-VI-NEXT: flat_store_dword v[0:1], v2
; GISEL-VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/valu-i1.ll b/llvm/test/CodeGen/AMDGPU/valu-i1.ll
index 9df052d6910e8..6f20a4e290c90 100644
--- a/llvm/test/CodeGen/AMDGPU/valu-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/valu-i1.ll
@@ -49,11 +49,11 @@ define amdgpu_kernel void @test_if(i32 %b, ptr addrspace(1) %src, ptr addrspace(
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_ashr_i32 s9, s8, 31
; SI-NEXT: s_lshl_b64 s[4:5], s[8:9], 2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_mov_b32_e32 v2, 13
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: .LBB0_8: ; %end
@@ -62,10 +62,10 @@ define amdgpu_kernel void @test_if(i32 %b, ptr addrspace(1) %src, ptr addrspace(
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_ashr_i32 s9, s8, 31
; SI-NEXT: s_lshl_b64 s[12:13], s[8:9], 2
-; SI-NEXT: v_mov_b32_e32 v1, s12
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_mov_b32_e32 v3, 17
+; SI-NEXT: v_mov_b32_e32 v1, s12
; SI-NEXT: v_mov_b32_e32 v2, s13
; SI-NEXT: buffer_store_dword v3, v[1:2], s[0:3], 0 addr64
; SI-NEXT: s_xor_b64 s[2:3], exec, -1
diff --git a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
index 10c2162f5eadb..868ce1992be4d 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
@@ -2212,10 +2212,10 @@ define amdgpu_kernel void @shuffle_scalar_load_v8i32_0123(ptr addrspace(4) %in,
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[2:3]
; GFX11-NEXT: s_endpgm
%ld8 = load <8 x i32>, ptr addrspace(4) %in, align 16
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll b/llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
index 0f67d80e97104..37bd98bc5c97b 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
@@ -521,12 +521,11 @@ define <8 x half> @baz() nounwind {
; CHECK-NEXT: v_mov_b32_e32 v46, v2
; CHECK-NEXT: v_dual_mov_b32 v0, v72 :: v_dual_mov_b32 v1, v73
; CHECK-NEXT: v_dual_mov_b32 v2, v74 :: v_dual_mov_b32 v3, v75
-; CHECK-NEXT: v_mov_b32_e32 v43, v34
-; CHECK-NEXT: v_dual_mov_b32 v42, v33 :: v_dual_mov_b32 v41, v32
-; CHECK-NEXT: v_dual_mov_b32 v40, v31 :: v_dual_mov_b32 v39, v30
-; CHECK-NEXT: v_dual_mov_b32 v38, v29 :: v_dual_mov_b32 v37, v28
-; CHECK-NEXT: v_dual_mov_b32 v36, v27 :: v_dual_mov_b32 v35, v26
-; CHECK-NEXT: v_mov_b32_e32 v34, v25
+; CHECK-NEXT: v_dual_mov_b32 v43, v34 :: v_dual_mov_b32 v42, v33
+; CHECK-NEXT: v_dual_mov_b32 v41, v32 :: v_dual_mov_b32 v40, v31
+; CHECK-NEXT: v_dual_mov_b32 v39, v30 :: v_dual_mov_b32 v38, v29
+; CHECK-NEXT: v_dual_mov_b32 v37, v28 :: v_dual_mov_b32 v36, v27
+; CHECK-NEXT: v_dual_mov_b32 v35, v26 :: v_dual_mov_b32 v34, v25
; CHECK-NEXT: v_mov_b32_e32 v33, v24
; CHECK-NEXT: v_mov_b32_e32 v32, v23
; CHECK-NEXT: v_mov_b32_e32 v31, v22
diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll
index 3c6714a2bea68..d857d147a248d 100644
--- a/llvm/test/CodeGen/AMDGPU/wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave32.ll
@@ -883,8 +883,8 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 {
; GFX1032-NEXT: s_cmp_ge_u32 s2, s0
; GFX1032-NEXT: s_cselect_b32 s4, s3, s1
; GFX1032-NEXT: .LBB15_5: ; %bb.split
-; GFX1032-NEXT: v_mov_b32_e32 v0, s4
; GFX1032-NEXT: v_mov_b32_e32 v2, 0
+; GFX1032-NEXT: v_mov_b32_e32 v0, s4
; GFX1032-NEXT: v_mov_b32_e32 v1, s5
; GFX1032-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] offset:16
; GFX1032-NEXT: s_endpgm
@@ -1040,8 +1040,8 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 {
; GFX1064-NEXT: s_cmp_ge_u32 s2, s0
; GFX1064-NEXT: s_cselect_b32 s4, s3, s1
; GFX1064-NEXT: .LBB15_5: ; %bb.split
-; GFX1064-NEXT: v_mov_b32_e32 v0, s4
; GFX1064-NEXT: v_mov_b32_e32 v2, 0
+; GFX1064-NEXT: v_mov_b32_e32 v0, s4
; GFX1064-NEXT: v_mov_b32_e32 v1, s5
; GFX1064-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] offset:16
; GFX1064-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
index 60ebc5f50bf3a..909d13fcc3c2c 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
@@ -1273,11 +1273,10 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i
; GISEL-NEXT: s_mov_b32 s1, s6
; GISEL-NEXT: s_mov_b32 s2, s7
; GISEL-NEXT: s_mov_b32 s3, s8
-; GISEL-NEXT: v_mov_b32_e32 v4, s4
; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v1, s1
; GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
-; GISEL-NEXT: v_mov_b32_e32 v5, s9
+; GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s9
; GISEL-NEXT: scratch_store_b32 off, v4, s10
; GISEL-NEXT: s_clause 0x1
; GISEL-NEXT: scratch_store_b128 off, v[0:3], s11
diff --git a/llvm/test/CodeGen/AMDGPU/wqm.ll b/llvm/test/CodeGen/AMDGPU/wqm.ll
index 10ec1adee4001..900f26f413499 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/wqm.ll
@@ -1949,9 +1949,9 @@ define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) nounwind {
; GFX9-W64-NEXT: s_cbranch_scc0 .LBB35_5
; GFX9-W64-NEXT: .LBB35_3: ; %loop
; GFX9-W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX9-W64-NEXT: v_cmp_lt_f32_e32 vcc, s4, v8
; GFX9-W64-NEXT: s_waitcnt vmcnt(0)
; GFX9-W64-NEXT: v_mov_b32_e32 v0, v4
-; GFX9-W64-NEXT: v_cmp_lt_f32_e32 vcc, s4, v8
; GFX9-W64-NEXT: v_mov_b32_e32 v1, v5
; GFX9-W64-NEXT: v_mov_b32_e32 v2, v6
; GFX9-W64-NEXT: v_mov_b32_e32 v3, v7
diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
index 0934a57a45847..9faa8aeb26de1 100644
--- a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
@@ -430,13 +430,13 @@ define amdgpu_kernel void @call(ptr addrspace(8) %tmp14, i32 %arg) {
; GFX9-O3-NEXT: v_cndmask_b32_e64 v6, 0, v0, s[20:21]
; GFX9-O3-NEXT: s_addc_u32 s9, s5, 0
; GFX9-O3-NEXT: v_or3_b32 v3, v5, v4, v3
-; GFX9-O3-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9-O3-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: s_getpc_b64 s[22:23]
; GFX9-O3-NEXT: s_add_u32 s22, s22, called at rel32@lo+4
; GFX9-O3-NEXT: s_addc_u32 s23, s23, called at rel32@hi+12
+; GFX9-O3-NEXT: s_mov_b64 s[4:5], s[0:1]
+; GFX9-O3-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-O3-NEXT: v_mov_b32_e32 v31, v3
+; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: s_mov_b64 s[2:3], s[26:27]
; GFX9-O3-NEXT: v_mov_b32_e32 v0, v6
; GFX9-O3-NEXT: s_swappc_b64 s[30:31], s[22:23]
@@ -695,8 +695,8 @@ define amdgpu_kernel void @call_i64(ptr addrspace(8) %tmp14, i64 %arg) {
; GFX9-O3-NEXT: v_or3_b32 v3, v5, v4, v3
; GFX9-O3-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-O3-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: v_mov_b32_e32 v31, v3
+; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: s_mov_b64 s[2:3], s[26:27]
; GFX9-O3-NEXT: v_mov_b32_e32 v0, v7
; GFX9-O3-NEXT: v_mov_b32_e32 v1, v6
@@ -1288,13 +1288,13 @@ define amdgpu_kernel void @strict_wwm_call(ptr addrspace(8) %tmp14, i32 %arg) {
; GFX9-O3-NEXT: v_cndmask_b32_e64 v6, 0, v0, s[20:21]
; GFX9-O3-NEXT: s_addc_u32 s9, s5, 0
; GFX9-O3-NEXT: v_or3_b32 v3, v5, v4, v3
-; GFX9-O3-NEXT: s_mov_b64 s[4:5], s[0:1]
-; GFX9-O3-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: s_getpc_b64 s[22:23]
; GFX9-O3-NEXT: s_add_u32 s22, s22, strict_wwm_called at rel32@lo+4
; GFX9-O3-NEXT: s_addc_u32 s23, s23, strict_wwm_called at rel32@hi+12
+; GFX9-O3-NEXT: s_mov_b64 s[4:5], s[0:1]
+; GFX9-O3-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9-O3-NEXT: v_mov_b32_e32 v31, v3
+; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: s_mov_b64 s[2:3], s[26:27]
; GFX9-O3-NEXT: v_mov_b32_e32 v0, v6
; GFX9-O3-NEXT: s_swappc_b64 s[30:31], s[22:23]
@@ -1553,8 +1553,8 @@ define amdgpu_kernel void @strict_wwm_call_i64(ptr addrspace(8) %tmp14, i64 %arg
; GFX9-O3-NEXT: v_or3_b32 v3, v5, v4, v3
; GFX9-O3-NEXT: s_mov_b64 s[4:5], s[0:1]
; GFX9-O3-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: v_mov_b32_e32 v31, v3
+; GFX9-O3-NEXT: s_mov_b64 s[0:1], s[24:25]
; GFX9-O3-NEXT: s_mov_b64 s[2:3], s[26:27]
; GFX9-O3-NEXT: v_mov_b32_e32 v0, v7
; GFX9-O3-NEXT: v_mov_b32_e32 v1, v6
diff --git a/llvm/test/CodeGen/AMDGPU/xor.ll b/llvm/test/CodeGen/AMDGPU/xor.ll
index fb05b3c77932c..93a20cad1f372 100644
--- a/llvm/test/CodeGen/AMDGPU/xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/xor.ll
@@ -651,9 +651,9 @@ define amdgpu_kernel void @scalar_xor_literal_i64(ptr addrspace(1) %out, [8 x i3
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_xor_b32 s1, s1, 0xf237b
; VI-NEXT: s_xor_b32 s0, s0, 0x3039
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -693,13 +693,13 @@ define amdgpu_kernel void @scalar_xor_literal_multi_use_i64(ptr addrspace(1) %ou
; VI-NEXT: s_mov_b32 s7, 0xf237b
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[6:7]
-; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: s_add_u32 s0, s2, 0x3039
-; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: s_addc_u32 s1, s3, 0xf237b
+; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
@@ -733,9 +733,9 @@ define amdgpu_kernel void @scalar_xor_inline_imm_i64(ptr addrspace(1) %out, [8 x
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_xor_b32 s0, s0, 63
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm
@@ -765,8 +765,8 @@ define amdgpu_kernel void @scalar_xor_neg_inline_imm_i64(ptr addrspace(1) %out,
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_xor_b64 s[0:1], s[0:1], -8
; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
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