[llvm] [NFC][SPIRV] Use `StringRef` by value (no `const`, no `&`) (PR #207940)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 7 02:10:49 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-spir-v
Author: Juan Manuel Martinez Caamaño (jmmartinez)
<details>
<summary>Changes</summary>
A `StringRef` is non-modifiable and it acts as a reference, so there is no need to declare it as `const` nor `&`.
---
Full diff: https://github.com/llvm/llvm-project/pull/207940.diff
6 Files Affected:
- (modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp (+11-11)
- (modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.h (+5-5)
- (modified) llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp (+1-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVMetadata.cpp (+1-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVUtils.cpp (+9-10)
- (modified) llvm/lib/Target/SPIRV/SPIRVUtils.h (+4-5)
``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 6b1abe326994a..7f01fc37af545 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1899,7 +1899,7 @@ static bool generateCastToPtrInst(const SPIRV::IncomingCall *Call,
return true;
}
-static bool generateDotOrFMulInst(const StringRef DemangledCall,
+static bool generateDotOrFMulInst(StringRef DemangledCall,
const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -2311,7 +2311,7 @@ getSamplerFilterModeFromBitmask(unsigned Bitmask) {
return SPIRV::SamplerFilterMode::Nearest;
}
-static bool generateReadImageInst(const StringRef DemangledCall,
+static bool generateReadImageInst(StringRef DemangledCall,
const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -2406,7 +2406,7 @@ static bool generateWriteImageInst(const SPIRV::IncomingCall *Call,
return true;
}
-static bool generateSampleImageInst(const StringRef DemangledCall,
+static bool generateSampleImageInst(StringRef DemangledCall,
const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -3175,7 +3175,7 @@ static bool generateAsyncCopy(const SPIRV::IncomingCall *Call,
}
}
-static bool generateConvertInst(const StringRef DemangledCall,
+static bool generateConvertInst(StringRef DemangledCall,
const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -3412,7 +3412,7 @@ namespace SPIRV {
// TODO: consider a major rework of mapping demangled calls into a builtin
// functions to unify search and decrease number of individual cases.
std::tuple<int, unsigned, unsigned>
-mapBuiltinToOpcode(const StringRef DemangledCall,
+mapBuiltinToOpcode(StringRef DemangledCall,
SPIRV::InstructionSet::InstructionSet Set) {
Register Reg;
SmallVector<Register> Args;
@@ -3485,7 +3485,7 @@ mapBuiltinToOpcode(const StringRef DemangledCall,
return std::make_tuple(-1, 0, 0);
}
-std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
+std::optional<bool> lowerBuiltin(StringRef DemangledCall,
SPIRV::InstructionSet::InstructionSet Set,
MachineIRBuilder &MIRBuilder,
const Register OrigRet, const Type *OrigRetTy,
@@ -3655,7 +3655,7 @@ Type *parseBuiltinCallArgumentType(StringRef TypeStr, LLVMContext &Ctx) {
}
bool parseBuiltinTypeStr(SmallVector<StringRef, 10> &BuiltinArgsTypeStrs,
- const StringRef DemangledCall, LLVMContext &Ctx) {
+ StringRef DemangledCall, LLVMContext &Ctx) {
auto Pos1 = DemangledCall.find('(');
if (Pos1 == StringRef::npos)
return false;
@@ -3667,8 +3667,8 @@ bool parseBuiltinTypeStr(SmallVector<StringRef, 10> &BuiltinArgsTypeStrs,
return true;
}
-Type *parseBuiltinCallArgumentBaseType(const StringRef DemangledCall,
- unsigned ArgIdx, LLVMContext &Ctx) {
+Type *parseBuiltinCallArgumentBaseType(StringRef DemangledCall, unsigned ArgIdx,
+ LLVMContext &Ctx) {
SmallVector<StringRef, 10> BuiltinArgsTypeStrs;
parseBuiltinTypeStr(BuiltinArgsTypeStrs, DemangledCall, Ctx);
if (ArgIdx >= BuiltinArgsTypeStrs.size())
@@ -3700,7 +3700,7 @@ struct OpenCLType {
// Misc functions for parsing builtin types.
//===----------------------------------------------------------------------===//
-static Type *parseTypeString(const StringRef Name, LLVMContext &Context) {
+static Type *parseTypeString(StringRef Name, LLVMContext &Context) {
if (Name.starts_with("void"))
return Type::getVoidTy(Context);
else if (Name.starts_with("int") || Name.starts_with("uint"))
@@ -3925,7 +3925,7 @@ lowerBuiltinType(const Type *OpaqueType,
unsigned NumStartingVRegs = MIRBuilder.getMRI()->getNumVirtRegs();
- const StringRef Name = BuiltinType->getName();
+ StringRef Name = BuiltinType->getName();
LLVM_DEBUG(dbgs() << "Lowering builtin type: " << Name << "\n");
SPIRVTypeInst TargetType = nullptr;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h
index 88afb38a7c5aa..00a02e85dd592 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h
@@ -34,7 +34,7 @@ std::string lookupBuiltinNameHelper(StringRef DemangledCall,
/// Register(0) otherwise.
/// \p OrigRetTy is the type of the \p OrigRet.
/// \p Args are the arguments of the lowered builtin call.
-std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
+std::optional<bool> lowerBuiltin(StringRef DemangledCall,
InstructionSet::InstructionSet Set,
MachineIRBuilder &MIRBuilder,
const Register OrigRet, const Type *OrigRetTy,
@@ -44,7 +44,7 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
/// Helper function for finding a builtin function attributes
/// by a demangled function name. Defined in SPIRVBuiltins.cpp.
std::tuple<int, unsigned, unsigned>
-mapBuiltinToOpcode(const StringRef DemangledCall,
+mapBuiltinToOpcode(StringRef DemangledCall,
SPIRV::InstructionSet::InstructionSet Set);
/// Parses the provided \p ArgIdx argument base type in the \p DemangledCall
@@ -55,10 +55,10 @@ mapBuiltinToOpcode(const StringRef DemangledCall,
///
/// \p DemangledCall is the skeleton of the lowered builtin function call.
/// \p ArgIdx is the index of the argument to parse.
-Type *parseBuiltinCallArgumentBaseType(const StringRef DemangledCall,
- unsigned ArgIdx, LLVMContext &Ctx);
+Type *parseBuiltinCallArgumentBaseType(StringRef DemangledCall, unsigned ArgIdx,
+ LLVMContext &Ctx);
bool parseBuiltinTypeStr(SmallVector<StringRef, 10> &BuiltinArgsTypeStrs,
- const StringRef DemangledCall, LLVMContext &Ctx);
+ StringRef DemangledCall, LLVMContext &Ctx);
Type *parseBuiltinCallArgumentType(StringRef TypeStr, LLVMContext &Ctx);
/// Translates a string representing a SPIR-V or OpenCL builtin type to a
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 39b4dbac78fb7..eea63194fa8b7 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -995,7 +995,7 @@ SPIRVTypeInst
SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty,
MachineIRBuilder &MIRBuilder) {
assert(Ty->hasName());
- const StringRef Name = Ty->hasName() ? Ty->getName() : "";
+ StringRef Name = Ty->hasName() ? Ty->getName() : "";
Register ResVReg = createTypeVReg(MIRBuilder);
return createConstOrTypeAtFunctionEntry(
MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVMetadata.cpp b/llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
index 3800aac70df32..ea05118981e71 100644
--- a/llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
@@ -16,7 +16,7 @@
using namespace llvm;
static MDString *getOCLKernelArgAttribute(const Function &F, unsigned ArgIdx,
- const StringRef AttributeName) {
+ StringRef AttributeName) {
assert(
F.getCallingConv() == CallingConv::SPIR_KERNEL &&
"Kernel attributes are attached/belong only to OpenCL kernel functions");
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
index d335c0596332a..d3feb6d20a794 100644
--- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
@@ -154,7 +154,7 @@ StringRef getOriginalAsmConstraints(const CallBase &CB) {
// 32-bit integer operands with the correct format, and unpack them if necessary
// when making string comparisons in compiler passes.
// SPIR-V requires null-terminated UTF-8 strings padded to 32-bit alignment.
-static uint32_t convertCharsToWord(const StringRef &Str, unsigned i) {
+static uint32_t convertCharsToWord(StringRef Str, unsigned i) {
uint32_t Word = 0u; // Padding/null bytes are zero-initialized.
unsigned Count = std::min(static_cast<size_t>(4), Str.size() - i);
std::memcpy(&Word, Str.data() + i, Count);
@@ -162,11 +162,9 @@ static uint32_t convertCharsToWord(const StringRef &Str, unsigned i) {
}
// Get length including padding and null terminator.
-static size_t getPaddedLen(const StringRef &Str) {
- return alignTo(Str.size() + 1, 4);
-}
+static size_t getPaddedLen(StringRef Str) { return alignTo(Str.size() + 1, 4); }
-void addStringImm(const StringRef &Str, MCInst &Inst) {
+void addStringImm(StringRef Str, MCInst &Inst) {
const size_t PaddedLen = getPaddedLen(Str);
for (unsigned i = 0; i < PaddedLen; i += 4) {
// Add an operand for the 32-bits of chars or padding.
@@ -174,7 +172,7 @@ void addStringImm(const StringRef &Str, MCInst &Inst) {
}
}
-void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB) {
+void addStringImm(StringRef Str, MachineInstrBuilder &MIB) {
const size_t PaddedLen = getPaddedLen(Str);
for (unsigned i = 0; i < PaddedLen; i += 4) {
// Add an operand for the 32-bits of chars or padding.
@@ -182,6 +180,7 @@ void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB) {
}
}
+
std::string getStringImm(const MachineInstr &MI, unsigned StartIndex) {
return getSPIRVStringOperand(MI, StartIndex);
}
@@ -225,7 +224,7 @@ void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) {
}
}
-void buildOpName(Register Target, const StringRef &Name,
+void buildOpName(Register Target, StringRef Name,
MachineIRBuilder &MIRBuilder) {
if (!Name.empty()) {
auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target);
@@ -233,7 +232,7 @@ void buildOpName(Register Target, const StringRef &Name,
}
}
-void buildOpName(Register Target, const StringRef &Name, MachineInstr &I,
+void buildOpName(Register Target, StringRef Name, MachineInstr &I,
const SPIRVInstrInfo &TII) {
if (!Name.empty()) {
auto MIB =
@@ -522,14 +521,14 @@ Type *getMDOperandAsType(const MDNode *N, unsigned I) {
return toTypedPointer(ElementTy);
}
-static bool isEnqueueKernelBI(const StringRef MangledName) {
+static bool isEnqueueKernelBI(StringRef MangledName) {
return MangledName == "__enqueue_kernel_basic" ||
MangledName == "__enqueue_kernel_basic_events" ||
MangledName == "__enqueue_kernel_varargs" ||
MangledName == "__enqueue_kernel_events_varargs";
}
-static bool isKernelQueryBI(const StringRef MangledName) {
+static bool isKernelQueryBI(StringRef MangledName) {
return MangledName == "__get_kernel_work_group_size_impl" ||
MangledName == "__get_kernel_sub_group_count_for_ndrange_impl" ||
MangledName == "__get_kernel_max_sub_group_size_for_ndrange_impl" ||
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h
index c9f25d733d983..59b480b6892b0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVUtils.h
+++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h
@@ -175,8 +175,8 @@ StringRef getOriginalAsmConstraints(const CallBase &CB);
// Add the given string as a series of integer operand, inserting null
// terminators and padding to make sure the operands all have 32-bit
// little-endian words.
-void addStringImm(const StringRef &Str, MCInst &Inst);
-void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB);
+void addStringImm(StringRef Str, MCInst &Inst);
+void addStringImm(StringRef Str, MachineInstrBuilder &MIB);
// Read the series of integer operands back as a null-terminated string using
// the reverse of the logic in addStringImm.
@@ -190,9 +190,8 @@ std::string getStringValueFromReg(Register Reg, MachineRegisterInfo &MRI);
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB);
// Add an OpName instruction for the given target register.
-void buildOpName(Register Target, const StringRef &Name,
- MachineIRBuilder &MIRBuilder);
-void buildOpName(Register Target, const StringRef &Name, MachineInstr &I,
+void buildOpName(Register Target, StringRef Name, MachineIRBuilder &MIRBuilder);
+void buildOpName(Register Target, StringRef Name, MachineInstr &I,
const SPIRVInstrInfo &TII);
// Add an OpDecorate instruction for the given Reg.
``````````
</details>
https://github.com/llvm/llvm-project/pull/207940
More information about the llvm-commits
mailing list