[llvm] [AArch64][DAG] Port adde and sube combine to AArch64 (PR #202227)

[Ricardo Jesus via llvm-commits]

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@@ -23171,6 +23171,29 @@ static SDValue foldADCToCINC(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond);
 }
 
+/// Takes advantage of the negation of the second operand by the with-carry-in
+/// instructions to fold:
+///
+///   AddWithCarry(X, -1, C) => SubWithCarry(X, 0, C)
+///   SubWithCarry(X, -1, C) => AddWithCarry(X, 0, C)
+///
+/// This allows using the zero register (xzr/wzr) to encode the immediate
+/// operand (rather than a MOV to a GPR).
+static SDValue performAddSubCarryCombine(SDNode *N, SelectionDAG &DAG,
+                                         unsigned NewOpcode) {
+  SDValue RHS = N->getOperand(1);
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
+    APInt Imm = C->getAPIntValue();
+    if (Imm.isAllOnes()) {
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rj-jesus wrote:

Can do `C->isAllOnes()`

https://github.com/llvm/llvm-project/pull/202227