[llvm] [X86] Add vXi64 MULHU/MULHS lowering, keeping full-width products scalar (PR #206983)
Rito Takeuchi via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 6 15:47:39 PDT 2026
https://github.com/Licht-T updated https://github.com/llvm/llvm-project/pull/206983
>From 536b39c1dd4232db0d2f8e602207aea279f34588 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Thu, 27 Nov 2025 15:03:10 +0000
Subject: [PATCH 1/7] [X86] Add ISD::MULHS/MULHU v4i64/v8i64 lowering
Avoid scalarisation of v4i64/v8i64 div-by-constant patterns by expanding ISD::MULHS/MULHU on AVX2+ targets
The generic ISD::MULHS/MULHU expansion provided by forceExpandMultiply is particularly useful as it matches very well with VPMULDQ/VPMULUDQ patterns.
I couldn't make v2i64 expansion worthwhile on x64 targets (although it could be worth it 32-bit if there's a demand).
ISD::MULHS on AVX2 targets is only a marginal benefit - the benefit of avoiding xmm<->gpr traffic and possible IMULQ bottlenecks is offset against poor v4i64 SRA handling.
Fixes #37771
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 2 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 11 +
llvm/test/CodeGen/X86/srem-vector-lkk.ll | 155 ++++++------
llvm/test/CodeGen/X86/urem-vector-lkk.ll | 131 +++++-----
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 228 +++++++++++-------
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 219 ++++-------------
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll | 128 ++++------
llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll | 214 +++-------------
8 files changed, 425 insertions(+), 663 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a4bcc8cb01126..0c95588ef08e0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -12650,7 +12650,7 @@ void TargetLowering::forceExpandMultiply(SelectionDAG &DAG, const SDLoc &dl,
// Hacker's Delight (itself derived from Knuth's Algorithm M from section
// 4.3.1). If Signed is set, we can use arithmetic right shifts to propagate
// sign bits while calculating the Hi half.
- unsigned Bits = VT.getSizeInBits();
+ unsigned Bits = VT.getScalarSizeInBits();
unsigned HalfBits = Bits / 2;
SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl, VT);
SDValue LL = DAG.getNode(ISD::AND, dl, VT, LHS, Mask);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index b33b01f804c6b..457b66582f9b1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1749,6 +1749,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
if (HasInt256) {
+ setOperationAction(ISD::MULHS, MVT::v4i64, Custom);
+ setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
// Custom legalize 2x32 to get a little better code.
@@ -2022,6 +2024,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
setOperationAction(ISD::MUL, MVT::v64i8, Custom);
+ setOperationAction(ISD::MULHS, MVT::v8i64, Custom);
+ setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
@@ -30259,6 +30263,13 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget,
if ((VT == MVT::v32i16 || VT == MVT::v64i8) && !Subtarget.hasBWI())
return splitVectorIntBinary(Op, DAG, dl);
+ if (VT.isVector() && VT.getVectorElementType() == MVT::i64) {
+ SDValue Lo, Hi;
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ TLI.forceExpandMultiply(DAG, dl, IsSigned, Lo, Hi, A, B);
+ return Hi;
+ }
+
if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) {
assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) ||
(VT == MVT::v8i32 && Subtarget.hasInt256()) ||
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index 678515c3e572e..d65c977592677 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -534,90 +534,85 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
;
; AVX2-LABEL: dont_fold_srem_i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $4, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (%rdx,%rdx,2), %rax
-; AVX2-NEXT: shlq $3, %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $11, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $8, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpmovsxdq {{.*#+}} ymm1 = [0,1681210440,18446744072402387656,1621997606]
+; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm2
+; AVX2-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,0,0,0,4294967295,0,0,0]
+; AVX2-NEXT: vpmuludq %ymm3, %ymm0, %ymm4
+; AVX2-NEXT: vpsllq $32, %ymm4, %ymm4
+; AVX2-NEXT: vpaddq %ymm4, %ymm2, %ymm2
+; AVX2-NEXT: vpshufd {{.*#+}} ymm4 = ymm0[1,1,3,3,5,5,7,7]
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm5 = [0,105075653,1493901669,3856996263]
+; AVX2-NEXT: vpmuludq %ymm5, %ymm4, %ymm6
+; AVX2-NEXT: vpsrad $31, %ymm0, %ymm7
+; AVX2-NEXT: vpsrlq $32, %ymm7, %ymm7
+; AVX2-NEXT: vpmuludq %ymm5, %ymm7, %ymm8
+; AVX2-NEXT: vpsllq $32, %ymm8, %ymm8
+; AVX2-NEXT: vpaddq %ymm6, %ymm8, %ymm6
+; AVX2-NEXT: vpmuludq %ymm5, %ymm0, %ymm5
+; AVX2-NEXT: vpsrlq $32, %ymm5, %ymm5
+; AVX2-NEXT: vpaddq %ymm5, %ymm6, %ymm5
+; AVX2-NEXT: vpxor %xmm6, %xmm6, %xmm6
+; AVX2-NEXT: vpblendd {{.*#+}} ymm8 = ymm5[0],ymm6[1],ymm5[2],ymm6[3],ymm5[4],ymm6[5],ymm5[6],ymm6[7]
+; AVX2-NEXT: vpaddq %ymm2, %ymm8, %ymm2
+; AVX2-NEXT: vpsrad $31, %ymm2, %ymm8
+; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[1,1,3,3,5,5,7,7]
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm8[1],ymm2[2],ymm8[3],ymm2[4],ymm8[5],ymm2[6],ymm8[7]
+; AVX2-NEXT: vpsrad $31, %ymm5, %ymm8
+; AVX2-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[1,1,3,3,5,5,7,7]
+; AVX2-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0],ymm8[1],ymm5[2],ymm8[3],ymm5[4],ymm8[5],ymm5[6],ymm8[7]
+; AVX2-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX2-NEXT: vpmuludq %ymm3, %ymm4, %ymm3
+; AVX2-NEXT: vpmuludq %ymm1, %ymm7, %ymm5
+; AVX2-NEXT: vpaddq %ymm5, %ymm3, %ymm3
+; AVX2-NEXT: vpsllq $32, %ymm3, %ymm3
+; AVX2-NEXT: vpmuludq %ymm1, %ymm4, %ymm1
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm6[2,3],ymm0[4,5],ymm6[6,7]
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm6[0,1],ymm2[2,3,4,5,6,7]
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [9223372036854775808,36028797018963968,576460752303423488,4503599627370496]
+; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsubq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsllq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: dont_fold_srem_i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX512-NEXT: vmovq %xmm1, %rcx
-; AVX512-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: addq %rcx, %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $4, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: leaq (%rdx,%rdx,2), %rax
-; AVX512-NEXT: shlq $3, %rax
-; AVX512-NEXT: subq %rax, %rdx
-; AVX512-NEXT: addq %rcx, %rdx
-; AVX512-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX512-NEXT: vmovq %rdx, %xmm1
-; AVX512-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $11, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: vmovq %rcx, %xmm2
-; AVX512-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm2[0]
-; AVX512-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $8, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: vmovq %rcx, %xmm1
-; AVX512-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX512-NEXT: vpsraq $32, %ymm0, %ymm1
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm2 = [0,105075653,1493901669,3856996263]
+; AVX512-NEXT: vpmullq %ymm2, %ymm1, %ymm3
+; AVX512-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512-NEXT: vpsraq $32, %ymm2, %ymm3
+; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX512-NEXT: vpblendd {{.*#+}} ymm5 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7]
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1681210440,18446744072402387656,1621997606]
+; AVX512-NEXT: vpmullq %ymm6, %ymm5, %ymm5
+; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX512-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX512-NEXT: vpsraq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpmuldq %ymm6, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm4[2,3],ymm0[4,5],ymm4[6,7]
+; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3,4,5,6,7]
+; AVX512-NEXT: vpsravq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [1,654,23,5423]
+; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/X86/urem-vector-lkk.ll b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
index 3faa2a0720d4e..166f9af2238b8 100644
--- a/llvm/test/CodeGen/X86/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
@@ -369,78 +369,73 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
;
; AVX2-LABEL: dont_fold_urem_i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rdx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $4, %rax
-; AVX2-NEXT: leaq (%rax,%rax,2), %rdx
-; AVX2-NEXT: shlq $3, %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rdx
-; AVX2-NEXT: shrq $12, %rdx
-; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX2-NEXT: mulq %rdx
-; AVX2-NEXT: shrq $7, %rdx
-; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm2
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm3 = [0,105075653,2987803337,3419025229]
+; AVX2-NEXT: vpmuludq %ymm3, %ymm2, %ymm4
+; AVX2-NEXT: vpmuludq %ymm3, %ymm1, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm3, %ymm3
+; AVX2-NEXT: vpaddq %ymm3, %ymm4, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm3, %ymm4
+; AVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0],ymm5[1],ymm3[2],ymm5[3],ymm3[4],ymm5[5],ymm3[6],ymm5[7]
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm5 = [0,1681210440,1680639376,3243995213]
+; AVX2-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm5, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm4, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm4 = [0,0,2147483648,0]
+; AVX2-NEXT: vpmuludq %ymm4, %ymm3, %ymm3
+; AVX2-NEXT: vpmuludq %ymm4, %ymm2, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX2-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsllq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: dont_fold_urem_i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX512-NEXT: vmovq %xmm1, %rdx
-; AVX512-NEXT: movabsq $7218291159277650633, %rax # imm = 0x642C8590B21642C9
-; AVX512-NEXT: mulxq %rax, %rax, %rax
-; AVX512-NEXT: movq %rdx, %rcx
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: shrq %rcx
-; AVX512-NEXT: addq %rax, %rcx
-; AVX512-NEXT: shrq $4, %rcx
-; AVX512-NEXT: leaq (%rcx,%rcx,2), %rax
-; AVX512-NEXT: shlq $3, %rax
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: addq %rdx, %rcx
-; AVX512-NEXT: vpextrq $1, %xmm1, %rdx
-; AVX512-NEXT: movabsq $-4513890722074972339, %rax # imm = 0xC15B704DCBCA2F4D
-; AVX512-NEXT: mulxq %rax, %rax, %rax
-; AVX512-NEXT: vmovq %rcx, %xmm1
-; AVX512-NEXT: shrq $12, %rax
-; AVX512-NEXT: imulq $5423, %rax, %rax # imm = 0x152F
-; AVX512-NEXT: subq %rax, %rdx
-; AVX512-NEXT: vmovq %rdx, %xmm2
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: movq %rax, %rdx
-; AVX512-NEXT: shrq %rdx
-; AVX512-NEXT: movabsq $7220743857598845893, %rcx # imm = 0x64353C48064353C5
-; AVX512-NEXT: mulxq %rcx, %rcx, %rcx
-; AVX512-NEXT: shrq $7, %rcx
-; AVX512-NEXT: imulq $654, %rcx, %rcx # imm = 0x28E
-; AVX512-NEXT: subq %rcx, %rax
-; AVX512-NEXT: vmovq %rax, %xmm0
-; AVX512-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
-; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX512-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX512-NEXT: vpsrlq $32, %ymm1, %ymm2
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm3 = [0,105075653,2987803337,3419025229]
+; AVX512-NEXT: vpmuludq %ymm3, %ymm2, %ymm4
+; AVX512-NEXT: vpmuludq %ymm3, %ymm1, %ymm3
+; AVX512-NEXT: vpsrlq $32, %ymm3, %ymm3
+; AVX512-NEXT: vpaddq %ymm3, %ymm4, %ymm3
+; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX512-NEXT: vpblendd {{.*#+}} ymm4 = ymm3[0],ymm4[1],ymm3[2],ymm4[3],ymm3[4],ymm4[5],ymm3[6],ymm4[7]
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm5 = [0,1681210440,1680639376,3243995213]
+; AVX512-NEXT: vpsrlq $32, %ymm3, %ymm3
+; AVX512-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm4, %ymm1, %ymm1
+; AVX512-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX512-NEXT: vpmuludq %ymm5, %ymm2, %ymm2
+; AVX512-NEXT: vpaddq %ymm3, %ymm2, %ymm2
+; AVX512-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm2
+; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm4 = [0,0,2147483648,0]
+; AVX512-NEXT: vpmuludq %ymm4, %ymm3, %ymm3
+; AVX512-NEXT: vpmuludq %ymm4, %ymm2, %ymm2
+; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpor %ymm2, %ymm3, %ymm2
+; AVX512-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX512-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3,4,5,6,7]
+; AVX512-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [1,654,23,5423]
+; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index fa5692aa9cef1..bde671cb4f4a8 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -45,42 +45,73 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: test_div7_4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rax
-; AVX2-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: retq
+; AVX2NOBW-LABEL: test_div7_4i64:
+; AVX2NOBW: # %bb.0:
+; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[1,1,3,3,5,5,7,7]
+; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
+; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2NOBW-NEXT: vpsrad $31, %ymm0, %ymm4
+; AVX2NOBW-NEXT: vpsrlq $32, %ymm4, %ymm4
+; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
+; AVX2NOBW-NEXT: vpsllq $32, %ymm5, %ymm5
+; AVX2NOBW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX2NOBW-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX2NOBW-NEXT: vpsrad $31, %ymm2, %ymm3
+; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm5 = ymm2[1,1,3,3,5,5,7,7]
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2],ymm3[3],ymm5[4],ymm3[5],ymm5[6],ymm3[7]
+; AVX2NOBW-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
+; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
+; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpsrad $31, %ymm0, %ymm2
+; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7]
+; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm3, %ymm0
+; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm4, %ymm2
+; AVX2NOBW-NEXT: vpsllq $32, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX2NOBW-NEXT: vpsrad $1, %ymm0, %ymm1
+; AVX2NOBW-NEXT: vpsrlq $1, %ymm0, %ymm2
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2],ymm1[3],ymm2[4],ymm1[5],ymm2[6],ymm1[7]
+; AVX2NOBW-NEXT: vpsrlq $63, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX2NOBW-NEXT: retq
+;
+; AVX512BW-LABEL: test_div7_4i64:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512BW-NEXT: vpsraq $32, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
+; AVX512BW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX512BW-NEXT: vpsrlq $32, %ymm1, %ymm4
+; AVX512BW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
+; AVX512BW-NEXT: vpsllq $32, %ymm5, %ymm5
+; AVX512BW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
+; AVX512BW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX512BW-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512BW-NEXT: vpsraq $32, %zmm2, %zmm3
+; AVX512BW-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
+; AVX512BW-NEXT: vpmuludq %ymm5, %ymm0, %ymm0
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm0, %ymm0
+; AVX512BW-NEXT: vpsraq $32, %zmm0, %zmm0
+; AVX512BW-NEXT: vpaddq %ymm0, %ymm3, %ymm0
+; AVX512BW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX512BW-NEXT: vpmuludq %ymm5, %ymm4, %ymm2
+; AVX512BW-NEXT: vpsllq $32, %ymm2, %ymm2
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX512BW-NEXT: vpsrlq $63, %ymm0, %ymm1
+; AVX512BW-NEXT: vpsraq $1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: retq
%res = sdiv <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
@@ -389,58 +420,79 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: test_rem7_4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: retq
+; AVX2NOBW-LABEL: test_rem7_4i64:
+; AVX2NOBW: # %bb.0:
+; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[1,1,3,3,5,5,7,7]
+; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
+; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2NOBW-NEXT: vpsrad $31, %ymm0, %ymm4
+; AVX2NOBW-NEXT: vpsrlq $32, %ymm4, %ymm4
+; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
+; AVX2NOBW-NEXT: vpsllq $32, %ymm5, %ymm5
+; AVX2NOBW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX2NOBW-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX2NOBW-NEXT: vpsrad $31, %ymm2, %ymm3
+; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm5 = ymm2[1,1,3,3,5,5,7,7]
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2],ymm3[3],ymm5[4],ymm3[5],ymm5[6],ymm3[7]
+; AVX2NOBW-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
+; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
+; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm0, %ymm6
+; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm6, %ymm2
+; AVX2NOBW-NEXT: vpsrad $31, %ymm2, %ymm6
+; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[1,1,3,3,5,5,7,7]
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm6[1],ymm2[2],ymm6[3],ymm2[4],ymm6[5],ymm2[6],ymm6[7]
+; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm4, %ymm3
+; AVX2NOBW-NEXT: vpsllq $32, %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpsrad $1, %ymm1, %ymm2
+; AVX2NOBW-NEXT: vpsrlq $1, %ymm1, %ymm3
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3],ymm3[4],ymm2[5],ymm3[6],ymm2[7]
+; AVX2NOBW-NEXT: vpsrlq $63, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX2NOBW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: retq
+;
+; AVX512BW-LABEL: test_rem7_4i64:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512BW-NEXT: vpsraq $32, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
+; AVX512BW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX512BW-NEXT: vpsrlq $32, %ymm1, %ymm4
+; AVX512BW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
+; AVX512BW-NEXT: vpsllq $32, %ymm5, %ymm5
+; AVX512BW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
+; AVX512BW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX512BW-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512BW-NEXT: vpsraq $32, %zmm2, %zmm3
+; AVX512BW-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
+; AVX512BW-NEXT: vpmuludq %ymm5, %ymm0, %ymm6
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm6, %ymm2
+; AVX512BW-NEXT: vpsraq $32, %zmm2, %zmm2
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512BW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
+; AVX512BW-NEXT: vpmuludq %ymm5, %ymm4, %ymm3
+; AVX512BW-NEXT: vpsllq $32, %ymm3, %ymm3
+; AVX512BW-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512BW-NEXT: vpsraq $1, %zmm1, %zmm1
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX512BW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: retq
%res = srem <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index b11756a5e3b4e..f8a3adf37852b 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -9,73 +9,31 @@
define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_div7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rax
-; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm1
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsraq $32, %zmm0, %zmm1
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
+; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
+; AVX-NEXT: vpsrlq $32, %zmm1, %zmm4
+; AVX-NEXT: vpmuludq %zmm2, %zmm4, %zmm5
+; AVX-NEXT: vpsllq $32, %zmm5, %zmm5
+; AVX-NEXT: vpaddq %zmm5, %zmm3, %zmm3
+; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
+; AVX-NEXT: vpsraq $32, %zmm2, %zmm3
+; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm5 = [1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513]
+; AVX-NEXT: vpmuludq %zmm5, %zmm0, %zmm0
+; AVX-NEXT: vpaddq %zmm2, %zmm0, %zmm0
+; AVX-NEXT: vpsraq $32, %zmm0, %zmm0
+; AVX-NEXT: vpaddq %zmm0, %zmm3, %zmm0
+; AVX-NEXT: vpmuludq %zmm5, %zmm1, %zmm1
+; AVX-NEXT: vpmuludq %zmm5, %zmm4, %zmm2
+; AVX-NEXT: vpsllq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm0, %zmm1, %zmm0
+; AVX-NEXT: vpsrlq $63, %zmm0, %zmm1
+; AVX-NEXT: vpsraq $1, %zmm0, %zmm0
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = sdiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
@@ -277,105 +235,34 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_rem7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm1
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsraq $32, %zmm0, %zmm1
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
+; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
+; AVX-NEXT: vpsrlq $32, %zmm1, %zmm4
+; AVX-NEXT: vpmuludq %zmm2, %zmm4, %zmm5
+; AVX-NEXT: vpsllq $32, %zmm5, %zmm5
+; AVX-NEXT: vpaddq %zmm5, %zmm3, %zmm3
+; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
+; AVX-NEXT: vpsraq $32, %zmm2, %zmm3
+; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm5 = [1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513]
+; AVX-NEXT: vpmuludq %zmm5, %zmm0, %zmm6
+; AVX-NEXT: vpaddq %zmm2, %zmm6, %zmm2
+; AVX-NEXT: vpsraq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
+; AVX-NEXT: vpmuludq %zmm5, %zmm1, %zmm1
+; AVX-NEXT: vpmuludq %zmm5, %zmm4, %zmm3
+; AVX-NEXT: vpsllq $32, %zmm3, %zmm3
+; AVX-NEXT: vpaddq %zmm3, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsrlq $63, %zmm1, %zmm2
+; AVX-NEXT: vpsraq $1, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsllq $3, %zmm1, %zmm2
+; AVX-NEXT: vpsubq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = srem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
index ca57359183312..37c416f18736a 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
@@ -49,39 +49,25 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
;
; AVX2-LABEL: test_div7_4i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: subq %rdx, %rcx
-; AVX2-NEXT: shrq %rcx
-; AVX2-NEXT: addq %rdx, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm1
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2454267027,2454267027,2454267027,2454267027]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [613566756,613566756,613566756,613566756]
+; AVX2-NEXT: vpmuludq %ymm4, %ymm0, %ymm5
+; AVX2-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpmuludq %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0
+; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpsrlq $2, %ymm0, %ymm0
; AVX2-NEXT: retq
%res = udiv <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
@@ -423,59 +409,29 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
;
; AVX2-LABEL: test_rem7_4i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: mulq %rsi
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: shrq %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: shrq $2, %rax
-; AVX2-NEXT: leaq (,%rax,8), %rdx
-; AVX2-NEXT: subq %rdx, %rax
-; AVX2-NEXT: addq %rcx, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm1
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2454267027,2454267027,2454267027,2454267027]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm3
+; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [613566756,613566756,613566756,613566756]
+; AVX2-NEXT: vpmuludq %ymm4, %ymm0, %ymm5
+; AVX2-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX2-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX2-NEXT: vpmuludq %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm2
+; AVX2-NEXT: vpsrlq $1, %ymm2, %ymm2
+; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpsrlq $2, %ymm1, %ymm1
+; AVX2-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX2-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
%res = urem <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
index b8a131e628007..31d70041f9d0b 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
@@ -9,73 +9,24 @@
define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_div7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm1
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: subq %rdx, %rcx
-; AVX-NEXT: shrq %rcx
-; AVX-NEXT: addq %rdx, %rcx
-; AVX-NEXT: vmovq %rcx, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $32, %zmm0, %zmm1
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027]
+; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
+; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm3
+; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm4 = [613566756,613566756,613566756,613566756,613566756,613566756,613566756,613566756]
+; AVX-NEXT: vpmuludq %zmm4, %zmm0, %zmm5
+; AVX-NEXT: vpaddq %zmm2, %zmm5, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpmuludq %zmm4, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm3, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsubq %zmm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $1, %zmm0, %zmm0
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: vpsrlq $2, %zmm0, %zmm0
; AVX-NEXT: retq
%res = udiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
@@ -295,113 +246,28 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_rem7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX-NEXT: movabsq $2635249153387078803, %rsi # imm = 0x2492492492492493
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm1
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm2
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: mulq %rsi
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: shrq %rax
-; AVX-NEXT: addq %rdx, %rax
-; AVX-NEXT: shrq $2, %rax
-; AVX-NEXT: leaq (,%rax,8), %rdx
-; AVX-NEXT: subq %rdx, %rax
-; AVX-NEXT: addq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $32, %zmm0, %zmm1
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027]
+; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
+; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm3
+; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
+; AVX-NEXT: vpbroadcastq {{.*#+}} zmm4 = [613566756,613566756,613566756,613566756,613566756,613566756,613566756,613566756]
+; AVX-NEXT: vpmuludq %zmm4, %zmm0, %zmm5
+; AVX-NEXT: vpaddq %zmm2, %zmm5, %zmm2
+; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
+; AVX-NEXT: vpmuludq %zmm4, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm3, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsubq %zmm1, %zmm0, %zmm2
+; AVX-NEXT: vpsrlq $1, %zmm2, %zmm2
+; AVX-NEXT: vpaddq %zmm1, %zmm2, %zmm1
+; AVX-NEXT: vpsrlq $2, %zmm1, %zmm1
+; AVX-NEXT: vpsllq $3, %zmm1, %zmm2
+; AVX-NEXT: vpsubq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = urem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
>From 0f7071ce5b50b5f2e1160e766cce4b462a61e3e6 Mon Sep 17 00:00:00 2001
From: Rito Takeuchi <licht-t at outlook.jp>
Date: Wed, 1 Jul 2026 01:05:58 +0900
Subject: [PATCH 2/7] [X86] Defer MULHS v4i64/v8i64 to a follow-up
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 2 -
llvm/test/CodeGen/X86/srem-vector-lkk.ll | 155 ++++++------
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 228 +++++++-----------
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 219 +++++++++++++----
4 files changed, 334 insertions(+), 270 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 457b66582f9b1..8c465e106d611 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1749,7 +1749,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
if (HasInt256) {
- setOperationAction(ISD::MULHS, MVT::v4i64, Custom);
setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
@@ -2024,7 +2023,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
setOperationAction(ISD::MUL, MVT::v64i8, Custom);
- setOperationAction(ISD::MULHS, MVT::v8i64, Custom);
setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index d65c977592677..678515c3e572e 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -534,85 +534,90 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
;
; AVX2-LABEL: dont_fold_srem_i64:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpmovsxdq {{.*#+}} ymm1 = [0,1681210440,18446744072402387656,1621997606]
-; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,0,0,0,4294967295,0,0,0]
-; AVX2-NEXT: vpmuludq %ymm3, %ymm0, %ymm4
-; AVX2-NEXT: vpsllq $32, %ymm4, %ymm4
-; AVX2-NEXT: vpaddq %ymm4, %ymm2, %ymm2
-; AVX2-NEXT: vpshufd {{.*#+}} ymm4 = ymm0[1,1,3,3,5,5,7,7]
-; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm5 = [0,105075653,1493901669,3856996263]
-; AVX2-NEXT: vpmuludq %ymm5, %ymm4, %ymm6
-; AVX2-NEXT: vpsrad $31, %ymm0, %ymm7
-; AVX2-NEXT: vpsrlq $32, %ymm7, %ymm7
-; AVX2-NEXT: vpmuludq %ymm5, %ymm7, %ymm8
-; AVX2-NEXT: vpsllq $32, %ymm8, %ymm8
-; AVX2-NEXT: vpaddq %ymm6, %ymm8, %ymm6
-; AVX2-NEXT: vpmuludq %ymm5, %ymm0, %ymm5
-; AVX2-NEXT: vpsrlq $32, %ymm5, %ymm5
-; AVX2-NEXT: vpaddq %ymm5, %ymm6, %ymm5
-; AVX2-NEXT: vpxor %xmm6, %xmm6, %xmm6
-; AVX2-NEXT: vpblendd {{.*#+}} ymm8 = ymm5[0],ymm6[1],ymm5[2],ymm6[3],ymm5[4],ymm6[5],ymm5[6],ymm6[7]
-; AVX2-NEXT: vpaddq %ymm2, %ymm8, %ymm2
-; AVX2-NEXT: vpsrad $31, %ymm2, %ymm8
-; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[1,1,3,3,5,5,7,7]
-; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm8[1],ymm2[2],ymm8[3],ymm2[4],ymm8[5],ymm2[6],ymm8[7]
-; AVX2-NEXT: vpsrad $31, %ymm5, %ymm8
-; AVX2-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[1,1,3,3,5,5,7,7]
-; AVX2-NEXT: vpblendd {{.*#+}} ymm5 = ymm5[0],ymm8[1],ymm5[2],ymm8[3],ymm5[4],ymm8[5],ymm5[6],ymm8[7]
-; AVX2-NEXT: vpaddq %ymm2, %ymm5, %ymm2
-; AVX2-NEXT: vpmuludq %ymm3, %ymm4, %ymm3
-; AVX2-NEXT: vpmuludq %ymm1, %ymm7, %ymm5
-; AVX2-NEXT: vpaddq %ymm5, %ymm3, %ymm3
-; AVX2-NEXT: vpsllq $32, %ymm3, %ymm3
-; AVX2-NEXT: vpmuludq %ymm1, %ymm4, %ymm1
-; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
-; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm6[2,3],ymm0[4,5],ymm6[6,7]
-; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
-; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX2-NEXT: vpsrlq $63, %ymm1, %ymm2
-; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm6[0,1],ymm2[2,3,4,5,6,7]
-; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [9223372036854775808,36028797018963968,576460752303423488,4503599627370496]
-; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
-; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX2-NEXT: vpsubq %ymm3, %ymm1, %ymm1
-; AVX2-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
-; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
-; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
-; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm1
-; AVX2-NEXT: vpsllq $32, %ymm1, %ymm1
-; AVX2-NEXT: vpaddq %ymm1, %ymm3, %ymm1
-; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rdx
+; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq $4, %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: leaq (%rdx,%rdx,2), %rax
+; AVX2-NEXT: shlq $3, %rax
+; AVX2-NEXT: subq %rax, %rdx
+; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm2
+; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX2-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rdx
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq $11, %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
+; AVX2-NEXT: subq %rax, %rcx
+; AVX2-NEXT: vmovq %rcx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rdx
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq $8, %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
+; AVX2-NEXT: subq %rax, %rcx
+; AVX2-NEXT: vmovq %rcx, %xmm0
+; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
+; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: dont_fold_srem_i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpsraq $32, %ymm0, %ymm1
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm2 = [0,105075653,1493901669,3856996263]
-; AVX512-NEXT: vpmullq %ymm2, %ymm1, %ymm3
-; AVX512-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
-; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm2
-; AVX512-NEXT: vpaddq %ymm2, %ymm3, %ymm2
-; AVX512-NEXT: vpsraq $32, %ymm2, %ymm3
-; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX512-NEXT: vpblendd {{.*#+}} ymm5 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7]
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1681210440,18446744072402387656,1621997606]
-; AVX512-NEXT: vpmullq %ymm6, %ymm5, %ymm5
-; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
-; AVX512-NEXT: vpaddq %ymm2, %ymm5, %ymm2
-; AVX512-NEXT: vpsraq $32, %ymm2, %ymm2
-; AVX512-NEXT: vpmuldq %ymm6, %ymm1, %ymm1
-; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
-; AVX512-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm4[2,3],ymm0[4,5],ymm4[6,7]
-; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
-; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX512-NEXT: vpsrlq $63, %ymm1, %ymm2
-; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3,4,5,6,7]
-; AVX512-NEXT: vpsravq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX512-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [1,654,23,5423]
-; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX512-NEXT: vmovq %xmm1, %rcx
+; AVX512-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
+; AVX512-NEXT: movq %rcx, %rax
+; AVX512-NEXT: imulq %rdx
+; AVX512-NEXT: addq %rcx, %rdx
+; AVX512-NEXT: movq %rdx, %rax
+; AVX512-NEXT: shrq $63, %rax
+; AVX512-NEXT: sarq $4, %rdx
+; AVX512-NEXT: addq %rax, %rdx
+; AVX512-NEXT: leaq (%rdx,%rdx,2), %rax
+; AVX512-NEXT: shlq $3, %rax
+; AVX512-NEXT: subq %rax, %rdx
+; AVX512-NEXT: addq %rcx, %rdx
+; AVX512-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX512-NEXT: vmovq %rdx, %xmm1
+; AVX512-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
+; AVX512-NEXT: movq %rcx, %rax
+; AVX512-NEXT: imulq %rdx
+; AVX512-NEXT: movq %rdx, %rax
+; AVX512-NEXT: shrq $63, %rax
+; AVX512-NEXT: sarq $11, %rdx
+; AVX512-NEXT: addq %rax, %rdx
+; AVX512-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
+; AVX512-NEXT: subq %rax, %rcx
+; AVX512-NEXT: vmovq %rcx, %xmm2
+; AVX512-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm2[0]
+; AVX512-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
+; AVX512-NEXT: movq %rcx, %rax
+; AVX512-NEXT: imulq %rdx
+; AVX512-NEXT: movq %rdx, %rax
+; AVX512-NEXT: shrq $63, %rax
+; AVX512-NEXT: sarq $8, %rdx
+; AVX512-NEXT: addq %rax, %rdx
+; AVX512-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
+; AVX512-NEXT: subq %rax, %rcx
+; AVX512-NEXT: vmovq %rcx, %xmm1
+; AVX512-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
+; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX512-NEXT: retq
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index bde671cb4f4a8..fa5692aa9cef1 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -45,73 +45,42 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2NOBW-LABEL: test_div7_4i64:
-; AVX2NOBW: # %bb.0:
-; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[1,1,3,3,5,5,7,7]
-; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
-; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
-; AVX2NOBW-NEXT: vpsrad $31, %ymm0, %ymm4
-; AVX2NOBW-NEXT: vpsrlq $32, %ymm4, %ymm4
-; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
-; AVX2NOBW-NEXT: vpsllq $32, %ymm5, %ymm5
-; AVX2NOBW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
-; AVX2NOBW-NEXT: vpsrlq $32, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
-; AVX2NOBW-NEXT: vpsrad $31, %ymm2, %ymm3
-; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm5 = ymm2[1,1,3,3,5,5,7,7]
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2],ymm3[3],ymm5[4],ymm3[5],ymm5[6],ymm3[7]
-; AVX2NOBW-NEXT: vpxor %xmm5, %xmm5, %xmm5
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
-; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
-; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpsrad $31, %ymm0, %ymm2
-; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7]
-; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm3, %ymm0
-; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm4, %ymm2
-; AVX2NOBW-NEXT: vpsllq $32, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
-; AVX2NOBW-NEXT: vpsrad $1, %ymm0, %ymm1
-; AVX2NOBW-NEXT: vpsrlq $1, %ymm0, %ymm2
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2],ymm1[3],ymm2[4],ymm1[5],ymm2[6],ymm1[7]
-; AVX2NOBW-NEXT: vpsrlq $63, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
-; AVX2NOBW-NEXT: retq
-;
-; AVX512BW-LABEL: test_div7_4i64:
-; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512BW-NEXT: vpsraq $32, %zmm0, %zmm1
-; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
-; AVX512BW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
-; AVX512BW-NEXT: vpsrlq $32, %ymm1, %ymm4
-; AVX512BW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
-; AVX512BW-NEXT: vpsllq $32, %ymm5, %ymm5
-; AVX512BW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
-; AVX512BW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
-; AVX512BW-NEXT: vpsrlq $32, %ymm2, %ymm2
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
-; AVX512BW-NEXT: vpsraq $32, %zmm2, %zmm3
-; AVX512BW-NEXT: vpxor %xmm5, %xmm5, %xmm5
-; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
-; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
-; AVX512BW-NEXT: vpmuludq %ymm5, %ymm0, %ymm0
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm0, %ymm0
-; AVX512BW-NEXT: vpsraq $32, %zmm0, %zmm0
-; AVX512BW-NEXT: vpaddq %ymm0, %ymm3, %ymm0
-; AVX512BW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
-; AVX512BW-NEXT: vpmuludq %ymm5, %ymm4, %ymm2
-; AVX512BW-NEXT: vpsllq $32, %ymm2, %ymm2
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vpsrlq $63, %ymm0, %ymm1
-; AVX512BW-NEXT: vpsraq $1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
-; AVX512BW-NEXT: retq
+; AVX2-LABEL: test_div7_4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm2
+; AVX2-NEXT: vmovq %xmm1, %rax
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm2
+; AVX2-NEXT: vmovq %xmm0, %rax
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm0
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
%res = sdiv <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
@@ -420,79 +389,58 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2NOBW-LABEL: test_rem7_4i64:
-; AVX2NOBW: # %bb.0:
-; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[1,1,3,3,5,5,7,7]
-; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
-; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
-; AVX2NOBW-NEXT: vpsrad $31, %ymm0, %ymm4
-; AVX2NOBW-NEXT: vpsrlq $32, %ymm4, %ymm4
-; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
-; AVX2NOBW-NEXT: vpsllq $32, %ymm5, %ymm5
-; AVX2NOBW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
-; AVX2NOBW-NEXT: vpsrlq $32, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
-; AVX2NOBW-NEXT: vpsrad $31, %ymm2, %ymm3
-; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm5 = ymm2[1,1,3,3,5,5,7,7]
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm3 = ymm5[0],ymm3[1],ymm5[2],ymm3[3],ymm5[4],ymm3[5],ymm5[6],ymm3[7]
-; AVX2NOBW-NEXT: vpxor %xmm5, %xmm5, %xmm5
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
-; AVX2NOBW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
-; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm0, %ymm6
-; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm6, %ymm2
-; AVX2NOBW-NEXT: vpsrad $31, %ymm2, %ymm6
-; AVX2NOBW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[1,1,3,3,5,5,7,7]
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm6[1],ymm2[2],ymm6[3],ymm2[4],ymm6[5],ymm2[6],ymm6[7]
-; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
-; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpmuludq %ymm5, %ymm4, %ymm3
-; AVX2NOBW-NEXT: vpsllq $32, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpaddq %ymm3, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpsrad $1, %ymm1, %ymm2
-; AVX2NOBW-NEXT: vpsrlq $1, %ymm1, %ymm3
-; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3],ymm3[4],ymm2[5],ymm3[6],ymm2[7]
-; AVX2NOBW-NEXT: vpsrlq $63, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm2, %ymm1
-; AVX2NOBW-NEXT: vpsllq $3, %ymm1, %ymm2
-; AVX2NOBW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
-; AVX2NOBW-NEXT: retq
-;
-; AVX512BW-LABEL: test_rem7_4i64:
-; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512BW-NEXT: vpsraq $32, %zmm0, %zmm1
-; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm2 = [613566757,613566757,613566757,613566757]
-; AVX512BW-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
-; AVX512BW-NEXT: vpsrlq $32, %ymm1, %ymm4
-; AVX512BW-NEXT: vpmuludq %ymm2, %ymm4, %ymm5
-; AVX512BW-NEXT: vpsllq $32, %ymm5, %ymm5
-; AVX512BW-NEXT: vpaddq %ymm5, %ymm3, %ymm3
-; AVX512BW-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
-; AVX512BW-NEXT: vpsrlq $32, %ymm2, %ymm2
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
-; AVX512BW-NEXT: vpsraq $32, %zmm2, %zmm3
-; AVX512BW-NEXT: vpxor %xmm5, %xmm5, %xmm5
-; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm5[1],ymm2[2],ymm5[3],ymm2[4],ymm5[5],ymm2[6],ymm5[7]
-; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1227133513,1227133513,1227133513,1227133513]
-; AVX512BW-NEXT: vpmuludq %ymm5, %ymm0, %ymm6
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm6, %ymm2
-; AVX512BW-NEXT: vpsraq $32, %zmm2, %zmm2
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm3, %ymm2
-; AVX512BW-NEXT: vpmuludq %ymm5, %ymm1, %ymm1
-; AVX512BW-NEXT: vpmuludq %ymm5, %ymm4, %ymm3
-; AVX512BW-NEXT: vpsllq $32, %ymm3, %ymm3
-; AVX512BW-NEXT: vpaddq %ymm3, %ymm1, %ymm1
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpsrlq $63, %ymm1, %ymm2
-; AVX512BW-NEXT: vpsraq $1, %zmm1, %zmm1
-; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpsllq $3, %ymm1, %ymm2
-; AVX512BW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
-; AVX512BW-NEXT: retq
+; AVX2-LABEL: test_rem7_4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: leaq (,%rdx,8), %rax
+; AVX2-NEXT: subq %rax, %rdx
+; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm2
+; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: leaq (,%rdx,8), %rax
+; AVX2-NEXT: subq %rax, %rdx
+; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: leaq (,%rdx,8), %rax
+; AVX2-NEXT: subq %rax, %rdx
+; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm2
+; AVX2-NEXT: vmovq %xmm0, %rcx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
+; AVX2-NEXT: movq %rdx, %rax
+; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: sarq %rdx
+; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: leaq (,%rdx,8), %rax
+; AVX2-NEXT: subq %rax, %rdx
+; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm0
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
%res = srem <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index f8a3adf37852b..b11756a5e3b4e 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -9,31 +9,73 @@
define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_div7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vpsraq $32, %zmm0, %zmm1
-; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
-; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
-; AVX-NEXT: vpsrlq $32, %zmm1, %zmm4
-; AVX-NEXT: vpmuludq %zmm2, %zmm4, %zmm5
-; AVX-NEXT: vpsllq $32, %zmm5, %zmm5
-; AVX-NEXT: vpaddq %zmm5, %zmm3, %zmm3
-; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
-; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
-; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
-; AVX-NEXT: vpsraq $32, %zmm2, %zmm3
-; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
-; AVX-NEXT: vpbroadcastq {{.*#+}} zmm5 = [1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513]
-; AVX-NEXT: vpmuludq %zmm5, %zmm0, %zmm0
-; AVX-NEXT: vpaddq %zmm2, %zmm0, %zmm0
-; AVX-NEXT: vpsraq $32, %zmm0, %zmm0
-; AVX-NEXT: vpaddq %zmm0, %zmm3, %zmm0
-; AVX-NEXT: vpmuludq %zmm5, %zmm1, %zmm1
-; AVX-NEXT: vpmuludq %zmm5, %zmm4, %zmm2
-; AVX-NEXT: vpsllq $32, %zmm2, %zmm2
-; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
-; AVX-NEXT: vpaddq %zmm0, %zmm1, %zmm0
-; AVX-NEXT: vpsrlq $63, %zmm0, %zmm1
-; AVX-NEXT: vpsraq $1, %zmm0, %zmm0
-; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
+; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
+; AVX-NEXT: vpextrq $1, %xmm1, %rax
+; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm2
+; AVX-NEXT: vmovq %xmm1, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm1
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
+; AVX-NEXT: vpextrq $1, %xmm2, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm3
+; AVX-NEXT: vmovq %xmm2, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm2
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
+; AVX-NEXT: vpextrq $1, %xmm2, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm3
+; AVX-NEXT: vmovq %xmm2, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm2
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; AVX-NEXT: vpextrq $1, %xmm0, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm3
+; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm0
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
+; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
+; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = sdiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
@@ -235,34 +277,105 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_rem7_8i64:
; AVX: # %bb.0:
-; AVX-NEXT: vpsraq $32, %zmm0, %zmm1
-; AVX-NEXT: vpbroadcastq {{.*#+}} zmm2 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
-; AVX-NEXT: vpmuludq %zmm2, %zmm1, %zmm3
-; AVX-NEXT: vpsrlq $32, %zmm1, %zmm4
-; AVX-NEXT: vpmuludq %zmm2, %zmm4, %zmm5
-; AVX-NEXT: vpsllq $32, %zmm5, %zmm5
-; AVX-NEXT: vpaddq %zmm5, %zmm3, %zmm3
-; AVX-NEXT: vpmuludq %zmm2, %zmm0, %zmm2
-; AVX-NEXT: vpsrlq $32, %zmm2, %zmm2
-; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
-; AVX-NEXT: vpsraq $32, %zmm2, %zmm3
-; AVX-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm2
-; AVX-NEXT: vpbroadcastq {{.*#+}} zmm5 = [1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513,1227133513]
-; AVX-NEXT: vpmuludq %zmm5, %zmm0, %zmm6
-; AVX-NEXT: vpaddq %zmm2, %zmm6, %zmm2
-; AVX-NEXT: vpsraq $32, %zmm2, %zmm2
-; AVX-NEXT: vpaddq %zmm2, %zmm3, %zmm2
-; AVX-NEXT: vpmuludq %zmm5, %zmm1, %zmm1
-; AVX-NEXT: vpmuludq %zmm5, %zmm4, %zmm3
-; AVX-NEXT: vpsllq $32, %zmm3, %zmm3
-; AVX-NEXT: vpaddq %zmm3, %zmm1, %zmm1
-; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
-; AVX-NEXT: vpsrlq $63, %zmm1, %zmm2
-; AVX-NEXT: vpsraq $1, %zmm1, %zmm1
-; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
-; AVX-NEXT: vpsllq $3, %zmm1, %zmm2
-; AVX-NEXT: vpsubq %zmm2, %zmm1, %zmm1
-; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
+; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
+; AVX-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm2
+; AVX-NEXT: vmovq %xmm1, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm1
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
+; AVX-NEXT: vpextrq $1, %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm3
+; AVX-NEXT: vmovq %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm2
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
+; AVX-NEXT: vpextrq $1, %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm3
+; AVX-NEXT: vmovq %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm2
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; AVX-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm3
+; AVX-NEXT: vmovq %xmm0, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
+; AVX-NEXT: movq %rdx, %rax
+; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: sarq %rdx
+; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: leaq (,%rdx,8), %rax
+; AVX-NEXT: subq %rax, %rdx
+; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %rdx, %xmm0
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
+; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
+; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = srem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
>From f5946af1c178c099b5a107da17f985ef776dd73b Mon Sep 17 00:00:00 2001
From: Rito Takeuchi <licht-t at outlook.jp>
Date: Wed, 1 Jul 2026 04:53:59 +0900
Subject: [PATCH 3/7] [X86] Keep full 128-bit products scalar via UMUL_LOHI
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 8 +-
.../X86/mulhu-v4i64-umul-lohi-guard.ll | 161 ++++++++++++++++++
2 files changed, 167 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8c465e106d611..a27ad2e27e70f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1749,7 +1749,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
if (HasInt256) {
- setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
+ setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
+ // Custom so the combiner keeps full products as UMUL_LOHI, not MULHU.
+ setOperationAction(ISD::UMUL_LOHI, MVT::v4i64, Custom);
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
// Custom legalize 2x32 to get a little better code.
@@ -2023,7 +2025,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v32i16, HasBWI ? Legal : Custom);
setOperationAction(ISD::MUL, MVT::v64i8, Custom);
- setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
+ setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
+ setOperationAction(ISD::UMUL_LOHI, MVT::v8i64, Custom);
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
@@ -34326,6 +34329,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
case ISD::MULHS:
case ISD::MULHU: return LowerMULH(Op, Subtarget, DAG);
+ case ISD::UMUL_LOHI: return DAG.UnrollVectorOp(Op.getNode());
case ISD::ROTL:
case ISD::ROTR: return LowerRotate(Op, Subtarget, DAG);
case ISD::SRA:
diff --git a/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll b/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
new file mode 100644
index 0000000000000..1886cc421d605
--- /dev/null
+++ b/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
@@ -0,0 +1,161 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512
+
+; Step 1 guard for the vXi64 MULHU lowering. The `zext to i128 / mul / lshr 64 /
+; trunc` idiom below is exactly what the loop vectorizer emits for a full
+; 128-bit product (e.g. a wyhash-style `lo ^ hi` mix). When BOTH halves are
+; used (UMUL_LOHI), vectorizing the high half via the vpmuludq schoolbook loses
+; to scalar codegen, where one multiply yields both halves; the lowering must
+; back off and let it scalarize. When only the high half is used (the
+; divide-by-constant case), it must still vectorize.
+
+; Both halves used -> must scalarize (no vpmuludq schoolbook for the high half).
+define <4 x i64> @umul_lohi_both_halves(<4 x i64> %a, <4 x i64> %b, ptr %plo) nounwind {
+; AVX2-LABEL: umul_lohi_both_halves:
+; AVX2: # %bb.0:
+; AVX2-NEXT: pushq %r14
+; AVX2-NEXT: pushq %rbx
+; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX2-NEXT: vmovq %xmm0, %rsi
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
+; AVX2-NEXT: vpextrq $1, %xmm0, %r8
+; AVX2-NEXT: vmovq %xmm0, %rax
+; AVX2-NEXT: vpextrq $1, %xmm1, %r14
+; AVX2-NEXT: vmovq %xmm1, %rbx
+; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0
+; AVX2-NEXT: vpextrq $1, %xmm0, %r11
+; AVX2-NEXT: vmovq %xmm0, %rdx
+; AVX2-NEXT: mulq %rdx
+; AVX2-NEXT: movq %rdx, %r9
+; AVX2-NEXT: movq %rax, %r10
+; AVX2-NEXT: movq %r8, %rax
+; AVX2-NEXT: mulq %r11
+; AVX2-NEXT: movq %rdx, %r8
+; AVX2-NEXT: movq %rax, %r11
+; AVX2-NEXT: movq %rsi, %rax
+; AVX2-NEXT: mulq %rbx
+; AVX2-NEXT: movq %rdx, %rsi
+; AVX2-NEXT: movq %rax, %rbx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: mulq %r14
+; AVX2-NEXT: vmovq %rax, %xmm0
+; AVX2-NEXT: vmovq %rbx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; AVX2-NEXT: vmovq %r11, %xmm0
+; AVX2-NEXT: vmovq %r10, %xmm2
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; AVX2-NEXT: vmovq %r8, %xmm0
+; AVX2-NEXT: vmovq %r9, %xmm3
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; AVX2-NEXT: vmovq %rdx, %xmm3
+; AVX2-NEXT: vmovq %rsi, %xmm4
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0
+; AVX2-NEXT: vmovdqa %xmm2, 16(%rdi)
+; AVX2-NEXT: vmovdqa %xmm1, (%rdi)
+; AVX2-NEXT: popq %rbx
+; AVX2-NEXT: popq %r14
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: umul_lohi_both_halves:
+; AVX512: # %bb.0:
+; AVX512-NEXT: pushq %r14
+; AVX512-NEXT: pushq %rbx
+; AVX512-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX512-NEXT: vmovq %xmm0, %rsi
+; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm0
+; AVX512-NEXT: vpextrq $1, %xmm0, %r8
+; AVX512-NEXT: vmovq %xmm0, %rax
+; AVX512-NEXT: vpextrq $1, %xmm1, %r14
+; AVX512-NEXT: vmovq %xmm1, %rbx
+; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm0
+; AVX512-NEXT: vpextrq $1, %xmm0, %r11
+; AVX512-NEXT: vmovq %xmm0, %rdx
+; AVX512-NEXT: mulq %rdx
+; AVX512-NEXT: movq %rdx, %r9
+; AVX512-NEXT: movq %rax, %r10
+; AVX512-NEXT: movq %r8, %rax
+; AVX512-NEXT: mulq %r11
+; AVX512-NEXT: movq %rdx, %r8
+; AVX512-NEXT: movq %rax, %r11
+; AVX512-NEXT: movq %rsi, %rax
+; AVX512-NEXT: mulq %rbx
+; AVX512-NEXT: movq %rdx, %rsi
+; AVX512-NEXT: movq %rax, %rbx
+; AVX512-NEXT: movq %rcx, %rax
+; AVX512-NEXT: mulq %r14
+; AVX512-NEXT: vmovq %rax, %xmm0
+; AVX512-NEXT: vmovq %rbx, %xmm1
+; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; AVX512-NEXT: vmovq %r11, %xmm0
+; AVX512-NEXT: vmovq %r10, %xmm2
+; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; AVX512-NEXT: vmovq %r8, %xmm0
+; AVX512-NEXT: vmovq %r9, %xmm3
+; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
+; AVX512-NEXT: vmovq %rdx, %xmm3
+; AVX512-NEXT: vmovq %rsi, %xmm4
+; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0
+; AVX512-NEXT: vmovdqa %xmm2, 16(%rdi)
+; AVX512-NEXT: vmovdqa %xmm1, (%rdi)
+; AVX512-NEXT: popq %rbx
+; AVX512-NEXT: popq %r14
+; AVX512-NEXT: retq
+ %za = zext <4 x i64> %a to <4 x i128>
+ %zb = zext <4 x i64> %b to <4 x i128>
+ %prod = mul nuw <4 x i128> %za, %zb
+ %lo = trunc <4 x i128> %prod to <4 x i64>
+ %shift = lshr <4 x i128> %prod, <i128 64, i128 64, i128 64, i128 64>
+ %hi = trunc <4 x i128> %shift to <4 x i64>
+ store <4 x i64> %lo, ptr %plo
+ ret <4 x i64> %hi
+}
+
+; Only the high half used -> MULHU should still vectorize (vpmuludq schoolbook).
+define <4 x i64> @mulhu_high_only(<4 x i64> %a, <4 x i64> %b) nounwind {
+; AVX2-LABEL: mulhu_high_only:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm2
+; AVX2-NEXT: vpmuludq %ymm1, %ymm2, %ymm3
+; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm4
+; AVX2-NEXT: vpsrlq $32, %ymm4, %ymm4
+; AVX2-NEXT: vpaddq %ymm4, %ymm3, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm3, %ymm4
+; AVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0],ymm5[1],ymm3[2],ymm5[3],ymm3[4],ymm5[5],ymm3[6],ymm5[7]
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: vpaddq %ymm3, %ymm0, %ymm0
+; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm0
+; AVX2-NEXT: vpmuludq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vpaddq %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: mulhu_high_only:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpsrlq $32, %ymm0, %ymm2
+; AVX512-NEXT: vpmuludq %ymm1, %ymm2, %ymm3
+; AVX512-NEXT: vpmuludq %ymm1, %ymm0, %ymm4
+; AVX512-NEXT: vpsrlq $32, %ymm4, %ymm4
+; AVX512-NEXT: vpaddq %ymm4, %ymm3, %ymm3
+; AVX512-NEXT: vpsrlq $32, %ymm3, %ymm4
+; AVX512-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX512-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0],ymm5[1],ymm3[2],ymm5[3],ymm3[4],ymm5[5],ymm3[6],ymm5[7]
+; AVX512-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX512-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: vpaddq %ymm3, %ymm0, %ymm0
+; AVX512-NEXT: vpsrlq $32, %ymm0, %ymm0
+; AVX512-NEXT: vpmuludq %ymm1, %ymm2, %ymm1
+; AVX512-NEXT: vpaddq %ymm4, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX512-NEXT: retq
+ %za = zext <4 x i64> %a to <4 x i128>
+ %zb = zext <4 x i64> %b to <4 x i128>
+ %prod = mul nuw <4 x i128> %za, %zb
+ %shift = lshr <4 x i128> %prod, <i128 64, i128 64, i128 64, i128 64>
+ %hi = trunc <4 x i128> %shift to <4 x i64>
+ ret <4 x i64> %hi
+}
>From feb9365474120ed7782e76cd1381064e5cb59f07 Mon Sep 17 00:00:00 2001
From: Rito Takeuchi <licht-t at outlook.jp>
Date: Fri, 3 Jul 2026 04:37:23 +0900
Subject: [PATCH 4/7] [X86] Fold MULHS/SMUL_LOHI v4i64/v8i64 in, gated on
AVX512DQ
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 13 +-
llvm/test/CodeGen/X86/srem-vector-lkk.ll | 134 +++++-------
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 192 ++++++++++--------
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 147 +++-----------
4 files changed, 202 insertions(+), 284 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a27ad2e27e70f..06df6d78953c0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1750,8 +1750,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
if (HasInt256) {
setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
- // Custom so the combiner keeps full products as UMUL_LOHI, not MULHU.
+ // MULHS is only a win when the low multiply can use vpmullq, so gate it
+ // on AVX512DQ+VL; without it the schoolbook loses to scalar (esp. AVX2).
+ if (Subtarget.hasDQI() && Subtarget.hasVLX())
+ setOperationAction(ISD::MULHS, MVT::v4i64, Custom);
+ // Custom so the combiner keeps full products as [SU]MUL_LOHI, not
+ // MULH[SU].
setOperationAction(ISD::UMUL_LOHI, MVT::v4i64, Custom);
+ setOperationAction(ISD::SMUL_LOHI, MVT::v4i64, Custom);
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
// Custom legalize 2x32 to get a little better code.
@@ -2026,7 +2032,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v64i8, Custom);
setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
+ // MULHS needs vpmullq (AVX512DQ) for its low multiply to be a win.
+ if (Subtarget.hasDQI())
+ setOperationAction(ISD::MULHS, MVT::v8i64, Custom);
setOperationAction(ISD::UMUL_LOHI, MVT::v8i64, Custom);
+ setOperationAction(ISD::SMUL_LOHI, MVT::v8i64, Custom);
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
@@ -34329,6 +34339,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
case ISD::MULHS:
case ISD::MULHU: return LowerMULH(Op, Subtarget, DAG);
+ case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: return DAG.UnrollVectorOp(Op.getNode());
case ISD::ROTL:
case ISD::ROTR: return LowerRotate(Op, Subtarget, DAG);
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index 678515c3e572e..464f4de867ecd 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -535,89 +535,67 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX2-LABEL: dont_fold_srem_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $4, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (%rdx,%rdx,2), %rax
-; AVX2-NEXT: shlq $3, %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
+; AVX2-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2-NEXT: movabsq $6966426675817289639, %rcx # imm = 0x60ADB826E5E517A7
+; AVX2-NEXT: imulq %rcx
; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $11, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq $8, %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX2-NEXT: subq %rax, %rcx
-; AVX2-NEXT: vmovq %rcx, %xmm0
-; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vmovq %xmm1, %rax
+; AVX2-NEXT: movabsq $-5614226457215950491, %rcx # imm = 0xB21642C8590B2165
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: vmovq %rdx, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2-NEXT: movabsq $7220743857598845893, %rcx # imm = 0x64353C48064353C5
+; AVX2-NEXT: imulq %rcx
+; AVX2-NEXT: vmovq %rdx, %xmm2
+; AVX2-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
+; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm2[2,3],ymm0[4,5],ymm2[6,7]
+; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpsrlq $63, %ymm1, %ymm3
+; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1],ymm3[2,3,4,5,6,7]
+; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [9223372036854775808,36028797018963968,576460752303423488,4503599627370496]
+; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsubq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm3
+; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsllq $32, %ymm1, %ymm1
+; AVX2-NEXT: vpaddq %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: dont_fold_srem_i64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX512-NEXT: vmovq %xmm1, %rcx
-; AVX512-NEXT: movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: addq %rcx, %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $4, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: leaq (%rdx,%rdx,2), %rax
-; AVX512-NEXT: shlq $3, %rax
-; AVX512-NEXT: subq %rax, %rdx
-; AVX512-NEXT: addq %rcx, %rdx
-; AVX512-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX512-NEXT: vmovq %rdx, %xmm1
-; AVX512-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $11, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: vmovq %rcx, %xmm2
-; AVX512-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm2[0]
-; AVX512-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
-; AVX512-NEXT: movq %rcx, %rax
-; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
-; AVX512-NEXT: sarq $8, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
-; AVX512-NEXT: subq %rax, %rcx
-; AVX512-NEXT: vmovq %rcx, %xmm1
-; AVX512-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX512-NEXT: vpsraq $32, %ymm0, %ymm1
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm2 = [0,105075653,1493901669,3856996263]
+; AVX512-NEXT: vpmullq %ymm2, %ymm1, %ymm3
+; AVX512-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX512-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512-NEXT: vpsraq $32, %ymm2, %ymm3
+; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX512-NEXT: vpblendd {{.*#+}} ymm5 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7]
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1681210440,18446744072402387656,1621997606]
+; AVX512-NEXT: vpmullq %ymm6, %ymm5, %ymm5
+; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX512-NEXT: vpaddq %ymm2, %ymm5, %ymm2
+; AVX512-NEXT: vpsraq $32, %ymm2, %ymm2
+; AVX512-NEXT: vpmuldq %ymm6, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512-NEXT: vpblendd {{.*#+}} ymm3 = ymm0[0,1],ymm4[2,3],ymm0[4,5],ymm4[6,7]
+; AVX512-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3,4,5,6,7]
+; AVX512-NEXT: vpsravq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [1,654,23,5423]
+; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index fa5692aa9cef1..9892ba039afba 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -45,42 +45,55 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: test_div7_4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rax
-; AVX2-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: retq
+; AVX2NOBW-LABEL: test_div7_4i64:
+; AVX2NOBW: # %bb.0:
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2NOBW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm1, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm1
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2NOBW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm0
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX2NOBW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpsrad $1, %ymm0, %ymm1
+; AVX2NOBW-NEXT: vpsrlq $1, %ymm0, %ymm2
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2],ymm1[3],ymm2[4],ymm1[5],ymm2[6],ymm1[7]
+; AVX2NOBW-NEXT: vpsrlq $63, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX2NOBW-NEXT: retq
+;
+; AVX512BW-LABEL: test_div7_4i64:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX512BW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm1, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm1
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX512BW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm0
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vpsrlq $63, %ymm0, %ymm1
+; AVX512BW-NEXT: vpsraq $1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: retq
%res = sdiv <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
@@ -389,58 +402,61 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: test_rem7_4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rcx
-; AVX2-NEXT: movq %rcx, %rax
-; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
-; AVX2-NEXT: leaq (,%rdx,8), %rax
-; AVX2-NEXT: subq %rax, %rdx
-; AVX2-NEXT: addq %rcx, %rdx
-; AVX2-NEXT: vmovq %rdx, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: retq
+; AVX2NOBW-LABEL: test_rem7_4i64:
+; AVX2NOBW: # %bb.0:
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2NOBW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm1, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm1
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX2NOBW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm2
+; AVX2NOBW-NEXT: vmovq %xmm0, %rax
+; AVX2NOBW-NEXT: imulq %rcx
+; AVX2NOBW-NEXT: vmovq %rdx, %xmm3
+; AVX2NOBW-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX2NOBW-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsrad $1, %ymm1, %ymm2
+; AVX2NOBW-NEXT: vpsrlq $1, %ymm1, %ymm3
+; AVX2NOBW-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3],ymm3[4],ymm2[5],ymm3[6],ymm2[7]
+; AVX2NOBW-NEXT: vpsrlq $63, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX2NOBW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: retq
+;
+; AVX512BW-LABEL: test_rem7_4i64:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vpextrq $1, %xmm1, %rax
+; AVX512BW-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm1, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm1
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; AVX512BW-NEXT: vpextrq $1, %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm2
+; AVX512BW-NEXT: vmovq %xmm0, %rax
+; AVX512BW-NEXT: imulq %rcx
+; AVX512BW-NEXT: vmovq %rdx, %xmm3
+; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
+; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
+; AVX512BW-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512BW-NEXT: vpsraq $1, %zmm1, %zmm1
+; AVX512BW-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsllq $3, %ymm1, %ymm2
+; AVX512BW-NEXT: vpsubq %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: retq
%res = srem <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %res
}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index b11756a5e3b4e..051c4de4fb62a 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -13,69 +13,40 @@ define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vpextrq $1, %xmm1, %rax
; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vmovq %xmm1, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrq $1, %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX-NEXT: vpextrq $1, %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
; AVX-NEXT: vmovq %xmm2, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
; AVX-NEXT: vmovq %rdx, %xmm0
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vpsrlq $63, %zmm0, %zmm1
+; AVX-NEXT: vpsraq $1, %zmm0, %zmm0
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = sdiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
@@ -278,104 +249,46 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_rem7_8i64:
; AVX: # %bb.0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rcx
-; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm1, %rax
+; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %xmm1, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vmovq %xmm2, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
+; AVX-NEXT: vpextrq $1, %xmm0, %rax
+; AVX-NEXT: imulq %rcx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: movq %rcx, %rax
-; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
-; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
-; AVX-NEXT: leaq (,%rdx,8), %rax
-; AVX-NEXT: subq %rax, %rdx
-; AVX-NEXT: addq %rcx, %rdx
-; AVX-NEXT: vmovq %rdx, %xmm0
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
-; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: imulq %rcx
+; AVX-NEXT: vmovq %rdx, %xmm4
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
+; AVX-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
+; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1
+; AVX-NEXT: vpsrlq $63, %zmm1, %zmm2
+; AVX-NEXT: vpsraq $1, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpsllq $3, %zmm1, %zmm2
+; AVX-NEXT: vpsubq %zmm2, %zmm1, %zmm1
+; AVX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX-NEXT: retq
%res = srem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res
>From 51e1c7c2a043ea08d8de2e58ac7c69a6163a83cb Mon Sep 17 00:00:00 2001
From: Rito Takeuchi <licht-t at outlook.jp>
Date: Fri, 3 Jul 2026 21:21:17 +0900
Subject: [PATCH 5/7] [X86] Rename dont_fold_{u,s}rem_i64 -> fold_{u,s}rem_i64
---
llvm/test/CodeGen/X86/srem-vector-lkk.ll | 14 +++++++-------
llvm/test/CodeGen/X86/urem-vector-lkk.ll | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index 464f4de867ecd..6a3324fb45121 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -398,9 +398,9 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
ret <4 x i16> %1
}
-; Don't fold i64 srem.
-define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
-; SSE2-LABEL: dont_fold_srem_i64:
+; Fold i64 srem.
+define <4 x i64> @fold_srem_i64(<4 x i64> %x) {
+; SSE2-LABEL: fold_srem_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: movq %xmm1, %rcx
@@ -445,7 +445,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE2-NEXT: retq
;
-; SSE4-LABEL: dont_fold_srem_i64:
+; SSE4-LABEL: fold_srem_i64:
; SSE4: # %bb.0:
; SSE4-NEXT: movdqa %xmm1, %xmm2
; SSE4-NEXT: movq %xmm1, %rcx
@@ -488,7 +488,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE4-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE4-NEXT: retq
;
-; AVX1-LABEL: dont_fold_srem_i64:
+; AVX1-LABEL: fold_srem_i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rcx
@@ -532,7 +532,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: dont_fold_srem_i64:
+; AVX2-LABEL: fold_srem_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
@@ -569,7 +569,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512-LABEL: dont_fold_srem_i64:
+; AVX512-LABEL: fold_srem_i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsraq $32, %ymm0, %ymm1
; AVX512-NEXT: vmovdqa {{.*#+}} ymm2 = [0,105075653,1493901669,3856996263]
diff --git a/llvm/test/CodeGen/X86/urem-vector-lkk.ll b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
index 166f9af2238b8..8327cb502bce3 100644
--- a/llvm/test/CodeGen/X86/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
@@ -248,9 +248,9 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
ret <4 x i16> %1
}
-; Don't fold i64 urem.
-define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
-; SSE2-LABEL: dont_fold_urem_i64:
+; Fold i64 urem.
+define <4 x i64> @fold_urem_i64(<4 x i64> %x) {
+; SSE2-LABEL: fold_urem_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: movq %xmm1, %rcx
@@ -290,7 +290,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE2-NEXT: retq
;
-; SSE4-LABEL: dont_fold_urem_i64:
+; SSE4-LABEL: fold_urem_i64:
; SSE4: # %bb.0:
; SSE4-NEXT: movq %xmm1, %rcx
; SSE4-NEXT: movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
@@ -328,7 +328,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; SSE4-NEXT: movdqa %xmm2, %xmm1
; SSE4-NEXT: retq
;
-; AVX1-LABEL: dont_fold_urem_i64:
+; AVX1-LABEL: fold_urem_i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rcx
@@ -367,7 +367,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: dont_fold_urem_i64:
+; AVX2-LABEL: fold_urem_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX2-NEXT: vpsrlq $32, %ymm1, %ymm2
@@ -405,7 +405,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512-LABEL: dont_fold_urem_i64:
+; AVX512-LABEL: fold_urem_i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
; AVX512-NEXT: vpsrlq $32, %ymm1, %ymm2
>From 610e02f2a5a4c74ce7abedcfd52f3448c31e445d Mon Sep 17 00:00:00 2001
From: Rito Takeuchi <licht-t at outlook.jp>
Date: Sun, 5 Jul 2026 18:11:13 +0900
Subject: [PATCH 6/7] [X86] minor comment fix in mulhu-v4i64-umul-lohi-guard
---
llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll b/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
index 1886cc421d605..baeb7de84de07 100644
--- a/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
+++ b/llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512
-; Step 1 guard for the vXi64 MULHU lowering. The `zext to i128 / mul / lshr 64 /
+; Guard for the vXi64 MULHU lowering. The `zext to i128 / mul / lshr 64 /
; trunc` idiom below is exactly what the loop vectorizer emits for a full
; 128-bit product (e.g. a wyhash-style `lo ^ hi` mix). When BOTH halves are
; used (UMUL_LOHI), vectorizing the high half via the vpmuludq schoolbook loses
>From d01386d4d31bb54727aa4249e798d90896d7145b Mon Sep 17 00:00:00 2001
From: Rito Takeuchi <licht-t at outlook.jp>
Date: Tue, 7 Jul 2026 00:59:23 +0900
Subject: [PATCH 7/7] [X86] drop VLX gate on v4i64 MULHS, and group with DQI
MUL
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 17 ++--
llvm/test/CodeGen/X86/srem-vector-lkk.ll | 98 +++++++++++++++++++++++-
llvm/test/CodeGen/X86/urem-vector-lkk.ll | 2 +-
3 files changed, 107 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 06df6d78953c0..091676661329a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1750,10 +1750,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
if (HasInt256) {
setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
- // MULHS is only a win when the low multiply can use vpmullq, so gate it
- // on AVX512DQ+VL; without it the schoolbook loses to scalar (esp. AVX2).
- if (Subtarget.hasDQI() && Subtarget.hasVLX())
- setOperationAction(ISD::MULHS, MVT::v4i64, Custom);
// Custom so the combiner keeps full products as [SU]MUL_LOHI, not
// MULH[SU].
setOperationAction(ISD::UMUL_LOHI, MVT::v4i64, Custom);
@@ -2032,9 +2028,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v64i8, Custom);
setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
- // MULHS needs vpmullq (AVX512DQ) for its low multiply to be a win.
- if (Subtarget.hasDQI())
- setOperationAction(ISD::MULHS, MVT::v8i64, Custom);
setOperationAction(ISD::UMUL_LOHI, MVT::v8i64, Custom);
setOperationAction(ISD::SMUL_LOHI, MVT::v8i64, Custom);
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
@@ -2118,9 +2111,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_UINT})
setOperationAction(Opc, MVT::v8i64, Custom);
- if (Subtarget.hasDQI())
+ if (Subtarget.hasDQI()) {
setOperationAction(ISD::MUL, MVT::v8i64, Legal);
+ // MULHS needs vpmullq (AVX512DQ) for its low multiply to be a win.
+ setOperationAction(ISD::MULHS, MVT::v8i64, Custom);
+ }
+
if (Subtarget.hasCDI()) {
// NonVLX sub-targets extend 128/256 vectors to use the 512 version.
for (auto VT : { MVT::v16i32, MVT::v8i64} ) {
@@ -2277,6 +2274,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
setOperationAction(ISD::MUL, MVT::v2i64, Legal);
setOperationAction(ISD::MUL, MVT::v4i64, Legal);
+
+ // MULHS is only a win when the low multiply can use vpmullq; non-VLX
+ // targets handle VPMULLQ by implicit widening.
+ setOperationAction(ISD::MULHS, MVT::v4i64, Custom);
}
if (Subtarget.hasCDI()) {
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index 6a3324fb45121..be540704f6871 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -4,6 +4,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX,AVX512DQNOVL
define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; SSE2-LABEL: fold_srem_vec_1:
@@ -79,6 +80,21 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,65412,98,64533,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: fold_srem_vec_1:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,0,0,65535,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [44151,48623,2675,32081,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm1, %xmm2, %xmm1
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm1, %xmm2
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovdw %zmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,65412,98,64533,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1
}
@@ -225,6 +241,20 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: dont_fold_srem_power_of_two:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [32769,32769,32769,44151,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm0, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm1, %xmm2
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovdw %zmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1
}
@@ -309,6 +339,23 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: dont_fold_srem_one:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3 # [0,12827,45591,12375,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm3, %xmm2
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm2, %xmm3
+; AVX512DQNOVL-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm2, %ymm2
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX512DQNOVL-NEXT: vpmovdw %zmm2, %ymm2
+; AVX512DQNOVL-NEXT: vpaddw %xmm1, %xmm2, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1
}
@@ -394,11 +441,28 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; AVX512-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,32768,23,5423,u,u,u,u]
; AVX512-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: dont_fold_urem_i16_smax:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,65535,1,0,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [0,32767,45591,12375,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpaddw %xmm1, %xmm2, %xmm1
+; AVX512DQNOVL-NEXT: vpsrlw $15, %xmm1, %xmm2
+; AVX512DQNOVL-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512DQNOVL-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3],xmm3[4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmovsxwd %xmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovdw %zmm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddw %xmm2, %xmm1, %xmm1
+; AVX512DQNOVL-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,32768,23,5423,u,u,u,u]
+; AVX512DQNOVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
+; AVX512DQNOVL-NEXT: vzeroupper
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
ret <4 x i16> %1
}
-; Fold i64 srem.
+; Fold i64 srem on AVX2+ targets.
define <4 x i64> @fold_srem_i64(<4 x i64> %x) {
; SSE2-LABEL: fold_srem_i64:
; SSE2: # %bb.0:
@@ -597,6 +661,38 @@ define <4 x i64> @fold_srem_i64(<4 x i64> %x) {
; AVX512-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [1,654,23,5423]
; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
+;
+; AVX512DQNOVL-LABEL: fold_srem_i64:
+; AVX512DQNOVL: # %bb.0:
+; AVX512DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512DQNOVL-NEXT: vpmovzxdq {{.*#+}} ymm1 = [0,105075653,1493901669,3856996263]
+; AVX512DQNOVL-NEXT: vpsraq $32, %zmm0, %zmm2
+; AVX512DQNOVL-NEXT: vpmullq %zmm1, %zmm2, %zmm3
+; AVX512DQNOVL-NEXT: vpmuludq %ymm1, %ymm0, %ymm1
+; AVX512DQNOVL-NEXT: vpsrlq $32, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddq %ymm1, %ymm3, %ymm1
+; AVX512DQNOVL-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm4 = ymm1[0],ymm3[1],ymm1[2],ymm3[3],ymm1[4],ymm3[5],ymm1[6],ymm3[7]
+; AVX512DQNOVL-NEXT: vpmovsxdq {{.*#+}} ymm5 = [0,1681210440,18446744072402387656,1621997606]
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm6 = ymm0[0],ymm3[1],ymm0[2],ymm3[3],ymm0[4],ymm3[5],ymm0[6],ymm3[7]
+; AVX512DQNOVL-NEXT: vpmullq %zmm5, %zmm6, %zmm6
+; AVX512DQNOVL-NEXT: vpaddq %ymm4, %ymm6, %ymm4
+; AVX512DQNOVL-NEXT: vpsraq $32, %zmm4, %zmm4
+; AVX512DQNOVL-NEXT: vpsraq $32, %zmm1, %zmm1
+; AVX512DQNOVL-NEXT: vpmuldq %ymm5, %ymm2, %ymm2
+; AVX512DQNOVL-NEXT: vpaddq %ymm1, %ymm2, %ymm1
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm2 = ymm0[0,1],ymm3[2,3],ymm0[4,5],ymm3[6,7]
+; AVX512DQNOVL-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpaddq %ymm4, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512DQNOVL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3,4,5,6,7]
+; AVX512DQNOVL-NEXT: vpmovsxbq {{.*#+}} ymm3 = [0,8,4,11]
+; AVX512DQNOVL-NEXT: vpsravq %zmm3, %zmm1, %zmm1
+; AVX512DQNOVL-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512DQNOVL-NEXT: vpmovsxwq {{.*#+}} ymm2 = [1,654,23,5423]
+; AVX512DQNOVL-NEXT: vpmullq %zmm2, %zmm1, %zmm1
+; AVX512DQNOVL-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; AVX512DQNOVL-NEXT: retq
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1
}
diff --git a/llvm/test/CodeGen/X86/urem-vector-lkk.ll b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
index 8327cb502bce3..7b3d0c9e12cfc 100644
--- a/llvm/test/CodeGen/X86/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/urem-vector-lkk.ll
@@ -248,7 +248,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
ret <4 x i16> %1
}
-; Fold i64 urem.
+; Fold i64 urem on AVX2+ targets.
define <4 x i64> @fold_urem_i64(<4 x i64> %x) {
; SSE2-LABEL: fold_urem_i64:
; SSE2: # %bb.0:
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