[llvm] 20e1215 - [TableGen][CC][NFC] Emit idiomatic guards for CallingConv. (#207758)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 6 09:59:23 PDT 2026
Author: Jason Eckhardt
Date: 2026-07-06T11:59:18-05:00
New Revision: 20e12152f9b218c42791151f0bca93a5a1763b64
URL: https://github.com/llvm/llvm-project/commit/20e12152f9b218c42791151f0bca93a5a1763b64
DIFF: https://github.com/llvm/llvm-project/commit/20e12152f9b218c42791151f0bca93a5a1763b64.diff
LOG: [TableGen][CC][NFC] Emit idiomatic guards for CallingConv. (#207758)
Emit independent guards for the two existing sections rather than the
if-else done today. This is in preparation for adding other sections
that must be includable exclusive of the other sections.
This also eliminates the current asymmetry between the automatic
IfGuardEmitter for the "if" portion vs the manually emitted "else"
section.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/lib/Target/ARC/ARCISelLowering.cpp
llvm/lib/Target/ARM/ARMCallingConv.cpp
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/BPF/BPFISelLowering.cpp
llvm/lib/Target/CSKY/CSKYISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Lanai/LanaiISelLowering.cpp
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/lib/Target/Mips/MipsFastISel.cpp
llvm/lib/Target/Mips/MipsISelLowering.cpp
llvm/lib/Target/PowerPC/PPCCallingConv.cpp
llvm/lib/Target/Sparc/SparcISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/X86/X86CallingConv.cpp
llvm/lib/Target/XCore/XCoreISelLowering.cpp
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
llvm/utils/TableGen/CallingConvEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
index cc46159915d76..b094a058e50a7 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
@@ -223,4 +223,5 @@ static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
// TableGen provides definitions of the calling convention analysis entry
// points.
+#define GET_CALLING_CONV_IMPL
#include "AArch64GenCallingConv.inc"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 5010720ca8e76..72f15b054c302 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -30,6 +30,7 @@
using namespace llvm;
+#define GET_CALLING_CONV_IMPL
#include "AMDGPUGenCallingConv.inc"
static cl::opt<bool> AMDGPUBypassSlowDiv(
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 981a30d4fb356..b413bd4d53cc2 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -26,6 +26,7 @@
using namespace llvm;
+#define GET_CALLING_CONV_IMPL
#include "R600GenCallingConv.inc"
R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp
index cbe9fb6239f7b..6ce05ad5dfef1 100644
--- a/llvm/lib/Target/ARC/ARCISelLowering.cpp
+++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp
@@ -236,6 +236,7 @@ SDValue ARCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ARCISD::GAWRAPPER, SDLoc(N), MVT::i32, GA);
}
+#define GET_CALLING_CONV_IMPL
#include "ARCGenCallingConv.inc"
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/ARMCallingConv.cpp b/llvm/lib/Target/ARM/ARMCallingConv.cpp
index 795476b3f386b..2ba040b8f4e50 100644
--- a/llvm/lib/Target/ARM/ARMCallingConv.cpp
+++ b/llvm/lib/Target/ARM/ARMCallingConv.cpp
@@ -330,4 +330,5 @@ static bool CC_ARM_AAPCS_Common_Custom_f16_Stack(unsigned ValNo, MVT ValVT,
}
// Include the table generated calling convention implementations.
+#define GET_CALLING_CONV_IMPL
#include "ARMGenCallingConv.inc"
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 89389f7da827b..d485b61c58ee0 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1151,6 +1151,7 @@ bool AVRTargetLowering::isOffsetFoldingLegal(
// Formal Arguments Calling Convention Implementation
//===----------------------------------------------------------------------===//
+#define GET_CALLING_CONV_IMPL
#include "AVRGenCallingConv.inc"
/// Registers for calling conventions, ordered in reverse as required by ABI.
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index 422a1ba5c4dd6..435f0e15a25c5 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -387,6 +387,7 @@ SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
}
// Calling Convention Implementation
+#define GET_CALLING_CONV_IMPL
#include "BPFGenCallingConv.inc"
// Apply AssertSext/AssertZext and truncate based on VA's LocInfo.
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index 738dcfb167e48..1bc3d5ca4431e 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -29,6 +29,7 @@ using namespace llvm;
STATISTIC(NumTailCalls, "Number of tail calls");
+#define GET_CALLING_CONV_IMPL
#include "CSKYGenCallingConv.inc"
static const MCPhysReg GPRArgRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3};
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 6b5e5ef1a3c81..57694bdf8c0c6 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -113,6 +113,7 @@ static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
return false;
}
+#define GET_CALLING_CONV_IMPL
#include "HexagonGenCallingConv.inc"
unsigned HexagonTargetLowering::getVectorTypeBreakdownForCallingConv(
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index ff35d981d6291..5831bd8685f72 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -351,6 +351,7 @@ void LanaiTargetLowering::LowerAsmOperandForConstraint(
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
+#define GET_CALLING_CONV_IMPL
#include "LanaiGenCallingConv.inc"
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 3621580d6ad35..d167e7f6597b6 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -230,6 +230,7 @@ MVT M68kTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
}
+#define GET_CALLING_CONV_IMPL
#include "M68kGenCallingConv.inc"
enum StructReturnType { NotStructReturn, RegStructReturn, StackStructReturn };
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index db716f02899b5..04a8a0721e6f5 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -230,6 +230,7 @@ MSP430TargetLowering::getRegForInlineAsmConstraint(
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
+#define GET_CALLING_CONV_IMPL
#include "MSP430GenCallingConv.inc"
/// For each argument in a function store the number of pieces it is composed
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 9645fb5293609..7ef770184e78e 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -285,6 +285,7 @@ static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
llvm_unreachable("should not be called");
}
+#define GET_CALLING_CONV_IMPL
#include "MipsGenCallingConv.inc"
CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 4389f0c8a649a..076ca31649c43 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3139,6 +3139,7 @@ static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
ISD::ArgFlagsTy ArgFlags, Type *OrigTy,
CCState &State);
+#define GET_CALLING_CONV_IMPL
#include "MipsGenCallingConv.inc"
CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp
index 332b5e07d3d5d..3f14cabe78ceb 100644
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp
@@ -193,4 +193,5 @@ static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
return true;
}
+#define GET_CALLING_CONV_IMPL
#include "PPCGenCallingConv.inc"
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index a41847a132dfb..c45babaec5dc2 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -223,6 +223,7 @@ static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
State);
}
+#define GET_CALLING_CONV_IMPL
#include "SparcGenCallingConv.inc"
// The calling conventions in SparcCallingConv.td are described in terms of the
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index e56a449cd455d..388e44af29aab 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1855,6 +1855,7 @@ void SystemZTargetLowering::LowerAsmOperandForConstraint(
// Calling conventions
//===----------------------------------------------------------------------===//
+#define GET_CALLING_CONV_IMPL
#include "SystemZGenCallingConv.inc"
const MCPhysReg *SystemZTargetLowering::getScratchRegisters(
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 23eb3034fe3e6..809423c2fb811 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -42,6 +42,7 @@ using namespace llvm;
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
+#define GET_CALLING_CONV_IMPL
#include "VEGenCallingConv.inc"
CCAssignFn *getReturnCC(CallingConv::ID CallConv) {
diff --git a/llvm/lib/Target/X86/X86CallingConv.cpp b/llvm/lib/Target/X86/X86CallingConv.cpp
index 5d5a705893242..ce2ce1cbc6379 100644
--- a/llvm/lib/Target/X86/X86CallingConv.cpp
+++ b/llvm/lib/Target/X86/X86CallingConv.cpp
@@ -406,4 +406,5 @@ static bool CC_X86_32_I128_FP128(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
}
// Provides entry points of CC_X86 and RetCC_X86.
+#define GET_CALLING_CONV_IMPL
#include "X86GenCallingConv.inc"
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index f54862a804a45..c3cbb4b4752d2 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -892,6 +892,7 @@ LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
+#define GET_CALLING_CONV_IMPL
#include "XCoreGenCallingConv.inc"
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 062911cd553b6..0c880234af65f 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -353,6 +353,7 @@ void XtensaTargetLowering::LowerAsmOperandForConstraint(
// Calling conventions
//===----------------------------------------------------------------------===//
+#define GET_CALLING_CONV_IMPL
#include "XtensaGenCallingConv.inc"
static const MCPhysReg IntRegs[] = {Xtensa::A2, Xtensa::A3, Xtensa::A4,
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index 369238dd70f7c..0c59f2b47215b 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -79,17 +79,19 @@ void CallingConvEmitter::run(raw_ostream &O) {
// Emit prototypes for all of the non-custom CC's so that they can forward ref
// each other.
Records.getTimer().startTimer("Emit prototypes");
- IfGuardEmitter IfGuard(O, "!defined(GET_CC_REGISTER_LISTS)");
- for (const Record *CC : CCs) {
- if (!CC->getValueAsBit("Custom"))
- emitCCHeader(O, CC, ";\n");
- }
+ {
+ IfDefEmitter IfGuard(O, "GET_CALLING_CONV_IMPL");
+ for (const Record *CC : CCs) {
+ if (!CC->getValueAsBit("Custom"))
+ emitCCHeader(O, CC, ";\n");
+ }
- // Emit each non-custom calling convention description in full.
- Records.getTimer().startTimer("Emit full descriptions");
- for (const Record *CC : CCs) {
- if (!CC->getValueAsBit("Custom"))
- emitCallingConv(CC, O);
+ // Emit each non-custom calling convention description in full.
+ Records.getTimer().startTimer("Emit full descriptions");
+ for (const Record *CC : CCs) {
+ if (!CC->getValueAsBit("Custom"))
+ emitCallingConv(CC, O);
+ }
}
emitArgRegisterLists(O);
@@ -365,7 +367,7 @@ void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
if (AssignedRegsMap.empty())
return;
- O << "\n#else\n\n";
+ IfDefEmitter IfGuard(O, "GET_CC_REGISTER_LISTS");
for (const auto &[RegName, Registers] : AssignedRegsMap) {
if (RegName.empty())
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