[llvm] [AArch64][DAG] Port adde and sube combine to AArch64 (PR #202227)

[via llvm-commits]

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@@ -3886,7 +3886,7 @@ static SDValue getCondCode(SelectionDAG &DAG, AArch64CC::CondCode CC) {
 unsigned numberOfInstrToLoadImm(const APInt &C) {
   uint64_t Imm = C.getZExtValue();
   SmallVector<AArch64_IMM::ImmInsnModel> Insn;
-  AArch64_IMM::expandMOVImm(Imm, 32, Insn);
+  AArch64_IMM::expandMOVImm(Imm, C.getBitWidth(), Insn);
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zip-stack-debug wrote:

And lo and behold, it should be C.getBitWidth() actually!

https://github.com/llvm/llvm-project/pull/202227