[llvm] [RegAlloc] Consider rematerialization over CSR use (PR #206756)
Lukas Sommer via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 6 08:09:41 PDT 2026
https://github.com/sommerlukas updated https://github.com/llvm/llvm-project/pull/206756
>From ac71d06d192a344181a00c926260fead4fdb4489 Mon Sep 17 00:00:00 2001
From: Lukas Sommer <lukas.sommer at amd.com>
Date: Tue, 30 Jun 2026 09:45:24 -0500
Subject: [PATCH 1/2] [RegAlloc] Consider rematerialization over CSR use
The first use of a callee-saved register incurs additional cost for
saving and restoring.
The existing logic already considers some alternatives such as region
split or spilling and chooses them if they are cheaper than CSR first
time use cost.
However, rematerialization isn't considered as alternative at the
moment. This patch adds consideration of rematerialization in a specific
scope and chooses rematerialization over CSR if cheaper.
Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
---
llvm/lib/CodeGen/RegAllocGreedy.cpp | 110 +-
llvm/lib/CodeGen/RegAllocGreedy.h | 3 +
.../amdgpu-simplify-libcall-pow-codegen.ll | 18 +-
.../AMDGPU/gfx-callable-argument-types.ll | 1133 +++++++----------
.../CodeGen/AMDGPU/i128-add-carry-chain.ll | 47 +-
llvm/test/CodeGen/AMDGPU/remat-csr.mir | 76 ++
.../AMDGPU/unstructured-cfg-def-use-issue.ll | 16 +-
7 files changed, 711 insertions(+), 692 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/remat-csr.mir
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6b8a9b8190f9a..de02558de5233 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2372,6 +2372,87 @@ BlockFrequency RAGreedy::calcSpillCost(const LiveInterval &LI) {
return BlockFrequency(SpillCost);
}
+bool RAGreedy::shouldAvoidCSRForRemat(const LiveInterval &VirtReg,
+ AllocationOrder &Order) const {
+ if (!VirtReg.isSpillable())
+ return false;
+
+ // This logic is intentionally narrow: handle a single concrete value
+ // whose def can be cheaply rematerialized at every use.
+ const VNInfo *OnlyVNI = nullptr;
+ for (const VNInfo *VNI : VirtReg.vnis()) {
+ if (!VNI || VNI->isUnused())
+ continue;
+ if (VNI->isPHIDef())
+ return false;
+ if (OnlyVNI)
+ return false;
+ OnlyVNI = VNI;
+ }
+ if (!OnlyVNI)
+ return false;
+
+ MachineInstr *DefMI = LIS->getInstructionFromIndex(OnlyVNI->def);
+ if (!DefMI || DefMI->isImplicitDef() || !TII->isReMaterializable(*DefMI) ||
+ !TII->isAsCheapAsAMove(*DefMI))
+ return false;
+
+ // This logic aims to address a specific problem: The first use of CSR for
+ // cheap-to-rematerialize live ranges because they cross calls, not because
+ // pressure requires it. With this check and the check for an available for a
+ // register that is not a first-use CSR below, we can scope this.
+ if (!Matrix->checkRegMaskInterference(VirtReg))
+ return false;
+
+ SmallPtrSet<MachineInstr *, 8> VisitedUses;
+ unsigned NumUses = 0;
+ for (MachineOperand &MO : MRI->use_nodbg_operands(VirtReg.reg())) {
+ if (MO.isUndef())
+ continue;
+
+ MachineInstr *UseMI = MO.getParent();
+ if (!VisitedUses.insert(UseMI).second)
+ continue;
+
+ SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
+ if (!VirtRegAuxInfo::allUsesAvailableAt(DefMI, UseIdx, *LIS, *MRI, *TII))
+ return false;
+
+ // Check if any register that is not a first-use CSR is available as
+ // destination for the rematerialization.
+ SlotIndex PrevIdx = UseIdx.getPrevSlot();
+ bool HasNoFirstCSRReg = false;
+ for (MCRegister RematPhysReg : Order) {
+ if (EvictAdvisor->isUnusedCalleeSavedReg(RematPhysReg))
+ continue;
+ if (!Matrix->checkInterference(PrevIdx, UseIdx, RematPhysReg)) {
+ HasNoFirstCSRReg = true;
+ break;
+ }
+ }
+ if (!HasNoFirstCSRReg)
+ return false;
+
+ ++NumUses;
+ }
+
+ if (!NumUses)
+ return false;
+
+ // Ideally, this would be handled with the CSR cost model, but the scales
+ // differ. The rationale for allowing a fan-out of 3 is simple: Saving and
+ // restoring the CSR will require at least two moves, so we can allow three
+ // uses, as the first is free and the two materializations will at most have
+ // the same cost as CSR save/restore.
+ // FIXME: Properly integrate into CSR cost model.
+ if (NumUses > 3)
+ return false;
+
+ LLVM_DEBUG(dbgs() << " rejecting CSR: cheap remat available for " << NumUses
+ << " use(s) with no-first-CSR registers\n");
+ return true;
+}
+
/// Using a CSR for the first time has a cost because it causes push|pop
/// to be added to prologue|epilogue. Splitting a cold section of the live
/// range can have lower cost than using the CSR for the first time;
@@ -2381,19 +2462,23 @@ BlockFrequency RAGreedy::calcSpillCost(const LiveInterval &LI) {
MCRegister RAGreedy::tryAssignCSRFirstTime(
const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
uint8_t &CostPerUseLimit, SmallVectorImpl<Register> &NewVRegs) {
- if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
- // We choose spill over using the CSR for the first time if the spill cost
- // is lower than CSRCost.
+ LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);
+
+ if (Stage == RS_Spill && VirtReg.isSpillable()) {
+ // We choose spill or rematerialize over using the CSR for the first time if
+ // the spill cost is lower than CSRCost.
SA->analyze(&VirtReg);
- if (calcSpillCost(VirtReg) >= CSRCost)
+ if (calcSpillCost(VirtReg) >= CSRCost &&
+ !shouldAvoidCSRForRemat(VirtReg, Order)) {
return PhysReg;
+ }
- // We are going to spill, set CostPerUseLimit to 1 to make sure that
- // we will not use a callee-saved register in tryEvict.
+ // We are going to spill or rematerialize, set CostPerUseLimit to 1 to make
+ // sure that we will not use a callee-saved register in tryEvict.
CostPerUseLimit = 1;
return MCRegister();
}
- if (ExtraInfo->getStage(VirtReg) < RS_Split) {
+ if (Stage < RS_Split) {
// We choose pre-splitting over using the CSR for the first time if
// the cost of splitting is lower than CSRCost.
SA->analyze(&VirtReg);
@@ -2401,14 +2486,23 @@ MCRegister RAGreedy::tryAssignCSRFirstTime(
BlockFrequency BestCost = CSRCost; // Don't modify CSRCost.
unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
NumCands, true /*IgnoreCSR*/);
- if (BestCand == NoCand)
+ if (BestCand == NoCand) {
+ if (shouldAvoidCSRForRemat(VirtReg, Order)) {
+ CostPerUseLimit = 1;
+ return MCRegister();
+ }
// Use the CSR if we can't find a region split below CSRCost.
return PhysReg;
+ }
// Perform the actual pre-splitting.
doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
return MCRegister();
}
+ if (shouldAvoidCSRForRemat(VirtReg, Order)) {
+ CostPerUseLimit = 1;
+ return MCRegister();
+ }
return PhysReg;
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h
index 465be0d76809e..8ee452e7e10a2 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -360,6 +360,9 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase,
AllocationOrder &Order, MCRegister PhysReg,
uint8_t &CostPerUseLimit,
SmallVectorImpl<Register> &NewVRegs);
+ /// Check if rematerialization is cheaper than using a CSR for the first time.
+ bool shouldAvoidCSRForRemat(const LiveInterval &VirtReg,
+ AllocationOrder &Order) const;
BlockFrequency calcSpillCost(const LiveInterval &LI);
void initializeCSRCost();
MCRegister tryBlockSplit(const LiveInterval &, AllocationOrder &,
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
index 20d421abf6a14..2947f73a09e8d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
@@ -683,7 +683,7 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) #0 {
; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
-; CHECK-NEXT: v_writelane_b32 v43, s16, 15
+; CHECK-NEXT: v_writelane_b32 v43, s16, 14
; CHECK-NEXT: s_addk_i32 s32, 0x800
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
@@ -700,9 +700,8 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) #0 {
; CHECK-NEXT: v_writelane_b32 v43, s51, 9
; CHECK-NEXT: v_writelane_b32 v43, s52, 10
; CHECK-NEXT: v_writelane_b32 v43, s53, 11
-; CHECK-NEXT: v_writelane_b32 v43, s54, 12
-; CHECK-NEXT: v_writelane_b32 v43, s30, 13
-; CHECK-NEXT: v_writelane_b32 v43, s31, 14
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
@@ -720,7 +719,6 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) #0 {
; CHECK-NEXT: s_mov_b64 s[36:37], s[8:9]
; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7]
; CHECK-NEXT: v_or_b32_e32 v42, 1, v2
-; CHECK-NEXT: s_brev_b32 s54, -2
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_cvt_f64_i32_e32 v[2:3], v42
@@ -740,13 +738,13 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) #0 {
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; CHECK-NEXT: v_bfi_b32 v1, s54, v1, v41
+; CHECK-NEXT: s_brev_b32 s4, -2
+; CHECK-NEXT: v_bfi_b32 v1, s4, v1, v41
; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; CHECK-NEXT: v_readlane_b32 s30, v43, 13
-; CHECK-NEXT: v_readlane_b32 s31, v43, 14
-; CHECK-NEXT: v_readlane_b32 s54, v43, 12
+; CHECK-NEXT: v_readlane_b32 s30, v43, 12
+; CHECK-NEXT: v_readlane_b32 s31, v43, 13
; CHECK-NEXT: v_readlane_b32 s53, v43, 11
; CHECK-NEXT: v_readlane_b32 s52, v43, 10
; CHECK-NEXT: v_readlane_b32 s51, v43, 9
@@ -760,7 +758,7 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) #0 {
; CHECK-NEXT: v_readlane_b32 s35, v43, 1
; CHECK-NEXT: v_readlane_b32 s34, v43, 0
; CHECK-NEXT: s_mov_b32 s32, s33
-; CHECK-NEXT: v_readlane_b32 s4, v43, 15
+; CHECK-NEXT: v_readlane_b32 s4, v43, 14
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
; CHECK-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b64 exec, s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
index 6922dc03f3203..148dcf314cfe1 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
@@ -4221,30 +4221,27 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX9-NEXT: s_mov_b32 s34, s33
; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
-; GFX9-NEXT: v_mov_b32_e32 v40, 0
-; GFX9-NEXT: v_mov_b32_e32 v41, 0
-; GFX9-NEXT: global_load_ubyte v0, v[40:41], off
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_load_ubyte v0, v[0:1], off
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_ret at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: global_store_byte v[40:41], v0, off
-; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s30, v42, 0
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: global_store_byte v[1:2], v0, off
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s34, v42, 2
+; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: s_mov_b32 s33, s34
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -4256,31 +4253,28 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_ret at abs32@lo
-; GFX10-NEXT: global_load_ubyte v0, v[40:41], off
+; GFX10-NEXT: global_load_ubyte v0, v[0:1], off
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: global_store_byte v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
-; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
-; GFX10-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
-; GFX10-NEXT: v_readlane_b32 s34, v42, 2
+; GFX10-NEXT: v_readlane_b32 s34, v40, 2
+; GFX10-NEXT: global_store_byte v[1:2], v0, off
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
@@ -4293,31 +4287,25 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[40:41], off
+; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: global_store_b8 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT: global_store_b8 v[1:2], v0, off
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -4329,31 +4317,25 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: global_load_u8 v0, v[40:41], off
+; GFX11-FAKE16-NEXT: global_load_u8 v0, v[0:1], off
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: global_store_b8 v[40:41], v0, off
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT: global_store_b8 v[1:2], v0, off
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -4365,31 +4347,28 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[40:41], off
+; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: global_store_byte v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
-; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
+; GFX10-SCRATCH-NEXT: global_store_byte v[1:2], v0, off
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
@@ -4409,17 +4388,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX9-NEXT: s_mov_b32 s34, s33
; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
-; GFX9-NEXT: v_mov_b32_e32 v40, 0
-; GFX9-NEXT: v_mov_b32_e32 v41, 0
-; GFX9-NEXT: global_load_ushort v0, v[40:41], off
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_load_ushort v0, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v1, 8
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i8_ret at abs32@lo
@@ -4428,16 +4405,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: global_store_short v[40:41], v0, off
-; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s30, v42, 0
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: global_store_short v[1:2], v0, off
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s34, v42, 2
+; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: s_mov_b32 s33, s34
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -4449,36 +4425,33 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_mov_b32_e32 v1, 8
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i8_ret at abs32@lo
-; GFX10-NEXT: global_load_ushort v0, v[40:41], off
+; GFX10-NEXT: global_load_ushort v0, v[0:1], off
+; GFX10-NEXT: v_mov_b32_e32 v1, 8
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
-; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: global_store_short v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
-; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_readlane_b32 s34, v40, 2
+; GFX10-NEXT: global_store_short v[1:2], v0, off
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
@@ -4491,20 +4464,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[40:41], off
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -4512,18 +4481,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
-; GFX11-TRUE16-NEXT: global_store_b16 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -4535,20 +4502,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: global_load_u16 v0, v[40:41], off
+; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -4556,17 +4519,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: global_store_b16 v[40:41], v0, off
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT: global_store_b16 v[1:2], v0, off
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -4578,36 +4540,33 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[40:41], off
+; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-SCRATCH-NEXT: global_store_short v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
-; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
+; GFX10-SCRATCH-NEXT: global_store_short v[1:2], v0, off
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
@@ -4627,17 +4586,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX9-NEXT: s_mov_b32 s34, s33
; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
-; GFX9-NEXT: v_mov_b32_e32 v40, 0
-; GFX9-NEXT: v_mov_b32_e32 v41, 0
-; GFX9-NEXT: global_load_dword v0, v[40:41], off
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -4649,16 +4606,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s34
; GFX9-NEXT: global_store_byte v[3:4], v2, off
-; GFX9-NEXT: global_store_short v[40:41], v0, off
-; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s30, v42, 0
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: global_store_short v[1:2], v0, off
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s34, v42, 2
+; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: s_mov_b32 s33, s34
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -4670,20 +4626,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
-; GFX10-NEXT: global_load_dword v0, v[40:41], off
+; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4691,17 +4645,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-NEXT: v_mov_b32_e32 v3, 2
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX10-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: global_store_byte v[3:4], v2, off
-; GFX10-NEXT: global_store_short v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
-; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_mov_b32 s32, s33
-; GFX10-NEXT: v_readlane_b32 s34, v42, 2
+; GFX10-NEXT: v_readlane_b32 s34, v40, 2
+; GFX10-NEXT: global_store_short v[1:2], v0, off
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
@@ -4714,20 +4667,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4735,18 +4684,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, 2 :: v_dual_mov_b32 v4, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: global_store_b8 v[3:4], v2, off
-; GFX11-TRUE16-NEXT: global_store_b16 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -4758,20 +4705,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off
+; GFX11-FAKE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4779,18 +4722,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 2 :: v_dual_mov_b32 v4, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: global_store_b8 v[3:4], v2, off
-; GFX11-FAKE16-NEXT: global_store_b16 v[40:41], v0, off
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT: global_store_b16 v[1:2], v0, off
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -4802,20 +4743,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off
+; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4823,17 +4762,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0
; GFX10-SCRATCH-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: global_store_byte v[3:4], v2, off
-; GFX10-SCRATCH-NEXT: global_store_short v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
-; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
+; GFX10-SCRATCH-NEXT: global_store_short v[1:2], v0, off
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
@@ -4853,17 +4791,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX9-NEXT: s_mov_b32 s34, s33
; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
-; GFX9-NEXT: v_mov_b32_e32 v40, 0
-; GFX9-NEXT: v_mov_b32_e32 v41, 0
-; GFX9-NEXT: global_load_dword v0, v[40:41], off
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret at abs32@lo
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -4875,16 +4811,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s34
; GFX9-NEXT: v_perm_b32 v1, v2, v3, s34
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: global_store_dword v[40:41], v0, off
-; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s30, v42, 0
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: global_store_dword v[1:2], v0, off
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s34, v42, 2
+; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: s_mov_b32 s33, s34
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -4896,20 +4831,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret at abs32@lo
-; GFX10-NEXT: global_load_dword v0, v[40:41], off
+; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4917,17 +4850,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX10-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
-; GFX10-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
-; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-NEXT: global_store_dword v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
-; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_readlane_b32 s34, v40, 2
+; GFX10-NEXT: global_store_dword v[1:2], v0, off
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
@@ -4940,20 +4872,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4962,18 +4890,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
-; GFX11-TRUE16-NEXT: global_store_b32 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT: global_store_b32 v[1:2], v0, off
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -4985,20 +4912,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off
+; GFX11-FAKE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5007,17 +4930,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: global_store_b32 v[40:41], v0, off
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT: global_store_b32 v[1:2], v0, off
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -5029,20 +4951,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off
+; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5050,17 +4970,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX10-SCRATCH-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
-; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
+; GFX10-SCRATCH-NEXT: global_store_dword v[1:2], v0, off
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
@@ -5080,17 +4999,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX9-NEXT: s_mov_b32 s34, s33
; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
-; GFX9-NEXT: v_mov_b32_e32 v40, 0
-; GFX9-NEXT: v_mov_b32_e32 v41, 0
-; GFX9-NEXT: global_load_dwordx2 v[5:6], v[40:41], off
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret at abs32@lo
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -5107,16 +5024,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v5
; GFX9-NEXT: global_store_byte v[0:1], v4, off
-; GFX9-NEXT: global_store_dword v[40:41], v2, off
-; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s30, v42, 0
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: global_store_dword v[0:1], v2, off
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s34, v42, 2
+; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: s_mov_b32 s33, s34
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -5128,20 +5044,18 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret at abs32@lo
-; GFX10-NEXT: global_load_dwordx2 v[5:6], v[40:41], off
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5153,18 +5067,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX10-NEXT: v_mov_b32_e32 v0, 4
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_lshl_or_b32 v2, v2, 16, v5
; GFX10-NEXT: s_mov_b32 s32, s33
-; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: global_store_byte v[0:1], v4, off
-; GFX10-NEXT: global_store_dword v[40:41], v2, off
-; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
-; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_readlane_b32 s34, v40, 2
+; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
@@ -5177,20 +5090,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: global_load_b64 v[5:6], v[40:41], off
+; GFX11-TRUE16-NEXT: global_load_b64 v[5:6], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5202,19 +5111,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v0, v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v5
-; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b8 v[0:1], v4, off
-; GFX11-TRUE16-NEXT: global_store_b32 v[40:41], v2, off
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT: global_store_b32 v[0:1], v2, off
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -5226,20 +5132,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: global_load_b64 v[5:6], v[40:41], off
+; GFX11-FAKE16-NEXT: global_load_b64 v[5:6], v[0:1], off
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5251,19 +5153,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v0, v1, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v5
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
-; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: global_store_b8 v[0:1], v4, off
-; GFX11-FAKE16-NEXT: global_store_b32 v[40:41], v2, off
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT: global_store_b32 v[0:1], v2, off
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -5275,20 +5174,18 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[40:41], off
+; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5300,18 +5197,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 4
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_lshl_or_b32 v2, v2, 16, v5
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: global_store_byte v[0:1], v4, off
-; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v2, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
-; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
+; GFX10-SCRATCH-NEXT: global_store_dword v[0:1], v2, off
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
@@ -5331,17 +5227,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX9-NEXT: s_mov_b32 s34, s33
; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
-; GFX9-NEXT: v_mov_b32_e32 v40, 0
-; GFX9-NEXT: v_mov_b32_e32 v41, 0
-; GFX9-NEXT: global_load_dwordx2 v[0:1], v[40:41], off
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret at abs32@lo
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -5361,16 +5255,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX9-NEXT: v_perm_b32 v1, v2, v3, s34
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v0
-; GFX9-NEXT: global_store_dwordx2 v[40:41], v[3:4], off
-; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s30, v42, 0
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: global_store_dwordx2 v[0:1], v[3:4], off
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s34, v42, 2
+; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: s_mov_b32 s33, s34
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -5382,20 +5275,18 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret at abs32@lo
-; GFX10-NEXT: global_load_dwordx2 v[0:1], v[40:41], off
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5410,18 +5301,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-NEXT: v_perm_b32 v5, v6, v7, 0xc0c0004
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX10-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX10-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_lshl_or_b32 v1, v5, 16, v4
-; GFX10-NEXT: s_mov_b32 s32, s33
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX10-NEXT: v_readlane_b32 s34, v42, 2
-; GFX10-NEXT: global_store_dwordx2 v[40:41], v[0:1], off
-; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
-; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: s_mov_b32 s32, s33
+; GFX10-NEXT: v_readlane_b32 s34, v40, 2
+; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
@@ -5434,20 +5324,16 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[40:41], off
+; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5460,22 +5346,20 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v6, v7, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v5, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-TRUE16-NEXT: global_store_b64 v[40:41], v[0:1], off
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -5487,20 +5371,16 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v[40:41], off
+; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5516,18 +5396,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v5, 16, v4
-; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
-; GFX11-FAKE16-NEXT: global_store_b64 v[40:41], v[0:1], off
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -5539,20 +5418,18 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[40:41], off
+; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5567,18 +5444,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_perm_b32 v5, v6, v7, 0xc0c0004
; GFX10-SCRATCH-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX10-SCRATCH-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_lshl_or_b32 v1, v5, 16, v4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
-; GFX10-SCRATCH-NEXT: global_store_dwordx2 v[40:41], v[0:1], off
-; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
-; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
+; GFX10-SCRATCH-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
@@ -5598,23 +5474,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX9-NEXT: s_mov_b32 s34, s33
; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_writelane_b32 v44, s34, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x800
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v44, s30, 0
-; GFX9-NEXT: v_writelane_b32 v44, s31, 1
-; GFX9-NEXT: v_mov_b32_e32 v40, 0
-; GFX9-NEXT: v_mov_b32_e32 v41, 0
-; GFX9-NEXT: v_mov_b32_e32 v42, 16
-; GFX9-NEXT: v_mov_b32_e32 v43, 0
-; GFX9-NEXT: global_load_dwordx4 v[0:3], v[40:41], off
-; GFX9-NEXT: global_load_dwordx4 v[16:19], v[42:43], off
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v4, 16
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
+; GFX9-NEXT: global_load_dwordx4 v[16:19], v[4:5], off
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v0
@@ -5678,21 +5550,20 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s34
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s34
; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v0
+; GFX9-NEXT: v_mov_b32_e32 v4, 16
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
-; GFX9-NEXT: global_store_dwordx4 v[42:43], v[0:3], off
-; GFX9-NEXT: global_store_dwordx4 v[40:41], v[6:9], off
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s30, v44, 0
-; GFX9-NEXT: v_readlane_b32 s31, v44, 1
+; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_store_dwordx4 v[0:1], v[6:9], off
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s34, v44, 2
+; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
-; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: s_mov_b32 s33, s34
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -5704,26 +5575,22 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s34, s33
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: v_writelane_b32 v44, s34, 2
-; GFX10-NEXT: s_addk_i32 s32, 0x400
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: v_writelane_b32 v44, s30, 0
-; GFX10-NEXT: v_writelane_b32 v44, s31, 1
-; GFX10-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_mov_b32_e32 v42, 16
-; GFX10-NEXT: v_mov_b32_e32 v43, 0
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_mov_b32_e32 v4, 16
+; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: global_load_dwordx4 v[0:3], v[40:41], off
-; GFX10-NEXT: global_load_dwordx4 v[16:19], v[42:43], off
+; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-NEXT: global_load_dwordx4 v[16:19], v[4:5], off
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -5787,19 +5654,18 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX10-NEXT: v_lshl_or_b32 v7, v14, 16, v13
; GFX10-NEXT: v_lshl_or_b32 v3, v2, 16, v0
-; GFX10-NEXT: global_store_dwordx4 v[42:43], v[7:10], off
-; GFX10-NEXT: global_store_dwordx4 v[40:41], v[3:6], off
-; GFX10-NEXT: s_clause 0x3 ; 16-byte Folded Reload
-; GFX10-NEXT: buffer_load_dword v43, off, s[0:3], s33
-; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4
-; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8
-; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12
-; GFX10-NEXT: v_readlane_b32 s30, v44, 0
-; GFX10-NEXT: v_readlane_b32 s31, v44, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 16
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
-; GFX10-NEXT: v_readlane_b32 s34, v44, 2
+; GFX10-NEXT: v_readlane_b32 s34, v40, 2
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
-; GFX10-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
@@ -5812,27 +5678,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-NEXT: s_mov_b32 s0, s33
; GFX11-NEXT: s_mov_b32 s33, s32
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
+; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: v_writelane_b32 v44, s0, 2
-; GFX11-NEXT: s_add_i32 s32, s32, 32
-; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Spill
-; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:12
-; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:8
-; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:4
-; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v43, s33
-; GFX11-NEXT: v_writelane_b32 v44, s30, 0
-; GFX11-NEXT: v_writelane_b32 v44, s31, 1
-; GFX11-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
-; GFX11-NEXT: v_dual_mov_b32 v42, 16 :: v_dual_mov_b32 v43, 0
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-DAG: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: global_load_b128 v[0:3], v[40:41], off
-; GFX11-NEXT: global_load_b128 v[16:19], v[42:43], off
+; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
+; GFX11-NEXT: global_load_b128 v[16:19], v[4:5], off
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -5893,20 +5751,16 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-NEXT: v_lshl_or_b32 v7, v14, 16, v13
; GFX11-NEXT: v_lshl_or_b32 v3, v2, 16, v0
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: global_store_b128 v[42:43], v[7:10], off
-; GFX11-NEXT: global_store_b128 v[40:41], v[3:6], off
-; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload
-; GFX11-NEXT: scratch_load_b32 v43, off, s33
-; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:4
-; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:8
-; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:12
-; GFX11-NEXT: v_readlane_b32 s30, v44, 0
-; GFX11-NEXT: v_readlane_b32 s31, v44, 1
-; GFX11-NEXT: s_mov_b32 s32, s33
-; GFX11-NEXT: v_readlane_b32 s0, v44, 2
+; GFX11-NEXT: v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-DAG: global_store_b128 v[0:1], v[7:10], off
+; GFX11-DAG: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-DAG: global_store_b128 v[0:1], v[3:6], off
+; GFX11-DAG: v_readlane_b32 s31, v40, 1
+; GFX11-DAG: s_mov_b32 s32, s33
+; GFX11-DAG: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-NEXT: scratch_load_b32 v44, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: s_mov_b32 s33, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -5918,26 +5772,22 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, s33
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v44, s33 offset:16 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s0, 2
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:12 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:4 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v43, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s31, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v42, 16
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v43, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 16
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
; GFX10-SCRATCH-NEXT: s_clause 0x1
-; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[40:41], off
-; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[42:43], off
+; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[4:5], off
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -6001,19 +5851,18 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX10-SCRATCH-NEXT: v_lshl_or_b32 v7, v14, 16, v13
; GFX10-SCRATCH-NEXT: v_lshl_or_b32 v3, v2, 16, v0
-; GFX10-SCRATCH-NEXT: global_store_dwordx4 v[42:43], v[7:10], off
-; GFX10-SCRATCH-NEXT: global_store_dwordx4 v[40:41], v[3:6], off
-; GFX10-SCRATCH-NEXT: s_clause 0x3 ; 16-byte Folded Reload
-; GFX10-SCRATCH-NEXT: scratch_load_dword v43, off, s33
-; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:4
-; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:8
-; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:12
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v44, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v44, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 16
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v44, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
+; GFX10-SCRATCH-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-SCRATCH-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
-; GFX10-SCRATCH-NEXT: scratch_load_dword v44, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
diff --git a/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll b/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
index f20dac700316a..c1580c72a4693 100644
--- a/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
+++ b/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
@@ -11,16 +11,15 @@ define i128 @i128_add_uniform_carry_to_divergent(i128 %x) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[18:19], -1
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
-; GFX9-NEXT: v_writelane_b32 v42, s16, 3
+; GFX9-NEXT: v_writelane_b32 v42, s16, 2
; GFX9-NEXT: s_add_i32 s32, s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v42, s34, 0
-; GFX9-NEXT: v_writelane_b32 v42, s30, 1
-; GFX9-NEXT: v_writelane_b32 v42, s31, 2
+; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX9-NEXT: s_mov_b32 s34, 32
-; GFX9-NEXT: v_lshlrev_b64 v[40:41], s34, v[0:1]
+; GFX9-NEXT: s_mov_b32 s16, 32
+; GFX9-NEXT: v_lshlrev_b64 v[40:41], s16, v[0:1]
; GFX9-NEXT: s_getpc_b64 s[16:17]
; GFX9-NEXT: s_add_u32 s16, s16, external at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s17, s17, external at gotpcrel32@hi+12
@@ -38,18 +37,18 @@ define i128 @i128_add_uniform_carry_to_divergent(i128 %x) #0 {
; GFX9-NEXT: v_addc_co_u32_e64 v2, s[8:9], v40, v0, s[8:9]
; GFX9-NEXT: v_mov_b32_e32 v0, s7
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[6:7], v41, v0, s[8:9]
-; GFX9-NEXT: v_lshrrev_b64 v[4:5], s34, v[2:3]
-; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], s34
+; GFX9-NEXT: s_mov_b32 s6, 32
+; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[2:3]
+; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], s6
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v3, v4
-; GFX9-NEXT: v_readlane_b32 s30, v42, 1
-; GFX9-NEXT: v_readlane_b32 s31, v42, 2
-; GFX9-NEXT: v_readlane_b32 s34, v42, 0
+; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s32, s33
-; GFX9-NEXT: v_readlane_b32 s4, v42, 3
+; GFX9-NEXT: v_readlane_b32 s4, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[6:7]
@@ -70,17 +69,16 @@ define i128 @i128_add_uniform_carry_to_divergent(i128 %x) #0 {
; GFX12-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-NEXT: v_writelane_b32 v42, s0, 3
+; GFX12-NEXT: v_writelane_b32 v42, s0, 2
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX12-NEXT: scratch_store_b32 off, v41, s33 ; 4-byte Folded Spill
-; GFX12-NEXT: v_writelane_b32 v42, s34, 0
-; GFX12-NEXT: v_writelane_b32 v42, s30, 1
-; GFX12-NEXT: v_writelane_b32 v42, s31, 2
+; GFX12-NEXT: v_writelane_b32 v42, s30, 0
+; GFX12-NEXT: v_writelane_b32 v42, s31, 1
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX12-NEXT: s_mov_b32 s34, 32
+; GFX12-NEXT: s_mov_b32 s0, 32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_lshlrev_b64_e64 v[40:41], s34, v[0:1]
+; GFX12-NEXT: v_lshlrev_b64_e64 v[40:41], s0, v[0:1]
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
@@ -103,18 +101,19 @@ define i128 @i128_add_uniform_carry_to_divergent(i128 %x) #0 {
; GFX12-NEXT: v_add_co_ci_u32_e64 v2, s2, v40, s2, s4
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, s2, v41, s3, s2
-; GFX12-NEXT: v_lshrrev_b64 v[3:4], s34, v[2:3]
-; GFX12-NEXT: s_lshr_b64 s[2:3], s[0:1], s34
+; GFX12-NEXT: s_mov_b32 s2, 32
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) depctr_va_sdst(0)
+; GFX12-NEXT: v_lshrrev_b64 v[3:4], s2, v[2:3]
+; GFX12-NEXT: s_lshr_b64 s[2:3], s[0:1], s2
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v1, s2
-; GFX12-NEXT: v_readlane_b32 s30, v42, 1
-; GFX12-NEXT: v_readlane_b32 s31, v42, 2
-; GFX12-NEXT: v_readlane_b32 s34, v42, 0
+; GFX12-NEXT: v_readlane_b32 s30, v42, 0
+; GFX12-NEXT: v_readlane_b32 s31, v42, 1
; GFX12-NEXT: scratch_load_b32 v41, off, s33 ; 4-byte Folded Reload
; GFX12-NEXT: scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload
; GFX12-NEXT: s_mov_b32 s32, s33
-; GFX12-NEXT: v_readlane_b32 s0, v42, 3
+; GFX12-NEXT: v_readlane_b32 s0, v42, 2
; GFX12-NEXT: s_or_saveexec_b32 s1, -1
; GFX12-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/remat-csr.mir b/llvm/test/CodeGen/AMDGPU/remat-csr.mir
new file mode 100644
index 0000000000000..50ffa9d6be1b6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/remat-csr.mir
@@ -0,0 +1,76 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=greedy %s -o - | FileCheck %s
+
+--- |
+ target triple = "amdgcn-amd-amdhsa"
+
+ define void @one_use() { ret void }
+ define void @two_uses() { ret void }
+ declare void @callee()
+...
+---
+name: one_use
+tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
+body: |
+ ; CHECK-LABEL: name: one_use
+ ; CHECK-NOT: assigned-phys: '$sgpr54'
+ ; CHECK: %[[MASK:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
+ ; CHECK-NEXT: %{{[0-9]+}}:vgpr_32 = V_BFI_B32_e64 %[[MASK]], %{{[0-9]+}}, %{{[0-9]+}}, implicit $exec
+ bb.0:
+ liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr32
+ %0:sgpr_64 = COPY $sgpr4_sgpr5
+ %1:sgpr_64 = COPY $sgpr6_sgpr7
+ %2:sgpr_64 = COPY $sgpr8_sgpr9
+ %3:sgpr_64 = COPY $sgpr10_sgpr11
+ %4:sgpr_32 = COPY $sgpr12
+ %5:sgpr_32 = COPY $sgpr13
+ %6:sgpr_32 = COPY $sgpr14
+ %7:sgpr_32 = COPY $sgpr15
+ %8:sreg_32 = S_MOV_B32 2147483647
+ ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ %9:sreg_64_xexec = IMPLICIT_DEF
+ dead $sgpr30_sgpr31 = SI_CALL %9, @callee, csr_amdgpu, implicit-def $vgpr0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7
+ %10:vgpr_32 = IMPLICIT_DEF
+ %11:vgpr_32 = IMPLICIT_DEF
+ %12:vgpr_32 = V_BFI_B32_e64 %8, %10, %11, implicit $exec
+ S_NOP 0, implicit %12
+ S_ENDPGM 0
+...
+---
+name: two_uses
+tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
+body: |
+ ; CHECK-LABEL: name: two_uses
+ ; CHECK-NOT: assigned-phys: '$sgpr54'
+ ; CHECK: %[[MASK0:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
+ ; CHECK: %{{[0-9]+}}:vgpr_32 = V_AND_B32_e64 %[[MASK0]], %{{[0-9]+}}, implicit $exec
+ ; CHECK: %[[MASK1:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
+ ; CHECK-NEXT: %{{[0-9]+}}:vgpr_32 = V_BFI_B32_e64 %[[MASK1]], %{{[0-9]+}}, %{{[0-9]+}}, implicit $exec
+ bb.0:
+ liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr32
+ %0:sgpr_64 = COPY $sgpr4_sgpr5
+ %1:sgpr_64 = COPY $sgpr6_sgpr7
+ %2:sgpr_64 = COPY $sgpr8_sgpr9
+ %3:sgpr_64 = COPY $sgpr10_sgpr11
+ %4:sgpr_32 = COPY $sgpr12
+ %5:sgpr_32 = COPY $sgpr13
+ %6:sgpr_32 = COPY $sgpr14
+ %7:sgpr_32 = COPY $sgpr15
+ %8:sreg_32 = S_MOV_B32 2147483647
+ %10:vgpr_32 = IMPLICIT_DEF
+ %11:vgpr_32 = V_AND_B32_e64 %8, %10, implicit $exec
+ ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ %9:sreg_64_xexec = IMPLICIT_DEF
+ dead $sgpr30_sgpr31 = SI_CALL %9, @callee, csr_amdgpu, implicit-def $vgpr0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
+ S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7
+ %12:vgpr_32 = IMPLICIT_DEF
+ %13:vgpr_32 = V_BFI_B32_e64 %8, %11, %12, implicit $exec
+ S_NOP 0, implicit %13
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
index fa0bdd8ad9ac9..578e0ee775a8e 100644
--- a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
+++ b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
@@ -300,7 +300,7 @@ define hidden void @blam() #0 {
; GCN-NEXT: v_writelane_b32 v45, s31, 25
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: flat_load_dword v43, v[0:1]
+; GCN-NEXT: flat_load_dword v44, v[0:1]
; GCN-NEXT: v_mov_b32_e32 v40, v31
; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v40
; GCN-NEXT: s_mov_b32 s54, s15
@@ -314,10 +314,10 @@ define hidden void @blam() #0 {
; GCN-NEXT: v_mov_b32_e32 v42, 0
; GCN-NEXT: s_mov_b64 s[66:67], 0
; GCN-NEXT: v_lshlrev_b32_e32 v41, 2, v0
-; GCN-NEXT: v_mov_b32_e32 v44, 0x7fc00000
+; GCN-NEXT: v_mov_b32_e32 v43, 0x7fc00000
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_eq_f32_e64 s[68:69], 0, v43
-; GCN-NEXT: v_cmp_neq_f32_e64 s[50:51], 0, v43
+; GCN-NEXT: v_cmp_eq_f32_e64 s[68:69], 0, v44
+; GCN-NEXT: v_cmp_neq_f32_e64 s[50:51], 0, v44
; GCN-NEXT: s_branch .LBB1_2
; GCN-NEXT: .LBB1_1: ; %Flow7
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
@@ -369,7 +369,7 @@ define hidden void @blam() #0 {
; GCN-NEXT: ; %bb.6: ; %bb16
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_or_b64 s[8:9], s[68:69], exec
-; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
+; GCN-NEXT: buffer_store_dword v43, off, s[0:3], 0
; GCN-NEXT: .LBB1_7: ; %Flow3
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[6:7]
@@ -380,7 +380,7 @@ define hidden void @blam() #0 {
; GCN-NEXT: ; %bb.8: ; %bb17
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_mov_b64 s[6:7], exec
-; GCN-NEXT: buffer_store_dword v43, off, s[0:3], 0
+; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
; GCN-NEXT: .LBB1_9: ; %Flow4
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[8:9]
@@ -411,7 +411,7 @@ define hidden void @blam() #0 {
; GCN-NEXT: ; %bb.14: ; %bb10
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_or_b64 s[10:11], s[6:7], exec
-; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
+; GCN-NEXT: buffer_store_dword v43, off, s[0:3], 0
; GCN-NEXT: .LBB1_15: ; %Flow6
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[12:13]
@@ -429,7 +429,7 @@ define hidden void @blam() #0 {
; GCN-NEXT: ; %bb.17: ; %bb18
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
-; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
+; GCN-NEXT: buffer_store_dword v43, off, s[0:3], 0
; GCN-NEXT: s_branch .LBB1_1
; GCN-NEXT: .LBB1_18: ; %DummyReturnBlock
; GCN-NEXT: s_or_b64 exec, exec, s[66:67]
>From d161ab52cc77aae71d8bf13e2558acd3b6eaebf9 Mon Sep 17 00:00:00 2001
From: Lukas Sommer <lukas.sommer at amd.com>
Date: Tue, 30 Jun 2026 11:04:25 -0500
Subject: [PATCH 2/2] Update other backends' tests
Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
---
.../Atomics/aarch64-atomic-load-rcpc_immo.ll | 8 +-
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 60 +-
.../Atomics/aarch64-atomicrmw-v8a_fp.ll | 60 +-
.../Atomics/aarch64_be-atomicrmw-lsfe.ll | 60 +-
.../Atomics/aarch64_be-atomicrmw-v8a_fp.ll | 60 +-
.../CodeGen/AArch64/GlobalISel/swifterror.ll | 2 +-
llvm/test/CodeGen/AArch64/addsub.ll | 9 +-
.../AArch64/clear-dead-implicit-def-impdef.ll | 28 +-
.../AArch64/combine-comparisons-by-cse.ll | 32 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 623 +++++++++---------
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 152 ++---
.../implicit-def-subreg-to-reg-regression.ll | 8 +-
.../AArch64/late-taildup-computed-goto.ll | 38 +-
llvm/test/CodeGen/AArch64/llvm.frexp.ll | 332 +++++-----
llvm/test/CodeGen/AArch64/llvm.modf.ll | 113 ++--
llvm/test/CodeGen/AArch64/llvm.sincos.ll | 52 +-
llvm/test/CodeGen/AArch64/llvm.sincospi.ll | 64 +-
...egalloc-last-chance-recolor-with-split.mir | 46 +-
...shrink-wrap-byval-inalloca-preallocated.ll | 60 +-
.../test/CodeGen/AArch64/sme-peephole-opts.ll | 11 +-
.../CodeGen/AArch64/sme-za-control-flow.ll | 77 ++-
.../test/CodeGen/AArch64/sme-za-exceptions.ll | 37 +-
llvm/test/CodeGen/AArch64/sme-zt0-state.ll | 96 +--
.../AArch64/stack-protector-darwin-got.ll | 18 +-
.../CodeGen/AArch64/sve-fixed-ld2-alloca.ll | 14 +-
...-streaming-mode-fixed-length-ld2-alloca.ll | 28 +-
llvm/test/CodeGen/AArch64/swifterror.ll | 78 +--
llvm/test/CodeGen/AArch64/swifttail-call.ll | 4 +-
llvm/test/CodeGen/AArch64/tailcc-tail-call.ll | 4 +-
llvm/test/CodeGen/AArch64/wineh-try-catch.ll | 34 +-
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll | 26 +-
llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll | 210 +++---
llvm/test/CodeGen/RISCV/atomic-signext.ll | 48 +-
llvm/test/CodeGen/RISCV/double-convert.ll | 81 ++-
llvm/test/CodeGen/RISCV/float-convert.ll | 139 ++--
llvm/test/CodeGen/RISCV/forced-atomics.ll | 72 +-
llvm/test/CodeGen/RISCV/half-convert.ll | 139 ++--
...e-outliner-and-machine-copy-propagation.ll | 14 +-
llvm/test/CodeGen/RISCV/pr135206.ll | 12 +-
.../RISCV/reduce-unnecessary-extension.ll | 6 +-
...regalloc-last-chance-recoloring-failure.ll | 66 +-
llvm/test/CodeGen/RISCV/remat.ll | 124 ++--
.../test/CodeGen/RISCV/rv64-double-convert.ll | 37 +-
llvm/test/CodeGen/RISCV/rv64-float-convert.ll | 37 +-
llvm/test/CodeGen/RISCV/rv64-half-convert.ll | 37 +-
.../rvv/fixed-vectors-shuffle-exact-vlen.ll | 11 +-
llvm/test/CodeGen/RISCV/rvv/localvar.ll | 56 +-
.../CodeGen/RISCV/rvv/rvv-out-arguments.ll | 96 +--
.../RISCV/rvv/stores-of-loads-merging.ll | 33 +-
llvm/test/CodeGen/RISCV/sextw-removal.ll | 12 +-
llvm/test/CodeGen/RISCV/shrinkwrap.ll | 152 ++---
llvm/test/CodeGen/RISCV/stack-guard-global.ll | 13 +-
.../CodeGen/RISCV/stack-protector-target.ll | 30 +-
53 files changed, 1728 insertions(+), 1931 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
index f91ab9fa3e8ca..c45d29ae71eef 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
@@ -902,7 +902,7 @@ define i8 @load_atomic_i8_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i8_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: orr x8, x19, #0x1
+; SDAG-AVOIDLDAPUR: orr x8, x8, #0x1
; SDAG-AVOIDLDAPUR: ldaprb w0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i8_from_gep:
@@ -922,7 +922,7 @@ define i16 @load_atomic_i16_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i16_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: orr x8, x19, #0x2
+; SDAG-AVOIDLDAPUR: orr x8, x8, #0x2
; SDAG-AVOIDLDAPUR: ldaprh w0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i16_from_gep:
@@ -942,7 +942,7 @@ define i32 @load_atomic_i32_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i32_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: add x8, x19, #4
+; SDAG-AVOIDLDAPUR: add x8, x8, #4
; SDAG-AVOIDLDAPUR: ldapr w0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i32_from_gep:
@@ -962,7 +962,7 @@ define i64 @load_atomic_i64_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i64_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: add x8, x19, #8
+; SDAG-AVOIDLDAPUR: add x8, x8, #8
; SDAG-AVOIDLDAPUR: ldapr x0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i64_from_gep:
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index 6a0b689b16888..372151989adc5 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -247,7 +247,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value monotonic, align 1
@@ -264,7 +264,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acquire, align 1
@@ -281,7 +281,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value release, align 1
@@ -298,7 +298,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acq_rel, align 1
@@ -315,7 +315,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value seq_cst, align 1
@@ -752,7 +752,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value monotonic, align 1
@@ -769,7 +769,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acquire, align 1
@@ -786,7 +786,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value release, align 1
@@ -803,7 +803,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acq_rel, align 1
@@ -820,7 +820,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value seq_cst, align 1
@@ -1138,7 +1138,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value monotonic, align 1
@@ -1155,7 +1155,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acquire, align 1
@@ -1172,7 +1172,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value release, align 1
@@ -1189,7 +1189,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acq_rel, align 1
@@ -1206,7 +1206,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value seq_cst, align 1
@@ -1524,7 +1524,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value monotonic, align 1
@@ -1541,7 +1541,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acquire, align 1
@@ -1558,7 +1558,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value release, align 1
@@ -1575,7 +1575,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acq_rel, align 1
@@ -1592,7 +1592,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value seq_cst, align 1
@@ -1910,7 +1910,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value monotonic, align 1
@@ -1927,7 +1927,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acquire, align 1
@@ -1944,7 +1944,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value release, align 1
@@ -1961,7 +1961,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acq_rel, align 1
@@ -1978,7 +1978,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value seq_cst, align 1
@@ -2296,7 +2296,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value monotonic, align 1
@@ -2313,7 +2313,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acquire, align 1
@@ -2330,7 +2330,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value release, align 1
@@ -2347,7 +2347,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acq_rel, align 1
@@ -2364,7 +2364,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value seq_cst, align 1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
index d71231059c3b3..32e382af71a46 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
@@ -363,7 +363,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value monotonic, align 1
@@ -380,7 +380,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acquire, align 1
@@ -397,7 +397,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value release, align 1
@@ -414,7 +414,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acq_rel, align 1
@@ -431,7 +431,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value seq_cst, align 1
@@ -868,7 +868,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value monotonic, align 1
@@ -885,7 +885,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acquire, align 1
@@ -902,7 +902,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value release, align 1
@@ -919,7 +919,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acq_rel, align 1
@@ -936,7 +936,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value seq_cst, align 1
@@ -1373,7 +1373,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value monotonic, align 1
@@ -1390,7 +1390,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acquire, align 1
@@ -1407,7 +1407,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value release, align 1
@@ -1424,7 +1424,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acq_rel, align 1
@@ -1441,7 +1441,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value seq_cst, align 1
@@ -1878,7 +1878,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value monotonic, align 1
@@ -1895,7 +1895,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acquire, align 1
@@ -1912,7 +1912,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value release, align 1
@@ -1929,7 +1929,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acq_rel, align 1
@@ -1946,7 +1946,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value seq_cst, align 1
@@ -2383,7 +2383,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value monotonic, align 1
@@ -2400,7 +2400,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acquire, align 1
@@ -2417,7 +2417,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value release, align 1
@@ -2434,7 +2434,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acq_rel, align 1
@@ -2451,7 +2451,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value seq_cst, align 1
@@ -2888,7 +2888,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value monotonic, align 1
@@ -2905,7 +2905,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acquire, align 1
@@ -2922,7 +2922,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value release, align 1
@@ -2939,7 +2939,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acq_rel, align 1
@@ -2956,7 +2956,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value seq_cst, align 1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll
index 9f0c6b07d7b7c..67ed1ef15c15c 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll
@@ -244,7 +244,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value monotonic, align 1
@@ -258,7 +258,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acquire, align 1
@@ -272,7 +272,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value release, align 1
@@ -286,7 +286,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acq_rel, align 1
@@ -300,7 +300,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value seq_cst, align 1
@@ -719,7 +719,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value monotonic, align 1
@@ -733,7 +733,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acquire, align 1
@@ -747,7 +747,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value release, align 1
@@ -761,7 +761,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acq_rel, align 1
@@ -775,7 +775,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value seq_cst, align 1
@@ -1090,7 +1090,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value monotonic, align 1
@@ -1104,7 +1104,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acquire, align 1
@@ -1118,7 +1118,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value release, align 1
@@ -1132,7 +1132,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acq_rel, align 1
@@ -1146,7 +1146,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value seq_cst, align 1
@@ -1461,7 +1461,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value monotonic, align 1
@@ -1475,7 +1475,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acquire, align 1
@@ -1489,7 +1489,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value release, align 1
@@ -1503,7 +1503,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acq_rel, align 1
@@ -1517,7 +1517,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value seq_cst, align 1
@@ -1832,7 +1832,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value monotonic, align 1
@@ -1846,7 +1846,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acquire, align 1
@@ -1860,7 +1860,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value release, align 1
@@ -1874,7 +1874,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acq_rel, align 1
@@ -1888,7 +1888,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value seq_cst, align 1
@@ -2203,7 +2203,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value monotonic, align 1
@@ -2217,7 +2217,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acquire, align 1
@@ -2231,7 +2231,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value release, align 1
@@ -2245,7 +2245,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acq_rel, align 1
@@ -2259,7 +2259,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value seq_cst, align 1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll
index fc3ed5680b23a..a4f5599acafee 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll
@@ -345,7 +345,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value monotonic, align 1
@@ -359,7 +359,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acquire, align 1
@@ -373,7 +373,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value release, align 1
@@ -387,7 +387,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acq_rel, align 1
@@ -401,7 +401,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value seq_cst, align 1
@@ -820,7 +820,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value monotonic, align 1
@@ -834,7 +834,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acquire, align 1
@@ -848,7 +848,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value release, align 1
@@ -862,7 +862,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acq_rel, align 1
@@ -876,7 +876,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value seq_cst, align 1
@@ -1295,7 +1295,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value monotonic, align 1
@@ -1309,7 +1309,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acquire, align 1
@@ -1323,7 +1323,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value release, align 1
@@ -1337,7 +1337,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acq_rel, align 1
@@ -1351,7 +1351,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value seq_cst, align 1
@@ -1770,7 +1770,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value monotonic, align 1
@@ -1784,7 +1784,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acquire, align 1
@@ -1798,7 +1798,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value release, align 1
@@ -1812,7 +1812,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acq_rel, align 1
@@ -1826,7 +1826,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value seq_cst, align 1
@@ -2245,7 +2245,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value monotonic, align 1
@@ -2259,7 +2259,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acquire, align 1
@@ -2273,7 +2273,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value release, align 1
@@ -2287,7 +2287,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acq_rel, align 1
@@ -2301,7 +2301,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value seq_cst, align 1
@@ -2720,7 +2720,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value monotonic, align 1
@@ -2734,7 +2734,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acquire, align 1
@@ -2748,7 +2748,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value release, align 1
@@ -2762,7 +2762,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acq_rel, align 1
@@ -2776,7 +2776,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value seq_cst, align 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll b/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
index 78fc6ccc50663..7baa24c16be78 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
@@ -55,11 +55,11 @@ handler:
; "caller2" is the caller of "foo", it calls "foo" inside a loop.
define float @caller2(ptr %error_ref) {
; CHECK-LABEL: caller2:
-; CHECK: fmov [[CMP:s[0-9]+]], #1.0
; CHECK: mov [[ID:x[0-9]+]], x0
; CHECK: mov x21, xzr
; CHECK: bl {{.*}}foo
; CHECK: cbnz x21
+; CHECK: fmov [[CMP:s[0-9]+]], #1.0
; CHECK: fcmp s0, [[CMP]]
; CHECK: b.le
; Access part of the error object and save it to error_ref
diff --git a/llvm/test/CodeGen/AArch64/addsub.ll b/llvm/test/CodeGen/AArch64/addsub.ll
index b8e5884866476..37d74518e520a 100644
--- a/llvm/test/CodeGen/AArch64/addsub.ll
+++ b/llvm/test/CodeGen/AArch64/addsub.ll
@@ -204,14 +204,13 @@ declare i32 @foox(i32)
define void @add_in_loop(i32 %0) {
; CHECK-LABEL: add_in_loop:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: mov w19, #43690 // =0xaaaa
-; CHECK-NEXT: movk w19, #170, lsl #16
; CHECK-NEXT: .LBB19_1: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: add w0, w0, w19
+; CHECK-NEXT: mov w8, #43690 // =0xaaaa
+; CHECK-NEXT: movk w8, #170, lsl #16
+; CHECK-NEXT: add w0, w0, w8
; CHECK-NEXT: bl foox
; CHECK-NEXT: b .LBB19_1
br label %2
diff --git a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll
index bc26eca6f27ef..6d8cfe0508144 100644
--- a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll
+++ b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll
@@ -14,7 +14,7 @@ define void @_ZN38SanitizerCommonInterceptors_Scanf_Test8TestBodyEv(ptr %.str.40
; CHECK-NEXT: stp x20, x19, [sp, #96] ; 16-byte Folded Spill
; CHECK-NEXT: stp x29, x30, [sp, #112] ; 16-byte Folded Spill
; CHECK-NEXT: mov x24, x6
-; CHECK-NEXT: mov x19, x5
+; CHECK-NEXT: mov x28, x5
; CHECK-NEXT: mov x20, x4
; CHECK-NEXT: mov x21, x3
; CHECK-NEXT: mov x22, x2
@@ -24,18 +24,18 @@ define void @_ZN38SanitizerCommonInterceptors_Scanf_Test8TestBodyEv(ptr %.str.40
; CHECK-NEXT: mov x0, #0 ; =0x0
; CHECK-NEXT: mov w1, #1 ; =0x1
; CHECK-NEXT: bl __ZL9testScanfPKcjz
-; CHECK-NEXT: mov w28, #4 ; =0x4
-; CHECK-NEXT: stp x28, x28, [sp, #8]
-; CHECK-NEXT: str x28, [sp]
+; CHECK-NEXT: mov w27, #4 ; =0x4
+; CHECK-NEXT: stp x27, x27, [sp, #8]
+; CHECK-NEXT: str x27, [sp]
; CHECK-NEXT: mov x0, #0 ; =0x0
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL9testScanfPKcjz
-; CHECK-NEXT: stp x28, xzr, [sp]
+; CHECK-NEXT: stp x27, xzr, [sp]
; CHECK-NEXT: mov x0, #0 ; =0x0
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL9testScanfPKcjz
-; CHECK-NEXT: mov w27, #8 ; =0x8
-; CHECK-NEXT: str x27, [sp]
+; CHECK-NEXT: mov w19, #8 ; =0x8
+; CHECK-NEXT: str x19, [sp]
; CHECK-NEXT: mov x0, #0 ; =0x0
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL9testScanfPKcjz
@@ -48,7 +48,7 @@ define void @_ZN38SanitizerCommonInterceptors_Scanf_Test8TestBodyEv(ptr %.str.40
; CHECK-NEXT: mov x0, #0 ; =0x0
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL9testScanfPKcjz
-; CHECK-NEXT: str x28, [sp]
+; CHECK-NEXT: str x27, [sp]
; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x26, _.str at GOTPAGE
; CHECK-NEXT: Lloh1:
@@ -57,28 +57,28 @@ define void @_ZN38SanitizerCommonInterceptors_Scanf_Test8TestBodyEv(ptr %.str.40
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL9testScanfPKcjz
; CHECK-NEXT: str wzr, [x24]
-; CHECK-NEXT: str x27, [sp]
+; CHECK-NEXT: str x19, [sp]
; CHECK-NEXT: mov x0, x25
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz
-; CHECK-NEXT: str x28, [sp]
+; CHECK-NEXT: str x27, [sp]
; CHECK-NEXT: mov x0, x23
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz
-; CHECK-NEXT: str x28, [sp]
+; CHECK-NEXT: str x27, [sp]
; CHECK-NEXT: mov x0, x22
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz
-; CHECK-NEXT: str x28, [sp]
+; CHECK-NEXT: str x27, [sp]
; CHECK-NEXT: mov x0, x21
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz
-; CHECK-NEXT: str x28, [sp]
+; CHECK-NEXT: str x27, [sp]
; CHECK-NEXT: mov x0, x20
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz
; CHECK-NEXT: str xzr, [sp]
-; CHECK-NEXT: mov x0, x19
+; CHECK-NEXT: mov x0, x28
; CHECK-NEXT: mov w1, #0 ; =0x0
; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz
; CHECK-NEXT: str xzr, [sp]
diff --git a/llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll b/llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
index 09e80ee936738..9bfcb3d3af605 100644
--- a/llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
+++ b/llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
@@ -519,40 +519,36 @@ declare ptr @Update(ptr) #1
define void @combine_non_adjacent_cmp_br(ptr nocapture readonly %hdCall) #0 {
; CHECK-LABEL: combine_non_adjacent_cmp_br:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: str x30, [sp, #-48]! // 8-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w21, -24
-; CHECK-NEXT: .cfi_offset w22, -32
-; CHECK-NEXT: .cfi_offset w30, -48
-; CHECK-NEXT: ldr x20, [x0]
-; CHECK-NEXT: mov w19, #24 // =0x18
-; CHECK-NEXT: adrp x22, glob
-; CHECK-NEXT: add x21, x20, #2
+; CHECK-NEXT: .cfi_offset w30, -32
+; CHECK-NEXT: ldr x19, [x0]
+; CHECK-NEXT: adrp x21, glob
+; CHECK-NEXT: add x20, x19, #2
; CHECK-NEXT: .LBB9_1: // %land.rhs
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldr x8, [x19]
+; CHECK-NEXT: mov w8, #24 // =0x18
+; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: cmp x8, #1
; CHECK-NEXT: b.lt .LBB9_3
; CHECK-NEXT: // %bb.2: // %while.body
; CHECK-NEXT: // in Loop: Header=BB9_1 Depth=1
-; CHECK-NEXT: ldr x0, [x22, :lo12:glob]
+; CHECK-NEXT: ldr x0, [x21, :lo12:glob]
; CHECK-NEXT: bl Update
-; CHECK-NEXT: sub x21, x21, #2
-; CHECK-NEXT: cmp x20, x21
+; CHECK-NEXT: sub x20, x20, #2
+; CHECK-NEXT: cmp x19, x20
; CHECK-NEXT: b.lt .LBB9_1
; CHECK-NEXT: .LBB9_3: // %while.end
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT: ldr x30, [sp], #48 // 8-byte Folded Reload
+; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w19
; CHECK-NEXT: .cfi_restore w20
; CHECK-NEXT: .cfi_restore w21
-; CHECK-NEXT: .cfi_restore w22
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 145aef9123a4e..96748c80ccf93 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -566,16 +566,13 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-SD-LABEL: test_signed_v2f128_v2i32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #112
+; CHECK-SD-NEXT: sub sp, sp, #96
; CHECK-SD-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-SD-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 112
+; CHECK-SD-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 96
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
-; CHECK-SD-NEXT: .cfi_offset w22, -32
-; CHECK-SD-NEXT: .cfi_offset w30, -48
+; CHECK-SD-NEXT: .cfi_offset w30, -32
; CHECK-SD-NEXT: mov v2.16b, v1.16b
; CHECK-SD-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-SD-NEXT: adrp x8, .LCPI15_0
@@ -586,24 +583,24 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: mov w19, w0
; CHECK-SD-NEXT: bl __fixtfsi
-; CHECK-SD-NEXT: adrp x8, .LCPI15_1
-; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
+; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: csel w19, w8, w0, mi
+; CHECK-SD-NEXT: adrp x8, .LCPI15_1
; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
-; CHECK-SD-NEXT: mov w20, #-2147483648 // =0x80000000
-; CHECK-SD-NEXT: csel w19, w20, w0, mi
; CHECK-SD-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-SD-NEXT: mov w21, #2147483647 // =0x7fffffff
+; CHECK-SD-NEXT: mov w8, #2147483647 // =0x7fffffff
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w19, w21, w19, gt
+; CHECK-SD-NEXT: csel w19, w8, w19, gt
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w22, wzr, w19, ne
+; CHECK-SD-NEXT: csel w20, wzr, w19, ne
; CHECK-SD-NEXT: bl __getf2
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: mov w19, w0
@@ -611,36 +608,35 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: csel w19, w20, w0, mi
+; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: csel w19, w8, w0, mi
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w19, w21, w19, gt
+; CHECK-SD-NEXT: mov w8, #2147483647 // =0x7fffffff
+; CHECK-SD-NEXT: csel w19, w8, w19, gt
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-SD-NEXT: csel w8, wzr, w19, ne
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: mov v0.s[1], w22
-; CHECK-SD-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.s[1], w20
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: add sp, sp, #112
+; CHECK-SD-NEXT: add sp, sp, #96
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: adrp x8, .LCPI15_1
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
@@ -650,23 +646,23 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
+; CHECK-GI-NEXT: mov x21, #-4603241769126068224 // =0xc01e000000000000
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
+; CHECK-GI-NEXT: csel x20, x8, x21, gt
; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: movk x8, #16413, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -676,7 +672,7 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
@@ -685,28 +681,29 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: csel x21, x8, x21, gt
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x8, x19, xzr, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: movk x8, #16413, lsl #48
+; CHECK-GI-NEXT: csel x8, x21, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #96
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -716,7 +713,7 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-LABEL: test_signed_v3f128_v3i32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sub sp, sp, #128
-; CHECK-SD-NEXT: stp x30, x23, [sp, #80] // 16-byte Folded Spill
+; CHECK-SD-NEXT: str x30, [sp, #80] // 8-byte Spill
; CHECK-SD-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
; CHECK-SD-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
; CHECK-SD-NEXT: .cfi_def_cfa_offset 128
@@ -724,7 +721,6 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-NEXT: .cfi_offset w20, -16
; CHECK-SD-NEXT: .cfi_offset w21, -24
; CHECK-SD-NEXT: .cfi_offset w22, -32
-; CHECK-SD-NEXT: .cfi_offset w23, -40
; CHECK-SD-NEXT: .cfi_offset w30, -48
; CHECK-SD-NEXT: str q0, [sp, #64] // 16-byte Spill
; CHECK-SD-NEXT: adrp x8, .LCPI16_0
@@ -736,18 +732,19 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: mov w19, w0
; CHECK-SD-NEXT: bl __fixtfsi
-; CHECK-SD-NEXT: adrp x8, .LCPI16_1
-; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
+; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: csel w19, w8, w0, mi
+; CHECK-SD-NEXT: adrp x8, .LCPI16_1
+; CHECK-SD-NEXT: mov w22, #-2147483648 // =0x80000000
; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
-; CHECK-SD-NEXT: mov w20, #-2147483648 // =0x80000000
-; CHECK-SD-NEXT: csel w19, w20, w0, mi
; CHECK-SD-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-SD-NEXT: mov w22, #2147483647 // =0x7fffffff
+; CHECK-SD-NEXT: mov w20, #2147483647 // =0x7fffffff
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w19, w22, w19, gt
+; CHECK-SD-NEXT: csel w19, w20, w19, gt
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
@@ -761,17 +758,17 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: csel w19, w20, w0, mi
+; CHECK-SD-NEXT: csel w19, w22, w0, mi
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w19, w22, w19, gt
+; CHECK-SD-NEXT: csel w19, w20, w19, gt
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w23, wzr, w19, ne
+; CHECK-SD-NEXT: csel w22, wzr, w19, ne
; CHECK-SD-NEXT: bl __getf2
; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-SD-NEXT: mov w19, w0
@@ -779,19 +776,20 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: csel w19, w20, w0, mi
+; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: csel w19, w8, w0, mi
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w19, w22, w19, gt
+; CHECK-SD-NEXT: csel w19, w20, w19, gt
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
+; CHECK-SD-NEXT: ldr x30, [sp, #80] // 8-byte Reload
; CHECK-SD-NEXT: csel w8, wzr, w19, ne
; CHECK-SD-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: mov v0.s[1], w23
-; CHECK-SD-NEXT: ldp x30, x23, [sp, #80] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.s[1], w22
; CHECK-SD-NEXT: mov v0.s[2], w21
; CHECK-SD-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
; CHECK-SD-NEXT: add sp, sp, #128
@@ -800,7 +798,7 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-LABEL: test_signed_v3f128_v3i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: stp x30, x23, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #80] // 8-byte Spill
; CHECK-GI-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
@@ -808,7 +806,6 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
; CHECK-GI-NEXT: .cfi_offset w30, -48
; CHECK-GI-NEXT: adrp x8, .LCPI16_1
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
@@ -819,23 +816,23 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
+; CHECK-GI-NEXT: mov x22, #-4603241769126068224 // =0xc01e000000000000
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
+; CHECK-GI-NEXT: csel x20, x8, x22, gt
; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: movk x8, #16413, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -844,7 +841,7 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
@@ -853,13 +850,15 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x23, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: csel x21, x8, x22, gt
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x8, x19, xzr, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: movk x8, #16413, lsl #48
+; CHECK-GI-NEXT: csel x8, x21, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
@@ -869,7 +868,7 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w23, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
@@ -878,26 +877,28 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: csel x22, x8, x22, gt
+; CHECK-GI-NEXT: mov v0.d[1], x22
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x8, x19, xzr, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: movk x8, #16413, lsl #48
+; CHECK-GI-NEXT: csel x8, x22, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldr x30, [sp, #80] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.s[1], w21
; CHECK-GI-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.s[1], w23
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w8
; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
@@ -1531,118 +1532,110 @@ define <2 x i64> @test_signed_v2f32_v2i64(<2 x float> %f) {
define <2 x i100> @test_signed_v2f32_v2i100(<2 x float> %f) {
; CHECK-SD-LABEL: test_signed_v2f32_v2i100:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #80
-; CHECK-SD-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-SD-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
-; CHECK-SD-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-SD-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 80
+; CHECK-SD-NEXT: sub sp, sp, #64
+; CHECK-SD-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
+; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
-; CHECK-SD-NEXT: .cfi_offset w22, -32
-; CHECK-SD-NEXT: .cfi_offset w30, -40
-; CHECK-SD-NEXT: .cfi_offset b8, -48
-; CHECK-SD-NEXT: .cfi_offset b9, -56
-; CHECK-SD-NEXT: .cfi_offset b10, -64
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: .cfi_offset b8, -40
+; CHECK-SD-NEXT: .cfi_offset b9, -48
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-SD-NEXT: bl __fixsfti
-; CHECK-SD-NEXT: movi v9.2s, #241, lsl #24
+; CHECK-SD-NEXT: movi v1.2s, #241, lsl #24
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: mov w8, #1895825407 // =0x70ffffff
-; CHECK-SD-NEXT: fmov s10, w8
-; CHECK-SD-NEXT: mov x21, #-34359738368 // =0xfffffff800000000
-; CHECK-SD-NEXT: mov x22, #34359738367 // =0x7ffffffff
+; CHECK-SD-NEXT: fmov s9, w8
+; CHECK-SD-NEXT: mov x9, #-34359738368 // =0xfffffff800000000
+; CHECK-SD-NEXT: mov x10, #34359738367 // =0x7ffffffff
; CHECK-SD-NEXT: mov s8, v0.s[1]
-; CHECK-SD-NEXT: fcmp s0, s9
+; CHECK-SD-NEXT: fcmp s0, s1
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
-; CHECK-SD-NEXT: fcmp s0, s10
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
+; CHECK-SD-NEXT: fcmp s0, s9
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp s0, s0
; CHECK-SD-NEXT: fmov s0, s8
; CHECK-SD-NEXT: csel x19, xzr, x8, vs
; CHECK-SD-NEXT: csel x20, xzr, x9, vs
; CHECK-SD-NEXT: bl __fixsfti
-; CHECK-SD-NEXT: fcmp s8, s9
-; CHECK-SD-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-SD-NEXT: movi v0.2s, #241, lsl #24
+; CHECK-SD-NEXT: mov x9, #-34359738368 // =0xfffffff800000000
+; CHECK-SD-NEXT: mov x10, #34359738367 // =0x7ffffffff
+; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-SD-NEXT: fcmp s8, s0
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
-; CHECK-SD-NEXT: fcmp s8, s10
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
+; CHECK-SD-NEXT: fcmp s8, s9
; CHECK-SD-NEXT: mov x0, x19
; CHECK-SD-NEXT: mov x1, x20
-; CHECK-SD-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp s8, s8
-; CHECK-SD-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-SD-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-SD-NEXT: csel x2, xzr, x8, vs
; CHECK-SD-NEXT: csel x3, xzr, x9, vs
-; CHECK-SD-NEXT: add sp, sp, #80
+; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f32_v2i100:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -40
-; CHECK-GI-NEXT: .cfi_offset b8, -48
-; CHECK-GI-NEXT: .cfi_offset b9, -56
-; CHECK-GI-NEXT: .cfi_offset b10, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: mov s8, v0.s[1]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-GI-NEXT: bl __fixsfti
-; CHECK-GI-NEXT: movi v9.2s, #241, lsl #24
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi v0.2s, #241, lsl #24
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w8, #1895825407 // =0x70ffffff
-; CHECK-GI-NEXT: fmov s10, w8
-; CHECK-GI-NEXT: mov x21, #34359738368 // =0x800000000
-; CHECK-GI-NEXT: mov x22, #34359738367 // =0x7ffffffff
-; CHECK-GI-NEXT: fcmp s0, s9
+; CHECK-GI-NEXT: fmov s9, w8
+; CHECK-GI-NEXT: mov x9, #34359738368 // =0x800000000
+; CHECK-GI-NEXT: mov x10, #34359738367 // =0x7ffffffff
+; CHECK-GI-NEXT: fcmp s1, s0
+; CHECK-GI-NEXT: fmov s0, s8
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
-; CHECK-GI-NEXT: fcmp s0, s10
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
+; CHECK-GI-NEXT: fcmp s1, s9
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
-; CHECK-GI-NEXT: fcmp s0, s0
-; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
+; CHECK-GI-NEXT: fcmp s1, s1
; CHECK-GI-NEXT: csel x19, xzr, x8, vs
; CHECK-GI-NEXT: csel x20, xzr, x9, vs
; CHECK-GI-NEXT: bl __fixsfti
-; CHECK-GI-NEXT: fcmp s8, s9
-; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-GI-NEXT: movi v0.2s, #241, lsl #24
+; CHECK-GI-NEXT: mov x9, #34359738368 // =0x800000000
+; CHECK-GI-NEXT: mov x10, #34359738367 // =0x7ffffffff
+; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: fcmp s8, s0
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
-; CHECK-GI-NEXT: fcmp s8, s10
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
+; CHECK-GI-NEXT: fcmp s8, s9
; CHECK-GI-NEXT: mov x0, x19
; CHECK-GI-NEXT: mov x1, x20
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
; CHECK-GI-NEXT: fcmp s8, s8
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel x2, xzr, x8, vs
; CHECK-GI-NEXT: csel x3, xzr, x9, vs
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i100> @llvm.fptosi.sat.v2f32.v2i100(<2 x float> %f)
ret <2 x i100> %x
@@ -1651,118 +1644,110 @@ define <2 x i100> @test_signed_v2f32_v2i100(<2 x float> %f) {
define <2 x i128> @test_signed_v2f32_v2i128(<2 x float> %f) {
; CHECK-SD-LABEL: test_signed_v2f32_v2i128:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #80
-; CHECK-SD-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-SD-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
-; CHECK-SD-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-SD-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 80
+; CHECK-SD-NEXT: sub sp, sp, #64
+; CHECK-SD-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
+; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
-; CHECK-SD-NEXT: .cfi_offset w22, -32
-; CHECK-SD-NEXT: .cfi_offset w30, -40
-; CHECK-SD-NEXT: .cfi_offset b8, -48
-; CHECK-SD-NEXT: .cfi_offset b9, -56
-; CHECK-SD-NEXT: .cfi_offset b10, -64
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: .cfi_offset b8, -40
+; CHECK-SD-NEXT: .cfi_offset b9, -48
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-SD-NEXT: bl __fixsfti
-; CHECK-SD-NEXT: movi v9.2s, #255, lsl #24
+; CHECK-SD-NEXT: movi v1.2s, #255, lsl #24
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: mov w8, #2130706431 // =0x7effffff
-; CHECK-SD-NEXT: fmov s10, w8
-; CHECK-SD-NEXT: mov x21, #-9223372036854775808 // =0x8000000000000000
-; CHECK-SD-NEXT: mov x22, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: fmov s9, w8
+; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-SD-NEXT: mov s8, v0.s[1]
-; CHECK-SD-NEXT: fcmp s0, s9
+; CHECK-SD-NEXT: fcmp s0, s1
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
-; CHECK-SD-NEXT: fcmp s0, s10
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
+; CHECK-SD-NEXT: fcmp s0, s9
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp s0, s0
; CHECK-SD-NEXT: fmov s0, s8
; CHECK-SD-NEXT: csel x19, xzr, x8, vs
; CHECK-SD-NEXT: csel x20, xzr, x9, vs
; CHECK-SD-NEXT: bl __fixsfti
-; CHECK-SD-NEXT: fcmp s8, s9
-; CHECK-SD-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-SD-NEXT: movi v0.2s, #255, lsl #24
+; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-SD-NEXT: fcmp s8, s0
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
-; CHECK-SD-NEXT: fcmp s8, s10
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
+; CHECK-SD-NEXT: fcmp s8, s9
; CHECK-SD-NEXT: mov x0, x19
; CHECK-SD-NEXT: mov x1, x20
-; CHECK-SD-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp s8, s8
-; CHECK-SD-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-SD-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-SD-NEXT: csel x2, xzr, x8, vs
; CHECK-SD-NEXT: csel x3, xzr, x9, vs
-; CHECK-SD-NEXT: add sp, sp, #80
+; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f32_v2i128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -40
-; CHECK-GI-NEXT: .cfi_offset b8, -48
-; CHECK-GI-NEXT: .cfi_offset b9, -56
-; CHECK-GI-NEXT: .cfi_offset b10, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: mov s8, v0.s[1]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-GI-NEXT: bl __fixsfti
-; CHECK-GI-NEXT: movi v9.2s, #255, lsl #24
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi v0.2s, #255, lsl #24
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w8, #2130706431 // =0x7effffff
-; CHECK-GI-NEXT: fmov s10, w8
-; CHECK-GI-NEXT: mov x21, #-9223372036854775808 // =0x8000000000000000
-; CHECK-GI-NEXT: mov x22, #9223372036854775807 // =0x7fffffffffffffff
-; CHECK-GI-NEXT: fcmp s0, s9
+; CHECK-GI-NEXT: fmov s9, w8
+; CHECK-GI-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-NEXT: fcmp s1, s0
+; CHECK-GI-NEXT: fmov s0, s8
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
-; CHECK-GI-NEXT: fcmp s0, s10
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
+; CHECK-GI-NEXT: fcmp s1, s9
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
-; CHECK-GI-NEXT: fcmp s0, s0
-; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
+; CHECK-GI-NEXT: fcmp s1, s1
; CHECK-GI-NEXT: csel x19, xzr, x8, vs
; CHECK-GI-NEXT: csel x20, xzr, x9, vs
; CHECK-GI-NEXT: bl __fixsfti
-; CHECK-GI-NEXT: fcmp s8, s9
-; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-GI-NEXT: movi v0.2s, #255, lsl #24
+; CHECK-GI-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: fcmp s8, s0
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
-; CHECK-GI-NEXT: fcmp s8, s10
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
+; CHECK-GI-NEXT: fcmp s8, s9
; CHECK-GI-NEXT: mov x0, x19
; CHECK-GI-NEXT: mov x1, x20
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
; CHECK-GI-NEXT: fcmp s8, s8
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel x2, xzr, x8, vs
; CHECK-GI-NEXT: csel x3, xzr, x9, vs
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i128> @llvm.fptosi.sat.v2f32.v2i128(<2 x float> %f)
ret <2 x i128> %x
@@ -2603,37 +2588,34 @@ define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
; CHECK-SD-LABEL: test_signed_v2f64_v2i100:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #80
+; CHECK-SD-NEXT: sub sp, sp, #64
; CHECK-SD-NEXT: str d10, [sp, #16] // 8-byte Spill
; CHECK-SD-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-SD-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-SD-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 80
+; CHECK-SD-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
-; CHECK-SD-NEXT: .cfi_offset w22, -32
-; CHECK-SD-NEXT: .cfi_offset w30, -40
-; CHECK-SD-NEXT: .cfi_offset b8, -48
-; CHECK-SD-NEXT: .cfi_offset b9, -56
-; CHECK-SD-NEXT: .cfi_offset b10, -64
+; CHECK-SD-NEXT: .cfi_offset w30, -24
+; CHECK-SD-NEXT: .cfi_offset b8, -32
+; CHECK-SD-NEXT: .cfi_offset b9, -40
+; CHECK-SD-NEXT: .cfi_offset b10, -48
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: bl __fixdfti
; CHECK-SD-NEXT: mov x8, #-4170333254945079296 // =0xc620000000000000
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-SD-NEXT: mov x21, #-34359738368 // =0xfffffff800000000
+; CHECK-SD-NEXT: mov x9, #-34359738368 // =0xfffffff800000000
; CHECK-SD-NEXT: fmov d9, x8
; CHECK-SD-NEXT: mov x8, #5053038781909696511 // =0x461fffffffffffff
-; CHECK-SD-NEXT: mov x22, #34359738367 // =0x7ffffffff
+; CHECK-SD-NEXT: mov x10, #34359738367 // =0x7ffffffff
; CHECK-SD-NEXT: fmov d10, x8
; CHECK-SD-NEXT: mov d8, v0.d[1]
; CHECK-SD-NEXT: fcmp d0, d9
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
; CHECK-SD-NEXT: fcmp d0, d10
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp d0, d0
; CHECK-SD-NEXT: fmov d0, d8
@@ -2641,80 +2623,79 @@ define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
; CHECK-SD-NEXT: csel x20, xzr, x9, vs
; CHECK-SD-NEXT: bl __fixdfti
; CHECK-SD-NEXT: fcmp d8, d9
+; CHECK-SD-NEXT: mov x9, #-34359738368 // =0xfffffff800000000
+; CHECK-SD-NEXT: mov x10, #34359738367 // =0x7ffffffff
; CHECK-SD-NEXT: ldr x30, [sp, #40] // 8-byte Reload
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
; CHECK-SD-NEXT: fcmp d8, d10
; CHECK-SD-NEXT: mov x0, x19
; CHECK-SD-NEXT: mov x1, x20
; CHECK-SD-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp d8, d8
-; CHECK-SD-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-SD-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-SD-NEXT: csel x2, xzr, x8, vs
; CHECK-SD-NEXT: csel x3, xzr, x9, vs
-; CHECK-SD-NEXT: add sp, sp, #80
+; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f64_v2i100:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: sub sp, sp, #64
; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -40
-; CHECK-GI-NEXT: .cfi_offset b8, -48
-; CHECK-GI-NEXT: .cfi_offset b9, -56
-; CHECK-GI-NEXT: .cfi_offset b10, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: .cfi_offset b9, -40
+; CHECK-GI-NEXT: .cfi_offset b10, -48
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: mov d8, v0.d[1]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: bl __fixdfti
; CHECK-GI-NEXT: mov x8, #-4170333254945079296 // =0xc620000000000000
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: mov x21, #34359738368 // =0x800000000
+; CHECK-GI-NEXT: mov x9, #34359738368 // =0x800000000
; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: mov x8, #5053038781909696511 // =0x461fffffffffffff
-; CHECK-GI-NEXT: mov x22, #34359738367 // =0x7ffffffff
+; CHECK-GI-NEXT: mov x10, #34359738367 // =0x7ffffffff
; CHECK-GI-NEXT: fmov d10, x8
; CHECK-GI-NEXT: fcmp d0, d9
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
; CHECK-GI-NEXT: fcmp d0, d10
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
; CHECK-GI-NEXT: fcmp d0, d0
; CHECK-GI-NEXT: fmov d0, d8
; CHECK-GI-NEXT: csel x19, xzr, x8, vs
; CHECK-GI-NEXT: csel x20, xzr, x9, vs
; CHECK-GI-NEXT: bl __fixdfti
; CHECK-GI-NEXT: fcmp d8, d9
+; CHECK-GI-NEXT: mov x9, #34359738368 // =0x800000000
+; CHECK-GI-NEXT: mov x10, #34359738367 // =0x7ffffffff
; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
; CHECK-GI-NEXT: fcmp d8, d10
; CHECK-GI-NEXT: mov x0, x19
; CHECK-GI-NEXT: mov x1, x20
; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
; CHECK-GI-NEXT: fcmp d8, d8
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel x2, xzr, x8, vs
; CHECK-GI-NEXT: csel x3, xzr, x9, vs
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double> %f)
ret <2 x i100> %x
@@ -2723,37 +2704,34 @@ define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
define <2 x i128> @test_signed_v2f64_v2i128(<2 x double> %f) {
; CHECK-SD-LABEL: test_signed_v2f64_v2i128:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #80
+; CHECK-SD-NEXT: sub sp, sp, #64
; CHECK-SD-NEXT: str d10, [sp, #16] // 8-byte Spill
; CHECK-SD-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-SD-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-SD-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 80
+; CHECK-SD-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
-; CHECK-SD-NEXT: .cfi_offset w22, -32
-; CHECK-SD-NEXT: .cfi_offset w30, -40
-; CHECK-SD-NEXT: .cfi_offset b8, -48
-; CHECK-SD-NEXT: .cfi_offset b9, -56
-; CHECK-SD-NEXT: .cfi_offset b10, -64
+; CHECK-SD-NEXT: .cfi_offset w30, -24
+; CHECK-SD-NEXT: .cfi_offset b8, -32
+; CHECK-SD-NEXT: .cfi_offset b9, -40
+; CHECK-SD-NEXT: .cfi_offset b10, -48
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: bl __fixdfti
; CHECK-SD-NEXT: mov x8, #-4044232465378705408 // =0xc7e0000000000000
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-SD-NEXT: mov x21, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
; CHECK-SD-NEXT: fmov d9, x8
; CHECK-SD-NEXT: mov x8, #5179139571476070399 // =0x47dfffffffffffff
-; CHECK-SD-NEXT: mov x22, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-SD-NEXT: fmov d10, x8
; CHECK-SD-NEXT: mov d8, v0.d[1]
; CHECK-SD-NEXT: fcmp d0, d9
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
; CHECK-SD-NEXT: fcmp d0, d10
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp d0, d0
; CHECK-SD-NEXT: fmov d0, d8
@@ -2761,80 +2739,79 @@ define <2 x i128> @test_signed_v2f64_v2i128(<2 x double> %f) {
; CHECK-SD-NEXT: csel x20, xzr, x9, vs
; CHECK-SD-NEXT: bl __fixdfti
; CHECK-SD-NEXT: fcmp d8, d9
+; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-SD-NEXT: ldr x30, [sp, #40] // 8-byte Reload
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
-; CHECK-SD-NEXT: csel x9, x21, x1, lt
+; CHECK-SD-NEXT: csel x9, x9, x1, lt
; CHECK-SD-NEXT: fcmp d8, d10
; CHECK-SD-NEXT: mov x0, x19
; CHECK-SD-NEXT: mov x1, x20
; CHECK-SD-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x9, x22, x9, gt
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x9, x10, x9, gt
; CHECK-SD-NEXT: csinv x8, x8, xzr, le
; CHECK-SD-NEXT: fcmp d8, d8
-; CHECK-SD-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-SD-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-SD-NEXT: csel x2, xzr, x8, vs
; CHECK-SD-NEXT: csel x3, xzr, x9, vs
-; CHECK-SD-NEXT: add sp, sp, #80
+; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f64_v2i128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: sub sp, sp, #64
; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -40
-; CHECK-GI-NEXT: .cfi_offset b8, -48
-; CHECK-GI-NEXT: .cfi_offset b9, -56
-; CHECK-GI-NEXT: .cfi_offset b10, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: .cfi_offset b9, -40
+; CHECK-GI-NEXT: .cfi_offset b10, -48
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: mov d8, v0.d[1]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: bl __fixdfti
; CHECK-GI-NEXT: mov x8, #-4044232465378705408 // =0xc7e0000000000000
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: mov x21, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: mov x8, #5179139571476070399 // =0x47dfffffffffffff
-; CHECK-GI-NEXT: mov x22, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-GI-NEXT: fmov d10, x8
; CHECK-GI-NEXT: fcmp d0, d9
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
; CHECK-GI-NEXT: fcmp d0, d10
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
; CHECK-GI-NEXT: fcmp d0, d0
; CHECK-GI-NEXT: fmov d0, d8
; CHECK-GI-NEXT: csel x19, xzr, x8, vs
; CHECK-GI-NEXT: csel x20, xzr, x9, vs
; CHECK-GI-NEXT: bl __fixdfti
; CHECK-GI-NEXT: fcmp d8, d9
+; CHECK-GI-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
-; CHECK-GI-NEXT: csel x9, x21, x1, lt
+; CHECK-GI-NEXT: csel x9, x9, x1, lt
; CHECK-GI-NEXT: fcmp d8, d10
; CHECK-GI-NEXT: mov x0, x19
; CHECK-GI-NEXT: mov x1, x20
; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: csinv x8, x8, xzr, le
-; CHECK-GI-NEXT: csel x9, x22, x9, gt
+; CHECK-GI-NEXT: csel x9, x10, x9, gt
; CHECK-GI-NEXT: fcmp d8, d8
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel x2, xzr, x8, vs
; CHECK-GI-NEXT: csel x3, xzr, x9, vs
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double> %f)
ret <2 x i128> %x
@@ -5062,14 +5039,11 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-SD-LABEL: test_signed_v2f128_v2i64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #96
-; CHECK-SD-NEXT: stp x30, x21, [sp, #64] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 96
+; CHECK-SD-NEXT: sub sp, sp, #80
+; CHECK-SD-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 80
; CHECK-SD-NEXT: .cfi_offset w19, -8
-; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
-; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: .cfi_offset w30, -16
; CHECK-SD-NEXT: mov v2.16b, v1.16b
; CHECK-SD-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-SD-NEXT: adrp x8, .LCPI86_0
@@ -5080,18 +5054,18 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: mov w19, w0
; CHECK-SD-NEXT: bl __fixtfdi
-; CHECK-SD-NEXT: adrp x8, .LCPI86_1
-; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
+; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: csel x19, x8, x0, mi
+; CHECK-SD-NEXT: adrp x8, .LCPI86_1
; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI86_1]
-; CHECK-SD-NEXT: mov x20, #-9223372036854775808 // =0x8000000000000000
-; CHECK-SD-NEXT: csel x19, x20, x0, mi
; CHECK-SD-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-SD-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel x19, x21, x19, gt
+; CHECK-SD-NEXT: csel x19, x8, x19, gt
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
@@ -5107,36 +5081,34 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: csel x19, x20, x0, mi
+; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: csel x19, x8, x0, mi
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel x19, x21, x19, gt
+; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: csel x19, x8, x19, gt
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: csel x8, xzr, x19, ne
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ldp x30, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: add sp, sp, #96
+; CHECK-SD-NEXT: add sp, sp, #80
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: stp x30, x23, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
@@ -5146,23 +5118,23 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4594234569871327232 // =0xc03e000000000000
+; CHECK-GI-NEXT: mov x21, #-4594234569871327232 // =0xc03e000000000000
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
+; CHECK-GI-NEXT: csel x20, x8, x21, gt
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x22, #-1125899906842624 // =0xfffc000000000000
+; CHECK-GI-NEXT: mov x8, #-1125899906842624 // =0xfffc000000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x23, #4629137466983448575 // =0x403dffffffffffff
-; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: csel x8, x19, x8, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x23, mi
+; CHECK-GI-NEXT: mov x8, #4629137466983448575 // =0x403dffffffffffff
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -5172,7 +5144,7 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x21, xzr, x19, ne
+; CHECK-GI-NEXT: csel x20, xzr, x19, ne
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
@@ -5181,27 +5153,28 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: csel x21, x8, x21, gt
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: mov x8, #-1125899906842624 // =0xfffc000000000000
+; CHECK-GI-NEXT: csel x8, x19, x8, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x23, mi
+; CHECK-GI-NEXT: mov x8, #4629137466983448575 // =0x403dffffffffffff
+; CHECK-GI-NEXT: csel x8, x21, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov d0, x21
+; CHECK-GI-NEXT: fmov d0, x20
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x8, xzr, x19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #96
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 083a84292029d..b48089132d3ee 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -563,16 +563,14 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
-; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: bl __gttf2
@@ -589,11 +587,11 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x21, #16414, lsl #48
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: movk x8, #16414, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
@@ -606,22 +604,23 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: csel x20, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x22
+; CHECK-GI-NEXT: csel x21, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x8, x20, xzr, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: movk x8, #16414, lsl #48
+; CHECK-GI-NEXT: csel x8, x21, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -693,7 +692,7 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v3f128_v3i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp x30, x23, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #48] // 8-byte Spill
; CHECK-GI-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
@@ -701,7 +700,6 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
; CHECK-GI-NEXT: .cfi_offset w30, -48
; CHECK-GI-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
@@ -720,11 +718,13 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: mov x22, #281474976579584 // =0xfffffffe0000
; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x21, #16414, lsl #48
+; CHECK-GI-NEXT: movk x22, #16414, lsl #48
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: movk x8, #16414, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
@@ -737,13 +737,13 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: csel x20, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x22
+; CHECK-GI-NEXT: csel x21, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x8, x20, xzr, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: csel x8, x21, x22, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
@@ -753,21 +753,23 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
+; CHECK-GI-NEXT: csel x21, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x22
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: mov v0.d[0], x21
+; CHECK-GI-NEXT: csel x22, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x22
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x22, xzr, mi
+; CHECK-GI-NEXT: csel x8, x21, xzr, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x21, mi
+; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: movk x8, #16414, lsl #48
+; CHECK-GI-NEXT: csel x8, x22, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
; CHECK-GI-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #48] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w0
@@ -1292,12 +1294,11 @@ define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sub sp, sp, #64
; CHECK-SD-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-SD-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
; CHECK-SD-NEXT: .cfi_offset w30, -32
; CHECK-SD-NEXT: .cfi_offset b8, -40
; CHECK-SD-NEXT: .cfi_offset b9, -48
@@ -1307,7 +1308,7 @@ define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
; CHECK-SD-NEXT: bl __fixunssfti
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: mov w8, #1904214015 // =0x717fffff
-; CHECK-SD-NEXT: mov x21, #68719476735 // =0xfffffffff
+; CHECK-SD-NEXT: mov x10, #68719476735 // =0xfffffffff
; CHECK-SD-NEXT: fmov s9, w8
; CHECK-SD-NEXT: mov s8, v0.s[1]
; CHECK-SD-NEXT: fcmp s0, #0.0
@@ -1315,19 +1316,20 @@ define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
; CHECK-SD-NEXT: csel x9, xzr, x1, lt
; CHECK-SD-NEXT: fcmp s0, s9
; CHECK-SD-NEXT: fmov s0, s8
-; CHECK-SD-NEXT: csel x19, x21, x9, gt
+; CHECK-SD-NEXT: csel x19, x10, x9, gt
; CHECK-SD-NEXT: csinv x20, x8, xzr, le
; CHECK-SD-NEXT: bl __fixunssfti
; CHECK-SD-NEXT: fcmp s8, #0.0
+; CHECK-SD-NEXT: mov x10, #68719476735 // =0xfffffffff
+; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
; CHECK-SD-NEXT: csel x9, xzr, x1, lt
; CHECK-SD-NEXT: fcmp s8, s9
; CHECK-SD-NEXT: mov x0, x20
; CHECK-SD-NEXT: mov x1, x19
; CHECK-SD-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x3, x21, x9, gt
-; CHECK-SD-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-SD-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x3, x10, x9, gt
; CHECK-SD-NEXT: csinv x2, x8, xzr, le
; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
@@ -1336,12 +1338,11 @@ define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #64
; CHECK-GI-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
@@ -1352,7 +1353,7 @@ define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
; CHECK-GI-NEXT: bl __fixunssfti
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w8, #1904214015 // =0x717fffff
-; CHECK-GI-NEXT: mov x21, #68719476735 // =0xfffffffff
+; CHECK-GI-NEXT: mov x10, #68719476735 // =0xfffffffff
; CHECK-GI-NEXT: fmov s9, w8
; CHECK-GI-NEXT: fcmp s0, #0.0
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
@@ -1360,19 +1361,20 @@ define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
; CHECK-GI-NEXT: fcmp s0, s9
; CHECK-GI-NEXT: fmov s0, s8
; CHECK-GI-NEXT: csinv x19, x8, xzr, le
-; CHECK-GI-NEXT: csel x20, x21, x9, gt
+; CHECK-GI-NEXT: csel x20, x10, x9, gt
; CHECK-GI-NEXT: bl __fixunssfti
; CHECK-GI-NEXT: fcmp s8, #0.0
+; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
; CHECK-GI-NEXT: csel x9, xzr, x1, lt
; CHECK-GI-NEXT: fcmp s8, s9
; CHECK-GI-NEXT: mov x0, x19
; CHECK-GI-NEXT: mov x1, x20
; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x3, x21, x9, gt
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-GI-NEXT: csinv x2, x8, xzr, le
+; CHECK-GI-NEXT: mov x8, #68719476735 // =0xfffffffff
+; CHECK-GI-NEXT: csel x3, x8, x9, gt
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float> %f)
@@ -2121,12 +2123,11 @@ define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sub sp, sp, #64
; CHECK-SD-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-SD-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w21, -24
; CHECK-SD-NEXT: .cfi_offset w30, -32
; CHECK-SD-NEXT: .cfi_offset b8, -40
; CHECK-SD-NEXT: .cfi_offset b9, -48
@@ -2135,7 +2136,7 @@ define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-SD-NEXT: bl __fixunsdfti
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: mov x8, #5057542381537067007 // =0x462fffffffffffff
-; CHECK-SD-NEXT: mov x21, #68719476735 // =0xfffffffff
+; CHECK-SD-NEXT: mov x10, #68719476735 // =0xfffffffff
; CHECK-SD-NEXT: fmov d9, x8
; CHECK-SD-NEXT: mov d8, v0.d[1]
; CHECK-SD-NEXT: fcmp d0, #0.0
@@ -2143,19 +2144,20 @@ define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-SD-NEXT: csel x9, xzr, x1, lt
; CHECK-SD-NEXT: fcmp d0, d9
; CHECK-SD-NEXT: fmov d0, d8
-; CHECK-SD-NEXT: csel x19, x21, x9, gt
+; CHECK-SD-NEXT: csel x19, x10, x9, gt
; CHECK-SD-NEXT: csinv x20, x8, xzr, le
; CHECK-SD-NEXT: bl __fixunsdfti
; CHECK-SD-NEXT: fcmp d8, #0.0
+; CHECK-SD-NEXT: mov x10, #68719476735 // =0xfffffffff
+; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
; CHECK-SD-NEXT: csel x9, xzr, x1, lt
; CHECK-SD-NEXT: fcmp d8, d9
; CHECK-SD-NEXT: mov x0, x20
; CHECK-SD-NEXT: mov x1, x19
; CHECK-SD-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x3, x21, x9, gt
-; CHECK-SD-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-SD-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x3, x10, x9, gt
; CHECK-SD-NEXT: csinv x2, x8, xzr, le
; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
@@ -2164,12 +2166,11 @@ define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #64
; CHECK-GI-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
@@ -2179,7 +2180,7 @@ define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-GI-NEXT: bl __fixunsdfti
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov x8, #5057542381537067007 // =0x462fffffffffffff
-; CHECK-GI-NEXT: mov x21, #68719476735 // =0xfffffffff
+; CHECK-GI-NEXT: mov x10, #68719476735 // =0xfffffffff
; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: fcmp d0, #0.0
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
@@ -2187,19 +2188,20 @@ define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-GI-NEXT: fcmp d0, d9
; CHECK-GI-NEXT: fmov d0, d8
; CHECK-GI-NEXT: csinv x19, x8, xzr, le
-; CHECK-GI-NEXT: csel x20, x21, x9, gt
+; CHECK-GI-NEXT: csel x20, x10, x9, gt
; CHECK-GI-NEXT: bl __fixunsdfti
; CHECK-GI-NEXT: fcmp d8, #0.0
+; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x0, lt
; CHECK-GI-NEXT: csel x9, xzr, x1, lt
; CHECK-GI-NEXT: fcmp d8, d9
; CHECK-GI-NEXT: mov x0, x19
; CHECK-GI-NEXT: mov x1, x20
; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x3, x21, x9, gt
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-GI-NEXT: csinv x2, x8, xzr, le
+; CHECK-GI-NEXT: mov x8, #68719476735 // =0xfffffffff
+; CHECK-GI-NEXT: csel x3, x8, x9, gt
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double> %f)
@@ -4124,17 +4126,14 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
-; CHECK-GI-NEXT: stp x30, x23, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: bl __gttf2
@@ -4150,12 +4149,12 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x21, #-562949953421312 // =0xfffe000000000000
+; CHECK-GI-NEXT: mov x8, #-562949953421312 // =0xfffe000000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #4629418941960159231 // =0x403effffffffffff
-; CHECK-GI-NEXT: csel x8, x19, x21, mi
+; CHECK-GI-NEXT: csel x8, x19, x8, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov x8, #4629418941960159231 // =0x403effffffffffff
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
@@ -4168,21 +4167,22 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: csel x20, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: csel x21, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: mov x8, #-562949953421312 // =0xfffe000000000000
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: mov x8, #4629418941960159231 // =0x403effffffffffff
+; CHECK-GI-NEXT: csel x8, x21, x8, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: fmov d0, x19
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x0
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll b/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
index 50fac819d4afe..ca9317ae3c321 100644
--- a/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
+++ b/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
@@ -27,7 +27,7 @@ define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %a
; CHECK-NEXT: .cfi_offset w26, -80
; CHECK-NEXT: .cfi_offset w27, -88
; CHECK-NEXT: .cfi_offset w28, -96
-; CHECK-NEXT: mov w19, w6
+; CHECK-NEXT: mov w28, w6
; CHECK-NEXT: mov w20, w5
; CHECK-NEXT: mov x21, x4
; CHECK-NEXT: mov x22, x3
@@ -39,7 +39,7 @@ define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %a
; CHECK-NEXT: adrp x27, LJTI0_0 at PAGE
; CHECK-NEXT: Lloh1:
; CHECK-NEXT: add x27, x27, LJTI0_0 at PAGEOFF
-; CHECK-NEXT: mov w28, #1 ; =0x1
+; CHECK-NEXT: mov w19, #1 ; =0x1
; CHECK-NEXT: ; implicit-def: $w8
; CHECK-NEXT: str x8, [sp, #40] ; 8-byte Spill
; CHECK-NEXT: b LBB0_2
@@ -64,7 +64,7 @@ define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %a
; CHECK-NEXT: br x8
; CHECK-NEXT: LBB0_4: ; %bb9
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: str w28, [x23]
+; CHECK-NEXT: str w19, [x23]
; CHECK-NEXT: b LBB0_2
; CHECK-NEXT: LBB0_5: ; %bb8
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
@@ -75,7 +75,7 @@ define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %a
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: mov w8, #1 ; =0x1
; CHECK-NEXT: str x8, [sp, #40] ; 8-byte Spill
-; CHECK-NEXT: tbz w19, #0, LBB0_2
+; CHECK-NEXT: tbz w28, #0, LBB0_2
; CHECK-NEXT: ; %bb.7: ; %bb14
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: mov x0, xzr
diff --git a/llvm/test/CodeGen/AArch64/late-taildup-computed-goto.ll b/llvm/test/CodeGen/AArch64/late-taildup-computed-goto.ll
index 381904f776604..16f771f4e6655 100644
--- a/llvm/test/CodeGen/AArch64/late-taildup-computed-goto.ll
+++ b/llvm/test/CodeGen/AArch64/late-taildup-computed-goto.ll
@@ -25,21 +25,20 @@ define void @test_interp(ptr %frame, ptr %dst) {
; CHECK-NEXT: adrp x21, _opcode.targets at PAGE
; CHECK-NEXT: Lloh1:
; CHECK-NEXT: add x21, x21, _opcode.targets at PAGEOFF
-; CHECK-NEXT: mov x24, xzr
+; CHECK-NEXT: mov x23, xzr
; CHECK-NEXT: add x8, x21, xzr, lsl #3
; CHECK-NEXT: mov x19, x1
; CHECK-NEXT: mov x20, x0
-; CHECK-NEXT: mov x23, xzr
-; CHECK-NEXT: mov w22, #1 ; =0x1
-; CHECK-NEXT: add x24, x24, #1
+; CHECK-NEXT: mov x22, xzr
+; CHECK-NEXT: add x23, x23, #1
; CHECK-NEXT: br x8
; CHECK-NEXT: Ltmp0: ; Block address taken
; CHECK-NEXT: LBB0_1: ; %loop.header
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: add x8, x21, x24, lsl #3
+; CHECK-NEXT: add x8, x21, x23, lsl #3
; CHECK-NEXT: mov x20, xzr
-; CHECK-NEXT: mov x23, xzr
-; CHECK-NEXT: add x24, x24, #1
+; CHECK-NEXT: mov x22, xzr
+; CHECK-NEXT: add x23, x23, #1
; CHECK-NEXT: br x8
; CHECK-NEXT: Ltmp1: ; Block address taken
; CHECK-NEXT: LBB0_2: ; %op1.bb
@@ -48,35 +47,36 @@ define void @test_interp(ptr %frame, ptr %dst) {
; CHECK-NEXT: LBB0_3: ; %op6.bb
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr x0, [x20, #-8]!
+; CHECK-NEXT: mov w9, #1 ; =0x1
; CHECK-NEXT: ldr x8, [x0, #8]
-; CHECK-NEXT: str x22, [x0]
+; CHECK-NEXT: str x9, [x0]
; CHECK-NEXT: ldr x8, [x8, #48]
; CHECK-NEXT: blr x8
-; CHECK-NEXT: add x8, x21, x24, lsl #3
-; CHECK-NEXT: add x24, x24, #1
+; CHECK-NEXT: add x8, x21, x23, lsl #3
+; CHECK-NEXT: add x23, x23, #1
; CHECK-NEXT: br x8
; CHECK-NEXT: Ltmp3: ; Block address taken
; CHECK-NEXT: LBB0_4: ; %op2.bb
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: add x8, x21, x24, lsl #3
+; CHECK-NEXT: add x8, x21, x23, lsl #3
; CHECK-NEXT: mov x20, xzr
-; CHECK-NEXT: str x23, [x19]
-; CHECK-NEXT: mov x23, xzr
-; CHECK-NEXT: add x24, x24, #1
+; CHECK-NEXT: str x22, [x19]
+; CHECK-NEXT: mov x22, xzr
+; CHECK-NEXT: add x23, x23, #1
; CHECK-NEXT: br x8
; CHECK-NEXT: Ltmp4: ; Block address taken
; CHECK-NEXT: LBB0_5: ; %op4.bb
; CHECK-NEXT: Ltmp5: ; Block address taken
; CHECK-NEXT: LBB0_6: ; %op5.bb
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: str x23, [x19]
-; CHECK-NEXT: ldur x8, [x23, #12]
+; CHECK-NEXT: str x22, [x19]
+; CHECK-NEXT: ldur x8, [x22, #12]
; CHECK-NEXT: ldur x9, [x20, #-8]
-; CHECK-NEXT: add x23, x23, #20
+; CHECK-NEXT: add x22, x22, #20
; CHECK-NEXT: stp x8, x9, [x20, #-8]
-; CHECK-NEXT: add x8, x21, x24, lsl #3
+; CHECK-NEXT: add x8, x21, x23, lsl #3
; CHECK-NEXT: add x20, x20, #8
-; CHECK-NEXT: add x24, x24, #1
+; CHECK-NEXT: add x23, x23, #1
; CHECK-NEXT: br x8
; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
entry:
diff --git a/llvm/test/CodeGen/AArch64/llvm.frexp.ll b/llvm/test/CodeGen/AArch64/llvm.frexp.ll
index 12534a1c0114a..a514fd01541b5 100644
--- a/llvm/test/CodeGen/AArch64/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AArch64/llvm.frexp.ll
@@ -85,21 +85,20 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov h1, v0.h[1]
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-NEXT: add x0, sp, #36
-; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT: add x19, sp, #36
+; CHECK-NEXT: add x0, sp, #44
+; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill
; CHECK-NEXT: fcvt s0, h1
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: add x0, sp, #32
+; CHECK-NEXT: add x0, sp, #40
; CHECK-NEXT: fcvt s1, h1
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-NEXT: fcvt h2, s0
-; CHECK-NEXT: add x0, sp, #40
+; CHECK-NEXT: add x0, sp, #56
; CHECK-NEXT: mov h1, v1.h[2]
; CHECK-NEXT: fcvt s0, h1
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
@@ -108,7 +107,7 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-NEXT: fcvt h2, s0
-; CHECK-NEXT: add x0, sp, #44
+; CHECK-NEXT: add x0, sp, #60
; CHECK-NEXT: mov h1, v1.h[3]
; CHECK-NEXT: fcvt s0, h1
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
@@ -116,10 +115,11 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind
; CHECK-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: fcvt h2, s0
-; CHECK-NEXT: ldr s1, [sp, #32]
+; CHECK-NEXT: ldr s1, [sp, #40]
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: ld1 { v1.s }[1], [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: add x8, sp, #44
+; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: mov v0.h[3], v2.h[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
@@ -132,21 +132,20 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind
; WINDOWS-NEXT: // kill: def $d0 killed $d0 def $q0
; WINDOWS-NEXT: mov h1, v0.h[1]
; WINDOWS-NEXT: str q0, [sp, #16] // 16-byte Spill
-; WINDOWS-NEXT: add x0, sp, #36
-; WINDOWS-NEXT: stp x19, x30, [sp, #48] // 16-byte Folded Spill
-; WINDOWS-NEXT: add x19, sp, #36
+; WINDOWS-NEXT: add x0, sp, #44
+; WINDOWS-NEXT: str x30, [sp, #48] // 8-byte Spill
; WINDOWS-NEXT: fcvt d0, h1
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; WINDOWS-NEXT: fcvt h0, d0
-; WINDOWS-NEXT: add x0, sp, #32
+; WINDOWS-NEXT: add x0, sp, #40
; WINDOWS-NEXT: fcvt d1, h1
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: fmov d0, d1
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; WINDOWS-NEXT: fcvt h2, d0
-; WINDOWS-NEXT: add x0, sp, #40
+; WINDOWS-NEXT: add x0, sp, #56
; WINDOWS-NEXT: mov h1, v1.h[2]
; WINDOWS-NEXT: fcvt d0, h1
; WINDOWS-NEXT: ldr q1, [sp] // 16-byte Reload
@@ -155,7 +154,7 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; WINDOWS-NEXT: fcvt h2, d0
-; WINDOWS-NEXT: add x0, sp, #44
+; WINDOWS-NEXT: add x0, sp, #60
; WINDOWS-NEXT: mov h1, v1.h[3]
; WINDOWS-NEXT: fcvt d0, h1
; WINDOWS-NEXT: ldr q1, [sp] // 16-byte Reload
@@ -163,10 +162,11 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind
; WINDOWS-NEXT: str q1, [sp] // 16-byte Spill
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: fcvt h2, d0
-; WINDOWS-NEXT: ldr s1, [sp, #32]
+; WINDOWS-NEXT: ldr s1, [sp, #40]
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
-; WINDOWS-NEXT: ld1 { v1.s }[1], [x19]
-; WINDOWS-NEXT: ldp x19, x30, [sp, #48] // 16-byte Folded Reload
+; WINDOWS-NEXT: add x8, sp, #44
+; WINDOWS-NEXT: ldr x30, [sp, #48] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v1.s }[1], [x8]
; WINDOWS-NEXT: // kill: def $d1 killed $d1 killed $q1
; WINDOWS-NEXT: mov v0.h[3], v2.h[0]
; WINDOWS-NEXT: // kill: def $d0 killed $d0 killed $q0
@@ -270,46 +270,46 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) nounwind
define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) nounwind {
; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: add x0, sp, #24
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: add x0, sp, #28
-; CHECK-NEXT: add x19, sp, #28
; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: fcvt s0, h0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr s0, [sp, #24]
-; CHECK-NEXT: ld1 { v0.s }[1], [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: add x8, sp, #28
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ld1 { v0.s }[1], [x8]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #48
+; WINDOWS-NEXT: sub sp, sp, #32
; WINDOWS-NEXT: // kill: def $d0 killed $d0 def $q0
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: add x0, sp, #24
; WINDOWS-NEXT: fcvt d0, h0
-; WINDOWS-NEXT: stp x19, x30, [sp, #32] // 16-byte Folded Spill
+; WINDOWS-NEXT: str x30, [sp, #16] // 8-byte Spill
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
; WINDOWS-NEXT: add x0, sp, #28
-; WINDOWS-NEXT: add x19, sp, #28
; WINDOWS-NEXT: mov h0, v0.h[1]
; WINDOWS-NEXT: fcvt d0, h0
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr s0, [sp, #24]
-; WINDOWS-NEXT: ld1 { v0.s }[1], [x19]
-; WINDOWS-NEXT: ldp x19, x30, [sp, #32] // 16-byte Folded Reload
+; WINDOWS-NEXT: add x8, sp, #28
+; WINDOWS-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v0.s }[1], [x8]
; WINDOWS-NEXT: // kill: def $d0 killed $d0 killed $q0
-; WINDOWS-NEXT: add sp, sp, #48
+; WINDOWS-NEXT: add sp, sp, #32
; WINDOWS-NEXT: ret
%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
%result.1 = extractvalue { <2 x half>, <2 x i32> } %result, 1
@@ -319,13 +319,11 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) nounwind {
define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_frexp_v3f32_v3i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: add x0, sp, #56
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill
-; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: add x19, sp, #56
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
@@ -336,45 +334,42 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) nounwi
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: add x0, sp, #60
-; CHECK-NEXT: add x20, sp, #60
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr s1, [sp, #44]
+; CHECK-NEXT: add x8, sp, #56
; CHECK-NEXT: ldr q2, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload
-; CHECK-NEXT: ld1 { v1.s }[1], [x19]
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-NEXT: mov v2.s[2], v0.s[0]
-; CHECK-NEXT: ld1 { v1.s }[2], [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add x8, sp, #60
+; CHECK-NEXT: ld1 { v1.s }[2], [x8]
; CHECK-NEXT: mov v0.16b, v2.16b
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v3f32_v3i32:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #80
+; WINDOWS-NEXT: sub sp, sp, #64
; WINDOWS-NEXT: mov s1, v0.s[1]
; WINDOWS-NEXT: str q0, [sp, #16] // 16-byte Spill
-; WINDOWS-NEXT: add x0, sp, #36
-; WINDOWS-NEXT: stp x19, x20, [sp, #48] // 16-byte Folded Spill
-; WINDOWS-NEXT: add x19, sp, #36
-; WINDOWS-NEXT: stp x21, x30, [sp, #64] // 16-byte Folded Spill
+; WINDOWS-NEXT: add x0, sp, #44
+; WINDOWS-NEXT: str x30, [sp, #48] // 8-byte Spill
; WINDOWS-NEXT: fcvt d0, s1
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: fcvt s0, d0
-; WINDOWS-NEXT: add x0, sp, #32
+; WINDOWS-NEXT: add x0, sp, #40
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: fcvt s0, d0
; WINDOWS-NEXT: ldr q1, [sp] // 16-byte Reload
-; WINDOWS-NEXT: add x0, sp, #40
-; WINDOWS-NEXT: add x20, sp, #40
+; WINDOWS-NEXT: add x0, sp, #56
; WINDOWS-NEXT: mov v0.s[1], v1.s[0]
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: ldr q0, [sp, #16] // 16-byte Reload
@@ -383,24 +378,25 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) nounwi
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: fcvt s0, d0
; WINDOWS-NEXT: ldr q1, [sp] // 16-byte Reload
-; WINDOWS-NEXT: add x0, sp, #44
-; WINDOWS-NEXT: add x21, sp, #44
+; WINDOWS-NEXT: add x0, sp, #60
; WINDOWS-NEXT: mov v1.s[2], v0.s[0]
; WINDOWS-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; WINDOWS-NEXT: mov s0, v0.s[3]
; WINDOWS-NEXT: str q1, [sp] // 16-byte Spill
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
-; WINDOWS-NEXT: ldr s1, [sp, #32]
+; WINDOWS-NEXT: ldr s1, [sp, #40]
+; WINDOWS-NEXT: add x8, sp, #44
; WINDOWS-NEXT: fcvt s2, d0
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
-; WINDOWS-NEXT: ld1 { v1.s }[1], [x19]
+; WINDOWS-NEXT: ldr x30, [sp, #48] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v1.s }[1], [x8]
+; WINDOWS-NEXT: add x8, sp, #56
; WINDOWS-NEXT: mov v0.s[3], v2.s[0]
-; WINDOWS-NEXT: ld1 { v1.s }[2], [x20]
-; WINDOWS-NEXT: ldp x19, x20, [sp, #48] // 16-byte Folded Reload
-; WINDOWS-NEXT: ld1 { v1.s }[3], [x21]
-; WINDOWS-NEXT: ldp x21, x30, [sp, #64] // 16-byte Folded Reload
-; WINDOWS-NEXT: add sp, sp, #80
+; WINDOWS-NEXT: ld1 { v1.s }[2], [x8]
+; WINDOWS-NEXT: add x8, sp, #60
+; WINDOWS-NEXT: ld1 { v1.s }[3], [x8]
+; WINDOWS-NEXT: add sp, sp, #64
; WINDOWS-NEXT: ret
%result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3f32.v3i32(<3 x float> %a)
ret { <3 x float>, <3 x i32> } %result
@@ -504,13 +500,12 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind {
define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) nounwind {
; CHECK-LABEL: test_frexp_v2f32_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #64
+; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: add x0, sp, #40
; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT: add x19, sp, #40
+; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
@@ -521,23 +516,23 @@ define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) nounwi
; CHECK-NEXT: ldr s1, [sp, #44]
; CHECK-NEXT: ldr q2, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-NEXT: ld1 { v1.s }[1], [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: add x8, sp, #40
+; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v0.s[1], v2.s[0]
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: add sp, sp, #64
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v2f32_v2i32:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #48
+; WINDOWS-NEXT: sub sp, sp, #32
; WINDOWS-NEXT: // kill: def $d0 killed $d0 def $q0
; WINDOWS-NEXT: mov s1, v0.s[1]
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: add x0, sp, #28
-; WINDOWS-NEXT: stp x19, x30, [sp, #32] // 16-byte Folded Spill
-; WINDOWS-NEXT: add x19, sp, #28
+; WINDOWS-NEXT: str x30, [sp, #16] // 8-byte Spill
; WINDOWS-NEXT: fcvt d0, s1
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q1, [sp] // 16-byte Reload
@@ -550,12 +545,13 @@ define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) nounwi
; WINDOWS-NEXT: fcvt s0, d0
; WINDOWS-NEXT: ldr s1, [sp, #24]
; WINDOWS-NEXT: ldr q2, [sp] // 16-byte Reload
-; WINDOWS-NEXT: ld1 { v1.s }[1], [x19]
-; WINDOWS-NEXT: ldp x19, x30, [sp, #32] // 16-byte Folded Reload
+; WINDOWS-NEXT: add x8, sp, #28
+; WINDOWS-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v1.s }[1], [x8]
; WINDOWS-NEXT: // kill: def $d1 killed $d1 killed $q1
; WINDOWS-NEXT: mov v0.s[1], v2.s[0]
; WINDOWS-NEXT: // kill: def $d0 killed $d0 killed $q0
-; WINDOWS-NEXT: add sp, sp, #48
+; WINDOWS-NEXT: add sp, sp, #32
; WINDOWS-NEXT: ret
%result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
ret { <2 x float>, <2 x i32> } %result
@@ -617,45 +613,45 @@ define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) nounwi
define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) nounwind {
; CHECK-LABEL: test_frexp_v2f32_v2i32_only_use_exp:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: add x0, sp, #28
-; CHECK-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: add x0, sp, #24
-; CHECK-NEXT: add x19, sp, #24
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr s0, [sp, #28]
-; CHECK-NEXT: ld1 { v0.s }[1], [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ld1 { v0.s }[1], [x8]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v2f32_v2i32_only_use_exp:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #48
+; WINDOWS-NEXT: sub sp, sp, #32
; WINDOWS-NEXT: // kill: def $d0 killed $d0 def $q0
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: add x0, sp, #24
; WINDOWS-NEXT: fcvt d0, s0
-; WINDOWS-NEXT: stp x19, x30, [sp, #32] // 16-byte Folded Spill
+; WINDOWS-NEXT: str x30, [sp, #16] // 8-byte Spill
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
; WINDOWS-NEXT: add x0, sp, #28
-; WINDOWS-NEXT: add x19, sp, #28
; WINDOWS-NEXT: mov s0, v0.s[1]
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr s0, [sp, #24]
-; WINDOWS-NEXT: ld1 { v0.s }[1], [x19]
-; WINDOWS-NEXT: ldp x19, x30, [sp, #32] // 16-byte Folded Reload
+; WINDOWS-NEXT: add x8, sp, #28
+; WINDOWS-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v0.s }[1], [x8]
; WINDOWS-NEXT: // kill: def $d0 killed $d0 killed $q0
-; WINDOWS-NEXT: add sp, sp, #48
+; WINDOWS-NEXT: add sp, sp, #32
; WINDOWS-NEXT: ret
%result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
%result.1 = extractvalue { <2 x float>, <2 x i32> } %result, 1
@@ -665,24 +661,21 @@ define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) nounwind {
define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwind {
; CHECK-LABEL: test_frexp_v4f32_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: add x0, sp, #40
-; CHECK-NEXT: stp x30, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: add x19, sp, #40
+; CHECK-NEXT: add x0, sp, #56
+; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-NEXT: add x0, sp, #44
+; CHECK-NEXT: add x0, sp, #60
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-NEXT: add x0, sp, #36
-; CHECK-NEXT: add x20, sp, #36
+; CHECK-NEXT: add x0, sp, #44
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
@@ -690,48 +683,46 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-NEXT: add x0, sp, #32
-; CHECK-NEXT: add x21, sp, #32
+; CHECK-NEXT: add x0, sp, #40
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-NEXT: bl frexpf
+; CHECK-NEXT: ldr s1, [sp, #60]
+; CHECK-NEXT: add x8, sp, #44
; CHECK-NEXT: ldr q3, [sp] // 16-byte Reload
-; CHECK-NEXT: ldr s1, [sp, #44]
+; CHECK-NEXT: ldr s2, [x8]
+; CHECK-NEXT: add x8, sp, #56
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-NEXT: ldr s2, [x20]
+; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
+; CHECK-NEXT: add x8, sp, #40
; CHECK-NEXT: mov v3.s[3], v0.s[0]
-; CHECK-NEXT: ld1 { v1.s }[1], [x19]
-; CHECK-NEXT: ld1 { v2.s }[1], [x21]
-; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-NEXT: ldp x30, x21, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ld1 { v2.s }[1], [x8]
; CHECK-NEXT: zip1 v1.2d, v1.2d, v2.2d
; CHECK-NEXT: mov v0.16b, v3.16b
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v4f32_v4i32:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #80
+; WINDOWS-NEXT: sub sp, sp, #64
; WINDOWS-NEXT: mov s1, v0.s[1]
; WINDOWS-NEXT: str q0, [sp, #16] // 16-byte Spill
-; WINDOWS-NEXT: add x0, sp, #36
-; WINDOWS-NEXT: stp x19, x20, [sp, #48] // 16-byte Folded Spill
-; WINDOWS-NEXT: add x19, sp, #36
-; WINDOWS-NEXT: stp x21, x30, [sp, #64] // 16-byte Folded Spill
+; WINDOWS-NEXT: add x0, sp, #44
+; WINDOWS-NEXT: str x30, [sp, #48] // 8-byte Spill
; WINDOWS-NEXT: fcvt d0, s1
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: fcvt s0, d0
-; WINDOWS-NEXT: add x0, sp, #32
+; WINDOWS-NEXT: add x0, sp, #40
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: fcvt s0, d0
; WINDOWS-NEXT: ldr q1, [sp] // 16-byte Reload
-; WINDOWS-NEXT: add x0, sp, #40
-; WINDOWS-NEXT: add x20, sp, #40
+; WINDOWS-NEXT: add x0, sp, #56
; WINDOWS-NEXT: mov v0.s[1], v1.s[0]
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: ldr q0, [sp, #16] // 16-byte Reload
@@ -740,24 +731,25 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: fcvt s0, d0
; WINDOWS-NEXT: ldr q1, [sp] // 16-byte Reload
-; WINDOWS-NEXT: add x0, sp, #44
-; WINDOWS-NEXT: add x21, sp, #44
+; WINDOWS-NEXT: add x0, sp, #60
; WINDOWS-NEXT: mov v1.s[2], v0.s[0]
; WINDOWS-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; WINDOWS-NEXT: mov s0, v0.s[3]
; WINDOWS-NEXT: str q1, [sp] // 16-byte Spill
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
-; WINDOWS-NEXT: ldr s1, [sp, #32]
+; WINDOWS-NEXT: ldr s1, [sp, #40]
+; WINDOWS-NEXT: add x8, sp, #44
; WINDOWS-NEXT: fcvt s2, d0
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
-; WINDOWS-NEXT: ld1 { v1.s }[1], [x19]
+; WINDOWS-NEXT: ldr x30, [sp, #48] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v1.s }[1], [x8]
+; WINDOWS-NEXT: add x8, sp, #56
; WINDOWS-NEXT: mov v0.s[3], v2.s[0]
-; WINDOWS-NEXT: ld1 { v1.s }[2], [x20]
-; WINDOWS-NEXT: ldp x19, x20, [sp, #48] // 16-byte Folded Reload
-; WINDOWS-NEXT: ld1 { v1.s }[3], [x21]
-; WINDOWS-NEXT: ldp x21, x30, [sp, #64] // 16-byte Folded Reload
-; WINDOWS-NEXT: add sp, sp, #80
+; WINDOWS-NEXT: ld1 { v1.s }[2], [x8]
+; WINDOWS-NEXT: add x8, sp, #60
+; WINDOWS-NEXT: ld1 { v1.s }[3], [x8]
+; WINDOWS-NEXT: add sp, sp, #64
; WINDOWS-NEXT: ret
%result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
ret { <4 x float>, <4 x i32> } %result
@@ -849,72 +841,68 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi
define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind {
; CHECK-LABEL: test_frexp_v4f32_v4i32_only_use_exp:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #64
-; CHECK-NEXT: add x0, sp, #28
-; CHECK-NEXT: stp x30, x21, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: add x0, sp, #44
+; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: add x0, sp, #24
-; CHECK-NEXT: add x19, sp, #24
+; CHECK-NEXT: add x0, sp, #40
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: add x0, sp, #20
-; CHECK-NEXT: add x20, sp, #20
+; CHECK-NEXT: add x0, sp, #28
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: add x0, sp, #16
-; CHECK-NEXT: add x21, sp, #16
+; CHECK-NEXT: add x0, sp, #24
; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: bl frexpf
-; CHECK-NEXT: ldr s0, [sp, #28]
-; CHECK-NEXT: ldr s1, [x20]
-; CHECK-NEXT: ld1 { v0.s }[1], [x19]
-; CHECK-NEXT: ld1 { v1.s }[1], [x21]
-; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldr s0, [sp, #44]
+; CHECK-NEXT: add x8, sp, #28
+; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-NEXT: ldr s1, [x8]
+; CHECK-NEXT: add x8, sp, #40
+; CHECK-NEXT: ld1 { v0.s }[1], [x8]
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-NEXT: add sp, sp, #64
+; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v4f32_v4i32_only_use_exp:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #64
+; WINDOWS-NEXT: sub sp, sp, #48
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: fcvt d0, s0
-; WINDOWS-NEXT: add x0, sp, #16
-; WINDOWS-NEXT: stp x19, x20, [sp, #32] // 16-byte Folded Spill
-; WINDOWS-NEXT: stp x21, x30, [sp, #48] // 16-byte Folded Spill
+; WINDOWS-NEXT: add x0, sp, #24
+; WINDOWS-NEXT: str x30, [sp, #32] // 8-byte Spill
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
-; WINDOWS-NEXT: add x0, sp, #20
-; WINDOWS-NEXT: add x19, sp, #20
+; WINDOWS-NEXT: add x0, sp, #28
; WINDOWS-NEXT: mov s0, v0.s[1]
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
-; WINDOWS-NEXT: add x0, sp, #24
-; WINDOWS-NEXT: add x20, sp, #24
+; WINDOWS-NEXT: add x0, sp, #40
; WINDOWS-NEXT: mov s0, v0.s[2]
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
-; WINDOWS-NEXT: add x0, sp, #28
-; WINDOWS-NEXT: add x21, sp, #28
+; WINDOWS-NEXT: add x0, sp, #44
; WINDOWS-NEXT: mov s0, v0.s[3]
; WINDOWS-NEXT: fcvt d0, s0
; WINDOWS-NEXT: bl frexp
-; WINDOWS-NEXT: ldr s0, [sp, #16]
-; WINDOWS-NEXT: ld1 { v0.s }[1], [x19]
-; WINDOWS-NEXT: ld1 { v0.s }[2], [x20]
-; WINDOWS-NEXT: ldp x19, x20, [sp, #32] // 16-byte Folded Reload
-; WINDOWS-NEXT: ld1 { v0.s }[3], [x21]
-; WINDOWS-NEXT: ldp x21, x30, [sp, #48] // 16-byte Folded Reload
-; WINDOWS-NEXT: add sp, sp, #64
+; WINDOWS-NEXT: ldr s0, [sp, #24]
+; WINDOWS-NEXT: add x8, sp, #28
+; WINDOWS-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v0.s }[1], [x8]
+; WINDOWS-NEXT: add x8, sp, #40
+; WINDOWS-NEXT: ld1 { v0.s }[2], [x8]
+; WINDOWS-NEXT: add x8, sp, #44
+; WINDOWS-NEXT: ld1 { v0.s }[3], [x8]
+; WINDOWS-NEXT: add sp, sp, #48
; WINDOWS-NEXT: ret
%result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
%result.1 = extractvalue { <4 x float>, <4 x i32> } %result, 1
@@ -990,12 +978,11 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind {
define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) nounwind {
; CHECK-LABEL: test_frexp_v2f64_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #64
+; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: add x0, sp, #40
-; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT: add x19, sp, #40
+; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl frexp
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
@@ -1005,22 +992,22 @@ define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) noun
; CHECK-NEXT: bl frexp
; CHECK-NEXT: ldr s1, [sp, #44]
; CHECK-NEXT: ldr q2, [sp, #16] // 16-byte Reload
+; CHECK-NEXT: add x8, sp, #40
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: ld1 { v1.s }[1], [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-NEXT: mov v0.d[1], v2.d[0]
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: add sp, sp, #64
+; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v2f64_v2i32:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #64
+; WINDOWS-NEXT: sub sp, sp, #48
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: mov d0, v0.d[1]
; WINDOWS-NEXT: add x0, sp, #40
-; WINDOWS-NEXT: stp x19, x30, [sp, #48] // 16-byte Folded Spill
-; WINDOWS-NEXT: add x19, sp, #40
+; WINDOWS-NEXT: str x30, [sp, #32] // 8-byte Spill
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: // kill: def $d0 killed $d0 def $q0
; WINDOWS-NEXT: str q0, [sp, #16] // 16-byte Spill
@@ -1030,12 +1017,13 @@ define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) noun
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr s1, [sp, #44]
; WINDOWS-NEXT: ldr q2, [sp, #16] // 16-byte Reload
+; WINDOWS-NEXT: add x8, sp, #40
; WINDOWS-NEXT: // kill: def $d0 killed $d0 def $q0
-; WINDOWS-NEXT: ld1 { v1.s }[1], [x19]
-; WINDOWS-NEXT: ldp x19, x30, [sp, #48] // 16-byte Folded Reload
+; WINDOWS-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v1.s }[1], [x8]
; WINDOWS-NEXT: mov v0.d[1], v2.d[0]
; WINDOWS-NEXT: // kill: def $d1 killed $d1 killed $q1
-; WINDOWS-NEXT: add sp, sp, #64
+; WINDOWS-NEXT: add sp, sp, #48
; WINDOWS-NEXT: ret
%result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
ret { <2 x double>, <2 x i32> } %result
@@ -1091,42 +1079,42 @@ define <2 x double> @test_frexp_v2f64_v2i32_only_use_fract(<2 x double> %a) noun
define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) nounwind {
; CHECK-LABEL: test_frexp_v2f64_v2i32_only_use_exp:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: add x0, sp, #28
-; CHECK-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: bl frexp
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: add x0, sp, #24
-; CHECK-NEXT: add x19, sp, #24
; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: bl frexp
; CHECK-NEXT: ldr s0, [sp, #28]
-; CHECK-NEXT: ld1 { v0.s }[1], [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ld1 { v0.s }[1], [x8]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
;
; WINDOWS-LABEL: test_frexp_v2f64_v2i32_only_use_exp:
; WINDOWS: // %bb.0:
-; WINDOWS-NEXT: sub sp, sp, #48
+; WINDOWS-NEXT: sub sp, sp, #32
; WINDOWS-NEXT: add x0, sp, #28
-; WINDOWS-NEXT: stp x19, x30, [sp, #32] // 16-byte Folded Spill
+; WINDOWS-NEXT: str x30, [sp, #16] // 8-byte Spill
; WINDOWS-NEXT: str q0, [sp] // 16-byte Spill
; WINDOWS-NEXT: // kill: def $d0 killed $d0 killed $q0
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr q0, [sp] // 16-byte Reload
; WINDOWS-NEXT: add x0, sp, #24
-; WINDOWS-NEXT: add x19, sp, #24
; WINDOWS-NEXT: mov d0, v0.d[1]
; WINDOWS-NEXT: bl frexp
; WINDOWS-NEXT: ldr s0, [sp, #28]
-; WINDOWS-NEXT: ld1 { v0.s }[1], [x19]
-; WINDOWS-NEXT: ldp x19, x30, [sp, #32] // 16-byte Folded Reload
+; WINDOWS-NEXT: add x8, sp, #24
+; WINDOWS-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; WINDOWS-NEXT: ld1 { v0.s }[1], [x8]
; WINDOWS-NEXT: // kill: def $d0 killed $d0 killed $q0
-; WINDOWS-NEXT: add sp, sp, #48
+; WINDOWS-NEXT: add sp, sp, #32
; WINDOWS-NEXT: ret
%result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
%result.1 = extractvalue { <2 x double>, <2 x i32> } %result, 1
diff --git a/llvm/test/CodeGen/AArch64/llvm.modf.ll b/llvm/test/CodeGen/AArch64/llvm.modf.ll
index e9544375adc09..e199c1f57d8df 100644
--- a/llvm/test/CodeGen/AArch64/llvm.modf.ll
+++ b/llvm/test/CodeGen/AArch64/llvm.modf.ll
@@ -167,17 +167,13 @@ define { float, float } @test_modf_f32(float %a) {
define { <3 x float>, <3 x float> } @test_modf_v3f32(<3 x float> %a) {
; CHECK-SD-LABEL: test_modf_v3f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #80
+; CHECK-SD-NEXT: sub sp, sp, #64
; CHECK-SD-NEXT: str x30, [sp, #48] // 8-byte Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 80
-; CHECK-SD-NEXT: .cfi_offset w19, -8
-; CHECK-SD-NEXT: .cfi_offset w20, -16
-; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
+; CHECK-SD-NEXT: .cfi_offset w30, -16
; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-SD-NEXT: mov s0, v0.s[1]
; CHECK-SD-NEXT: add x0, sp, #56
-; CHECK-SD-NEXT: add x19, sp, #56
; CHECK-SD-NEXT: bl modff
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
@@ -188,63 +184,62 @@ define { <3 x float>, <3 x float> } @test_modf_v3f32(<3 x float> %a) {
; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-SD-NEXT: add x0, sp, #60
-; CHECK-SD-NEXT: add x20, sp, #60
; CHECK-SD-NEXT: mov v0.s[1], v1.s[0]
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-SD-NEXT: mov s0, v0.s[2]
; CHECK-SD-NEXT: bl modff
; CHECK-SD-NEXT: ldr s1, [sp, #44]
+; CHECK-SD-NEXT: add x8, sp, #56
; CHECK-SD-NEXT: ldr q2, [sp] // 16-byte Reload
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-SD-NEXT: ldr x30, [sp, #48] // 8-byte Reload
-; CHECK-SD-NEXT: ld1 { v1.s }[1], [x19]
+; CHECK-SD-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-SD-NEXT: mov v2.s[2], v0.s[0]
-; CHECK-SD-NEXT: ld1 { v1.s }[2], [x20]
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-SD-NEXT: add x8, sp, #60
+; CHECK-SD-NEXT: ld1 { v1.s }[2], [x8]
; CHECK-SD-NEXT: mov v0.16b, v2.16b
-; CHECK-SD-NEXT: add sp, sp, #80
+; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_modf_v3f32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #112
; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
-; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: .cfi_offset b8, -24
; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: add x0, sp, #68
+; CHECK-GI-NEXT: add x0, sp, #76
; CHECK-GI-NEXT: mov s8, v0.s[1]
; CHECK-GI-NEXT: mov s9, v0.s[2]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-GI-NEXT: bl modff
-; CHECK-GI-NEXT: ldr s1, [sp, #68]
+; CHECK-GI-NEXT: ldr s1, [sp, #76]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-GI-NEXT: add x0, sp, #72
+; CHECK-GI-NEXT: add x0, sp, #104
; CHECK-GI-NEXT: stp q0, q1, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: fmov s0, s8
; CHECK-GI-NEXT: bl modff
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: add x0, sp, #76
-; CHECK-GI-NEXT: add x19, sp, #76
-; CHECK-GI-NEXT: ldr s0, [sp, #72]
+; CHECK-GI-NEXT: add x0, sp, #108
+; CHECK-GI-NEXT: ldr s0, [sp, #104]
; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: fmov s0, s9
; CHECK-GI-NEXT: bl modff
; CHECK-GI-NEXT: ldp q3, q2, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-GI-NEXT: add x8, sp, #108
; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: mov v2.s[1], v1.s[0]
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov v1.s[1], v3.s[0]
; CHECK-GI-NEXT: mov v2.s[2], v0.s[0]
-; CHECK-GI-NEXT: ld1 { v1.s }[2], [x19]
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ld1 { v1.s }[2], [x8]
; CHECK-GI-NEXT: mov v0.16b, v2.16b
; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
@@ -255,15 +250,13 @@ define { <3 x float>, <3 x float> } @test_modf_v3f32(<3 x float> %a) {
define { <2 x float>, <2 x float> } @test_modf_v2f32(<2 x float> %a) {
; CHECK-SD-LABEL: test_modf_v2f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #64
-; CHECK-SD-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
-; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
; CHECK-SD-NEXT: .cfi_offset w30, -16
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-SD-NEXT: add x0, sp, #40
-; CHECK-SD-NEXT: add x19, sp, #40
; CHECK-SD-NEXT: mov s0, v0.s[1]
; CHECK-SD-NEXT: bl modff
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0
@@ -275,23 +268,23 @@ define { <2 x float>, <2 x float> } @test_modf_v2f32(<2 x float> %a) {
; CHECK-SD-NEXT: ldr s1, [sp, #44]
; CHECK-SD-NEXT: ldr q2, [sp, #16] // 16-byte Reload
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-SD-NEXT: ld1 { v1.s }[1], [x19]
-; CHECK-SD-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-SD-NEXT: add x8, sp, #40
+; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-SD-NEXT: mov v0.s[1], v2.s[0]
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-SD-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: add sp, sp, #64
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-SD-NEXT: add sp, sp, #48
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_modf_v2f32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #64
-; CHECK-GI-NEXT: str d8, [sp, #32] // 8-byte Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
+; CHECK-GI-NEXT: str x30, [sp, #56] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
-; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset b8, -16
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: add x0, sp, #40
; CHECK-GI-NEXT: mov s8, v0.s[1]
@@ -300,17 +293,17 @@ define { <2 x float>, <2 x float> } @test_modf_v2f32(<2 x float> %a) {
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: add x0, sp, #44
-; CHECK-GI-NEXT: add x19, sp, #44
; CHECK-GI-NEXT: ldr s0, [sp, #40]
; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: fmov s0, s8
; CHECK-GI-NEXT: bl modff
; CHECK-GI-NEXT: ldp q2, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-GI-NEXT: ldr d8, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: add x8, sp, #44
+; CHECK-GI-NEXT: ldr x30, [sp, #56] // 8-byte Reload
+; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
; CHECK-GI-NEXT: mov v2.s[1], v0.s[0]
-; CHECK-GI-NEXT: ld1 { v1.s }[1], [x19]
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-GI-NEXT: fmov d0, d2
; CHECK-GI-NEXT: add sp, sp, #64
@@ -338,59 +331,57 @@ define { <2 x double>, <2 x double> } @test_modf_v2f64(<2 x double> %a) {
; CHECK-SD-LABEL: test_modf_v2f64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sub sp, sp, #64
-; CHECK-SD-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-SD-NEXT: str x30, [sp, #48] // 8-byte Spill
; CHECK-SD-NEXT: .cfi_def_cfa_offset 64
-; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w30, -16
; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-SD-NEXT: mov d0, v0.d[1]
-; CHECK-SD-NEXT: add x0, sp, #32
-; CHECK-SD-NEXT: add x19, sp, #32
+; CHECK-SD-NEXT: add x0, sp, #40
; CHECK-SD-NEXT: bl modf
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-SD-NEXT: add x0, sp, #40
+; CHECK-SD-NEXT: add x0, sp, #56
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: bl modf
-; CHECK-SD-NEXT: ldr d1, [sp, #40]
+; CHECK-SD-NEXT: ldr d1, [sp, #56]
+; CHECK-SD-NEXT: add x8, sp, #40
; CHECK-SD-NEXT: ldr q2, [sp, #16] // 16-byte Reload
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: ld1 { v1.d }[1], [x19]
-; CHECK-SD-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldr x30, [sp, #48] // 8-byte Reload
+; CHECK-SD-NEXT: ld1 { v1.d }[1], [x8]
; CHECK-SD-NEXT: mov v0.d[1], v2.d[0]
; CHECK-SD-NEXT: add sp, sp, #64
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_modf_v2f64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: sub sp, sp, #64
; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
-; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -32
-; CHECK-GI-NEXT: add x0, sp, #40
+; CHECK-GI-NEXT: str x30, [sp, #56] // 8-byte Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset b8, -16
+; CHECK-GI-NEXT: add x0, sp, #32
; CHECK-GI-NEXT: mov d8, v0.d[1]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: bl modf
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: add x0, sp, #56
-; CHECK-GI-NEXT: add x19, sp, #56
-; CHECK-GI-NEXT: ldr d0, [sp, #40]
+; CHECK-GI-NEXT: add x0, sp, #40
+; CHECK-GI-NEXT: ldr d0, [sp, #32]
; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: fmov d0, d8
; CHECK-GI-NEXT: bl modf
; CHECK-GI-NEXT: ldp q2, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: add x8, sp, #40
+; CHECK-GI-NEXT: ldr x30, [sp, #56] // 8-byte Reload
; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
; CHECK-GI-NEXT: mov v2.d[1], v0.d[0]
-; CHECK-GI-NEXT: ld1 { v1.d }[1], [x19]
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ld1 { v1.d }[1], [x8]
; CHECK-GI-NEXT: mov v0.16b, v2.16b
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%result = call { <2 x double>, <2 x double> } @llvm.modf.v2f64(<2 x double> %a)
ret { <2 x double>, <2 x double> } %result
diff --git a/llvm/test/CodeGen/AArch64/llvm.sincos.ll b/llvm/test/CodeGen/AArch64/llvm.sincos.ll
index bb549496c7a4f..daec97b9ea63f 100644
--- a/llvm/test/CodeGen/AArch64/llvm.sincos.ll
+++ b/llvm/test/CodeGen/AArch64/llvm.sincos.ll
@@ -374,38 +374,34 @@ define { float, float } @test_sincos_f32(float %a) nounwind {
define { <3 x float>, <3 x float> } @test_sincos_v3f32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_sincos_v3f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: add x0, sp, #20
; CHECK-NEXT: add x1, sp, #16
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
-; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sincosf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: add x0, sp, #28
; CHECK-NEXT: add x1, sp, #24
-; CHECK-NEXT: add x19, sp, #28
-; CHECK-NEXT: add x20, sp, #24
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: bl sincosf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: add x0, sp, #44
; CHECK-NEXT: add x1, sp, #40
-; CHECK-NEXT: add x21, sp, #44
-; CHECK-NEXT: add x22, sp, #40
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl sincosf
; CHECK-NEXT: ldp s1, s0, [sp, #16]
+; CHECK-NEXT: add x8, sp, #28
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-NEXT: ld1 { v0.s }[1], [x19]
-; CHECK-NEXT: ld1 { v1.s }[1], [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-NEXT: ld1 { v0.s }[2], [x21]
-; CHECK-NEXT: ld1 { v1.s }[2], [x22]
-; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ld1 { v0.s }[1], [x8]
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
+; CHECK-NEXT: add x8, sp, #44
+; CHECK-NEXT: ld1 { v0.s }[2], [x8]
+; CHECK-NEXT: add x8, sp, #40
+; CHECK-NEXT: ld1 { v1.s }[2], [x8]
+; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
;
; NO-LIBCALL-LABEL: test_sincos_v3f32:
@@ -461,30 +457,28 @@ define { <3 x float>, <3 x float> } @test_sincos_v3f32(<3 x float> %a) nounwind
define { <2 x float>, <2 x float> } @test_sincos_v2f32(<2 x float> %a) nounwind {
; CHECK-LABEL: test_sincos_v2f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #64
+; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: add x0, sp, #44
; CHECK-NEXT: add x1, sp, #40
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
-; CHECK-NEXT: stp x20, x19, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sincosf
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: add x0, sp, #28
; CHECK-NEXT: add x1, sp, #24
-; CHECK-NEXT: add x19, sp, #28
-; CHECK-NEXT: add x20, sp, #24
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: bl sincosf
; CHECK-NEXT: ldp s1, s0, [sp, #40]
+; CHECK-NEXT: add x8, sp, #28
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-NEXT: ld1 { v0.s }[1], [x19]
-; CHECK-NEXT: ld1 { v1.s }[1], [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ld1 { v0.s }[1], [x8]
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: ld1 { v1.s }[1], [x8]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: add sp, sp, #64
+; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
;
; NO-LIBCALL-LABEL: test_sincos_v2f32:
@@ -561,28 +555,26 @@ define { double, double } @test_sincos_f64(double %a) nounwind {
define { <2 x double>, <2 x double> } @test_sincos_v2f64(<2 x double> %a) nounwind {
; CHECK-LABEL: test_sincos_v2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: add x0, sp, #56
; CHECK-NEXT: add x1, sp, #40
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill
-; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: bl sincos
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: add x0, sp, #32
; CHECK-NEXT: add x1, sp, #24
-; CHECK-NEXT: add x19, sp, #32
-; CHECK-NEXT: add x20, sp, #24
; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: bl sincos
; CHECK-NEXT: ldr d0, [sp, #56]
; CHECK-NEXT: ldr d1, [sp, #40]
+; CHECK-NEXT: add x8, sp, #32
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload
-; CHECK-NEXT: ld1 { v0.d }[1], [x19]
-; CHECK-NEXT: ld1 { v1.d }[1], [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ld1 { v0.d }[1], [x8]
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: ld1 { v1.d }[1], [x8]
+; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret
;
; NO-LIBCALL-LABEL: test_sincos_v2f64:
diff --git a/llvm/test/CodeGen/AArch64/llvm.sincospi.ll b/llvm/test/CodeGen/AArch64/llvm.sincospi.ll
index 6d2288b06acce..b991ffc921363 100644
--- a/llvm/test/CodeGen/AArch64/llvm.sincospi.ll
+++ b/llvm/test/CodeGen/AArch64/llvm.sincospi.ll
@@ -133,38 +133,34 @@ define { float, float } @test_sincospi_f32(float %a) #0 {
define { <3 x float>, <3 x float> } @test_sincospi_v3f32(<3 x float> %a) #0 {
; CHECK-LABEL: test_sincospi_v3f32:
; CHECK: ; %bb.0:
-; CHECK-NEXT: sub sp, sp, #96
+; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: add x0, sp, #28
; CHECK-NEXT: add x1, sp, #24
-; CHECK-NEXT: stp x22, x21, [sp, #48] ; 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #64] ; 16-byte Folded Spill
-; CHECK-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
; CHECK-NEXT: str q0, [sp] ; 16-byte Spill
; CHECK-NEXT: ; kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl ___sincospif
; CHECK-NEXT: ldr q0, [sp] ; 16-byte Reload
; CHECK-NEXT: add x0, sp, #36
; CHECK-NEXT: add x1, sp, #32
-; CHECK-NEXT: add x19, sp, #36
-; CHECK-NEXT: add x20, sp, #32
; CHECK-NEXT: mov s0, v0[1]
; CHECK-NEXT: bl ___sincospif
; CHECK-NEXT: ldr q0, [sp] ; 16-byte Reload
; CHECK-NEXT: add x0, sp, #44
; CHECK-NEXT: add x1, sp, #40
-; CHECK-NEXT: add x21, sp, #44
-; CHECK-NEXT: add x22, sp, #40
; CHECK-NEXT: mov s0, v0[2]
; CHECK-NEXT: bl ___sincospif
; CHECK-NEXT: ldp s1, s0, [sp, #24]
-; CHECK-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
-; CHECK-NEXT: ld1.s { v0 }[1], [x19]
-; CHECK-NEXT: ld1.s { v1 }[1], [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
-; CHECK-NEXT: ld1.s { v0 }[2], [x21]
-; CHECK-NEXT: ld1.s { v1 }[2], [x22]
-; CHECK-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #96
+; CHECK-NEXT: add x8, sp, #36
+; CHECK-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-NEXT: ld1.s { v0 }[1], [x8]
+; CHECK-NEXT: add x8, sp, #32
+; CHECK-NEXT: ld1.s { v1 }[1], [x8]
+; CHECK-NEXT: add x8, sp, #44
+; CHECK-NEXT: ld1.s { v0 }[2], [x8]
+; CHECK-NEXT: add x8, sp, #40
+; CHECK-NEXT: ld1.s { v1 }[2], [x8]
+; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret
%result = call { <3 x float>, <3 x float> } @llvm.sincospi.v3f32(<3 x float> %a)
ret { <3 x float>, <3 x float> } %result
@@ -173,30 +169,28 @@ define { <3 x float>, <3 x float> } @test_sincospi_v3f32(<3 x float> %a) #0 {
define { <2 x float>, <2 x float> } @test_sincospi_v2f32(<2 x float> %a) #0 {
; CHECK-LABEL: test_sincospi_v2f32:
; CHECK: ; %bb.0:
-; CHECK-NEXT: sub sp, sp, #64
+; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: add x0, sp, #28
; CHECK-NEXT: add x1, sp, #24
-; CHECK-NEXT: stp x20, x19, [sp, #32] ; 16-byte Folded Spill
-; CHECK-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
; CHECK-NEXT: str q0, [sp] ; 16-byte Spill
; CHECK-NEXT: ; kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl ___sincospif
; CHECK-NEXT: ldr q0, [sp] ; 16-byte Reload
; CHECK-NEXT: add x0, sp, #20
; CHECK-NEXT: add x1, sp, #16
-; CHECK-NEXT: add x19, sp, #20
-; CHECK-NEXT: add x20, sp, #16
; CHECK-NEXT: mov s0, v0[1]
; CHECK-NEXT: bl ___sincospif
; CHECK-NEXT: ldp s1, s0, [sp, #24]
-; CHECK-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
-; CHECK-NEXT: ld1.s { v0 }[1], [x19]
-; CHECK-NEXT: ld1.s { v1 }[1], [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #32] ; 16-byte Folded Reload
+; CHECK-NEXT: add x8, sp, #20
+; CHECK-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-NEXT: ld1.s { v0 }[1], [x8]
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: ld1.s { v1 }[1], [x8]
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ; kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: add sp, sp, #64
+; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%result = call { <2 x float>, <2 x float> } @llvm.sincospi.v2f32(<2 x float> %a)
ret { <2 x float>, <2 x float> } %result
@@ -221,27 +215,25 @@ define { double, double } @test_sincospi_f64(double %a) #0 {
define { <2 x double>, <2 x double> } @test_sincospi_v2f64(<2 x double> %a) #0 {
; CHECK-LABEL: test_sincospi_v2f64:
; CHECK: ; %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: add x0, sp, #40
; CHECK-NEXT: add x1, sp, #32
-; CHECK-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill
-; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
+; CHECK-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
; CHECK-NEXT: str q0, [sp] ; 16-byte Spill
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: bl ___sincospi
; CHECK-NEXT: ldr q0, [sp] ; 16-byte Reload
; CHECK-NEXT: add x0, sp, #24
; CHECK-NEXT: add x1, sp, #16
-; CHECK-NEXT: add x19, sp, #24
-; CHECK-NEXT: add x20, sp, #16
; CHECK-NEXT: mov d0, v0[1]
; CHECK-NEXT: bl ___sincospi
; CHECK-NEXT: ldp d1, d0, [sp, #32]
-; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
-; CHECK-NEXT: ld1.d { v0 }[1], [x19]
-; CHECK-NEXT: ld1.d { v1 }[1], [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-NEXT: ld1.d { v0 }[1], [x8]
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: ld1.d { v1 }[1], [x8]
+; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret
%result = call { <2 x double>, <2 x double> } @llvm.sincospi.v2f64(<2 x double> %a)
ret { <2 x double>, <2 x double> } %result
diff --git a/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir b/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
index 73a22b71980cb..de43fadadaa35 100644
--- a/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
+++ b/llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
@@ -306,8 +306,8 @@ body: |
; CHECK-NEXT: renamable $w21 = MOVi32imm -8280
; CHECK-NEXT: renamable $w23 = MOVi32imm -6
; CHECK-NEXT: renamable $w25 = MOVi32imm 3, implicit-def $x25
- ; CHECK-NEXT: renamable $w24 = MOVi32imm 2143289344
- ; CHECK-NEXT: renamable $x22 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $w22 = MOVi32imm 2143289344
+ ; CHECK-NEXT: renamable $x24 = IMPLICIT_DEF
; CHECK-NEXT: dead renamable $x8 = IMPLICIT_DEF
; CHECK-NEXT: renamable $x26 = IMPLICIT_DEF
; CHECK-NEXT: renamable $x19 = IMPLICIT_DEF
@@ -330,7 +330,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb27:
; CHECK-NEXT: successors: %bb.4(0x80000000), %bb.13(0x00000000)
- ; CHECK-NEXT: liveins: $w21, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $w21, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $fp = nuw nsw ADDXri renamable $x25, 1, 0
; CHECK-NEXT: CBNZW $wzr, %bb.13
@@ -338,57 +338,57 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.bb41:
; CHECK-NEXT: successors: %bb.5(0x7ffff777), %bb.6(0x00000889)
- ; CHECK-NEXT: liveins: $fp, $w21, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w21, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: CBZW $wzr, %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
; CHECK-NEXT: successors: %bb.7(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: B %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.bb42:
; CHECK-NEXT: successors: %bb.7(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w21, $w23, $w24, $x20, $x25, $x27
+ ; CHECK-NEXT: liveins: $fp, $w21, $w22, $w23, $x20, $x25, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x19 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
- ; CHECK-NEXT: renamable $w22 = MOVi32imm 2, implicit-def $x22
+ ; CHECK-NEXT: renamable $w24 = MOVi32imm 2, implicit-def $x24
; CHECK-NEXT: renamable $w26 = MOVi32imm 95
- ; CHECK-NEXT: renamable $x27, dead renamable $x19 = STATEPOINT 2882400000, 0, 0, @wombat, 2, 0, 2, 0, 2, 35, 2, 0, 2, 1, 2, 0, 2, 125, 2, 0, 2, 14, 2, 0, 2, 0, killed renamable $x19, 2, 7, 2, 0, 2, 3, killed renamable $w26, 2, 3, renamable $w22, 2, 3, 2, 4278124286, 2, 3, killed renamable $w21, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 2, 2, 7, 2, 0, 2, 3, 2, 4278124286, 2, 0, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 3, killed renamable $x27(tied-def 0), 1, 8, %stack.1, 0, renamable $x19(tied-def 1), 2, 0, 2, 3, 0, 0, 1, 1, 2, 2, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x22 :: (load store (s64) on %stack.1)
+ ; CHECK-NEXT: renamable $x27, dead renamable $x19 = STATEPOINT 2882400000, 0, 0, @wombat, 2, 0, 2, 0, 2, 35, 2, 0, 2, 1, 2, 0, 2, 125, 2, 0, 2, 14, 2, 0, 2, 0, killed renamable $x19, 2, 7, 2, 0, 2, 3, killed renamable $w26, 2, 3, renamable $w24, 2, 3, 2, 4278124286, 2, 3, killed renamable $w21, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 2, 2, 7, 2, 0, 2, 3, 2, 4278124286, 2, 0, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 3, killed renamable $x27(tied-def 0), 1, 8, %stack.1, 0, renamable $x19(tied-def 1), 2, 0, 2, 3, 0, 0, 1, 1, 2, 2, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x24 :: (load store (s64) on %stack.1)
; CHECK-NEXT: renamable $w10 = MOVi32imm 2, implicit-def $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x19 = COPY $xzr
; CHECK-NEXT: renamable $x8 = LDRXui %stack.1, 0 :: (load (s64) from %stack.1)
; CHECK-NEXT: dead renamable $x8 = nuw ADDXri killed renamable $x8, 24, 0
- ; CHECK-NEXT: renamable $x22 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $x24 = IMPLICIT_DEF
; CHECK-NEXT: renamable $x26 = IMPLICIT_DEF
; CHECK-NEXT: renamable $x8 = IMPLICIT_DEF
; CHECK-NEXT: KILL killed renamable $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.bb48:
; CHECK-NEXT: successors: %bb.8(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.bb79:
; CHECK-NEXT: successors: %bb.9(0x04000000), %bb.8(0x7c000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: CBNZW $wzr, %bb.8
; CHECK-NEXT: B %bb.9
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.9.bb81:
; CHECK-NEXT: successors: %bb.11(0x78787f1d), %bb.10(0x078780e3)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, renamable $x22, 0 :: (store unordered (s64), addrspace 1)
+ ; CHECK-NEXT: STRXui $xzr, renamable $x24, 0 :: (store unordered (s64), addrspace 1)
; CHECK-NEXT: CBNZW $wzr, %bb.11
; CHECK-NEXT: B %bb.10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.10.bb82:
; CHECK-NEXT: successors: %bb.11(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: BL @blam.1, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
@@ -397,13 +397,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.11.bb83:
; CHECK-NEXT: successors: %bb.12(0x7ffff777), %bb.17(0x00000889)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: CBZW $wzr, %bb.17
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.12:
; CHECK-NEXT: successors: %bb.18(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: B %bb.18
; CHECK-NEXT: {{ $}}
@@ -442,34 +442,34 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.17.bb96:
; CHECK-NEXT: successors: %bb.18(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x20, $x25, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x20, $x25, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x19 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
; CHECK-NEXT: renamable $w21 = MOVi32imm 2, implicit-def $x21
- ; CHECK-NEXT: renamable $w22 = MOVi32imm 95
- ; CHECK-NEXT: renamable $x27, dead renamable $x19 = STATEPOINT 2882400000, 0, 0, @wombat, 2, 0, 2, 0, 2, 35, 2, 0, 2, 1, 2, 0, 2, 250, 2, 0, 2, 14, 2, 0, 2, 0, killed renamable $x19, 2, 7, 2, 0, 2, 3, killed renamable $w22, 2, 3, renamable $w21, 2, 3, 2, 4278124286, 2, 3, renamable $w21, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 0, 2, 7, 2, 0, 2, 3, 2, 4278124286, 2, 0, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.2, 0, killed renamable $x27(tied-def 0), 1, 8, %stack.1, 0, renamable $x19(tied-def 1), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x21 :: (load store (s64) on %stack.1), (load store (s64) on %stack.2)
+ ; CHECK-NEXT: renamable $w24 = MOVi32imm 95
+ ; CHECK-NEXT: renamable $x27, dead renamable $x19 = STATEPOINT 2882400000, 0, 0, @wombat, 2, 0, 2, 0, 2, 35, 2, 0, 2, 1, 2, 0, 2, 250, 2, 0, 2, 14, 2, 0, 2, 0, killed renamable $x19, 2, 7, 2, 0, 2, 3, killed renamable $w24, 2, 3, renamable $w21, 2, 3, 2, 4278124286, 2, 3, renamable $w21, 2, 7, 2, 0, 2, 3, 2, 230, 2, 7, 2, 0, 2, 4, 2, 0, 2, 7, 2, 0, 2, 3, 2, 4278124286, 2, 0, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.2, 0, killed renamable $x27(tied-def 0), 1, 8, %stack.1, 0, renamable $x19(tied-def 1), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr, implicit killed $x21 :: (load store (s64) on %stack.1), (load store (s64) on %stack.2)
; CHECK-NEXT: renamable $w10 = MOVi32imm 2, implicit-def $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: renamable $x8 = LDRXui %stack.1, 0 :: (load (s64) from %stack.1)
; CHECK-NEXT: dead renamable $x8 = nuw ADDXri killed renamable $x8, 24, 0
; CHECK-NEXT: renamable $x8 = LDRXui %stack.2, 0 :: (load (s64) from %stack.2)
- ; CHECK-NEXT: renamable $x22 = nuw ADDXri killed renamable $x8, 848, 0
+ ; CHECK-NEXT: renamable $x24 = nuw ADDXri killed renamable $x8, 848, 0
; CHECK-NEXT: renamable $x26 = IMPLICIT_DEF
; CHECK-NEXT: renamable $x19 = IMPLICIT_DEF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.18.bb105:
; CHECK-NEXT: successors: %bb.20(0x00000000), %bb.19(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: STRWui renamable $w20, renamable $x19, 0 :: (store unordered (s32), addrspace 1)
- ; CHECK-NEXT: STRWui renamable $w24, renamable $x26, 0 :: (store unordered (s32), align 8, addrspace 1)
+ ; CHECK-NEXT: STRWui renamable $w22, renamable $x26, 0 :: (store unordered (s32), align 8, addrspace 1)
; CHECK-NEXT: CBZX renamable $x27, %bb.20
; CHECK-NEXT: B %bb.19
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.19.bb115:
; CHECK-NEXT: successors: %bb.16(0x00000000), %bb.3(0x80000000)
- ; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
+ ; CHECK-NEXT: liveins: $fp, $w22, $w23, $x10, $x19, $x20, $x24, $x25, $x26, $x27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x8 = COPY $xzr
; CHECK-NEXT: renamable $w9 = LDRWui renamable $x8, 0 :: (load unordered (s32) from `ptr addrspace(1) null`, addrspace 1)
diff --git a/llvm/test/CodeGen/AArch64/shrink-wrap-byval-inalloca-preallocated.ll b/llvm/test/CodeGen/AArch64/shrink-wrap-byval-inalloca-preallocated.ll
index 8b58ba633b814..4fec3a349b592 100644
--- a/llvm/test/CodeGen/AArch64/shrink-wrap-byval-inalloca-preallocated.ll
+++ b/llvm/test/CodeGen/AArch64/shrink-wrap-byval-inalloca-preallocated.ll
@@ -59,31 +59,27 @@ exit:
define void @test_byval_pointers(ptr %a, ptr byval(%struct.s) %b) {
; CHECK-LABEL: test_byval_pointers:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
-; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_offset w19, -24
-; CHECK-NEXT: .cfi_offset w20, -32
-; CHECK-NEXT: ldr d0, [sp, #40]
+; CHECK-NEXT: ldr d0, [sp, #24]
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: mov x8, #1 ; =0x1
; CHECK-NEXT: movk x8, #2047, lsl #16
; CHECK-NEXT: fadd d0, d1, d0
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: fcmp d0, d1
-; CHECK-NEXT: str d0, [sp, #32]
+; CHECK-NEXT: str d0, [sp, #16]
; CHECK-NEXT: b.mi LBB1_2
; CHECK-NEXT: b.gt LBB1_2
; CHECK-NEXT: ; %bb.1: ; %then
-; CHECK-NEXT: add x1, sp, #32
-; CHECK-NEXT: add x19, sp, #32
+; CHECK-NEXT: add x1, sp, #16
; CHECK-NEXT: bl _fn
-; CHECK-NEXT: str xzr, [x19]
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: str xzr, [x8]
; CHECK-NEXT: LBB1_2: ; %exit
-; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
%l.a = load double, ptr %a, align 8
@@ -107,31 +103,27 @@ exit:
define void @test_inalloca_pointers(ptr %a, ptr inalloca(%struct.s) %b) {
; CHECK-LABEL: test_inalloca_pointers:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
-; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_offset w19, -24
-; CHECK-NEXT: .cfi_offset w20, -32
-; CHECK-NEXT: ldr d0, [sp, #40]
+; CHECK-NEXT: ldr d0, [sp, #24]
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: mov x8, #1 ; =0x1
; CHECK-NEXT: movk x8, #2047, lsl #16
; CHECK-NEXT: fadd d0, d1, d0
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: fcmp d0, d1
-; CHECK-NEXT: str d0, [sp, #32]
+; CHECK-NEXT: str d0, [sp, #16]
; CHECK-NEXT: b.mi LBB2_2
; CHECK-NEXT: b.gt LBB2_2
; CHECK-NEXT: ; %bb.1: ; %then
-; CHECK-NEXT: add x1, sp, #32
-; CHECK-NEXT: add x19, sp, #32
+; CHECK-NEXT: add x1, sp, #16
; CHECK-NEXT: bl _fn
-; CHECK-NEXT: str xzr, [x19]
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: str xzr, [x8]
; CHECK-NEXT: LBB2_2: ; %exit
-; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
%l.a = load double, ptr %a, align 8
@@ -155,31 +147,27 @@ exit:
define void @test_preallocated_pointers(ptr %a, ptr preallocated(%struct.s) %b) {
; CHECK-LABEL: test_preallocated_pointers:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
-; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_offset w19, -24
-; CHECK-NEXT: .cfi_offset w20, -32
-; CHECK-NEXT: ldr d0, [sp, #40]
+; CHECK-NEXT: ldr d0, [sp, #24]
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: mov x8, #1 ; =0x1
; CHECK-NEXT: movk x8, #2047, lsl #16
; CHECK-NEXT: fadd d0, d1, d0
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: fcmp d0, d1
-; CHECK-NEXT: str d0, [sp, #32]
+; CHECK-NEXT: str d0, [sp, #16]
; CHECK-NEXT: b.mi LBB3_2
; CHECK-NEXT: b.gt LBB3_2
; CHECK-NEXT: ; %bb.1: ; %then
-; CHECK-NEXT: add x1, sp, #32
-; CHECK-NEXT: add x19, sp, #32
+; CHECK-NEXT: add x1, sp, #16
; CHECK-NEXT: bl _fn
-; CHECK-NEXT: str xzr, [x19]
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: str xzr, [x8]
; CHECK-NEXT: LBB3_2: ; %exit
-; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
%l.a = load double, ptr %a, align 8
diff --git a/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll b/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
index 36539d94338a0..d0f53b8802c41 100644
--- a/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
+++ b/llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
@@ -225,15 +225,16 @@ define void @test7() nounwind "aarch64_inout_zt0" {
; CHECK-LABEL: test7:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: mov x19, sp
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: bl callee
; CHECK-NEXT: bl callee
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
call void @callee()
diff --git a/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll b/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll
index 8068e11b37a65..53a9b8fee8de4 100644
--- a/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll
+++ b/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll
@@ -8,7 +8,7 @@ define void @private_za_loop(i32 %n) "aarch64_inout_za" nounwind {
; CHECK-LABEL: private_za_loop:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1
@@ -20,7 +20,6 @@ define void @private_za_loop(i32 %n) "aarch64_inout_za" nounwind {
; CHECK-NEXT: b.lt .LBB0_5
; CHECK-NEXT: // %bb.1: // %loop.preheader
; CHECK-NEXT: mov w19, w0
-; CHECK-NEXT: sub x20, x29, #16
; CHECK-NEXT: b .LBB0_3
; CHECK-NEXT: .LBB0_2: // %loop
; CHECK-NEXT: // in Loop: Header=BB0_3 Depth=1
@@ -28,7 +27,8 @@ define void @private_za_loop(i32 %n) "aarch64_inout_za" nounwind {
; CHECK-NEXT: cbz w19, .LBB0_5
; CHECK-NEXT: .LBB0_3: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: msr TPIDR2_EL0, x20
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
; CHECK-NEXT: bl private_za_call
; CHECK-NEXT: sub w19, w19, #1
; CHECK-NEXT: smstart za
@@ -41,7 +41,7 @@ define void @private_za_loop(i32 %n) "aarch64_inout_za" nounwind {
; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .LBB0_5: // %exit
; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
@@ -64,7 +64,7 @@ define void @private_za_loop_active_entry_and_exit(i32 %n) "aarch64_inout_za" no
; CHECK-LABEL: private_za_loop_active_entry_and_exit:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1
@@ -75,17 +75,20 @@ define void @private_za_loop_active_entry_and_exit(i32 %n) "aarch64_inout_za" no
; CHECK-NEXT: stp x9, x8, [x29, #-16]
; CHECK-NEXT: bl shared_za_call
; CHECK-NEXT: cmp w19, #1
-; CHECK-NEXT: b.lt .LBB1_5
-; CHECK-NEXT: // %bb.1: // %loop.preheader
-; CHECK-NEXT: sub x20, x29, #16
-; CHECK-NEXT: b .LBB1_3
+; CHECK-NEXT: b.ge .LBB1_3
+; CHECK-NEXT: .LBB1_1: // %exit
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: b shared_za_call
; CHECK-NEXT: .LBB1_2: // %loop
; CHECK-NEXT: // in Loop: Header=BB1_3 Depth=1
; CHECK-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-NEXT: cbz w19, .LBB1_5
+; CHECK-NEXT: cbz w19, .LBB1_1
; CHECK-NEXT: .LBB1_3: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: msr TPIDR2_EL0, x20
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
; CHECK-NEXT: bl private_za_call
; CHECK-NEXT: sub w19, w19, #1
; CHECK-NEXT: smstart za
@@ -96,11 +99,6 @@ define void @private_za_loop_active_entry_and_exit(i32 %n) "aarch64_inout_za" no
; CHECK-NEXT: // in Loop: Header=BB1_3 Depth=1
; CHECK-NEXT: bl __arm_tpidr2_restore
; CHECK-NEXT: b .LBB1_2
-; CHECK-NEXT: .LBB1_5: // %exit
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
-; CHECK-NEXT: b shared_za_call
entry:
%cmpgt = icmp sgt i32 %n, 0
tail call void @shared_za_call()
@@ -193,7 +191,7 @@ define void @mixed_shared_private_za_loop(ptr %cond) "aarch64_inout_za" nounwind
; CHECK-LABEL: mixed_shared_private_za_loop:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1
@@ -201,7 +199,6 @@ define void @mixed_shared_private_za_loop(ptr %cond) "aarch64_inout_za" nounwind
; CHECK-NEXT: msub x9, x8, x8, x9
; CHECK-NEXT: mov sp, x9
; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: sub x20, x29, #16
; CHECK-NEXT: stp x9, x8, [x29, #-16]
; CHECK-NEXT: b .LBB4_2
; CHECK-NEXT: .LBB4_1: // %loop
@@ -211,7 +208,8 @@ define void @mixed_shared_private_za_loop(ptr %cond) "aarch64_inout_za" nounwind
; CHECK-NEXT: .LBB4_2: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: bl shared_za_call
-; CHECK-NEXT: msr TPIDR2_EL0, x20
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
; CHECK-NEXT: bl private_za_call
; CHECK-NEXT: ldrb w8, [x19]
; CHECK-NEXT: smstart za
@@ -225,7 +223,7 @@ define void @mixed_shared_private_za_loop(ptr %cond) "aarch64_inout_za" nounwind
; CHECK-NEXT: .LBB4_4: // %exit
; CHECK-NEXT: bl shared_za_call
; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
; CHECK-NEXT: ret
br label %loop
@@ -509,7 +507,7 @@ define void @nested_cond_in_loop(i32 %n, i1 %cond) "aarch64_inout_za" nounwind {
; CHECK-LABEL: nested_cond_in_loop:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-48]! // 16-byte Folded Spill
-; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: str x21, [sp, #16] // 8-byte Spill
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: sub sp, sp, #16
@@ -524,7 +522,6 @@ define void @nested_cond_in_loop(i32 %n, i1 %cond) "aarch64_inout_za" nounwind {
; CHECK-NEXT: mov w19, w1
; CHECK-NEXT: mov w20, w0
; CHECK-NEXT: mov w21, wzr
-; CHECK-NEXT: sub x22, x29, #16
; CHECK-NEXT: b .LBB10_4
; CHECK-NEXT: .LBB10_2: // %use_shared
; CHECK-NEXT: // in Loop: Header=BB10_4 Depth=1
@@ -539,7 +536,8 @@ define void @nested_cond_in_loop(i32 %n, i1 %cond) "aarch64_inout_za" nounwind {
; CHECK-NEXT: tbnz w19, #0, .LBB10_2
; CHECK-NEXT: // %bb.5: // %use_private
; CHECK-NEXT: // in Loop: Header=BB10_4 Depth=1
-; CHECK-NEXT: msr TPIDR2_EL0, x22
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
; CHECK-NEXT: bl private_za_call
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
@@ -555,7 +553,7 @@ define void @nested_cond_in_loop(i32 %n, i1 %cond) "aarch64_inout_za" nounwind {
; CHECK-NEXT: .LBB10_8: // %exit
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x21, [sp, #16] // 8-byte Reload
; CHECK-NEXT: ldp x29, x30, [sp], #48 // 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
@@ -587,7 +585,7 @@ define void @loop_with_external_entry(i1 %c1, i1 %c2) "aarch64_inout_za" nounwin
; CHECK-LABEL: loop_with_external_entry:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1
@@ -596,31 +594,30 @@ define void @loop_with_external_entry(i1 %c1, i1 %c2) "aarch64_inout_za" nounwin
; CHECK-NEXT: mov sp, x9
; CHECK-NEXT: mov w19, w1
; CHECK-NEXT: stp x9, x8, [x29, #-16]
-; CHECK-NEXT: tbz w0, #0, .LBB11_2
+; CHECK-NEXT: tbz w0, #0, .LBB11_3
; CHECK-NEXT: // %bb.1: // %init
; CHECK-NEXT: bl shared_za_call
-; CHECK-NEXT: .LBB11_2: // %loop.preheader
-; CHECK-NEXT: sub x20, x29, #16
-; CHECK-NEXT: b .LBB11_4
-; CHECK-NEXT: .LBB11_3: // %loop
-; CHECK-NEXT: // in Loop: Header=BB11_4 Depth=1
+; CHECK-NEXT: b .LBB11_3
+; CHECK-NEXT: .LBB11_2: // %loop
+; CHECK-NEXT: // in Loop: Header=BB11_3 Depth=1
; CHECK-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-NEXT: tbz w19, #0, .LBB11_6
-; CHECK-NEXT: .LBB11_4: // %loop
+; CHECK-NEXT: tbz w19, #0, .LBB11_5
+; CHECK-NEXT: .LBB11_3: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: msr TPIDR2_EL0, x20
+; CHECK-NEXT: sub x8, x29, #16
+; CHECK-NEXT: msr TPIDR2_EL0, x8
; CHECK-NEXT: bl private_za_call
; CHECK-NEXT: smstart za
; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: sub x0, x29, #16
-; CHECK-NEXT: cbnz x8, .LBB11_3
-; CHECK-NEXT: // %bb.5: // %loop
-; CHECK-NEXT: // in Loop: Header=BB11_4 Depth=1
+; CHECK-NEXT: cbnz x8, .LBB11_2
+; CHECK-NEXT: // %bb.4: // %loop
+; CHECK-NEXT: // in Loop: Header=BB11_3 Depth=1
; CHECK-NEXT: bl __arm_tpidr2_restore
-; CHECK-NEXT: b .LBB11_3
-; CHECK-NEXT: .LBB11_6: // %exit
+; CHECK-NEXT: b .LBB11_2
+; CHECK-NEXT: .LBB11_5: // %exit
; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
index 6eb4de449aaa6..d57f3878a9952 100644
--- a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll
@@ -306,13 +306,11 @@ define void @try_catch_shared_zt0_callee() "aarch64_inout_zt0" personality ptr @
; CHECK-NEXT: .cfi_personality 156, DW.ref.__gxx_personality_v0
; CHECK-NEXT: .cfi_lsda 28, .Lexception3
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #96
-; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 96
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
+; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: .Ltmp9: // EH_LABEL
; CHECK-NEXT: mov x19, sp
; CHECK-NEXT: str zt0, [x19]
@@ -322,18 +320,18 @@ define void @try_catch_shared_zt0_callee() "aarch64_inout_zt0" personality ptr @
; CHECK-NEXT: smstart za
; CHECK-NEXT: ldr zt0, [x19]
; CHECK-NEXT: // %bb.1: // %return_normally
-; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
-; CHECK-NEXT: add sp, sp, #96
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %unwind_dtors
; CHECK-NEXT: .Ltmp11: // EH_LABEL
-; CHECK-NEXT: mov x20, sp
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x20]
+; CHECK-NEXT: ldr zt0, [x8]
; CHECK-NEXT: bl shared_zt0_call
-; CHECK-NEXT: str zt0, [x20]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: mov x0, x19
; CHECK-NEXT: bl _Unwind_Resume
@@ -554,20 +552,20 @@ define void @try_catch_inout_zt0() "aarch64_inout_zt0" personality ptr @__gxx_pe
; CHECK-NEXT: .cfi_lsda 28, .Lexception7
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
; CHECK-NEXT: .cfi_def_cfa_offset 80
-; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: .Ltmp21: // EH_LABEL
-; CHECK-NEXT: mov x19, sp
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: bl may_throw
; CHECK-NEXT: .Ltmp22: // EH_LABEL
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
; CHECK-NEXT: .LBB7_1: // %exit
-; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: // %catch
@@ -575,7 +573,8 @@ define void @try_catch_inout_zt0() "aarch64_inout_zt0" personality ptr @__gxx_pe
; CHECK-NEXT: bl __cxa_begin_catch
; CHECK-NEXT: bl __cxa_end_catch
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
; CHECK-NEXT: b .LBB7_1
entry:
invoke void @may_throw()
diff --git a/llvm/test/CodeGen/AArch64/sme-zt0-state.ll b/llvm/test/CodeGen/AArch64/sme-zt0-state.ll
index 7ef3262e5811c..23b9e8b11e57e 100644
--- a/llvm/test/CodeGen/AArch64/sme-zt0-state.ll
+++ b/llvm/test/CodeGen/AArch64/sme-zt0-state.ll
@@ -11,14 +11,15 @@ define void @zt0_in_caller_no_state_callee(ptr %callee) "aarch64_in_zt0" nounwin
; CHECK-LABEL: zt0_in_caller_no_state_callee:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: mov x19, sp
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: blr x0
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
call void %callee();
@@ -31,18 +32,17 @@ define void @zt0_in_caller_no_state_callee(ptr %callee) "aarch64_in_zt0" nounwin
define void @za_zt0_shared_caller_no_state_callee(ptr %callee) "aarch64_inout_za" "aarch64_in_zt0" nounwind {
; CHECK-LABEL: za_zt0_shared_caller_no_state_callee:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: msub x9, x8, x8, x9
; CHECK-NEXT: mov sp, x9
-; CHECK-NEXT: sub x19, x29, #64
+; CHECK-NEXT: sub x11, x29, #64
; CHECK-NEXT: sub x10, x29, #80
; CHECK-NEXT: stp x9, x8, [x29, #-80]
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: str zt0, [x11]
; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: blr x0
; CHECK-NEXT: smstart za
@@ -52,11 +52,11 @@ define void @za_zt0_shared_caller_no_state_callee(ptr %callee) "aarch64_inout_za
; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: bl __arm_tpidr2_restore
; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: sub x8, x29, #64
; CHECK-NEXT: msr TPIDR2_EL0, xzr
-; CHECK-NEXT: ldr zt0, [x19]
+; CHECK-NEXT: ldr zt0, [x8]
; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
-; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
call void %callee();
ret void;
@@ -83,12 +83,13 @@ define void @za_zt0_shared_caller_za_shared_callee(ptr %callee) "aarch64_inout_z
; CHECK-LABEL: za_zt0_shared_caller_za_shared_callee:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: mov x19, sp
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: blr x0
-; CHECK-NEXT: ldr zt0, [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
call void %callee() "aarch64_inout_za";
@@ -115,14 +116,15 @@ define void @zt0_in_caller_zt0_new_callee(ptr %callee) "aarch64_in_zt0" nounwind
; CHECK-LABEL: zt0_in_caller_zt0_new_callee:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: mov x19, sp
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: blr x0
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
call void %callee() "aarch64_new_zt0";
@@ -149,14 +151,15 @@ define i64 @zt0_new_caller_abi_routine_callee() "aarch64_inout_zt0" nounwind {
; CHECK-LABEL: zt0_new_caller_abi_routine_callee:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: mov x19, sp
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: bl __arm_sme_state
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
%res = call {i64, i64} @__arm_sme_state()
@@ -247,22 +250,21 @@ define void @shared_za_new_zt0(ptr %callee) "aarch64_inout_za" "aarch64_new_zt0"
define void @zt0_multiple_private_za_calls(ptr %callee) "aarch64_in_zt0" nounwind {
; CHECK-LABEL: zt0_multiple_private_za_calls:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #96
-; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-NEXT: mov x20, sp
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-NEXT: str zt0, [x20]
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: blr x0
; CHECK-NEXT: blr x19
; CHECK-NEXT: blr x19
; CHECK-NEXT: blr x19
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x20]
-; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
-; CHECK-NEXT: add sp, sp, #96
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
call void %callee()
call void %callee()
@@ -275,14 +277,15 @@ define void @disable_tailcallopt(ptr %callee) "aarch64_inout_zt0" nounwind {
; CHECK-LABEL: disable_tailcallopt:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: mov x19, sp
-; CHECK-NEXT: str zt0, [x19]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-NEXT: str zt0, [x8]
; CHECK-NEXT: smstop za
; CHECK-NEXT: blr x0
; CHECK-NEXT: smstart za
-; CHECK-NEXT: ldr zt0, [x19]
-; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr zt0, [x8]
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
tail call void %callee()
@@ -296,18 +299,18 @@ define void @za_zt0_private_za_to_shared_za(ptr %callee) "aarch64_inout_za" "aar
; CHECK-LABEL: za_zt0_private_za_to_shared_za:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: msub x9, x8, x8, x9
; CHECK-NEXT: mov sp, x9
-; CHECK-NEXT: sub x20, x29, #64
+; CHECK-NEXT: sub x11, x29, #64
; CHECK-NEXT: sub x10, x29, #80
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: stp x9, x8, [x29, #-80]
-; CHECK-NEXT: str zt0, [x20]
+; CHECK-NEXT: str zt0, [x11]
; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: blr x0
; CHECK-NEXT: smstart za
@@ -319,9 +322,10 @@ define void @za_zt0_private_za_to_shared_za(ptr %callee) "aarch64_inout_za" "aar
; CHECK-NEXT: .LBB14_2:
; CHECK-NEXT: msr TPIDR2_EL0, xzr
; CHECK-NEXT: blr x19
-; CHECK-NEXT: ldr zt0, [x20]
+; CHECK-NEXT: sub x8, x29, #64
+; CHECK-NEXT: ldr zt0, [x8]
; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload
; CHECK-NEXT: ret
call void %callee()
diff --git a/llvm/test/CodeGen/AArch64/stack-protector-darwin-got.ll b/llvm/test/CodeGen/AArch64/stack-protector-darwin-got.ll
index 8d144c12ae3f1..2b6a13832def5 100644
--- a/llvm/test/CodeGen/AArch64/stack-protector-darwin-got.ll
+++ b/llvm/test/CodeGen/AArch64/stack-protector-darwin-got.ll
@@ -8,18 +8,14 @@
define void @test(ptr %a) #0 {
; CHECK-LABEL: test:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill
-; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 80
+; CHECK-NEXT: sub sp, sp, #64
+; CHECK-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_offset w19, -24
-; CHECK-NEXT: .cfi_offset w20, -32
; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x8, ___stack_chk_guard at GOTPAGE
; CHECK-NEXT: mov x1, x0
-; CHECK-NEXT: add x19, sp, #16
; CHECK-NEXT: Lloh1:
; CHECK-NEXT: ldr x8, [x8, ___stack_chk_guard at GOTPAGEOFF]
; CHECK-NEXT: Lloh2:
@@ -32,7 +28,8 @@ define void @test(ptr %a) #0 {
; CHECK-NEXT: adrp x0, l_.str at PAGE
; CHECK-NEXT: Lloh4:
; CHECK-NEXT: add x0, x0, l_.str at PAGEOFF
-; CHECK-NEXT: str x19, [sp]
+; CHECK-NEXT: add x8, sp, #16
+; CHECK-NEXT: str x8, [sp]
; CHECK-NEXT: bl _printf
; CHECK-NEXT: Lloh5:
; CHECK-NEXT: adrp x8, ___stack_chk_guard at GOTPAGE
@@ -44,9 +41,8 @@ define void @test(ptr %a) #0 {
; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: b.ne LBB0_2
; CHECK-NEXT: ; %bb.1: ; %entry
-; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
-; CHECK-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %entry
; CHECK-NEXT: bl ___stack_chk_fail
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
index 6d3612c909032..baa19a2d6b6af 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
@@ -8,19 +8,17 @@ declare void @def(ptr)
define void @st1d_fixed(ptr %ptr) #0 {
; CHECK-LABEL: st1d_fixed:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #160
-; CHECK-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #144
+; CHECK-NEXT: stp x30, x19, [sp, #128] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: mov x0, sp
-; CHECK-NEXT: str x30, [sp, #128] // 8-byte Spill
-; CHECK-NEXT: mov x20, sp
; CHECK-NEXT: bl def
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x20]
-; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Reload
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x8]
; CHECK-NEXT: str z0, [x19]
-; CHECK-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #160
+; CHECK-NEXT: ldp x30, x19, [sp, #128] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #144
; CHECK-NEXT: ret
%alloc = alloca [16 x double]
call void @def(ptr %alloc)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
index 1306331d2e44a..bf086bf896206 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
@@ -10,20 +10,20 @@ declare void @def(ptr)
define void @alloc_v4i8(ptr %st_ptr) nounwind {
; CHECK-LABEL: alloc_v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: add x0, sp, #12
-; CHECK-NEXT: add x20, sp, #12
; CHECK-NEXT: bl def
; CHECK-NEXT: ptrue p0.b, vl2
-; CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x20]
+; CHECK-NEXT: add x8, sp, #12
+; CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x8]
; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: mov z1.b, z0.b[1]
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
; CHECK-NEXT: st1b { z0.s }, p0, [x19]
-; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload
+; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: alloc_v4i8:
@@ -168,21 +168,19 @@ define void @alloc_v32i8(ptr %st_ptr) nounwind {
define void @alloc_v8f64(ptr %st_ptr) nounwind {
; CHECK-LABEL: alloc_v8f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #96
-; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: mov x0, sp
-; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-NEXT: mov x20, sp
; CHECK-NEXT: bl def
; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mov x8, #4 // =0x4
-; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x20]
-; CHECK-NEXT: ld2d { z1.d, z2.d }, p0/z, [x20, x8, lsl #3]
-; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x9]
+; CHECK-NEXT: ld2d { z1.d, z2.d }, p0/z, [x9, x8, lsl #3]
; CHECK-NEXT: stp q0, q1, [x19]
-; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #96
+; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: alloc_v8f64:
diff --git a/llvm/test/CodeGen/AArch64/swifterror.ll b/llvm/test/CodeGen/AArch64/swifterror.ll
index 1ef88cfc16069..bb6efaa2a56d4 100644
--- a/llvm/test/CodeGen/AArch64/swifterror.ll
+++ b/llvm/test/CodeGen/AArch64/swifterror.ll
@@ -215,12 +215,11 @@ handler:
define float @caller2(ptr %error_ref) {
; CHECK-APPLE-AARCH64-LABEL: caller2:
; CHECK-APPLE-AARCH64: ; %bb.0: ; %entry
-; CHECK-APPLE-AARCH64-NEXT: sub sp, sp, #80
-; CHECK-APPLE-AARCH64-NEXT: stp d9, d8, [sp, #16] ; 16-byte Folded Spill
-; CHECK-APPLE-AARCH64-NEXT: stp x22, x21, [sp, #32] ; 16-byte Folded Spill
-; CHECK-APPLE-AARCH64-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill
-; CHECK-APPLE-AARCH64-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
-; CHECK-APPLE-AARCH64-NEXT: add x29, sp, #64
+; CHECK-APPLE-AARCH64-NEXT: sub sp, sp, #64
+; CHECK-APPLE-AARCH64-NEXT: stp x22, x21, [sp, #16] ; 16-byte Folded Spill
+; CHECK-APPLE-AARCH64-NEXT: stp x20, x19, [sp, #32] ; 16-byte Folded Spill
+; CHECK-APPLE-AARCH64-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
+; CHECK-APPLE-AARCH64-NEXT: add x29, sp, #48
; CHECK-APPLE-AARCH64-NEXT: .cfi_def_cfa w29, 16
; CHECK-APPLE-AARCH64-NEXT: .cfi_offset w30, -8
; CHECK-APPLE-AARCH64-NEXT: .cfi_offset w29, -16
@@ -228,9 +227,6 @@ define float @caller2(ptr %error_ref) {
; CHECK-APPLE-AARCH64-NEXT: .cfi_offset w20, -32
; CHECK-APPLE-AARCH64-NEXT: .cfi_offset w21, -40
; CHECK-APPLE-AARCH64-NEXT: .cfi_offset w22, -48
-; CHECK-APPLE-AARCH64-NEXT: .cfi_offset b8, -56
-; CHECK-APPLE-AARCH64-NEXT: .cfi_offset b9, -64
-; CHECK-APPLE-AARCH64-NEXT: fmov s8, #1.00000000
; CHECK-APPLE-AARCH64-NEXT: mov x19, x0
; CHECK-APPLE-AARCH64-NEXT: LBB2_1: ; %bb_loop
; CHECK-APPLE-AARCH64-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -239,7 +235,8 @@ define float @caller2(ptr %error_ref) {
; CHECK-APPLE-AARCH64-NEXT: cbnz x21, LBB2_4
; CHECK-APPLE-AARCH64-NEXT: ; %bb.2: ; %cont
; CHECK-APPLE-AARCH64-NEXT: ; in Loop: Header=BB2_1 Depth=1
-; CHECK-APPLE-AARCH64-NEXT: fcmp s0, s8
+; CHECK-APPLE-AARCH64-NEXT: fmov s1, #1.00000000
+; CHECK-APPLE-AARCH64-NEXT: fcmp s0, s1
; CHECK-APPLE-AARCH64-NEXT: b.le LBB2_1
; CHECK-APPLE-AARCH64-NEXT: ; %bb.3: ; %bb_end
; CHECK-APPLE-AARCH64-NEXT: ldrb w8, [x21, #8]
@@ -248,11 +245,10 @@ define float @caller2(ptr %error_ref) {
; CHECK-APPLE-AARCH64-NEXT: mov x0, x21
; CHECK-APPLE-AARCH64-NEXT: bl _free
; CHECK-APPLE-AARCH64-NEXT: fmov s0, #1.00000000
-; CHECK-APPLE-AARCH64-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
-; CHECK-APPLE-AARCH64-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
-; CHECK-APPLE-AARCH64-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload
-; CHECK-APPLE-AARCH64-NEXT: ldp d9, d8, [sp, #16] ; 16-byte Folded Reload
-; CHECK-APPLE-AARCH64-NEXT: add sp, sp, #80
+; CHECK-APPLE-AARCH64-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-APPLE-AARCH64-NEXT: ldp x20, x19, [sp, #32] ; 16-byte Folded Reload
+; CHECK-APPLE-AARCH64-NEXT: ldp x22, x21, [sp, #16] ; 16-byte Folded Reload
+; CHECK-APPLE-AARCH64-NEXT: add sp, sp, #64
; CHECK-APPLE-AARCH64-NEXT: ret
;
; CHECK-O0-AARCH64-LABEL: caller2:
@@ -297,12 +293,11 @@ define float @caller2(ptr %error_ref) {
;
; CHECK-APPLE-ARM64_32-LABEL: caller2:
; CHECK-APPLE-ARM64_32: ; %bb.0: ; %entry
-; CHECK-APPLE-ARM64_32-NEXT: sub sp, sp, #80
-; CHECK-APPLE-ARM64_32-NEXT: stp d9, d8, [sp, #16] ; 16-byte Folded Spill
-; CHECK-APPLE-ARM64_32-NEXT: stp x22, x21, [sp, #32] ; 16-byte Folded Spill
-; CHECK-APPLE-ARM64_32-NEXT: stp x20, x19, [sp, #48] ; 16-byte Folded Spill
-; CHECK-APPLE-ARM64_32-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
-; CHECK-APPLE-ARM64_32-NEXT: add x29, sp, #64
+; CHECK-APPLE-ARM64_32-NEXT: sub sp, sp, #64
+; CHECK-APPLE-ARM64_32-NEXT: stp x22, x21, [sp, #16] ; 16-byte Folded Spill
+; CHECK-APPLE-ARM64_32-NEXT: stp x20, x19, [sp, #32] ; 16-byte Folded Spill
+; CHECK-APPLE-ARM64_32-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
+; CHECK-APPLE-ARM64_32-NEXT: add x29, sp, #48
; CHECK-APPLE-ARM64_32-NEXT: .cfi_def_cfa w29, 16
; CHECK-APPLE-ARM64_32-NEXT: .cfi_offset w30, -8
; CHECK-APPLE-ARM64_32-NEXT: .cfi_offset w29, -16
@@ -310,9 +305,6 @@ define float @caller2(ptr %error_ref) {
; CHECK-APPLE-ARM64_32-NEXT: .cfi_offset w20, -32
; CHECK-APPLE-ARM64_32-NEXT: .cfi_offset w21, -40
; CHECK-APPLE-ARM64_32-NEXT: .cfi_offset w22, -48
-; CHECK-APPLE-ARM64_32-NEXT: .cfi_offset b8, -56
-; CHECK-APPLE-ARM64_32-NEXT: .cfi_offset b9, -64
-; CHECK-APPLE-ARM64_32-NEXT: fmov s8, #1.00000000
; CHECK-APPLE-ARM64_32-NEXT: mov x19, x0
; CHECK-APPLE-ARM64_32-NEXT: LBB2_1: ; %bb_loop
; CHECK-APPLE-ARM64_32-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -321,7 +313,8 @@ define float @caller2(ptr %error_ref) {
; CHECK-APPLE-ARM64_32-NEXT: cbnz w21, LBB2_4
; CHECK-APPLE-ARM64_32-NEXT: ; %bb.2: ; %cont
; CHECK-APPLE-ARM64_32-NEXT: ; in Loop: Header=BB2_1 Depth=1
-; CHECK-APPLE-ARM64_32-NEXT: fcmp s0, s8
+; CHECK-APPLE-ARM64_32-NEXT: fmov s1, #1.00000000
+; CHECK-APPLE-ARM64_32-NEXT: fcmp s0, s1
; CHECK-APPLE-ARM64_32-NEXT: b.le LBB2_1
; CHECK-APPLE-ARM64_32-NEXT: ; %bb.3: ; %bb_end
; CHECK-APPLE-ARM64_32-NEXT: ldrb w8, [x21, #8]
@@ -330,11 +323,10 @@ define float @caller2(ptr %error_ref) {
; CHECK-APPLE-ARM64_32-NEXT: mov x0, x21
; CHECK-APPLE-ARM64_32-NEXT: bl _free
; CHECK-APPLE-ARM64_32-NEXT: fmov s0, #1.00000000
-; CHECK-APPLE-ARM64_32-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
-; CHECK-APPLE-ARM64_32-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
-; CHECK-APPLE-ARM64_32-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload
-; CHECK-APPLE-ARM64_32-NEXT: ldp d9, d8, [sp, #16] ; 16-byte Folded Reload
-; CHECK-APPLE-ARM64_32-NEXT: add sp, sp, #80
+; CHECK-APPLE-ARM64_32-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-APPLE-ARM64_32-NEXT: ldp x20, x19, [sp, #32] ; 16-byte Folded Reload
+; CHECK-APPLE-ARM64_32-NEXT: ldp x22, x21, [sp, #16] ; 16-byte Folded Reload
+; CHECK-APPLE-ARM64_32-NEXT: add sp, sp, #64
; CHECK-APPLE-ARM64_32-NEXT: ret
;
; CHECK-O0-ARM64_32-LABEL: caller2:
@@ -501,26 +493,23 @@ normal:
define float @foo_loop(ptr swifterror %error_ptr_ref, i32 %cc, float %cc2) {
; CHECK-APPLE-LABEL: foo_loop:
; CHECK-APPLE: ; %bb.0: ; %entry
-; CHECK-APPLE-NEXT: stp d9, d8, [sp, #-48]! ; 16-byte Folded Spill
-; CHECK-APPLE-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill
-; CHECK-APPLE-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
-; CHECK-APPLE-NEXT: add x29, sp, #32
+; CHECK-APPLE-NEXT: str d8, [sp, #-32]! ; 8-byte Folded Spill
+; CHECK-APPLE-NEXT: str x19, [sp, #8] ; 8-byte Spill
+; CHECK-APPLE-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-APPLE-NEXT: add x29, sp, #16
; CHECK-APPLE-NEXT: .cfi_def_cfa w29, 16
; CHECK-APPLE-NEXT: .cfi_offset w30, -8
; CHECK-APPLE-NEXT: .cfi_offset w29, -16
; CHECK-APPLE-NEXT: .cfi_offset w19, -24
-; CHECK-APPLE-NEXT: .cfi_offset w20, -32
-; CHECK-APPLE-NEXT: .cfi_offset b8, -40
-; CHECK-APPLE-NEXT: .cfi_offset b9, -48
+; CHECK-APPLE-NEXT: .cfi_offset b8, -32
; CHECK-APPLE-NEXT: fmov s8, s0
; CHECK-APPLE-NEXT: mov w19, w0
; CHECK-APPLE-NEXT: mov x0, x21
-; CHECK-APPLE-NEXT: fmov s9, #1.00000000
-; CHECK-APPLE-NEXT: mov w20, #1 ; =0x1
; CHECK-APPLE-NEXT: b LBB4_2
; CHECK-APPLE-NEXT: LBB4_1: ; %bb_cont
; CHECK-APPLE-NEXT: ; in Loop: Header=BB4_2 Depth=1
-; CHECK-APPLE-NEXT: fcmp s8, s9
+; CHECK-APPLE-NEXT: fmov s0, #1.00000000
+; CHECK-APPLE-NEXT: fcmp s8, s0
; CHECK-APPLE-NEXT: b.gt LBB4_4
; CHECK-APPLE-NEXT: LBB4_2: ; %bb_loop
; CHECK-APPLE-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -529,14 +518,15 @@ define float @foo_loop(ptr swifterror %error_ptr_ref, i32 %cc, float %cc2) {
; CHECK-APPLE-NEXT: ; in Loop: Header=BB4_2 Depth=1
; CHECK-APPLE-NEXT: mov w0, #16 ; =0x10
; CHECK-APPLE-NEXT: bl _malloc
-; CHECK-APPLE-NEXT: strb w20, [x0, #8]
+; CHECK-APPLE-NEXT: mov w8, #1 ; =0x1
+; CHECK-APPLE-NEXT: strb w8, [x0, #8]
; CHECK-APPLE-NEXT: b LBB4_1
; CHECK-APPLE-NEXT: LBB4_4: ; %bb_end
; CHECK-APPLE-NEXT: movi d0, #0000000000000000
; CHECK-APPLE-NEXT: mov x21, x0
-; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
-; CHECK-APPLE-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload
-; CHECK-APPLE-NEXT: ldp d9, d8, [sp], #48 ; 16-byte Folded Reload
+; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-APPLE-NEXT: ldr x19, [sp, #8] ; 8-byte Reload
+; CHECK-APPLE-NEXT: ldr d8, [sp], #32 ; 8-byte Folded Reload
; CHECK-APPLE-NEXT: ret
;
; CHECK-O0-AARCH64-LABEL: foo_loop:
diff --git a/llvm/test/CodeGen/AArch64/swifttail-call.ll b/llvm/test/CodeGen/AArch64/swifttail-call.ll
index 01532b9e1cc5e..178d0da2bd98b 100644
--- a/llvm/test/CodeGen/AArch64/swifttail-call.ll
+++ b/llvm/test/CodeGen/AArch64/swifttail-call.ll
@@ -179,7 +179,7 @@ define void @fromC_totail() #0 {
define void @fromC_totail_noreservedframe(i32 %len) #0 {
; COMMON-LABEL: fromC_totail_noreservedframe:
-; COMMON: stp x29, x30, [sp, #-48]!
+; COMMON: stp x29, x30, [sp, #-32]!
; COMMON: mov w[[TMP:[0-9]+]], #42
; Note stack is subtracted here to allocate space for arg
@@ -232,4 +232,4 @@ define swiftcc ptr @CallSwiftSelf(ptr swiftself %closure, ptr %context) #0 {
ret ptr %res
}
-attributes #0 = { uwtable }
\ No newline at end of file
+attributes #0 = { uwtable }
diff --git a/llvm/test/CodeGen/AArch64/tailcc-tail-call.ll b/llvm/test/CodeGen/AArch64/tailcc-tail-call.ll
index a1482ac5d53cb..3d9f2f485056c 100644
--- a/llvm/test/CodeGen/AArch64/tailcc-tail-call.ll
+++ b/llvm/test/CodeGen/AArch64/tailcc-tail-call.ll
@@ -186,7 +186,7 @@ define void @fromC_totail() #0 {
define void @fromC_totail_noreservedframe(i32 %len) #0 {
; COMMON-LABEL: fromC_totail_noreservedframe:
-; COMMON: stp x29, x30, [sp, #-32]!
+; COMMON: stp x29, x30, [sp, #-16]!
; COMMON: mov w[[TMP:[0-9]+]], #42
; Note stack is subtracted here to allocate space for arg
@@ -229,4 +229,4 @@ define tailcc void @fromtail_toC() #0 {
ret void
}
-attributes #0 = { uwtable }
\ No newline at end of file
+attributes #0 = { uwtable }
diff --git a/llvm/test/CodeGen/AArch64/wineh-try-catch.ll b/llvm/test/CodeGen/AArch64/wineh-try-catch.ll
index 6bb22fca24591..8f7db747cfbe7 100644
--- a/llvm/test/CodeGen/AArch64/wineh-try-catch.ll
+++ b/llvm/test/CodeGen/AArch64/wineh-try-catch.ll
@@ -15,11 +15,10 @@
; We check this offset in the table later on.
; CHECK-LABEL: "?func@@YAHXZ":
-; CHECK: stp x19, x20, [sp, #-64]!
-; CHECK: str x21, [sp, #16]
-; CHECK: str x28, [sp, #24]
-; CHECK: stp x29, x30, [sp, #32]
-; CHECK: add x29, sp, #32
+; CHECK: str x19, [sp, #-48]!
+; CHECK: str x28, [sp, #8]
+; CHECK: stp x29, x30, [sp, #16]
+; CHECK: add x29, sp, #16
; CHECK: sub sp, sp, #608
; CHECK: mov x19, sp
; CHECK: mov x0, #-2
@@ -47,11 +46,10 @@
; CHECK-LABEL: "?catch$4@?0??func@@YAHXZ at 4HA":
; Check that the stack space is allocated only for the callee saved registers.
-; CHECK: stp x19, x20, [sp, #-48]!
-; CHECK: str x21, [sp, #16]
-; CHECK: str x28, [sp, #24]
-; CHECK: stp x29, x30, [sp, #32]
-; CHECK: add x20, x19, #0
+; CHECK: str x19, [sp, #-32]!
+; CHECK: str x28, [sp, #8]
+; CHECK: stp x29, x30, [sp, #16]
+; CHECK: add x0, x19, #0
; Check that there are no further stack updates.
; CHECK-NOT: sub sp, sp
@@ -85,18 +83,16 @@
; UNWIND: Function: ?func@@YAHXZ (0x0)
; UNWIND: Prologue [
-; UNWIND-NEXT: ; add fp, sp, #32
-; UNWIND-NEXT: ; stp x29, x30, [sp, #32]
-; UNWIND-NEXT: ; str x28, [sp, #24]
-; UNWIND-NEXT: ; str x21, [sp, #16]
-; UNWIND-NEXT: ; stp x19, x20, [sp, #-64]!
+; UNWIND-NEXT: ; add fp, sp, #16
+; UNWIND-NEXT: ; stp x29, x30, [sp, #16]
+; UNWIND-NEXT: ; str x28, [sp, #8]
+; UNWIND-NEXT: ; str x19, [sp, #-48]!
; UNWIND-NEXT: ; end
; UNWIND: Function: ?catch$4@?0??func@@YAHXZ at 4HA
; UNWIND: Prologue [
-; UNWIND-NEXT: ; stp x29, x30, [sp, #32]
-; UNWIND-NEXT: ; str x28, [sp, #24]
-; UNWIND-NEXT: ; str x21, [sp, #16]
-; UNWIND-NEXT: ; stp x19, x20, [sp, #-48]!
+; UNWIND-NEXT: ; stp x29, x30, [sp, #16]
+; UNWIND-NEXT: ; str x28, [sp, #8]
+; UNWIND-NEXT: ; str x19, [sp, #-32]!
; UNWIND-NEXT: ; end
target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 969a5bc71be7b..aed6752798697 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -63,13 +63,11 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-LABEL: log2_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a1, a0
-; RV64I-NEXT: li s0, 31
; RV64I-NEXT: beqz a1, .LBB1_2
; RV64I-NEXT: # %bb.1: # %cond.false
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
@@ -102,14 +100,14 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: li a1, 32
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: sub a0, a1, a0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: .LBB1_3: # %cond.end
-; RV64I-NEXT: subw a0, s0, a0
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: li a1, 31
+; RV64I-NEXT: subw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: log2_i32:
@@ -127,14 +125,12 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-LABEL: log2_ceil_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addiw a0, a0, -1
-; RV64I-NEXT: li s0, 32
; RV64I-NEXT: li a1, 32
; RV64I-NEXT: beqz a0, .LBB2_2
; RV64I-NEXT: # %bb.1: # %cond.false
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
@@ -167,11 +163,11 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: li a1, 32
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: sub a1, a1, a0
-; RV64I-NEXT: .LBB2_2: # %cond.end
-; RV64I-NEXT: subw a0, s0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: .LBB2_2: # %cond.end
+; RV64I-NEXT: li a0, 32
+; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: log2_ceil_i32:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
index 8f5c126d9e549..6874c079b7fec 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
@@ -1214,111 +1214,109 @@ define void @va3_caller() nounwind {
define iXLen @va4_va_copy(i32 %argno, ...) nounwind {
; RV32-LABEL: va4_va_copy:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -64
-; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw a1, 36(sp)
-; RV32-NEXT: sw a2, 40(sp)
-; RV32-NEXT: sw a3, 44(sp)
-; RV32-NEXT: sw a4, 48(sp)
-; RV32-NEXT: addi a0, sp, 36
-; RV32-NEXT: sw a5, 52(sp)
-; RV32-NEXT: sw a6, 56(sp)
-; RV32-NEXT: sw a7, 60(sp)
-; RV32-NEXT: sw a0, 16(sp)
-; RV32-NEXT: lw a0, 16(sp)
+; RV32-NEXT: addi sp, sp, -48
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw a1, 20(sp)
+; RV32-NEXT: sw a2, 24(sp)
+; RV32-NEXT: sw a3, 28(sp)
+; RV32-NEXT: sw a4, 32(sp)
+; RV32-NEXT: addi a0, sp, 20
+; RV32-NEXT: sw a5, 36(sp)
+; RV32-NEXT: sw a6, 40(sp)
+; RV32-NEXT: sw a7, 44(sp)
+; RV32-NEXT: sw a0, 4(sp)
+; RV32-NEXT: lw a0, 4(sp)
; RV32-NEXT: addi a0, a0, 3
-; RV32-NEXT: li s0, -4
-; RV32-NEXT: and a0, a0, s0
+; RV32-NEXT: li a1, -4
+; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: addi a1, a0, 4
-; RV32-NEXT: sw a1, 16(sp)
-; RV32-NEXT: lw a1, 16(sp)
-; RV32-NEXT: lw s1, 0(a0)
-; RV32-NEXT: sw a1, 12(sp)
-; RV32-NEXT: lw a0, 12(sp)
+; RV32-NEXT: sw a1, 4(sp)
+; RV32-NEXT: lw a1, 4(sp)
+; RV32-NEXT: lw s0, 0(a0)
+; RV32-NEXT: sw a1, 0(sp)
+; RV32-NEXT: lw a0, 0(sp)
; RV32-NEXT: call notdead
-; RV32-NEXT: lw a0, 16(sp)
+; RV32-NEXT: lw a0, 4(sp)
; RV32-NEXT: addi a0, a0, 3
-; RV32-NEXT: and a0, a0, s0
+; RV32-NEXT: li a2, -4
+; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: addi a1, a0, 4
-; RV32-NEXT: sw a1, 16(sp)
-; RV32-NEXT: lw a1, 16(sp)
+; RV32-NEXT: sw a1, 4(sp)
+; RV32-NEXT: lw a1, 4(sp)
; RV32-NEXT: addi a1, a1, 3
-; RV32-NEXT: and a1, a1, s0
+; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: addi a2, a1, 4
; RV32-NEXT: lw a0, 0(a0)
-; RV32-NEXT: sw a2, 16(sp)
-; RV32-NEXT: lw a2, 16(sp)
+; RV32-NEXT: sw a2, 4(sp)
+; RV32-NEXT: lw a2, 4(sp)
; RV32-NEXT: addi a2, a2, 3
; RV32-NEXT: andi a2, a2, -4
; RV32-NEXT: addi a3, a2, 4
; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: sw a3, 16(sp)
+; RV32-NEXT: sw a3, 4(sp)
; RV32-NEXT: lw a2, 0(a2)
-; RV32-NEXT: add a0, a0, s1
+; RV32-NEXT: add a0, a0, s0
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 64
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 48
; RV32-NEXT: ret
;
; RV64-LABEL: va4_va_copy:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -112
-; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd a1, 56(sp)
-; RV64-NEXT: sd a2, 64(sp)
-; RV64-NEXT: sd a3, 72(sp)
-; RV64-NEXT: sd a4, 80(sp)
-; RV64-NEXT: addi a0, sp, 56
-; RV64-NEXT: sd a5, 88(sp)
-; RV64-NEXT: sd a6, 96(sp)
-; RV64-NEXT: sd a7, 104(sp)
-; RV64-NEXT: sd a0, 16(sp)
-; RV64-NEXT: ld a0, 16(sp)
+; RV64-NEXT: addi sp, sp, -96
+; RV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd a1, 40(sp)
+; RV64-NEXT: sd a2, 48(sp)
+; RV64-NEXT: sd a3, 56(sp)
+; RV64-NEXT: sd a4, 64(sp)
+; RV64-NEXT: addi a0, sp, 40
+; RV64-NEXT: sd a5, 72(sp)
+; RV64-NEXT: sd a6, 80(sp)
+; RV64-NEXT: sd a7, 88(sp)
+; RV64-NEXT: sd a0, 8(sp)
+; RV64-NEXT: ld a0, 8(sp)
; RV64-NEXT: addi a0, a0, 7
-; RV64-NEXT: li s0, -8
-; RV64-NEXT: and a0, a0, s0
+; RV64-NEXT: li a1, -8
+; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: addi a1, a0, 8
-; RV64-NEXT: sd a1, 16(sp)
-; RV64-NEXT: ld a1, 16(sp)
-; RV64-NEXT: ld s1, 0(a0)
; RV64-NEXT: sd a1, 8(sp)
-; RV64-NEXT: lw a0, 12(sp)
-; RV64-NEXT: lwu a1, 8(sp)
+; RV64-NEXT: ld a1, 8(sp)
+; RV64-NEXT: ld s0, 0(a0)
+; RV64-NEXT: sd a1, 0(sp)
+; RV64-NEXT: lw a0, 4(sp)
+; RV64-NEXT: lwu a1, 0(sp)
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: call notdead
-; RV64-NEXT: ld a0, 16(sp)
+; RV64-NEXT: ld a0, 8(sp)
; RV64-NEXT: addi a0, a0, 7
-; RV64-NEXT: and a0, a0, s0
+; RV64-NEXT: li a2, -8
+; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: addi a1, a0, 8
-; RV64-NEXT: sd a1, 16(sp)
-; RV64-NEXT: ld a1, 16(sp)
+; RV64-NEXT: sd a1, 8(sp)
+; RV64-NEXT: ld a1, 8(sp)
; RV64-NEXT: addi a1, a1, 7
-; RV64-NEXT: and a1, a1, s0
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: addi a2, a1, 8
; RV64-NEXT: ld a0, 0(a0)
-; RV64-NEXT: sd a2, 16(sp)
-; RV64-NEXT: ld a2, 16(sp)
+; RV64-NEXT: sd a2, 8(sp)
+; RV64-NEXT: ld a2, 8(sp)
; RV64-NEXT: addi a2, a2, 7
; RV64-NEXT: andi a2, a2, -8
; RV64-NEXT: addi a3, a2, 8
; RV64-NEXT: ld a1, 0(a1)
-; RV64-NEXT: sd a3, 16(sp)
+; RV64-NEXT: sd a3, 8(sp)
; RV64-NEXT: ld a2, 0(a2)
-; RV64-NEXT: add a0, a0, s1
+; RV64-NEXT: add a0, a0, s0
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: add a0, a0, a1
-; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64-NEXT: addi sp, sp, 112
+; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 96
; RV64-NEXT: ret
;
; RV32-WITHFP-LABEL: va4_va_copy:
@@ -1327,7 +1325,6 @@ define iXLen @va4_va_copy(i32 %argno, ...) nounwind {
; RV32-WITHFP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32-WITHFP-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 32
; RV32-WITHFP-NEXT: sw a1, 36(sp)
; RV32-WITHFP-NEXT: sw a2, 40(sp)
@@ -1337,43 +1334,43 @@ define iXLen @va4_va_copy(i32 %argno, ...) nounwind {
; RV32-WITHFP-NEXT: sw a5, 52(sp)
; RV32-WITHFP-NEXT: sw a6, 56(sp)
; RV32-WITHFP-NEXT: sw a7, 60(sp)
-; RV32-WITHFP-NEXT: sw a0, 12(sp)
-; RV32-WITHFP-NEXT: lw a0, 12(sp)
+; RV32-WITHFP-NEXT: sw a0, 16(sp)
+; RV32-WITHFP-NEXT: lw a0, 16(sp)
; RV32-WITHFP-NEXT: addi a0, a0, 3
-; RV32-WITHFP-NEXT: li s1, -4
-; RV32-WITHFP-NEXT: and a0, a0, s1
+; RV32-WITHFP-NEXT: li a1, -4
+; RV32-WITHFP-NEXT: and a0, a0, a1
; RV32-WITHFP-NEXT: addi a1, a0, 4
+; RV32-WITHFP-NEXT: sw a1, 16(sp)
+; RV32-WITHFP-NEXT: lw a1, 16(sp)
+; RV32-WITHFP-NEXT: lw s1, 0(a0)
; RV32-WITHFP-NEXT: sw a1, 12(sp)
-; RV32-WITHFP-NEXT: lw a1, 12(sp)
-; RV32-WITHFP-NEXT: lw s2, 0(a0)
-; RV32-WITHFP-NEXT: sw a1, 8(sp)
-; RV32-WITHFP-NEXT: lw a0, 8(sp)
-; RV32-WITHFP-NEXT: call notdead
; RV32-WITHFP-NEXT: lw a0, 12(sp)
+; RV32-WITHFP-NEXT: call notdead
+; RV32-WITHFP-NEXT: lw a0, 16(sp)
; RV32-WITHFP-NEXT: addi a0, a0, 3
-; RV32-WITHFP-NEXT: and a0, a0, s1
+; RV32-WITHFP-NEXT: li a2, -4
+; RV32-WITHFP-NEXT: and a0, a0, a2
; RV32-WITHFP-NEXT: addi a1, a0, 4
-; RV32-WITHFP-NEXT: sw a1, 12(sp)
-; RV32-WITHFP-NEXT: lw a1, 12(sp)
+; RV32-WITHFP-NEXT: sw a1, 16(sp)
+; RV32-WITHFP-NEXT: lw a1, 16(sp)
; RV32-WITHFP-NEXT: addi a1, a1, 3
-; RV32-WITHFP-NEXT: and a1, a1, s1
+; RV32-WITHFP-NEXT: and a1, a1, a2
; RV32-WITHFP-NEXT: addi a2, a1, 4
; RV32-WITHFP-NEXT: lw a0, 0(a0)
-; RV32-WITHFP-NEXT: sw a2, 12(sp)
-; RV32-WITHFP-NEXT: lw a2, 12(sp)
+; RV32-WITHFP-NEXT: sw a2, 16(sp)
+; RV32-WITHFP-NEXT: lw a2, 16(sp)
; RV32-WITHFP-NEXT: addi a2, a2, 3
; RV32-WITHFP-NEXT: andi a2, a2, -4
; RV32-WITHFP-NEXT: addi a3, a2, 4
; RV32-WITHFP-NEXT: lw a1, 0(a1)
-; RV32-WITHFP-NEXT: sw a3, 12(sp)
+; RV32-WITHFP-NEXT: sw a3, 16(sp)
; RV32-WITHFP-NEXT: lw a2, 0(a2)
-; RV32-WITHFP-NEXT: add a0, a0, s2
+; RV32-WITHFP-NEXT: add a0, a0, s1
; RV32-WITHFP-NEXT: add a1, a1, a2
; RV32-WITHFP-NEXT: add a0, a0, a1
; RV32-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32-WITHFP-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 64
; RV32-WITHFP-NEXT: ret
;
@@ -1383,7 +1380,6 @@ define iXLen @va4_va_copy(i32 %argno, ...) nounwind {
; RV64-WITHFP-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64-WITHFP-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: addi s0, sp, 48
; RV64-WITHFP-NEXT: sd a1, 56(sp)
; RV64-WITHFP-NEXT: sd a2, 64(sp)
@@ -1393,46 +1389,46 @@ define iXLen @va4_va_copy(i32 %argno, ...) nounwind {
; RV64-WITHFP-NEXT: sd a5, 88(sp)
; RV64-WITHFP-NEXT: sd a6, 96(sp)
; RV64-WITHFP-NEXT: sd a7, 104(sp)
-; RV64-WITHFP-NEXT: sd a0, 8(sp)
-; RV64-WITHFP-NEXT: ld a0, 8(sp)
+; RV64-WITHFP-NEXT: sd a0, 16(sp)
+; RV64-WITHFP-NEXT: ld a0, 16(sp)
; RV64-WITHFP-NEXT: addi a0, a0, 7
-; RV64-WITHFP-NEXT: li s1, -8
-; RV64-WITHFP-NEXT: and a0, a0, s1
+; RV64-WITHFP-NEXT: li a1, -8
+; RV64-WITHFP-NEXT: and a0, a0, a1
; RV64-WITHFP-NEXT: addi a1, a0, 8
+; RV64-WITHFP-NEXT: sd a1, 16(sp)
+; RV64-WITHFP-NEXT: ld a1, 16(sp)
+; RV64-WITHFP-NEXT: ld s1, 0(a0)
; RV64-WITHFP-NEXT: sd a1, 8(sp)
-; RV64-WITHFP-NEXT: ld a1, 8(sp)
-; RV64-WITHFP-NEXT: ld s2, 0(a0)
-; RV64-WITHFP-NEXT: sd a1, 0(sp)
-; RV64-WITHFP-NEXT: lw a0, 4(sp)
-; RV64-WITHFP-NEXT: lwu a1, 0(sp)
+; RV64-WITHFP-NEXT: lw a0, 12(sp)
+; RV64-WITHFP-NEXT: lwu a1, 8(sp)
; RV64-WITHFP-NEXT: slli a0, a0, 32
; RV64-WITHFP-NEXT: or a0, a0, a1
; RV64-WITHFP-NEXT: call notdead
-; RV64-WITHFP-NEXT: ld a0, 8(sp)
+; RV64-WITHFP-NEXT: ld a0, 16(sp)
; RV64-WITHFP-NEXT: addi a0, a0, 7
-; RV64-WITHFP-NEXT: and a0, a0, s1
+; RV64-WITHFP-NEXT: li a2, -8
+; RV64-WITHFP-NEXT: and a0, a0, a2
; RV64-WITHFP-NEXT: addi a1, a0, 8
-; RV64-WITHFP-NEXT: sd a1, 8(sp)
-; RV64-WITHFP-NEXT: ld a1, 8(sp)
+; RV64-WITHFP-NEXT: sd a1, 16(sp)
+; RV64-WITHFP-NEXT: ld a1, 16(sp)
; RV64-WITHFP-NEXT: addi a1, a1, 7
-; RV64-WITHFP-NEXT: and a1, a1, s1
+; RV64-WITHFP-NEXT: and a1, a1, a2
; RV64-WITHFP-NEXT: addi a2, a1, 8
; RV64-WITHFP-NEXT: ld a0, 0(a0)
-; RV64-WITHFP-NEXT: sd a2, 8(sp)
-; RV64-WITHFP-NEXT: ld a2, 8(sp)
+; RV64-WITHFP-NEXT: sd a2, 16(sp)
+; RV64-WITHFP-NEXT: ld a2, 16(sp)
; RV64-WITHFP-NEXT: addi a2, a2, 7
; RV64-WITHFP-NEXT: andi a2, a2, -8
; RV64-WITHFP-NEXT: addi a3, a2, 8
; RV64-WITHFP-NEXT: ld a1, 0(a1)
-; RV64-WITHFP-NEXT: sd a3, 8(sp)
+; RV64-WITHFP-NEXT: sd a3, 16(sp)
; RV64-WITHFP-NEXT: ld a2, 0(a2)
-; RV64-WITHFP-NEXT: add a0, a0, s2
+; RV64-WITHFP-NEXT: add a0, a0, s1
; RV64-WITHFP-NEXT: add a1, a1, a2
; RV64-WITHFP-NEXT: add a0, a0, a1
; RV64-WITHFP-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64-WITHFP-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 112
; RV64-WITHFP-NEXT: ret
%vargs = alloca ptr
diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index 5a042a4b26c08..838ff3d6634dd 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -7581,7 +7581,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: beqz a1, .LBB61_5
@@ -7590,22 +7589,22 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_4
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: li s1, 2
; RV32I-NEXT: j .LBB61_3
; RV32I-NEXT: .LBB61_2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB61_3 Depth=1
-; RV32I-NEXT: sw a1, 0(sp)
-; RV32I-NEXT: mv a1, sp
+; RV32I-NEXT: sw a1, 4(sp)
+; RV32I-NEXT: addi a1, sp, 4
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a1, 0(sp)
+; RV32I-NEXT: lw a1, 4(sp)
; RV32I-NEXT: bnez a0, .LBB61_8
; RV32I-NEXT: .LBB61_3: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt a1, s1, .LBB61_2
+; RV32I-NEXT: li a0, 2
+; RV32I-NEXT: blt a1, a0, .LBB61_2
; RV32I-NEXT: # %bb.4: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB61_3 Depth=1
; RV32I-NEXT: li a2, 1
@@ -7622,7 +7621,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
@@ -7681,7 +7679,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: beqz a1, .LBB61_5
@@ -7690,23 +7687,23 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: li s1, 2
; RV64I-NEXT: j .LBB61_3
; RV64I-NEXT: .LBB61_2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB61_3 Depth=1
-; RV64I-NEXT: sw a1, 4(sp)
-; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: sw a1, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: lw a1, 12(sp)
; RV64I-NEXT: bnez a0, .LBB61_8
; RV64I-NEXT: .LBB61_3: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt a0, s1, .LBB61_2
+; RV64I-NEXT: li a3, 2
+; RV64I-NEXT: blt a0, a3, .LBB61_2
; RV64I-NEXT: # %bb.4: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB61_3 Depth=1
; RV64I-NEXT: li a2, 1
@@ -7723,7 +7720,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
@@ -7989,7 +7985,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: beqz a1, .LBB63_5
@@ -7998,22 +7993,22 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_4
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: li s1, 2
; RV32I-NEXT: j .LBB63_3
; RV32I-NEXT: .LBB63_2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB63_3 Depth=1
-; RV32I-NEXT: sw a1, 0(sp)
-; RV32I-NEXT: mv a1, sp
+; RV32I-NEXT: sw a1, 4(sp)
+; RV32I-NEXT: addi a1, sp, 4
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a1, 0(sp)
+; RV32I-NEXT: lw a1, 4(sp)
; RV32I-NEXT: bnez a0, .LBB63_8
; RV32I-NEXT: .LBB63_3: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu a1, s1, .LBB63_2
+; RV32I-NEXT: li a0, 2
+; RV32I-NEXT: bltu a1, a0, .LBB63_2
; RV32I-NEXT: # %bb.4: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB63_3 Depth=1
; RV32I-NEXT: li a2, 1
@@ -8031,7 +8026,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
@@ -8092,7 +8086,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: beqz a1, .LBB63_5
@@ -8101,23 +8094,23 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: li s1, 2
; RV64I-NEXT: j .LBB63_3
; RV64I-NEXT: .LBB63_2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB63_3 Depth=1
-; RV64I-NEXT: sw a1, 4(sp)
-; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: sw a1, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: lw a1, 12(sp)
; RV64I-NEXT: bnez a0, .LBB63_8
; RV64I-NEXT: .LBB63_3: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu a0, s1, .LBB63_2
+; RV64I-NEXT: li a3, 2
+; RV64I-NEXT: bltu a0, a3, .LBB63_2
; RV64I-NEXT: # %bb.4: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB63_3 Depth=1
; RV64I-NEXT: li a2, 1
@@ -8135,7 +8128,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 3c1cb9b554ac1..6b5914baf6f87 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -205,12 +205,11 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
;
; RV64I-LABEL: fcvt_w_d_sat:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, -497
; RV64I-NEXT: slli a1, a1, 53
@@ -219,7 +218,6 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixdfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lui s3, 524288
; RV64I-NEXT: bgez s2, .LBB3_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 524288
@@ -232,7 +230,8 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV64I-NEXT: call __gtdf2
; RV64I-NEXT: blez a0, .LBB3_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: addiw s1, s3, -1
+; RV64I-NEXT: lui s1, 524288
+; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: .LBB3_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -240,12 +239,11 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
@@ -837,12 +835,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
;
; RV64I-LABEL: fcvt_l_d_sat:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, -481
; RV64I-NEXT: slli a1, a1, 53
@@ -851,10 +848,10 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixdfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: li s3, -1
; RV64I-NEXT: bgez s2, .LBB12_2
; RV64I-NEXT: # %bb.1: # %start
-; RV64I-NEXT: slli s1, s3, 63
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: slli s1, s1, 63
; RV64I-NEXT: .LBB12_2: # %start
; RV64I-NEXT: li a0, 543
; RV64I-NEXT: slli a0, a0, 53
@@ -863,7 +860,8 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV64I-NEXT: call __gtdf2
; RV64I-NEXT: blez a0, .LBB12_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: srli s1, s3, 1
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: srli s1, s1, 1
; RV64I-NEXT: .LBB12_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -871,12 +869,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
@@ -2525,12 +2522,11 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
;
; RV64I-LABEL: fcvt_w_d_sat_sext:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, -497
; RV64I-NEXT: slli a1, a1, 53
@@ -2539,7 +2535,6 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixdfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lui s3, 524288
; RV64I-NEXT: bgez s2, .LBB34_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 524288
@@ -2552,7 +2547,8 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
; RV64I-NEXT: call __gtdf2
; RV64I-NEXT: blez a0, .LBB34_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: addi s1, s3, -1
+; RV64I-NEXT: lui s1, 524288
+; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: .LBB34_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -2561,12 +2557,11 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index b2a99d96dce62..0837f22437a75 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -65,12 +65,11 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
;
; RV32I-LABEL: fcvt_w_s_sat:
; RV32I: # %bb.0: # %start
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 847872
; RV32I-NEXT: call __gesf2
@@ -78,7 +77,6 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi
; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lui s3, 524288
; RV32I-NEXT: bgez s2, .LBB1_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 524288
@@ -89,7 +87,8 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB1_4
; RV32I-NEXT: # %bb.3: # %start
-; RV32I-NEXT: addi s1, s3, -1
+; RV32I-NEXT: lui s1, 524288
+; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: .LBB1_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
@@ -97,22 +96,20 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcvt_w_s_sat:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 847872
; RV64I-NEXT: call __gesf2
@@ -120,7 +117,6 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lui s3, 524288
; RV64I-NEXT: bgez s2, .LBB1_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 524288
@@ -131,7 +127,8 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB1_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: addiw s1, s3, -1
+; RV64I-NEXT: lui s1, 524288
+; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: .LBB1_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -139,12 +136,11 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
@@ -708,7 +704,6 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a1, 913408
; RV32I-NEXT: call __gesf2
@@ -717,7 +712,6 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32I-NEXT: call __fixsfdi
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: bgez s3, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s0, 524288
@@ -729,7 +723,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: blez a0, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start
-; RV32I-NEXT: addi s0, s5, -1
+; RV32I-NEXT: lui s0, 524288
+; RV32I-NEXT: addi s0, s0, -1
; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1
@@ -750,18 +745,16 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcvt_l_s_sat:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 913408
; RV64I-NEXT: call __gesf2
@@ -769,10 +762,10 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: li s3, -1
; RV64I-NEXT: bgez s2, .LBB12_2
; RV64I-NEXT: # %bb.1: # %start
-; RV64I-NEXT: slli s1, s3, 63
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: slli s1, s1, 63
; RV64I-NEXT: .LBB12_2: # %start
; RV64I-NEXT: lui a1, 389120
; RV64I-NEXT: addi a1, a1, -1
@@ -780,7 +773,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB12_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: srli s1, s3, 1
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: srli s1, s1, 1
; RV64I-NEXT: .LBB12_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -788,12 +782,11 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
%0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
@@ -2169,12 +2162,11 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
;
; RV32I-LABEL: fcvt_w_s_sat_sext:
; RV32I: # %bb.0: # %start
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 847872
; RV32I-NEXT: call __gesf2
@@ -2182,7 +2174,6 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi
; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lui s3, 524288
; RV32I-NEXT: bgez s2, .LBB32_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 524288
@@ -2193,7 +2184,8 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB32_4
; RV32I-NEXT: # %bb.3: # %start
-; RV32I-NEXT: addi s1, s3, -1
+; RV32I-NEXT: lui s1, 524288
+; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: .LBB32_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
@@ -2201,22 +2193,20 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcvt_w_s_sat_sext:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 847872
; RV64I-NEXT: call __gesf2
@@ -2224,7 +2214,6 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lui s3, 524288
; RV64I-NEXT: bgez s2, .LBB32_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 524288
@@ -2235,7 +2224,8 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB32_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: addi s1, s3, -1
+; RV64I-NEXT: lui s1, 524288
+; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: .LBB32_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -2244,12 +2234,11 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll
index a15ecc6a15878..6959938b22da2 100644
--- a/llvm/test/CodeGen/RISCV/forced-atomics.ll
+++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll
@@ -1472,27 +1472,26 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16
; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: mv s0, a0
; RV32-NO-ATOMIC-NEXT: li a1, 0
; RV32-NO-ATOMIC-NEXT: call __atomic_load_4
; RV32-NO-ATOMIC-NEXT: mv a1, a0
-; RV32-NO-ATOMIC-NEXT: li s1, 2
; RV32-NO-ATOMIC-NEXT: j .LBB24_2
; RV32-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp)
-; RV32-NO-ATOMIC-NEXT: mv a1, sp
+; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp)
+; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4
; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp)
+; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB24_4
; RV32-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NO-ATOMIC-NEXT: mv a2, a1
-; RV32-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1
+; RV32-NO-ATOMIC-NEXT: li a0, 2
+; RV32-NO-ATOMIC-NEXT: blt a1, a0, .LBB24_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1
@@ -1501,7 +1500,6 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16
; RV32-NO-ATOMIC-NEXT: ret
;
@@ -1530,28 +1528,27 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_4
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB24_2
; RV64-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp)
-; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4
+; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp)
+; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB24_4
; RV64-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: sext.w a0, a1
; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: blt a0, s1, .LBB24_1
+; RV64-NO-ATOMIC-NEXT: li a3, 2
+; RV64-NO-ATOMIC-NEXT: blt a0, a3, .LBB24_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -1560,7 +1557,6 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
@@ -1702,27 +1698,26 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16
; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: mv s0, a0
; RV32-NO-ATOMIC-NEXT: li a1, 0
; RV32-NO-ATOMIC-NEXT: call __atomic_load_4
; RV32-NO-ATOMIC-NEXT: mv a1, a0
-; RV32-NO-ATOMIC-NEXT: li s1, 2
; RV32-NO-ATOMIC-NEXT: j .LBB26_2
; RV32-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
-; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp)
-; RV32-NO-ATOMIC-NEXT: mv a1, sp
+; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp)
+; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4
; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp)
+; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB26_4
; RV32-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NO-ATOMIC-NEXT: mv a2, a1
-; RV32-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1
+; RV32-NO-ATOMIC-NEXT: li a0, 2
+; RV32-NO-ATOMIC-NEXT: bltu a1, a0, .LBB26_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1
@@ -1731,7 +1726,6 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16
; RV32-NO-ATOMIC-NEXT: ret
;
@@ -1760,28 +1754,27 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_4
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB26_2
; RV64-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp)
-; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4
+; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp)
+; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB26_4
; RV64-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: sext.w a0, a1
; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: bltu a0, s1, .LBB26_1
+; RV64-NO-ATOMIC-NEXT: li a3, 2
+; RV64-NO-ATOMIC-NEXT: bltu a0, a3, .LBB26_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -1790,7 +1783,6 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
@@ -3539,27 +3531,26 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_8
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB50_2
; RV64-NO-ATOMIC-NEXT: .LBB50_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp)
-; RV64-NO-ATOMIC-NEXT: mv a1, sp
+; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8
-; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp)
+; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB50_4
; RV64-NO-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB50_1
+; RV64-NO-ATOMIC-NEXT: li a0, 2
+; RV64-NO-ATOMIC-NEXT: blt a1, a0, .LBB50_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -3568,7 +3559,6 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
@@ -3738,27 +3728,26 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_8
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB52_2
; RV64-NO-ATOMIC-NEXT: .LBB52_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp)
-; RV64-NO-ATOMIC-NEXT: mv a1, sp
+; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8
-; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp)
+; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB52_4
; RV64-NO-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB52_1
+; RV64-NO-ATOMIC-NEXT: li a0, 2
+; RV64-NO-ATOMIC-NEXT: bltu a1, a0, .LBB52_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -3767,7 +3756,6 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 646b13c825195..fc94c36f0580d 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1195,12 +1195,11 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
;
; RV32I-LABEL: fcvt_w_h_sat:
; RV32I: # %bb.0: # %start
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2
@@ -1211,7 +1210,6 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi
; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lui s3, 524288
; RV32I-NEXT: bgez s2, .LBB5_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 524288
@@ -1222,7 +1220,8 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB5_4
; RV32I-NEXT: # %bb.3: # %start
-; RV32I-NEXT: addi s1, s3, -1
+; RV32I-NEXT: lui s1, 524288
+; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: .LBB5_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
@@ -1230,22 +1229,20 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcvt_w_h_sat:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2
@@ -1256,7 +1253,6 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lui s3, 524288
; RV64I-NEXT: bgez s2, .LBB5_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 524288
@@ -1267,7 +1263,8 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB5_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: addiw s1, s3, -1
+; RV64I-NEXT: lui s1, 524288
+; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: .LBB5_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -1275,12 +1272,11 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV32ID-ILP32-LABEL: fcvt_w_h_sat:
@@ -2358,7 +2354,6 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __extendhfsf2
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a1, 913408
@@ -2368,7 +2363,6 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32I-NEXT: call __fixsfdi
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: bgez s3, .LBB10_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 524288
@@ -2380,7 +2374,8 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: blez a0, .LBB10_4
; RV32I-NEXT: # %bb.3: # %start
-; RV32I-NEXT: addi s1, s5, -1
+; RV32I-NEXT: lui s1, 524288
+; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: .LBB10_4: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2
@@ -2401,18 +2396,16 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcvt_l_h_sat:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2
@@ -2423,10 +2416,10 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: li s3, -1
; RV64I-NEXT: bgez s2, .LBB10_2
; RV64I-NEXT: # %bb.1: # %start
-; RV64I-NEXT: slli s1, s3, 63
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: slli s1, s1, 63
; RV64I-NEXT: .LBB10_2: # %start
; RV64I-NEXT: lui a1, 389120
; RV64I-NEXT: addi a1, a1, -1
@@ -2434,7 +2427,8 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB10_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: srli s1, s3, 1
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: srli s1, s1, 1
; RV64I-NEXT: .LBB10_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -2442,12 +2436,11 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV32ID-ILP32-LABEL: fcvt_l_h_sat:
@@ -8445,12 +8438,11 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
;
; RV32I-LABEL: fcvt_w_h_sat_sext:
; RV32I: # %bb.0: # %start
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2
@@ -8461,7 +8453,6 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi
; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lui s3, 524288
; RV32I-NEXT: bgez s2, .LBB40_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 524288
@@ -8472,7 +8463,8 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB40_4
; RV32I-NEXT: # %bb.3: # %start
-; RV32I-NEXT: addi s1, s3, -1
+; RV32I-NEXT: lui s1, 524288
+; RV32I-NEXT: addi s1, s1, -1
; RV32I-NEXT: .LBB40_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
@@ -8480,22 +8472,20 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcvt_w_h_sat_sext:
; RV64I: # %bb.0: # %start
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2
@@ -8506,7 +8496,6 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi
; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lui s3, 524288
; RV64I-NEXT: bgez s2, .LBB40_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 524288
@@ -8517,7 +8506,8 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB40_4
; RV64I-NEXT: # %bb.3: # %start
-; RV64I-NEXT: addi s1, s3, -1
+; RV64I-NEXT: lui s1, 524288
+; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: .LBB40_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -8526,12 +8516,11 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV32ID-ILP32-LABEL: fcvt_w_h_sat_sext:
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll b/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
index a1a6fa1f62a54..d9a91630df7e1 100644
--- a/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
@@ -142,10 +142,9 @@ declare void @exit(i32 signext) noreturn
;
; RV64I-LABEL: main:
; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: addi sp, sp, -32
-; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: call t0, OUTLINED_FUNCTION_0
; RV64I-NEXT: call nge
; RV64I-NEXT: bnez a0, .LBB4_9
@@ -163,12 +162,13 @@ declare void @exit(i32 signext) noreturn
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call ngt
-; RV64I-NEXT: li s1, -1
-; RV64I-NEXT: bne a0, s1, .LBB4_9
+; RV64I-NEXT: li a1, -1
+; RV64I-NEXT: bne a0, a1, .LBB4_9
; RV64I-NEXT: # %bb.4: # %if.end12
; RV64I-NEXT: call t0, OUTLINED_FUNCTION_0
; RV64I-NEXT: call nle
-; RV64I-NEXT: bne a0, s1, .LBB4_9
+; RV64I-NEXT: li a1, -1
+; RV64I-NEXT: bne a0, a1, .LBB4_9
; RV64I-NEXT: # %bb.5: # %if.end16
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: mv a0, s0
diff --git a/llvm/test/CodeGen/RISCV/pr135206.ll b/llvm/test/CodeGen/RISCV/pr135206.ll
index ce462a0bf8cec..13f265b2fba4e 100644
--- a/llvm/test/CodeGen/RISCV/pr135206.ll
+++ b/llvm/test/CodeGen/RISCV/pr135206.ll
@@ -40,17 +40,17 @@ define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: addi s0, sp, 48
-; CHECK-NEXT: vse8.v v8, (s0)
+; CHECK-NEXT: addi s2, sp, 48
+; CHECK-NEXT: vse8.v v8, (s2)
; CHECK-NEXT: addi s1, sp, 32
; CHECK-NEXT: lui a0, 353637
; CHECK-NEXT: addi a0, a0, 1622
; CHECK-NEXT: vse8.v v8, (s1)
; CHECK-NEXT: slli a1, a0, 32
-; CHECK-NEXT: addi s2, sp, 16
+; CHECK-NEXT: addi s0, sp, 16
; CHECK-NEXT: add s3, a0, a1
; CHECK-NEXT: sd s3, 64(sp)
-; CHECK-NEXT: vse8.v v8, (s2)
+; CHECK-NEXT: vse8.v v8, (s0)
; CHECK-NEXT: call bar
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: lui a1, 8
@@ -58,10 +58,10 @@ define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vse8.v v8, (s0)
+; CHECK-NEXT: vse8.v v8, (s2)
; CHECK-NEXT: vse8.v v8, (s1)
; CHECK-NEXT: sd s3, 64(sp)
-; CHECK-NEXT: vse8.v v8, (s2)
+; CHECK-NEXT: vse8.v v8, (s0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: lui a1, 8
diff --git a/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
index 351408a7f085c..1fe08ba003fe2 100644
--- a/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
+++ b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
@@ -62,9 +62,7 @@ define signext i32 @test_loop() nounwind {
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: li s1, -16
-; RV64I-NEXT: lui s2, %hi(PL_reg_match_utf8)
; RV64I-NEXT: j .LBB1_2
; RV64I-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=1
; RV64I-NEXT: mv a0, s0
@@ -72,7 +70,8 @@ define signext i32 @test_loop() nounwind {
; RV64I-NEXT: addiw s1, s1, 1
; RV64I-NEXT: beqz s1, .LBB1_4
; RV64I-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(s2)
+; RV64I-NEXT: lui a0, %hi(PL_reg_match_utf8)
+; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(a0)
; RV64I-NEXT: beqz s0, .LBB1_1
; RV64I-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=1
; RV64I-NEXT: mv a0, s0
@@ -88,7 +87,6 @@ define signext i32 @test_loop() nounwind {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
br label %1
diff --git a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
index c399a1c3ca07f..7f5d4545d8985 100644
--- a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
+++ b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
@@ -13,39 +13,38 @@
define void @last_chance_recoloring_failure() {
; CHECK-LABEL: last_chance_recoloring_failure:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -32
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi sp, sp, -48
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8
-; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 16 * vlenb
; CHECK-NEXT: li a0, 55
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vloxseg2ei32.v v16, (a1), v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: li s0, 36
-; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
+; CHECK-NEXT: li a0, 36
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: addi a0, sp, 32
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: call func
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: addi a0, sp, 32
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
+; CHECK-NEXT: li a0, 36
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwsub.wv v8, v24, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, mu
; CHECK-NEXT: vfdiv.vv v8, v24, v8, v0.t
@@ -53,50 +52,47 @@ define void @last_chance_recoloring_failure() {
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: .cfi_def_cfa sp, 32
-; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: .cfi_def_cfa sp, 48
+; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: .cfi_restore ra
-; CHECK-NEXT: .cfi_restore s0
-; CHECK-NEXT: addi sp, sp, 32
+; CHECK-NEXT: addi sp, sp, 48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
; SUBREGLIVENESS-LABEL: last_chance_recoloring_failure:
; SUBREGLIVENESS: # %bb.0: # %entry
-; SUBREGLIVENESS-NEXT: addi sp, sp, -32
-; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32
-; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; SUBREGLIVENESS-NEXT: addi sp, sp, -48
+; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 48
+; SUBREGLIVENESS-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8
-; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
; SUBREGLIVENESS-NEXT: slli a0, a0, 4
; SUBREGLIVENESS-NEXT: sub sp, sp, a0
-; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
+; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 16 * vlenb
; SUBREGLIVENESS-NEXT: li a0, 55
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v16, (a1), v8
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
; SUBREGLIVENESS-NEXT: slli a0, a0, 3
; SUBREGLIVENESS-NEXT: add a0, sp, a0
-; SUBREGLIVENESS-NEXT: addi a0, a0, 16
+; SUBREGLIVENESS-NEXT: addi a0, a0, 32
; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; SUBREGLIVENESS-NEXT: li s0, 36
-; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
+; SUBREGLIVENESS-NEXT: li a0, 36
+; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; SUBREGLIVENESS-NEXT: vmclr.m v0
; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t
-; SUBREGLIVENESS-NEXT: addi a0, sp, 16
+; SUBREGLIVENESS-NEXT: addi a0, sp, 32
; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; SUBREGLIVENESS-NEXT: call func
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
; SUBREGLIVENESS-NEXT: slli a0, a0, 3
; SUBREGLIVENESS-NEXT: add a0, sp, a0
-; SUBREGLIVENESS-NEXT: addi a0, a0, 16
+; SUBREGLIVENESS-NEXT: addi a0, a0, 32
; SUBREGLIVENESS-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; SUBREGLIVENESS-NEXT: addi a0, sp, 16
+; SUBREGLIVENESS-NEXT: addi a0, sp, 32
; SUBREGLIVENESS-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
+; SUBREGLIVENESS-NEXT: li a0, 36
+; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v16
; SUBREGLIVENESS-NEXT: vsetvli zero, zero, e32, m8, tu, mu
; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v24, v8, v0.t
@@ -104,12 +100,10 @@ define void @last_chance_recoloring_failure() {
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
; SUBREGLIVENESS-NEXT: slli a0, a0, 4
; SUBREGLIVENESS-NEXT: add sp, sp, a0
-; SUBREGLIVENESS-NEXT: .cfi_def_cfa sp, 32
-; SUBREGLIVENESS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; SUBREGLIVENESS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; SUBREGLIVENESS-NEXT: .cfi_def_cfa sp, 48
+; SUBREGLIVENESS-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; SUBREGLIVENESS-NEXT: .cfi_restore ra
-; SUBREGLIVENESS-NEXT: .cfi_restore s0
-; SUBREGLIVENESS-NEXT: addi sp, sp, 32
+; SUBREGLIVENESS-NEXT: addi sp, sp, 48
; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 0
; SUBREGLIVENESS-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/remat.ll b/llvm/test/CodeGen/RISCV/remat.ll
index bfdaf30ea6fa7..45d1977520f6a 100644
--- a/llvm/test/CodeGen/RISCV/remat.ll
+++ b/llvm/test/CodeGen/RISCV/remat.ll
@@ -22,110 +22,98 @@
define i32 @test() nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -112
-; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: lui s0, %hi(a)
-; CHECK-NEXT: lw a0, %lo(a)(s0)
-; CHECK-NEXT: beqz a0, .LBB0_11
+; CHECK-NEXT: lui a0, %hi(a)
+; CHECK-NEXT: lw a0, %lo(a)(a0)
+; CHECK-NEXT: beqz a0, .LBB0_12
; CHECK-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-NEXT: lui s1, %hi(l)
-; CHECK-NEXT: lui s2, %hi(k)
-; CHECK-NEXT: lui s3, %hi(j)
-; CHECK-NEXT: lui s4, %hi(i)
-; CHECK-NEXT: lui s5, %hi(d)
-; CHECK-NEXT: lui s6, %hi(e)
-; CHECK-NEXT: lui s7, %hi(f)
-; CHECK-NEXT: lui s8, %hi(g)
-; CHECK-NEXT: lui s9, %hi(h)
-; CHECK-NEXT: lui s10, %hi(c)
-; CHECK-NEXT: lui s11, %hi(b)
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: lui s0, %hi(d)
+; CHECK-NEXT: lui s1, %hi(e)
; CHECK-NEXT: j .LBB0_3
; CHECK-NEXT: .LBB0_2: # %for.inc
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a0, %lo(a)(s0)
+; CHECK-NEXT: lui a1, %hi(a)
+; CHECK-NEXT: lw a0, %lo(a)(a1)
; CHECK-NEXT: addiw a0, a0, -1
-; CHECK-NEXT: sw a0, %lo(a)(s0)
+; CHECK-NEXT: sw a0, %lo(a)(a1)
; CHECK-NEXT: beqz a0, .LBB0_11
; CHECK-NEXT: .LBB0_3: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: lw a1, %lo(l)(s1)
+; CHECK-NEXT: lui a1, %hi(l)
+; CHECK-NEXT: lw a1, %lo(l)(a1)
; CHECK-NEXT: beqz a1, .LBB0_5
; CHECK-NEXT: # %bb.4: # %if.then
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a4, %lo(e)(s6)
-; CHECK-NEXT: lw a3, %lo(d)(s5)
-; CHECK-NEXT: lw a2, %lo(c)(s10)
-; CHECK-NEXT: lw a1, %lo(b)(s11)
+; CHECK-NEXT: lw a4, %lo(e)(s1)
+; CHECK-NEXT: lw a3, %lo(d)(s0)
+; CHECK-NEXT: lui a1, %hi(c)
+; CHECK-NEXT: lw a2, %lo(c)(a1)
+; CHECK-NEXT: lui a1, %hi(b)
+; CHECK-NEXT: lw a1, %lo(b)(a1)
; CHECK-NEXT: li a5, 32
; CHECK-NEXT: call foo
; CHECK-NEXT: .LBB0_5: # %if.end
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a0, %lo(k)(s2)
+; CHECK-NEXT: lui a0, %hi(k)
+; CHECK-NEXT: lw a0, %lo(k)(a0)
; CHECK-NEXT: beqz a0, .LBB0_7
; CHECK-NEXT: # %bb.6: # %if.then3
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a4, %lo(f)(s7)
-; CHECK-NEXT: lw a3, %lo(e)(s6)
-; CHECK-NEXT: lw a2, %lo(d)(s5)
-; CHECK-NEXT: lw a1, %lo(c)(s10)
-; CHECK-NEXT: lw a0, %lo(b)(s11)
+; CHECK-NEXT: lui a0, %hi(f)
+; CHECK-NEXT: lw a4, %lo(f)(a0)
+; CHECK-NEXT: lw a3, %lo(e)(s1)
+; CHECK-NEXT: lw a2, %lo(d)(s0)
+; CHECK-NEXT: lui a0, %hi(c)
+; CHECK-NEXT: lw a1, %lo(c)(a0)
+; CHECK-NEXT: lui a0, %hi(b)
+; CHECK-NEXT: lw a0, %lo(b)(a0)
; CHECK-NEXT: li a5, 64
; CHECK-NEXT: call foo
; CHECK-NEXT: .LBB0_7: # %if.end5
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a0, %lo(j)(s3)
+; CHECK-NEXT: lui a0, %hi(j)
+; CHECK-NEXT: lw a0, %lo(j)(a0)
; CHECK-NEXT: beqz a0, .LBB0_9
; CHECK-NEXT: # %bb.8: # %if.then7
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a4, %lo(g)(s8)
-; CHECK-NEXT: lw a3, %lo(f)(s7)
-; CHECK-NEXT: lw a2, %lo(e)(s6)
-; CHECK-NEXT: lw a1, %lo(d)(s5)
-; CHECK-NEXT: lw a0, %lo(c)(s10)
+; CHECK-NEXT: lui a0, %hi(g)
+; CHECK-NEXT: lw a4, %lo(g)(a0)
+; CHECK-NEXT: lui a0, %hi(f)
+; CHECK-NEXT: lw a3, %lo(f)(a0)
+; CHECK-NEXT: lw a2, %lo(e)(s1)
+; CHECK-NEXT: lw a1, %lo(d)(s0)
+; CHECK-NEXT: lui a0, %hi(c)
+; CHECK-NEXT: lw a0, %lo(c)(a0)
; CHECK-NEXT: li a5, 32
; CHECK-NEXT: call foo
; CHECK-NEXT: .LBB0_9: # %if.end9
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a0, %lo(i)(s4)
+; CHECK-NEXT: lui a0, %hi(i)
+; CHECK-NEXT: lw a0, %lo(i)(a0)
; CHECK-NEXT: beqz a0, .LBB0_2
; CHECK-NEXT: # %bb.10: # %if.then11
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
-; CHECK-NEXT: lw a4, %lo(h)(s9)
-; CHECK-NEXT: lw a3, %lo(g)(s8)
-; CHECK-NEXT: lw a2, %lo(f)(s7)
-; CHECK-NEXT: lw a1, %lo(e)(s6)
-; CHECK-NEXT: lw a0, %lo(d)(s5)
+; CHECK-NEXT: lui a0, %hi(h)
+; CHECK-NEXT: lw a4, %lo(h)(a0)
+; CHECK-NEXT: lui a0, %hi(g)
+; CHECK-NEXT: lw a3, %lo(g)(a0)
+; CHECK-NEXT: lui a0, %hi(f)
+; CHECK-NEXT: lw a2, %lo(f)(a0)
+; CHECK-NEXT: lw a1, %lo(e)(s1)
+; CHECK-NEXT: lw a0, %lo(d)(s0)
; CHECK-NEXT: li a5, 32
; CHECK-NEXT: call foo
; CHECK-NEXT: j .LBB0_2
-; CHECK-NEXT: .LBB0_11: # %for.end
+; CHECK-NEXT: .LBB0_11:
+; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 32
+; CHECK-NEXT: .LBB0_12: # %for.end
; CHECK-NEXT: li a0, 1
-; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 112
; CHECK-NEXT: ret
entry:
%.pr = load i32, ptr @a, align 4
diff --git a/llvm/test/CodeGen/RISCV/rv64-double-convert.ll b/llvm/test/CodeGen/RISCV/rv64-double-convert.ll
index bc0a5af35208e..255ab2f0d0fea 100644
--- a/llvm/test/CodeGen/RISCV/rv64-double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-double-convert.ll
@@ -61,14 +61,13 @@ define double @uitofp_i128_to_f64(i128 %a) nounwind {
define i128 @fptosi_sat_f64_to_i128(double %a) nounwind {
; RV64I-LABEL: fptosi_sat_f64_to_i128:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, -449
; RV64I-NEXT: slli a1, a1, 53
@@ -78,10 +77,10 @@ define i128 @fptosi_sat_f64_to_i128(double %a) nounwind {
; RV64I-NEXT: call __fixdfti
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: li s5, -1
; RV64I-NEXT: bgez s3, .LBB4_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: slli s1, s5, 63
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: slli s1, s1, 63
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: li a0, 575
; RV64I-NEXT: slli a0, a0, 53
@@ -91,7 +90,8 @@ define i128 @fptosi_sat_f64_to_i128(double %a) nounwind {
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: blez a0, .LBB4_4
; RV64I-NEXT: # %bb.3:
-; RV64I-NEXT: srli s1, s5, 1
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: srli s1, s1, 1
; RV64I-NEXT: .LBB4_4:
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -106,14 +106,13 @@ define i128 @fptosi_sat_f64_to_i128(double %a) nounwind {
; RV64I-NEXT: or a2, a2, a1
; RV64I-NEXT: and a1, a0, s1
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64ID-LABEL: fptosi_sat_f64_to_i128:
diff --git a/llvm/test/CodeGen/RISCV/rv64-float-convert.ll b/llvm/test/CodeGen/RISCV/rv64-float-convert.ll
index df9a3da095729..3efd825a6b14a 100644
--- a/llvm/test/CodeGen/RISCV/rv64-float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-float-convert.ll
@@ -61,14 +61,13 @@ define float @uitofp_i128_to_f32(i128 %a) nounwind {
define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
; RV64I-LABEL: fptosi_sat_f32_to_i128:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 1044480
; RV64I-NEXT: call __gesf2
@@ -77,10 +76,10 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
; RV64I-NEXT: call __fixsfti
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: li s5, -1
; RV64I-NEXT: bgez s3, .LBB4_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: slli s1, s5, 63
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: slli s1, s1, 63
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: lui a1, 520192
; RV64I-NEXT: addi a1, a1, -1
@@ -89,7 +88,8 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: blez a0, .LBB4_4
; RV64I-NEXT: # %bb.3:
-; RV64I-NEXT: srli s1, s5, 1
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: srli s1, s1, 1
; RV64I-NEXT: .LBB4_4:
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@@ -104,14 +104,13 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
; RV64I-NEXT: or a2, a2, a1
; RV64I-NEXT: and a1, a0, s1
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IF-LABEL: fptosi_sat_f32_to_i128:
diff --git a/llvm/test/CodeGen/RISCV/rv64-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64-half-convert.ll
index 8f101741375be..15241fe0253a9 100644
--- a/llvm/test/CodeGen/RISCV/rv64-half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-half-convert.ll
@@ -137,14 +137,13 @@ define i128 @fptoui_f16_to_i128(half %a) nounwind {
define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
; RV64I-LABEL: fptosi_sat_f16_to_i128:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: lui a1, 1044480
@@ -154,10 +153,10 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
; RV64I-NEXT: call __fixsfti
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: li s5, -1
; RV64I-NEXT: bgez s3, .LBB4_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: slli s1, s5, 63
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: slli s1, s1, 63
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: lui a1, 520192
; RV64I-NEXT: addi a1, a1, -1
@@ -166,7 +165,8 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: blez a0, .LBB4_4
; RV64I-NEXT: # %bb.3:
-; RV64I-NEXT: srli s1, s5, 1
+; RV64I-NEXT: li s1, -1
+; RV64I-NEXT: srli s1, s1, 1
; RV64I-NEXT: .LBB4_4:
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s2
@@ -181,14 +181,13 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
; RV64I-NEXT: or a2, a2, a1
; RV64I-NEXT: and a1, a0, s1
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IZFH-LABEL: fptosi_sat_f16_to_i128:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
index 534eb5ca75fc4..39a3bb0ae73a1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
@@ -246,10 +246,8 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vsca
; RV64-NEXT: .cfi_def_cfa_offset 256
; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
-; RV64-NEXT: sd s1, 232(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: .cfi_offset s0, -16
-; RV64-NEXT: .cfi_offset s1, -24
; RV64-NEXT: addi s0, sp, 256
; RV64-NEXT: .cfi_def_cfa s0, 0
; RV64-NEXT: andi sp, sp, -128
@@ -258,21 +256,20 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vsca
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vmv.v.i v0, 1
; RV64-NEXT: vslidedown.vi v18, v15, 1, v0.t
-; RV64-NEXT: mv s1, sp
-; RV64-NEXT: vs8r.v v16, (s1)
+; RV64-NEXT: mv a1, sp
+; RV64-NEXT: vs8r.v v16, (a1)
; RV64-NEXT: andi a0, a0, 15
; RV64-NEXT: li a1, 8
; RV64-NEXT: call __muldi3
-; RV64-NEXT: add a0, s1, a0
+; RV64-NEXT: mv a1, sp
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: ld a0, 0(a0)
; RV64-NEXT: addi sp, s0, -256
; RV64-NEXT: .cfi_def_cfa sp, 256
; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
-; RV64-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
; RV64-NEXT: .cfi_restore ra
; RV64-NEXT: .cfi_restore s0
-; RV64-NEXT: .cfi_restore s1
; RV64-NEXT: addi sp, sp, 256
; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/localvar.ll b/llvm/test/CodeGen/RISCV/rvv/localvar.ll
index f7c921c487e63..88b6e05bba22a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/localvar.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/localvar.ll
@@ -210,10 +210,8 @@ define void @local_var_m2_with_varsize_object(i64 %n) {
; RV64IV-NEXT: .cfi_def_cfa_offset 32
; RV64IV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64IV-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IV-NEXT: .cfi_offset ra, -8
; RV64IV-NEXT: .cfi_offset s0, -16
-; RV64IV-NEXT: .cfi_offset s1, -24
; RV64IV-NEXT: addi s0, sp, 32
; RV64IV-NEXT: .cfi_def_cfa s0, 0
; RV64IV-NEXT: csrr a1, vlenb
@@ -227,12 +225,12 @@ define void @local_var_m2_with_varsize_object(i64 %n) {
; RV64IV-NEXT: slli a1, a1, 1
; RV64IV-NEXT: sub a1, s0, a1
; RV64IV-NEXT: addi a1, a1, -32
-; RV64IV-NEXT: csrr s1, vlenb
-; RV64IV-NEXT: slli s1, s1, 1
-; RV64IV-NEXT: sub s1, s0, s1
-; RV64IV-NEXT: addi s1, s1, -32
; RV64IV-NEXT: call notdead
-; RV64IV-NEXT: vl2r.v v8, (s1)
+; RV64IV-NEXT: csrr a0, vlenb
+; RV64IV-NEXT: slli a0, a0, 1
+; RV64IV-NEXT: sub a0, s0, a0
+; RV64IV-NEXT: addi a0, a0, -32
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub a0, s0, a0
@@ -242,10 +240,8 @@ define void @local_var_m2_with_varsize_object(i64 %n) {
; RV64IV-NEXT: .cfi_def_cfa sp, 32
; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64IV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64IV-NEXT: .cfi_restore ra
; RV64IV-NEXT: .cfi_restore s0
-; RV64IV-NEXT: .cfi_restore s1
; RV64IV-NEXT: addi sp, sp, 32
; RV64IV-NEXT: .cfi_def_cfa_offset 0
; RV64IV-NEXT: ret
@@ -261,17 +257,15 @@ define void @local_var_m2_with_varsize_object(i64 %n) {
define void @local_var_m2_with_bp(i64 %n) {
; RV64IV-LABEL: local_var_m2_with_bp:
; RV64IV: # %bb.0:
-; RV64IV-NEXT: addi sp, sp, -256
-; RV64IV-NEXT: .cfi_def_cfa_offset 256
-; RV64IV-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
-; RV64IV-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
-; RV64IV-NEXT: sd s1, 232(sp) # 8-byte Folded Spill
-; RV64IV-NEXT: sd s2, 224(sp) # 8-byte Folded Spill
+; RV64IV-NEXT: addi sp, sp, -272
+; RV64IV-NEXT: .cfi_def_cfa_offset 272
+; RV64IV-NEXT: sd ra, 264(sp) # 8-byte Folded Spill
+; RV64IV-NEXT: sd s0, 256(sp) # 8-byte Folded Spill
+; RV64IV-NEXT: sd s1, 248(sp) # 8-byte Folded Spill
; RV64IV-NEXT: .cfi_offset ra, -8
; RV64IV-NEXT: .cfi_offset s0, -16
; RV64IV-NEXT: .cfi_offset s1, -24
-; RV64IV-NEXT: .cfi_offset s2, -32
-; RV64IV-NEXT: addi s0, sp, 256
+; RV64IV-NEXT: addi s0, sp, 272
; RV64IV-NEXT: .cfi_def_cfa s0, 0
; RV64IV-NEXT: csrr a1, vlenb
; RV64IV-NEXT: slli a1, a1, 2
@@ -286,28 +280,26 @@ define void @local_var_m2_with_bp(i64 %n) {
; RV64IV-NEXT: csrr a2, vlenb
; RV64IV-NEXT: slli a2, a2, 1
; RV64IV-NEXT: add a2, s1, a2
-; RV64IV-NEXT: addi a2, a2, 224
-; RV64IV-NEXT: csrr s2, vlenb
-; RV64IV-NEXT: slli s2, s2, 1
-; RV64IV-NEXT: add s2, s1, s2
-; RV64IV-NEXT: addi s2, s2, 224
+; RV64IV-NEXT: addi a2, a2, 240
; RV64IV-NEXT: call notdead2
; RV64IV-NEXT: lw zero, 124(s1)
-; RV64IV-NEXT: vl2r.v v8, (s2)
-; RV64IV-NEXT: addi a0, s1, 224
+; RV64IV-NEXT: csrr a0, vlenb
+; RV64IV-NEXT: slli a0, a0, 1
+; RV64IV-NEXT: add a0, s1, a0
+; RV64IV-NEXT: addi a0, a0, 240
+; RV64IV-NEXT: vl2r.v v8, (a0)
+; RV64IV-NEXT: addi a0, s1, 240
; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: lw zero, 120(s1)
-; RV64IV-NEXT: addi sp, s0, -256
-; RV64IV-NEXT: .cfi_def_cfa sp, 256
-; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
-; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
-; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
-; RV64IV-NEXT: ld s2, 224(sp) # 8-byte Folded Reload
+; RV64IV-NEXT: addi sp, s0, -272
+; RV64IV-NEXT: .cfi_def_cfa sp, 272
+; RV64IV-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
+; RV64IV-NEXT: ld s0, 256(sp) # 8-byte Folded Reload
+; RV64IV-NEXT: ld s1, 248(sp) # 8-byte Folded Reload
; RV64IV-NEXT: .cfi_restore ra
; RV64IV-NEXT: .cfi_restore s0
; RV64IV-NEXT: .cfi_restore s1
-; RV64IV-NEXT: .cfi_restore s2
-; RV64IV-NEXT: addi sp, sp, 256
+; RV64IV-NEXT: addi sp, sp, 272
; RV64IV-NEXT: .cfi_def_cfa_offset 0
; RV64IV-NEXT: ret
%1 = alloca i8, i64 %n
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
index 3e43bb68c79b9..5a6c2ee338140 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
@@ -64,80 +64,86 @@ entry:
define dso_local signext i32 @main() #0 {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -112
-; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
-; CHECK-NEXT: addi s0, sp, 112
+; CHECK-NEXT: addi sp, sp, -96
+; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi s0, sp, 96
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: sw zero, -36(s0)
+; CHECK-NEXT: sw zero, -28(s0)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: addi a0, s0, -64
+; CHECK-NEXT: addi a0, s0, -48
; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vsetivli a1, 4, e32, m8, ta, ma
-; CHECK-NEXT: sd a1, -72(s0)
-; CHECK-NEXT: ld a1, -72(s0)
+; CHECK-NEXT: sd a1, -56(s0)
+; CHECK-NEXT: ld a1, -56(s0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: csrr s1, vlenb
-; CHECK-NEXT: slli s1, s1, 3
-; CHECK-NEXT: sub s1, s0, s1
-; CHECK-NEXT: addi s1, s1, -112
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a1, s0, a1
+; CHECK-NEXT: addi a1, a1, -96
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vse32.v v8, (s1)
+; CHECK-NEXT: vse32.v v8, (a1)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a2, s0, a2
+; CHECK-NEXT: addi a2, a2, -96
; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: sw a0, -60(s0)
+; CHECK-NEXT: sw a0, -64(s0)
+; CHECK-NEXT: sw a0, -68(s0)
+; CHECK-NEXT: sw a0, -72(s0)
; CHECK-NEXT: sw a0, -76(s0)
; CHECK-NEXT: sw a0, -80(s0)
; CHECK-NEXT: sw a0, -84(s0)
; CHECK-NEXT: sw a0, -88(s0)
; CHECK-NEXT: sw a0, -92(s0)
; CHECK-NEXT: sw a0, -96(s0)
-; CHECK-NEXT: sw a0, -100(s0)
-; CHECK-NEXT: sw a0, -104(s0)
-; CHECK-NEXT: sw a0, -108(s0)
-; CHECK-NEXT: sw a0, -112(s0)
-; CHECK-NEXT: lw a0, -76(s0)
-; CHECK-NEXT: lw a1, -80(s0)
-; CHECK-NEXT: vle32.v v8, (s1)
-; CHECK-NEXT: lw a2, -84(s0)
-; CHECK-NEXT: lw a3, -88(s0)
-; CHECK-NEXT: lw a4, -92(s0)
-; CHECK-NEXT: lw a5, -96(s0)
-; CHECK-NEXT: lw a6, -100(s0)
-; CHECK-NEXT: lw a7, -104(s0)
-; CHECK-NEXT: lw t0, -108(s0)
-; CHECK-NEXT: lw t1, -112(s0)
+; CHECK-NEXT: lw a0, -60(s0)
+; CHECK-NEXT: lw a1, -64(s0)
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: lw a2, -68(s0)
+; CHECK-NEXT: lw a3, -72(s0)
+; CHECK-NEXT: lw a4, -76(s0)
+; CHECK-NEXT: lw a5, -80(s0)
+; CHECK-NEXT: lw a6, -84(s0)
+; CHECK-NEXT: lw a7, -88(s0)
+; CHECK-NEXT: lw t0, -92(s0)
+; CHECK-NEXT: lw t1, -96(s0)
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd t1, 8(sp)
; CHECK-NEXT: sd t0, 0(sp)
; CHECK-NEXT: call lots_args
; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: lw a0, -76(s0)
-; CHECK-NEXT: lw a1, -80(s0)
+; CHECK-NEXT: lw a0, -60(s0)
+; CHECK-NEXT: lw a1, -64(s0)
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vle32.v v8, (s1)
-; CHECK-NEXT: lw a2, -84(s0)
-; CHECK-NEXT: lw a3, -88(s0)
-; CHECK-NEXT: lw a4, -92(s0)
-; CHECK-NEXT: lw a5, -96(s0)
-; CHECK-NEXT: lw a6, -100(s0)
-; CHECK-NEXT: lw a7, -104(s0)
-; CHECK-NEXT: lw t0, -108(s0)
-; CHECK-NEXT: lw t1, -112(s0)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a2, s0, a2
+; CHECK-NEXT: addi a2, a2, -96
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: lw a2, -68(s0)
+; CHECK-NEXT: lw a3, -72(s0)
+; CHECK-NEXT: lw a4, -76(s0)
+; CHECK-NEXT: lw a5, -80(s0)
+; CHECK-NEXT: lw a6, -84(s0)
+; CHECK-NEXT: lw a7, -88(s0)
+; CHECK-NEXT: lw t0, -92(s0)
+; CHECK-NEXT: lw t1, -96(s0)
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd t1, 8(sp)
; CHECK-NEXT: sd t0, 0(sp)
; CHECK-NEXT: call lots_args
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: addi sp, s0, -112
-; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 112
+; CHECK-NEXT: addi sp, s0, -96
+; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret
entry:
%retval = alloca i32, align 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll b/llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll
index bb1079cced273..b196614237510 100644
--- a/llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll
@@ -391,39 +391,36 @@ define void @v2i8_v4i8(ptr %p, ptr %q) {
define void @v16i8_v32i8(ptr %p, ptr %q) {
; CHECK-LABEL: v16i8_v32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -64
-; CHECK-NEXT: .cfi_def_cfa_offset 64
-; CHECK-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16
-; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
-; CHECK-NEXT: li s1, 32
-; CHECK-NEXT: vsetvli zero, s1, e8, m2, ta, ma
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 2 * vlenb
+; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 32
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: call g
-; CHECK-NEXT: addi a0, sp, 32
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, s1, e8, m2, ta, ma
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vse8.v v8, (s0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: sh1add sp, a0, sp
-; CHECK-NEXT: .cfi_def_cfa sp, 64
-; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT: .cfi_def_cfa sp, 32
+; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: .cfi_restore ra
; CHECK-NEXT: .cfi_restore s0
-; CHECK-NEXT: .cfi_restore s1
-; CHECK-NEXT: addi sp, sp, 64
+; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
%p0 = getelementptr i8, ptr %p, i64 0
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index f54332133a776..735e10ab6d40b 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -462,18 +462,16 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: sraw a0, a0, a1
-; CHECK-NEXT: li s0, 254
; CHECK-NEXT: .LBB8_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: call bar
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slti a0, a0, 255
-; CHECK-NEXT: blt s0, a1, .LBB8_1
+; CHECK-NEXT: li a2, 254
+; CHECK-NEXT: blt a2, a1, .LBB8_1
; CHECK-NEXT: # %bb.2: # %bb7
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
@@ -481,18 +479,16 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind {
; NOREMOVAL: # %bb.0: # %bb
; NOREMOVAL-NEXT: addi sp, sp, -16
; NOREMOVAL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; NOREMOVAL-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; NOREMOVAL-NEXT: sraw a1, a0, a1
-; NOREMOVAL-NEXT: li s0, 254
; NOREMOVAL-NEXT: .LBB8_1: # %bb2
; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1
; NOREMOVAL-NEXT: sext.w a0, a1
; NOREMOVAL-NEXT: call bar
; NOREMOVAL-NEXT: slti a1, a0, 255
-; NOREMOVAL-NEXT: blt s0, a0, .LBB8_1
+; NOREMOVAL-NEXT: li a2, 254
+; NOREMOVAL-NEXT: blt a2, a0, .LBB8_1
; NOREMOVAL-NEXT: # %bb.2: # %bb7
; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; NOREMOVAL-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; NOREMOVAL-NEXT: addi sp, sp, 16
; NOREMOVAL-NEXT: ret
bb:
diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll
index e06673d44ea75..a7cbbfb5b17c2 100644
--- a/llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -174,103 +174,99 @@ define void @li_straightline_a(i32 zeroext %a, i32 zeroext %b) {
; RV32I-SW-NO-NEXT: .cfi_def_cfa_offset 16
; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NO-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-SW-NO-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-SW-NO-NEXT: .cfi_offset ra, -4
; RV32I-SW-NO-NEXT: .cfi_offset s0, -8
-; RV32I-SW-NO-NEXT: .cfi_offset s1, -12
-; RV32I-SW-NO-NEXT: li s1, 57
-; RV32I-SW-NO-NEXT: beq a0, s1, .LBB2_3
+; RV32I-SW-NO-NEXT: li a2, 57
+; RV32I-SW-NO-NEXT: beq a0, a2, .LBB2_3
; RV32I-SW-NO-NEXT: # %bb.1: # %do_call
; RV32I-SW-NO-NEXT: mv s0, a1
; RV32I-SW-NO-NEXT: call foo
-; RV32I-SW-NO-NEXT: beq s0, s1, .LBB2_3
+; RV32I-SW-NO-NEXT: li a0, 57
+; RV32I-SW-NO-NEXT: beq s0, a0, .LBB2_3
; RV32I-SW-NO-NEXT: # %bb.2: # %do_call2
; RV32I-SW-NO-NEXT: call foo
; RV32I-SW-NO-NEXT: .LBB2_3: # %exit
; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-SW-NO-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: .cfi_restore ra
; RV32I-SW-NO-NEXT: .cfi_restore s0
-; RV32I-SW-NO-NEXT: .cfi_restore s1
; RV32I-SW-NO-NEXT: addi sp, sp, 16
; RV32I-SW-NO-NEXT: .cfi_def_cfa_offset 0
; RV32I-SW-NO-NEXT: ret
;
; RV32I-SW-LABEL: li_straightline_a:
; RV32I-SW: # %bb.0:
+; RV32I-SW-NEXT: li a2, 57
+; RV32I-SW-NEXT: beq a0, a2, .LBB2_4
+; RV32I-SW-NEXT: # %bb.1: # %do_call
; RV32I-SW-NEXT: addi sp, sp, -16
; RV32I-SW-NEXT: .cfi_def_cfa_offset 16
; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-SW-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: .cfi_offset ra, -4
; RV32I-SW-NEXT: .cfi_offset s0, -8
-; RV32I-SW-NEXT: .cfi_offset s1, -12
-; RV32I-SW-NEXT: li s1, 57
-; RV32I-SW-NEXT: beq a0, s1, .LBB2_3
-; RV32I-SW-NEXT: # %bb.1: # %do_call
; RV32I-SW-NEXT: mv s0, a1
; RV32I-SW-NEXT: call foo
-; RV32I-SW-NEXT: beq s0, s1, .LBB2_3
+; RV32I-SW-NEXT: li a0, 57
+; RV32I-SW-NEXT: beq s0, a0, .LBB2_3
; RV32I-SW-NEXT: # %bb.2: # %do_call2
; RV32I-SW-NEXT: call foo
-; RV32I-SW-NEXT: .LBB2_3: # %exit
+; RV32I-SW-NEXT: .LBB2_3:
; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-SW-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: .cfi_restore ra
; RV32I-SW-NEXT: .cfi_restore s0
-; RV32I-SW-NEXT: .cfi_restore s1
; RV32I-SW-NEXT: addi sp, sp, 16
; RV32I-SW-NEXT: .cfi_def_cfa_offset 0
+; RV32I-SW-NEXT: .LBB2_4: # %exit
; RV32I-SW-NEXT: ret
;
; RV32I-SW-SR-LABEL: li_straightline_a:
; RV32I-SW-SR: # %bb.0:
-; RV32I-SW-SR-NEXT: call t0, __riscv_save_2
+; RV32I-SW-SR-NEXT: li a2, 57
+; RV32I-SW-SR-NEXT: beq a0, a2, .LBB2_4
+; RV32I-SW-SR-NEXT: # %bb.1: # %do_call
+; RV32I-SW-SR-NEXT: call t0, __riscv_save_1
; RV32I-SW-SR-NEXT: .cfi_def_cfa_offset 16
; RV32I-SW-SR-NEXT: .cfi_offset ra, -4
; RV32I-SW-SR-NEXT: .cfi_offset s0, -8
-; RV32I-SW-SR-NEXT: .cfi_offset s1, -12
-; RV32I-SW-SR-NEXT: li s1, 57
-; RV32I-SW-SR-NEXT: beq a0, s1, .LBB2_3
-; RV32I-SW-SR-NEXT: # %bb.1: # %do_call
; RV32I-SW-SR-NEXT: mv s0, a1
; RV32I-SW-SR-NEXT: call foo
-; RV32I-SW-SR-NEXT: beq s0, s1, .LBB2_3
+; RV32I-SW-SR-NEXT: li a0, 57
+; RV32I-SW-SR-NEXT: beq s0, a0, .LBB2_3
; RV32I-SW-SR-NEXT: # %bb.2: # %do_call2
; RV32I-SW-SR-NEXT: call foo
-; RV32I-SW-SR-NEXT: .LBB2_3: # %exit
-; RV32I-SW-SR-NEXT: tail __riscv_restore_2
+; RV32I-SW-SR-NEXT: .LBB2_3:
+; RV32I-SW-SR-NEXT: tail __riscv_restore_1
+; RV32I-SW-SR-NEXT: j .LBB2_4
+; RV32I-SW-SR-NEXT: .LBB2_4: # %exit
+; RV32I-SW-SR-NEXT: ret
;
; RV64I-SW-LABEL: li_straightline_a:
; RV64I-SW: # %bb.0:
-; RV64I-SW-NEXT: addi sp, sp, -32
-; RV64I-SW-NEXT: .cfi_def_cfa_offset 32
-; RV64I-SW-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-SW-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-SW-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-SW-NEXT: li a2, 57
+; RV64I-SW-NEXT: beq a0, a2, .LBB2_4
+; RV64I-SW-NEXT: # %bb.1: # %do_call
+; RV64I-SW-NEXT: addi sp, sp, -16
+; RV64I-SW-NEXT: .cfi_def_cfa_offset 16
+; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-SW-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-SW-NEXT: .cfi_offset ra, -8
; RV64I-SW-NEXT: .cfi_offset s0, -16
-; RV64I-SW-NEXT: .cfi_offset s1, -24
-; RV64I-SW-NEXT: li s1, 57
-; RV64I-SW-NEXT: beq a0, s1, .LBB2_3
-; RV64I-SW-NEXT: # %bb.1: # %do_call
; RV64I-SW-NEXT: mv s0, a1
; RV64I-SW-NEXT: call foo
-; RV64I-SW-NEXT: beq s0, s1, .LBB2_3
+; RV64I-SW-NEXT: li a0, 57
+; RV64I-SW-NEXT: beq s0, a0, .LBB2_3
; RV64I-SW-NEXT: # %bb.2: # %do_call2
; RV64I-SW-NEXT: call foo
-; RV64I-SW-NEXT: .LBB2_3: # %exit
-; RV64I-SW-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-SW-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-SW-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-SW-NEXT: .LBB2_3:
+; RV64I-SW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-SW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-SW-NEXT: .cfi_restore ra
; RV64I-SW-NEXT: .cfi_restore s0
-; RV64I-SW-NEXT: .cfi_restore s1
-; RV64I-SW-NEXT: addi sp, sp, 32
+; RV64I-SW-NEXT: addi sp, sp, 16
; RV64I-SW-NEXT: .cfi_def_cfa_offset 0
+; RV64I-SW-NEXT: .LBB2_4: # %exit
; RV64I-SW-NEXT: ret
%cmp0 = icmp eq i32 %a, 57
br i1 %cmp0, label %exit, label %do_call
@@ -518,103 +514,99 @@ define void @li_loop(i32 zeroext %a, i32 zeroext %b) {
; RV32I-SW-NO-NEXT: .cfi_def_cfa_offset 16
; RV32I-SW-NO-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NO-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-SW-NO-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-SW-NO-NEXT: .cfi_offset ra, -4
; RV32I-SW-NO-NEXT: .cfi_offset s0, -8
-; RV32I-SW-NO-NEXT: .cfi_offset s1, -12
-; RV32I-SW-NO-NEXT: li s1, 57
-; RV32I-SW-NO-NEXT: beq a0, s1, .LBB5_3
+; RV32I-SW-NO-NEXT: li a2, 57
+; RV32I-SW-NO-NEXT: beq a0, a2, .LBB5_3
; RV32I-SW-NO-NEXT: # %bb.1: # %do_call.preheader
; RV32I-SW-NO-NEXT: mv s0, a1
; RV32I-SW-NO-NEXT: .LBB5_2: # %do_call
; RV32I-SW-NO-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-SW-NO-NEXT: call foo
-; RV32I-SW-NO-NEXT: bne s0, s1, .LBB5_2
+; RV32I-SW-NO-NEXT: li a0, 57
+; RV32I-SW-NO-NEXT: bne s0, a0, .LBB5_2
; RV32I-SW-NO-NEXT: .LBB5_3: # %exit
; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-SW-NO-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: .cfi_restore ra
; RV32I-SW-NO-NEXT: .cfi_restore s0
-; RV32I-SW-NO-NEXT: .cfi_restore s1
; RV32I-SW-NO-NEXT: addi sp, sp, 16
; RV32I-SW-NO-NEXT: .cfi_def_cfa_offset 0
; RV32I-SW-NO-NEXT: ret
;
; RV32I-SW-LABEL: li_loop:
; RV32I-SW: # %bb.0:
+; RV32I-SW-NEXT: li a2, 57
+; RV32I-SW-NEXT: beq a0, a2, .LBB5_4
+; RV32I-SW-NEXT: # %bb.1: # %do_call.preheader
; RV32I-SW-NEXT: addi sp, sp, -16
; RV32I-SW-NEXT: .cfi_def_cfa_offset 16
; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-SW-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: .cfi_offset ra, -4
; RV32I-SW-NEXT: .cfi_offset s0, -8
-; RV32I-SW-NEXT: .cfi_offset s1, -12
-; RV32I-SW-NEXT: li s1, 57
-; RV32I-SW-NEXT: beq a0, s1, .LBB5_3
-; RV32I-SW-NEXT: # %bb.1: # %do_call.preheader
; RV32I-SW-NEXT: mv s0, a1
; RV32I-SW-NEXT: .LBB5_2: # %do_call
; RV32I-SW-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-SW-NEXT: call foo
-; RV32I-SW-NEXT: bne s0, s1, .LBB5_2
-; RV32I-SW-NEXT: .LBB5_3: # %exit
+; RV32I-SW-NEXT: li a0, 57
+; RV32I-SW-NEXT: bne s0, a0, .LBB5_2
+; RV32I-SW-NEXT: # %bb.3:
; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-SW-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: .cfi_restore ra
; RV32I-SW-NEXT: .cfi_restore s0
-; RV32I-SW-NEXT: .cfi_restore s1
; RV32I-SW-NEXT: addi sp, sp, 16
; RV32I-SW-NEXT: .cfi_def_cfa_offset 0
+; RV32I-SW-NEXT: .LBB5_4: # %exit
; RV32I-SW-NEXT: ret
;
; RV32I-SW-SR-LABEL: li_loop:
; RV32I-SW-SR: # %bb.0:
-; RV32I-SW-SR-NEXT: call t0, __riscv_save_2
+; RV32I-SW-SR-NEXT: li a2, 57
+; RV32I-SW-SR-NEXT: beq a0, a2, .LBB5_4
+; RV32I-SW-SR-NEXT: # %bb.1: # %do_call.preheader
+; RV32I-SW-SR-NEXT: call t0, __riscv_save_1
; RV32I-SW-SR-NEXT: .cfi_def_cfa_offset 16
; RV32I-SW-SR-NEXT: .cfi_offset ra, -4
; RV32I-SW-SR-NEXT: .cfi_offset s0, -8
-; RV32I-SW-SR-NEXT: .cfi_offset s1, -12
-; RV32I-SW-SR-NEXT: li s1, 57
-; RV32I-SW-SR-NEXT: beq a0, s1, .LBB5_3
-; RV32I-SW-SR-NEXT: # %bb.1: # %do_call.preheader
; RV32I-SW-SR-NEXT: mv s0, a1
; RV32I-SW-SR-NEXT: .LBB5_2: # %do_call
; RV32I-SW-SR-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-SW-SR-NEXT: call foo
-; RV32I-SW-SR-NEXT: bne s0, s1, .LBB5_2
-; RV32I-SW-SR-NEXT: .LBB5_3: # %exit
-; RV32I-SW-SR-NEXT: tail __riscv_restore_2
+; RV32I-SW-SR-NEXT: li a0, 57
+; RV32I-SW-SR-NEXT: bne s0, a0, .LBB5_2
+; RV32I-SW-SR-NEXT: # %bb.3:
+; RV32I-SW-SR-NEXT: tail __riscv_restore_1
+; RV32I-SW-SR-NEXT: j .LBB5_4
+; RV32I-SW-SR-NEXT: .LBB5_4: # %exit
+; RV32I-SW-SR-NEXT: ret
;
; RV64I-SW-LABEL: li_loop:
; RV64I-SW: # %bb.0:
-; RV64I-SW-NEXT: addi sp, sp, -32
-; RV64I-SW-NEXT: .cfi_def_cfa_offset 32
-; RV64I-SW-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-SW-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-SW-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-SW-NEXT: li a2, 57
+; RV64I-SW-NEXT: beq a0, a2, .LBB5_4
+; RV64I-SW-NEXT: # %bb.1: # %do_call.preheader
+; RV64I-SW-NEXT: addi sp, sp, -16
+; RV64I-SW-NEXT: .cfi_def_cfa_offset 16
+; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-SW-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-SW-NEXT: .cfi_offset ra, -8
; RV64I-SW-NEXT: .cfi_offset s0, -16
-; RV64I-SW-NEXT: .cfi_offset s1, -24
-; RV64I-SW-NEXT: li s1, 57
-; RV64I-SW-NEXT: beq a0, s1, .LBB5_3
-; RV64I-SW-NEXT: # %bb.1: # %do_call.preheader
; RV64I-SW-NEXT: mv s0, a1
; RV64I-SW-NEXT: .LBB5_2: # %do_call
; RV64I-SW-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-SW-NEXT: call foo
-; RV64I-SW-NEXT: bne s0, s1, .LBB5_2
-; RV64I-SW-NEXT: .LBB5_3: # %exit
-; RV64I-SW-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-SW-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-SW-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-SW-NEXT: li a0, 57
+; RV64I-SW-NEXT: bne s0, a0, .LBB5_2
+; RV64I-SW-NEXT: # %bb.3:
+; RV64I-SW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-SW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-SW-NEXT: .cfi_restore ra
; RV64I-SW-NEXT: .cfi_restore s0
-; RV64I-SW-NEXT: .cfi_restore s1
-; RV64I-SW-NEXT: addi sp, sp, 32
+; RV64I-SW-NEXT: addi sp, sp, 16
; RV64I-SW-NEXT: .cfi_def_cfa_offset 0
+; RV64I-SW-NEXT: .LBB5_4: # %exit
; RV64I-SW-NEXT: ret
%cmp0 = icmp eq i32 %a, 57
br i1 %cmp0, label %exit, label %do_call
diff --git a/llvm/test/CodeGen/RISCV/stack-guard-global.ll b/llvm/test/CodeGen/RISCV/stack-guard-global.ll
index da26ceb5e9c01..606905f9be06d 100644
--- a/llvm/test/CodeGen/RISCV/stack-guard-global.ll
+++ b/llvm/test/CodeGen/RISCV/stack-guard-global.ll
@@ -8,25 +8,24 @@ define void @foo(i64 %t) sspstrong nounwind {
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 32
-; CHECK-NEXT: lui s1, %hi(__stack_chk_guard)
-; CHECK-NEXT: ld a1, %lo(__stack_chk_guard)(s1)
-; CHECK-NEXT: sd a1, -32(s0)
+; CHECK-NEXT: lui a1, %hi(__stack_chk_guard)
+; CHECK-NEXT: ld a1, %lo(__stack_chk_guard)(a1)
+; CHECK-NEXT: sd a1, -24(s0)
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, 15
; CHECK-NEXT: andi a0, a0, -16
; CHECK-NEXT: sub a0, sp, a0
; CHECK-NEXT: mv sp, a0
; CHECK-NEXT: call baz
-; CHECK-NEXT: ld a0, %lo(__stack_chk_guard)(s1)
-; CHECK-NEXT: ld a1, -32(s0)
+; CHECK-NEXT: lui a0, %hi(__stack_chk_guard)
+; CHECK-NEXT: ld a0, %lo(__stack_chk_guard)(a0)
+; CHECK-NEXT: ld a1, -24(s0)
; CHECK-NEXT: bne a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2:
diff --git a/llvm/test/CodeGen/RISCV/stack-protector-target.ll b/llvm/test/CodeGen/RISCV/stack-protector-target.ll
index b01b044db5d6f..d15128df7b6eb 100644
--- a/llvm/test/CodeGen/RISCV/stack-protector-target.ll
+++ b/llvm/test/CodeGen/RISCV/stack-protector-target.ll
@@ -12,18 +12,17 @@ define void @func() sspreq nounwind {
; LINUX-RISCV64: # %bb.0:
; LINUX-RISCV64-NEXT: addi sp, sp, -32
; LINUX-RISCV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; LINUX-RISCV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; LINUX-RISCV64-NEXT: lui s0, %hi(__stack_chk_guard)
-; LINUX-RISCV64-NEXT: ld a0, %lo(__stack_chk_guard)(s0)
-; LINUX-RISCV64-NEXT: sd a0, 8(sp)
-; LINUX-RISCV64-NEXT: addi a0, sp, 4
+; LINUX-RISCV64-NEXT: lui a0, %hi(__stack_chk_guard)
+; LINUX-RISCV64-NEXT: ld a0, %lo(__stack_chk_guard)(a0)
+; LINUX-RISCV64-NEXT: sd a0, 16(sp)
+; LINUX-RISCV64-NEXT: addi a0, sp, 12
; LINUX-RISCV64-NEXT: call capture
-; LINUX-RISCV64-NEXT: ld a0, %lo(__stack_chk_guard)(s0)
-; LINUX-RISCV64-NEXT: ld a1, 8(sp)
+; LINUX-RISCV64-NEXT: lui a0, %hi(__stack_chk_guard)
+; LINUX-RISCV64-NEXT: ld a0, %lo(__stack_chk_guard)(a0)
+; LINUX-RISCV64-NEXT: ld a1, 16(sp)
; LINUX-RISCV64-NEXT: bne a0, a1, .LBB0_2
; LINUX-RISCV64-NEXT: # %bb.1:
; LINUX-RISCV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; LINUX-RISCV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LINUX-RISCV64-NEXT: addi sp, sp, 32
; LINUX-RISCV64-NEXT: ret
; LINUX-RISCV64-NEXT: .LBB0_2:
@@ -69,18 +68,17 @@ define void @func() sspreq nounwind {
; OPENBSD-RISCV64: # %bb.0:
; OPENBSD-RISCV64-NEXT: addi sp, sp, -32
; OPENBSD-RISCV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; OPENBSD-RISCV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; OPENBSD-RISCV64-NEXT: lui s0, %hi(__guard_local)
-; OPENBSD-RISCV64-NEXT: ld a0, %lo(__guard_local)(s0)
-; OPENBSD-RISCV64-NEXT: sd a0, 8(sp)
-; OPENBSD-RISCV64-NEXT: addi a0, sp, 4
+; OPENBSD-RISCV64-NEXT: lui a0, %hi(__guard_local)
+; OPENBSD-RISCV64-NEXT: ld a0, %lo(__guard_local)(a0)
+; OPENBSD-RISCV64-NEXT: sd a0, 16(sp)
+; OPENBSD-RISCV64-NEXT: addi a0, sp, 12
; OPENBSD-RISCV64-NEXT: call capture
-; OPENBSD-RISCV64-NEXT: ld a0, %lo(__guard_local)(s0)
-; OPENBSD-RISCV64-NEXT: ld a1, 8(sp)
+; OPENBSD-RISCV64-NEXT: lui a0, %hi(__guard_local)
+; OPENBSD-RISCV64-NEXT: ld a0, %lo(__guard_local)(a0)
+; OPENBSD-RISCV64-NEXT: ld a1, 16(sp)
; OPENBSD-RISCV64-NEXT: bne a0, a1, .LBB0_2
; OPENBSD-RISCV64-NEXT: # %bb.1: # %SP_return
; OPENBSD-RISCV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; OPENBSD-RISCV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; OPENBSD-RISCV64-NEXT: addi sp, sp, 32
; OPENBSD-RISCV64-NEXT: ret
; OPENBSD-RISCV64-NEXT: .LBB0_2: # %CallStackCheckFailBlk
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