[llvm] [RISCV][P-ext] Improve codegen for packed reverse intrinsics (PR #207575)
Hongyu Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 6 06:44:54 PDT 2026
https://github.com/XChy updated https://github.com/llvm/llvm-project/pull/207575
>From 46791061ea3201625be1137b6ddd04369ddfeb8c Mon Sep 17 00:00:00 2001
From: XChy <xxs_chy at outlook.com>
Date: Sun, 5 Jul 2026 17:50:57 +0800
Subject: [PATCH 1/2] [RISCV][P-ext] Fold packed reverse intrinsics
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 31 ++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 24 ++++++++
llvm/test/CodeGen/RISCV/rvp-reverse.ll | 68 +++++----------------
3 files changed, 69 insertions(+), 54 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0c510b0ed74c7..f5c7f37a181e5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -584,6 +584,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SSUBSAT, VTs, Legal);
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal);
setOperationAction(ISD::BITREVERSE, VTs, Legal);
+ setOperationAction(ISD::VECTOR_SHUFFLE, VTs, Custom);
+ setOperationAction(ISD::VECTOR_REVERSE, VTs, Legal);
for (MVT VT : VTs) {
if (VT != MVT::v2i32)
setOperationAction({ISD::ABS, ISD::ABDS, ISD::ABDU}, VT, Legal);
@@ -647,6 +649,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SSHLSAT, {MVT::v2i32, MVT::v4i16}, Custom);
setOperationAction(ISD::BSWAP, MVT::v4i16, Legal);
setOperationAction(ISD::BITREVERSE, {MVT::v4i16, MVT::v8i8}, Legal);
+ setOperationAction(ISD::VECTOR_SHUFFLE, P64VecVTs, Custom);
+ setOperationAction(ISD::VECTOR_REVERSE, P64VecVTs, Legal);
setOperationAction(ISD::SPLAT_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::BUILD_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
@@ -6320,6 +6324,33 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
unsigned NumElts = VT.getVectorNumElements();
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
+ // Select an element reverse shuffle to VECTOR_REVERSE (rev8/rev16/ppairoe.*).
+ if (Subtarget.hasStdExtP() && !Subtarget.hasVInstructions()) {
+ // Reverse of the low L lanes, higher lanes poison. L == NumElts is a plain
+ // reverse; L == NumElts/2 is a widened RV64 v4i8/v2i16 reverse.
+ ArrayRef<int> Mask = SVN->getMask();
+ auto IsLowReverse = [&](unsigned L) {
+ return V2.isUndef() &&
+ ShuffleVectorInst::isReverseMask(Mask.take_front(L), L) &&
+ all_of(Mask.drop_front(L), [](int M) { return M < 0; });
+ };
+ if (IsLowReverse(NumElts))
+ return DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V1);
+ // Widened: reversing sends the low-half lanes to the top half, so shift
+ // them back down by half the register. Only the 64-bit packed types are
+ // legal here, so the register is XLen (i64).
+ if (Subtarget.is64Bit() && VT.getSizeInBits() == 64 &&
+ IsLowReverse(NumElts / 2)) {
+ SDValue Rev = DAG.getBitcast(
+ MVT::i64, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V1));
+ SDValue Srl =
+ DAG.getNode(ISD::SRL, DL, MVT::i64, Rev,
+ DAG.getConstant(VT.getSizeInBits() / 2, DL, MVT::i64));
+ return DAG.getBitcast(VT, Srl);
+ }
+ return SDValue();
+ }
+
if (VT.getVectorElementType() == MVT::i1) {
// Lower to a vror.vi of a larger element type if possible before we promote
// i1s to i8s.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 9114dfbf50a55..4492cb2186e90 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2223,6 +2223,11 @@ let append Predicates = [IsRV32] in {
def : Pat<(v2i16 (bitreverse GPR:$rs)),
(PPAIROE_H (REV_RV32 GPR:$rs), (REV_RV32 GPR:$rs))>;
+ // Element reverse (prev): reverse the byte/halfword order of the register.
+ def : Pat<(v4i8 (vector_reverse (v4i8 GPR:$rs))), (REV8_RV32 GPR:$rs)>;
+ def : Pat<(v2i16 (vector_reverse (v2i16 GPR:$rs))),
+ (PPAIROE_H GPR:$rs, GPR:$rs)>;
+
// Load/Store patterns
def : StPat<store, SW, GPR, v4i8>;
def : StPat<store, SW, GPR, v2i16>;
@@ -2453,6 +2458,19 @@ let append Predicates = [IsRV32] in {
(BuildGPRPair (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)),
(REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd))))>;
+ // Element reverse (prev): swap the two halves and reverse within each.
+ def : Pat<(v8i8 (vector_reverse (v8i8 GPRPair:$rs))),
+ (BuildGPRPair (REV8_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
+ (REV8_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
+ def : Pat<(v4i16 (vector_reverse (v4i16 GPRPair:$rs))),
+ (BuildGPRPair (PPAIROE_H (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd),
+ (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
+ (PPAIROE_H (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even),
+ (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
+ def : Pat<(v2i32 (vector_reverse (v2i32 GPRPair:$rs))),
+ (BuildGPRPair (i32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
+ (i32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
+
// splat pattern
def : Pat<(v8i8 (splat_vector (XLenVT GPR:$rs2))),
(PADD_DBS (v8i8 X0_Pair), GPR:$rs2)>;
@@ -2671,6 +2689,12 @@ let append Predicates = [IsRV64] in {
def : Pat<(v2i32 (bitreverse GPR:$rs)),
(PPAIROE_W (REV_RV64 GPR:$rs), (REV_RV64 GPR:$rs))>;
+ // Element reverse (prev): reverse the byte/halfword/word order of the register.
+ def : Pat<(v8i8 (vector_reverse (v8i8 GPR:$rs))), (REV8_RV64 GPR:$rs)>;
+ def : Pat<(v4i16 (vector_reverse (v4i16 GPR:$rs))), (REV16_RV64 GPR:$rs)>;
+ def : Pat<(v2i32 (vector_reverse (v2i32 GPR:$rs))),
+ (PPAIROE_W GPR:$rs, GPR:$rs)>;
+
// Load/Store patterns
def : StPat<store, SD, GPR, v8i8>;
def : StPat<store, SD, GPR, v4i16>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-reverse.ll b/llvm/test/CodeGen/RISCV/rvp-reverse.ll
index a503dd339b2ad..7490e8f3ab833 100644
--- a/llvm/test/CodeGen/RISCV/rvp-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-reverse.ll
@@ -9,22 +9,13 @@
define <4 x i8> @test_prev_v4i8(<4 x i8> %a) {
; RV32-LABEL: test_prev_v4i8:
; RV32: # %bb.0:
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: srli a0, a0, 16
-; RV32-NEXT: srli a3, a1, 8
-; RV32-NEXT: srli a2, a1, 24
-; RV32-NEXT: ppaire.db a0, a2, a0
-; RV32-NEXT: pack a0, a0, a1
+; RV32-NEXT: rev8 a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_prev_v4i8:
; RV64: # %bb.0:
-; RV64-NEXT: srli a1, a0, 8
-; RV64-NEXT: srli a2, a0, 16
-; RV64-NEXT: srli a3, a0, 24
-; RV64-NEXT: ppaire.b a0, a1, a0
-; RV64-NEXT: ppaire.b a1, a3, a2
-; RV64-NEXT: ppaire.h a0, a1, a0
+; RV64-NEXT: rev8 a0, a0
+; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: ret
%r = shufflevector <4 x i8> %a, <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i8> %r
@@ -33,14 +24,13 @@ define <4 x i8> @test_prev_v4i8(<4 x i8> %a) {
define <2 x i16> @test_prev_v2i16(<2 x i16> %a) {
; RV32-LABEL: test_prev_v2i16:
; RV32: # %bb.0:
-; RV32-NEXT: srli a1, a0, 16
-; RV32-NEXT: pack a0, a1, a0
+; RV32-NEXT: ppairoe.h a0, a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: test_prev_v2i16:
; RV64: # %bb.0:
-; RV64-NEXT: srli a1, a0, 16
-; RV64-NEXT: ppaire.h a0, a1, a0
+; RV64-NEXT: rev16 a0, a0
+; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: ret
%r = shufflevector <2 x i16> %a, <2 x i16> poison, <2 x i32> <i32 1, i32 0>
ret <2 x i16> %r
@@ -49,36 +39,14 @@ define <2 x i16> @test_prev_v2i16(<2 x i16> %a) {
define <8 x i8> @test_prev_v8i8(<8 x i8> %a) {
; RV32-LABEL: test_prev_v8i8:
; RV32: # %bb.0:
-; RV32-NEXT: srli a2, a0, 8
-; RV32-NEXT: srli a3, a0, 16
-; RV32-NEXT: srli a4, a0, 24
-; RV32-NEXT: ppaire.b a0, a2, a0
-; RV32-NEXT: ppaire.b a2, a4, a3
-; RV32-NEXT: srli a3, a1, 8
-; RV32-NEXT: srli a4, a1, 16
-; RV32-NEXT: srli a5, a1, 24
-; RV32-NEXT: ppaire.b a3, a3, a1
-; RV32-NEXT: ppaire.b a4, a5, a4
-; RV32-NEXT: pack a1, a2, a0
-; RV32-NEXT: pack a0, a4, a3
+; RV32-NEXT: rev8 a2, a0
+; RV32-NEXT: rev8 a0, a1
+; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
;
; RV64-LABEL: test_prev_v8i8:
; RV64: # %bb.0:
-; RV64-NEXT: srli a1, a0, 8
-; RV64-NEXT: srli a2, a0, 16
-; RV64-NEXT: srli a3, a0, 24
-; RV64-NEXT: ppaire.b a1, a1, a0
-; RV64-NEXT: ppaire.b a2, a3, a2
-; RV64-NEXT: srli a3, a0, 32
-; RV64-NEXT: srli a4, a0, 40
-; RV64-NEXT: srli a5, a0, 48
-; RV64-NEXT: srli a0, a0, 56
-; RV64-NEXT: ppaire.b a3, a4, a3
-; RV64-NEXT: ppaire.b a0, a0, a5
-; RV64-NEXT: ppaire.h a1, a2, a1
-; RV64-NEXT: ppaire.h a0, a0, a3
-; RV64-NEXT: pack a0, a0, a1
+; RV64-NEXT: rev8 a0, a0
; RV64-NEXT: ret
%r = shufflevector <8 x i8> %a, <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %r
@@ -87,21 +55,14 @@ define <8 x i8> @test_prev_v8i8(<8 x i8> %a) {
define <4 x i16> @test_prev_v4i16(<4 x i16> %a) {
; RV32-LABEL: test_prev_v4i16:
; RV32: # %bb.0:
-; RV32-NEXT: srli a2, a0, 16
-; RV32-NEXT: srli a3, a1, 16
-; RV32-NEXT: pack a2, a2, a0
-; RV32-NEXT: pack a0, a3, a1
+; RV32-NEXT: ppairoe.h a2, a0, a0
+; RV32-NEXT: ppairoe.h a0, a1, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
;
; RV64-LABEL: test_prev_v4i16:
; RV64: # %bb.0:
-; RV64-NEXT: srli a1, a0, 16
-; RV64-NEXT: srli a2, a0, 32
-; RV64-NEXT: srli a3, a0, 48
-; RV64-NEXT: ppaire.h a0, a1, a0
-; RV64-NEXT: ppaire.h a1, a3, a2
-; RV64-NEXT: pack a0, a1, a0
+; RV64-NEXT: rev16 a0, a0
; RV64-NEXT: ret
%r = shufflevector <4 x i16> %a, <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i16> %r
@@ -117,8 +78,7 @@ define <2 x i32> @test_prev_v2i32(<2 x i32> %a) {
;
; RV64-LABEL: test_prev_v2i32:
; RV64: # %bb.0:
-; RV64-NEXT: srli a1, a0, 32
-; RV64-NEXT: pack a0, a1, a0
+; RV64-NEXT: ppairoe.w a0, a0, a0
; RV64-NEXT: ret
%r = shufflevector <2 x i32> %a, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
ret <2 x i32> %r
>From 060fd7af75574052676372430b56e225d039759e Mon Sep 17 00:00:00 2001
From: XChy <xxs_chy at outlook.com>
Date: Mon, 6 Jul 2026 21:37:08 +0800
Subject: [PATCH 2/2] split the 64-bit reverse during lowering
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 21 ++++++++++++++++++++-
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 13 -------------
2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f5c7f37a181e5..a750a3a5a2df8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -650,7 +650,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BSWAP, MVT::v4i16, Legal);
setOperationAction(ISD::BITREVERSE, {MVT::v4i16, MVT::v8i8}, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, P64VecVTs, Custom);
- setOperationAction(ISD::VECTOR_REVERSE, P64VecVTs, Legal);
+ setOperationAction(ISD::VECTOR_REVERSE, P64VecVTs, Custom);
setOperationAction(ISD::SPLAT_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::BUILD_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
@@ -13573,6 +13573,25 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT VecVT = Op.getSimpleValueType();
+
+ // Reverse a 64-bit packed vector on RV32 by reversing each 32-bit half and
+ // swapping them.
+ if (Subtarget.hasStdExtP() && !Subtarget.hasVInstructions()) {
+ assert(!Subtarget.is64Bit() && VecVT.getSizeInBits() == 64 &&
+ "Unexpected packed VECTOR_REVERSE type");
+ SDValue V = Op.getOperand(0);
+ if (VecVT == MVT::v2i32) {
+ // A 2-element reverse is just an element swap.
+ SDValue Lo = DAG.getExtractVectorElt(DL, MVT::i32, V, 0);
+ SDValue Hi = DAG.getExtractVectorElt(DL, MVT::i32, V, 1);
+ return DAG.getBuildVector(VecVT, DL, {Hi, Lo});
+ }
+ auto [Lo, Hi] = DAG.SplitVector(V, DL);
+ Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, Lo.getSimpleValueType(), Lo);
+ Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, Hi.getSimpleValueType(), Hi);
+ return DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, Hi, Lo);
+ }
+
if (VecVT.getVectorElementType() == MVT::i1) {
MVT WidenVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount());
SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, Op.getOperand(0));
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 4492cb2186e90..7b6ffb8e2d5d7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2458,19 +2458,6 @@ let append Predicates = [IsRV32] in {
(BuildGPRPair (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)),
(REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd))))>;
- // Element reverse (prev): swap the two halves and reverse within each.
- def : Pat<(v8i8 (vector_reverse (v8i8 GPRPair:$rs))),
- (BuildGPRPair (REV8_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
- (REV8_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
- def : Pat<(v4i16 (vector_reverse (v4i16 GPRPair:$rs))),
- (BuildGPRPair (PPAIROE_H (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd),
- (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
- (PPAIROE_H (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even),
- (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
- def : Pat<(v2i32 (vector_reverse (v2i32 GPRPair:$rs))),
- (BuildGPRPair (i32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
- (i32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
-
// splat pattern
def : Pat<(v8i8 (splat_vector (XLenVT GPR:$rs2))),
(PADD_DBS (v8i8 X0_Pair), GPR:$rs2)>;
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