[llvm] [AArch64] optimize lowering for icmp on i128 when RHS is an immediate (PR #181822)

[Cheng Lingfei via llvm-commits]

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@@ -12284,13 +12286,20 @@ static SDValue performOrXorChainCombine(SDNode *N, SelectionDAG &DAG) {
   });
   if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && isNullConstant(RHS) &&
       LHS->getOpcode() == ISD::OR && LHS->hasOneUse() &&
-      isOrXorChain(LHS, DAG, NumXors, SawXor, RequireLegalCmpImmediates,
-                   WorkList) &&
+      isOrXorChain(LHS, DAG, NumLeaves, NumXors, SawXor,
+                   RequireLegalCmpImmediates, WorkList) &&
       SawXor) {
     // A CCMP sequence serializes the comparisons through NZCV. Keep the
-    // transform to short chains where the instruction-count reduction outweighs
-    // the longer dependency chain.
-    if (WorkList.size() > 5)
+    // default transform to short chains, but account for real XOR leaves: each
+    // one removed is a code-size and front-end win. Under size optimization,
+    // prefer the smaller CCMP form unless another guard rejects it.
+    const Function &F = DAG.getMachineFunction().getFunction();
+    unsigned Limit = 5;
+    if (NumXors >= 6)
+      Limit = 6;
+    if (F.hasOptSize() || F.hasMinSize())
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clingfei wrote:

Done. Thanks. 

https://github.com/llvm/llvm-project/pull/181822