[llvm] [AMDGPU] Add custom lowering of llvm.convert.from.arbitrary.fp for FP8 (PR #194144)

[Matt Arsenault via llvm-commits]

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@@ -10804,6 +10818,72 @@ SDValue SITargetLowering::lowerWorkitemID(SelectionDAG &DAG, SDValue Op,
                      DAG.getValueType(SmallVT));
 }
 
+// Pack a vector of i8 lanes into i32 via bitcast.
+// FIXME: packing loses lane-wise poison. Should we do something about it?
+SDValue SITargetLowering::packBytesToI32(SelectionDAG &DAG, const SDLoc &SL,
+                                         SDValue Src) {
+  assert(Src.getValueType() == MVT::v2i8 &&
+         "packBytesToI32 expects a v2i8 source");
+  // Widen v2i8 to v4i8 with the high half poison, then bitcast to i32. This
+  // selects to v_perm_b32, packing two i8 values into low 16 bits of an i32.
+  SDValue Wide = DAG.getNode(ISD::CONCAT_VECTORS, SL, MVT::v4i8, Src,
+                             DAG.getPOISON(MVT::v2i8));
+  return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Wide);
+}
+
+SDValue SITargetLowering::lowerFromFP8ToF32(SDValue Op, bool IsBF8,
+                                            SelectionDAG &DAG) const {
+  SDLoc SL(Op);
+  SDValue Src = Op.getOperand(0);
+  unsigned Opc = IsBF8 ? AMDGPUISD::CVT_PK_F32_BF8 : AMDGPUISD::CVT_PK_F32_FP8;
+  SDValue PackedI32 = packBytesToI32(DAG, SL, Src);
+  return DAG.getNode(Opc, SL, MVT::v2f32, PackedI32);
+}
+
+SDValue SITargetLowering::lowerFromFP8ToF16(SDValue Op, bool IsBF8,
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arsenm wrote:

You can merge this and lowerFromFP8ToF32 if you stop hardcoding the result type. You can also compute the source integer type 

https://github.com/llvm/llvm-project/pull/194144