[llvm] [SelectionDAG] Add computeKnownBits support for ISD::VECREDUCE_ADD (PR #207631)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+sve  | FileCheck %s --check-prefix=CHECK
+
+declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)
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RKSimon wrote:

we don't need forward declarations anymore

https://github.com/llvm/llvm-project/pull/207631