[llvm] [AArch64] Expand FORM_TRANSPOSED_REG_TUPLE to copies before regalloc (PR #207205)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 6 02:32:59 PDT 2026
================
@@ -510,6 +510,37 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
return I.get();
}
+// Encourage placing FORM_TRANSPOSED_REG immediately before the instruction that
+// uses/consumes it. This ensures it has a short live range, which means we're
+// more likely to allocate registers its operands first (which works best for
+// the hints in AArch64RegisterInfo::getRegAllocationHints).
+static bool scheduleFormTransposedTupleAdjacentToUsers(
+ const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI,
+ const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
+
+ auto *TRI = TSI.getRegisterInfo();
+ if (!FirstMI) {
+ // The SecondMI must be a multi-vector operation. So limit this to
+ // instructions that use full tuple registers (not a sub-register).
+ const MachineRegisterInfo &MRI = SecondMI.getMF()->getRegInfo();
+ for (const MachineOperand &Use : SecondMI.uses()) {
+ if (Use.isReg() && Use.getReg().isVirtual() && !Use.getSubReg() &&
+ TRI->isSubRegValidForRegClass(MRI.getRegClass(Use.getReg()),
+ AArch64::zsub0))
+ return true;
+ }
+ return false;
+ }
+
+ if (FirstMI->getOpcode() != AArch64::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO &&
+ FirstMI->getOpcode() != AArch64::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO)
+ return false;
+
+ Register TupleDef = FirstMI->getOperand(0).getReg();
+ return SecondMI.findRegisterUseOperandIdx(TupleDef, TSI.getRegisterInfo()) !=
+ -1;
----------------
sdesmalen-arm wrote:
Does this really matter though? we already know that SecondMI must use the TupleDef in some form (otherwise, this function wouldn't have been called).
Replacing this whole function with:
```
return !FirstMI ||
FirstMI->getOpcode() == AArch64::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO ||
FirstMI->getOpcode() == AArch64::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO;
```
fails none of the tests.
https://github.com/llvm/llvm-project/pull/207205
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