[llvm] [GlobalISel][AArch64] Legalize PHIs with vectors smaller than 64-bits (PR #207356)
Ömer Sinan Ağacan via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 6 02:29:08 PDT 2026
https://github.com/osa1 updated https://github.com/llvm/llvm-project/pull/207356
>From 7081cc73d924684bfdd12905600b3b45ff50c80f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Fri, 3 Jul 2026 09:12:55 +0100
Subject: [PATCH 1/2] [GlobalISel][AArch64] Legalize PHIs with vectors smaller
than 64-bits
New negalization rule added as the last to not change legalization of
small vectors in existing tests.
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 3 +-
.../AArch64/GlobalISel/legalize-phi.mir | 61 +++++++++++++++++++
2 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 1d08ce1312263..01268ce5c0b4a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -158,7 +158,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampMaxNumElements(0, s64, 2)
- .clampMaxNumElements(0, p0, 2);
+ .clampMaxNumElements(0, p0, 2)
+ .widenVectorEltsToVectorMinSize(0, 64);
getActionDefinitionsBuilder(G_INSERT)
.legalIf(all(typeInSet(0, {s32, s64, p0}), typeInSet(1, {s8, s16, s32}),
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index a94d8cf3094f8..1831fb315328c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -946,3 +946,64 @@ body: |
$q0 = COPY %unmerge_1(<2 x p0>)
$q1 = COPY %unmerge_2(<2 x p0>)
RET_ReallyLR implicit $q0, implicit $q1
+...
+---
+name: v4s1
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: v4s1
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $d0, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i16>) = COPY $d0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[XOR]], [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[AND]](i32), %bb.2
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x i16>) = G_PHI %46(<4 x i16>), %bb.2, [[COPY1]](<4 x i16>), %bb.0
+ ; CHECK-NEXT: $d0 = COPY [[PHI]](<4 x i16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[BUILD_VECTOR]](<8 x i8>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x i16>), [[UV1:%[0-9]+]]:_(<4 x i16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x i16>)
+ ; CHECK-NEXT: G_BR %bb.1
+ bb.1.entry:
+ successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ liveins: $d0, $w0
+
+ %3:_(i32) = COPY $w0
+ %2:_(i8) = G_TRUNC %3(i32)
+ %4:_(<4 x i16>) = COPY $d0
+ %1:_(<4 x i1>) = G_TRUNC %4(<4 x i16>)
+ %5:_(i8) = G_ASSERT_ZEXT %2, 1
+ %0:_(i1) = G_TRUNC %5(i8)
+ %8:_(i1) = G_CONSTANT i1 false
+ %7:_(<4 x i1>) = G_BUILD_VECTOR %8(i1), %8(i1), %8(i1), %8(i1)
+ %11:_(i1) = G_CONSTANT i1 true
+ %12:_(i1) = G_XOR %0, %11
+ G_BRCOND %12(i1), %bb.3
+ G_BR %bb.2
+
+ bb.2:
+ %9:_(<4 x i1>) = G_PHI %7(<4 x i1>), %bb.3, %1(<4 x i1>), %bb.1
+ %10:_(<4 x i16>) = G_ANYEXT %9(<4 x i1>)
+ $d0 = COPY %10(<4 x i16>)
+ RET_ReallyLR implicit $d0
+
+ bb.3:
+ successors: %bb.2(0x80000000)
+
+ G_BR %bb.2
+...
>From 6366eec2c4b27b16aa3f0fa4cab9431d97e83018 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omeragacan at gmail.com>
Date: Mon, 6 Jul 2026 10:28:50 +0100
Subject: [PATCH 2/2] Address comment
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +-
.../AArch64/GlobalISel/legalize-phi.mir | 19 +++++++++++++------
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 59f258b22ac75..e4e58327ead53 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -157,7 +157,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v2s32, v4s32)
.clampMaxNumElements(0, s64, 2)
.clampMaxNumElements(0, p0, 2)
- .widenVectorEltsToVectorMinSize(0, 64);
+ .widenScalarOrEltToNextPow2OrMinSize(0, 8);
getActionDefinitionsBuilder(G_INSERT)
.legalIf(all(typeInSet(0, {s32, s64, p0}), typeInSet(1, {s8, s16, s32}),
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 1831fb315328c..37527cf830fb0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -962,22 +962,29 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[COPY1]](<4 x i16>)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[UV]](i16)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[UV1]](i16)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i8) = G_TRUNC [[UV2]](i16)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[UV3]](i16)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[TRUNC]](i8), [[TRUNC1]](i8), [[TRUNC2]](i8), [[TRUNC3]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[XOR]], [[C1]]
; CHECK-NEXT: G_BRCOND [[AND]](i32), %bb.2
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x i16>) = G_PHI %46(<4 x i16>), %bb.2, [[COPY1]](<4 x i16>), %bb.0
- ; CHECK-NEXT: $d0 = COPY [[PHI]](<4 x i16>)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<8 x i8>) = G_PHI %20(<8 x i8>), %bb.2, [[BUILD_VECTOR]](<8 x i8>), %bb.0
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[PHI]](<8 x i8>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<4 x i16>), [[UV5:%[0-9]+]]:_(<4 x i16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x i16>)
+ ; CHECK-NEXT: $d0 = COPY [[UV4]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[BUILD_VECTOR]](<8 x i8>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x i16>), [[UV1:%[0-9]+]]:_(<4 x i16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x i16>)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[C]](i8), [[C]](i8), [[C]](i8), [[C]](i8), [[DEF1]](i8), [[DEF1]](i8), [[DEF1]](i8), [[DEF1]](i8)
; CHECK-NEXT: G_BR %bb.1
bb.1.entry:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
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