[llvm] [X86] Add ISD::VECREDUCE_MUL lowering instead of matching in DAG (PR #207593)

[Simon Pilgrim via llvm-commits]

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@@ -34351,6 +34355,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::VECREDUCE_AND:
   case ISD::VECREDUCE_OR:
   case ISD::VECREDUCE_XOR:      return LowerVECREDUCE(Op, Subtarget, DAG, true);
+  case ISD::VECREDUCE_MUL:      return LowerVECREDUCE(Op, Subtarget, DAG, false);
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RKSimon wrote:

I've moved to the default scalarisation - its better than I remember it (I was still fighting regressions when I made the change and didn't revisit it) - the only (minor) remaining regression is the pre-SSE4 vXi32 reductions - WDYT is it worth adding a special case for it?

https://github.com/llvm/llvm-project/pull/207593