[llvm] [RISCV][NFC] Remove unnecessary ZIP/VISNI checks (PR #207683)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 6 02:03:34 PDT 2026
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/207683
>From 0b3244ed539fea804686c5d1939bd55cd39aebe4 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Mon, 6 Jul 2026 16:43:15 +0800
Subject: [PATCH] [RISCV][NFC] Remove unnecessary ZIP/VISNI checks
We should remove them when removing `XRivosVizip` and `XRivosVisni`
but it seems UTC failed to do that.
---
.../RISCV/rvv/fixed-vectors-extract.ll | 119 --
.../CodeGen/RISCV/rvv/fixed-vectors-insert.ll | 95 -
.../fixed-vectors-shuffle-deinterleave2.ll | 48 -
.../fixed-vectors-shuffle-int-interleave.ll | 54 -
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 45 -
.../RISCV/rvv/vector-interleave-fixed.ll | 442 -----
.../CodeGen/RISCV/rvv/vector-interleave.ll | 1645 -----------------
7 files changed, 2448 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
index 0e37fd8812c8e..831713780d26e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
@@ -713,28 +713,6 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind {
; RV64M-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64M-NEXT: addi sp, sp, 256
; RV64M-NEXT: ret
-; VISNI-LABEL: extractelt_v32i32_idx:
-; VISNI: # %bb.0:
-; VISNI-NEXT: addi sp, sp, -256
-; VISNI-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
-; VISNI-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
-; VISNI-NEXT: addi s0, sp, 256
-; VISNI-NEXT: andi sp, sp, -128
-; VISNI-NEXT: li a2, 32
-; VISNI-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; VISNI-NEXT: vle32.v v8, (a0)
-; VISNI-NEXT: vadd.vv v8, v8, v8
-; VISNI-NEXT: andi a1, a1, 31
-; VISNI-NEXT: slli a1, a1, 2
-; VISNI-NEXT: mv a0, sp
-; VISNI-NEXT: or a1, a0, a1
-; VISNI-NEXT: vse32.v v8, (a0)
-; VISNI-NEXT: lw a0, 0(a1)
-; VISNI-NEXT: addi sp, s0, -256
-; VISNI-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
-; VISNI-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
-; VISNI-NEXT: addi sp, sp, 256
-; VISNI-NEXT: ret
%a = load <32 x i32>, ptr %x
%b = add <32 x i32> %a, %a
%c = extractelement <32 x i32> %b, i32 %idx
@@ -791,30 +769,6 @@ define i32 @extractelt_v64i32_idx(<64 x i32> %a, i32 zeroext %idx) nounwind {
; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 384
; RV64-NEXT: ret
-; VISNI-LABEL: extractelt_v64i32_idx:
-; VISNI: # %bb.0:
-; VISNI-NEXT: addi sp, sp, -384
-; VISNI-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
-; VISNI-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
-; VISNI-NEXT: addi s0, sp, 384
-; VISNI-NEXT: andi sp, sp, -128
-; VISNI-NEXT: li a1, 32
-; VISNI-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; VISNI-NEXT: vadd.vv v16, v16, v16
-; VISNI-NEXT: addi a1, sp, 128
-; VISNI-NEXT: vse32.v v16, (a1)
-; VISNI-NEXT: vadd.vv v8, v8, v8
-; VISNI-NEXT: andi a0, a0, 63
-; VISNI-NEXT: mv a1, sp
-; VISNI-NEXT: slli a0, a0, 2
-; VISNI-NEXT: add a0, a1, a0
-; VISNI-NEXT: vse32.v v8, (a1)
-; VISNI-NEXT: lw a0, 0(a0)
-; VISNI-NEXT: addi sp, s0, -384
-; VISNI-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
-; VISNI-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
-; VISNI-NEXT: addi sp, sp, 384
-; VISNI-NEXT: ret
%b = add <64 x i32> %a, %a
%c = extractelement <64 x i32> %b, i32 %idx
ret i32 %c
@@ -932,13 +886,6 @@ define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
; RV64-NEXT: li a1, 13
; RV64-NEXT: subw a0, a1, a0
; RV64-NEXT: ret
-; VISNI-LABEL: extractelt_sub_v4i32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: li a0, 13
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: ri.vextract.x.v a1, v8, 2
-; VISNI-NEXT: subw a0, a0, a1
-; VISNI-NEXT: ret
%bo = sub <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %x
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -980,13 +927,6 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
; RV64M-NEXT: li a1, 13
; RV64M-NEXT: mulw a0, a0, a1
; RV64M-NEXT: ret
-; VISNI-LABEL: extractelt_mul_v4i32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: li a0, 13
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: ri.vextract.x.v a1, v8, 2
-; VISNI-NEXT: mulw a0, a1, a0
-; VISNI-NEXT: ret
%bo = mul <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -1064,18 +1004,6 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV64M-NEXT: srai a0, a0, 34
; RV64M-NEXT: add a0, a0, a1
; RV64M-NEXT: ret
-; VISNI-LABEL: extractelt_sdiv_v4i32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: lui a0, 322639
-; VISNI-NEXT: addi a0, a0, -945
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: ri.vextract.x.v a1, v8, 2
-; VISNI-NEXT: sext.w a1, a1
-; VISNI-NEXT: mul a0, a1, a0
-; VISNI-NEXT: srli a1, a0, 63
-; VISNI-NEXT: srai a0, a0, 34
-; VISNI-NEXT: add a0, a0, a1
-; VISNI-NEXT: ret
%bo = sdiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -1130,17 +1058,6 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
; RV64M-NEXT: mulhu a0, a1, a0
; RV64M-NEXT: srli a0, a0, 34
; RV64M-NEXT: ret
-; VISNI-LABEL: extractelt_udiv_v4i32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: lui a0, 322639
-; VISNI-NEXT: addi a0, a0, -945
-; VISNI-NEXT: slli a0, a0, 32
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: ri.vextract.x.v a1, v8, 2
-; VISNI-NEXT: slli a1, a1, 32
-; VISNI-NEXT: mulhu a0, a1, a0
-; VISNI-NEXT: srli a0, a0, 34
-; VISNI-NEXT: ret
%bo = udiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -1156,15 +1073,6 @@ define float @extractelt_fadd_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfmv.f.s fa4, v8
; CHECK-NEXT: fadd.s fa0, fa4, fa5
; CHECK-NEXT: ret
-; VISNI-LABEL: extractelt_fadd_v4f32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: lui a0, 267520
-; VISNI-NEXT: fmv.w.x fa5, a0
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: vslidedown.vi v8, v8, 2
-; VISNI-NEXT: vfmv.f.s fa4, v8
-; VISNI-NEXT: fadd.s fa0, fa4, fa5
-; VISNI-NEXT: ret
%bo = fadd <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
@@ -1180,15 +1088,6 @@ define float @extractelt_fsub_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfmv.f.s fa4, v8
; CHECK-NEXT: fsub.s fa0, fa5, fa4
; CHECK-NEXT: ret
-; VISNI-LABEL: extractelt_fsub_v4f32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: lui a0, 267520
-; VISNI-NEXT: fmv.w.x fa5, a0
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: vslidedown.vi v8, v8, 2
-; VISNI-NEXT: vfmv.f.s fa4, v8
-; VISNI-NEXT: fsub.s fa0, fa5, fa4
-; VISNI-NEXT: ret
%bo = fsub <4 x float> <float 11.0, float 12.0, float 13.0, float 14.0>, %x
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
@@ -1204,15 +1103,6 @@ define float @extractelt_fmul_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfmv.f.s fa4, v8
; CHECK-NEXT: fmul.s fa0, fa4, fa5
; CHECK-NEXT: ret
-; VISNI-LABEL: extractelt_fmul_v4f32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: lui a0, 267520
-; VISNI-NEXT: fmv.w.x fa5, a0
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: vslidedown.vi v8, v8, 2
-; VISNI-NEXT: vfmv.f.s fa4, v8
-; VISNI-NEXT: fmul.s fa0, fa4, fa5
-; VISNI-NEXT: ret
%bo = fmul <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
@@ -1228,15 +1118,6 @@ define float @extractelt_fdiv_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfmv.f.s fa4, v8
; CHECK-NEXT: fdiv.s fa0, fa4, fa5
; CHECK-NEXT: ret
-; VISNI-LABEL: extractelt_fdiv_v4f32:
-; VISNI: # %bb.0:
-; VISNI-NEXT: lui a0, 267520
-; VISNI-NEXT: fmv.w.x fa5, a0
-; VISNI-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; VISNI-NEXT: vslidedown.vi v8, v8, 2
-; VISNI-NEXT: vfmv.f.s fa4, v8
-; VISNI-NEXT: fdiv.s fa0, fa4, fa5
-; VISNI-NEXT: ret
%bo = fdiv <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
index a90980bcbbf42..b096c1c0f7e43 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
@@ -37,15 +37,6 @@ define <4 x i32> @insertelt_v4i32_idx(<4 x i32> %a, i32 %y, i32 zeroext %idx) {
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
-;
-; VISNI-LABEL: insertelt_v4i32_idx:
-; VISNI: # %bb.0:
-; VISNI-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; VISNI-NEXT: vmv.s.x v9, a0
-; VISNI-NEXT: addi a0, a1, 1
-; VISNI-NEXT: vsetvli zero, a0, e32, m1, tu, ma
-; VISNI-NEXT: vslideup.vx v8, v9, a1
-; VISNI-NEXT: ret
%b = insertelement <4 x i32> %a, i32 %y, i32 %idx
ret <4 x i32> %b
}
@@ -193,39 +184,6 @@ define <64 x i32> @insertelt_v64i32_idx(<64 x i32> %a, i32 %y, i32 zeroext %idx)
; RV64-NEXT: addi sp, sp, 384
; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
-;
-; VISNI-LABEL: insertelt_v64i32_idx:
-; VISNI: # %bb.0:
-; VISNI-NEXT: addi sp, sp, -384
-; VISNI-NEXT: .cfi_def_cfa_offset 384
-; VISNI-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
-; VISNI-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
-; VISNI-NEXT: .cfi_offset ra, -8
-; VISNI-NEXT: .cfi_offset s0, -16
-; VISNI-NEXT: addi s0, sp, 384
-; VISNI-NEXT: .cfi_def_cfa s0, 0
-; VISNI-NEXT: andi sp, sp, -128
-; VISNI-NEXT: addi a2, sp, 128
-; VISNI-NEXT: li a3, 32
-; VISNI-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; VISNI-NEXT: vse32.v v16, (a2)
-; VISNI-NEXT: mv a3, sp
-; VISNI-NEXT: vse32.v v8, (a3)
-; VISNI-NEXT: andi a1, a1, 63
-; VISNI-NEXT: slli a1, a1, 2
-; VISNI-NEXT: add a1, a3, a1
-; VISNI-NEXT: sw a0, 0(a1)
-; VISNI-NEXT: vle32.v v8, (a3)
-; VISNI-NEXT: vle32.v v16, (a2)
-; VISNI-NEXT: addi sp, s0, -384
-; VISNI-NEXT: .cfi_def_cfa sp, 384
-; VISNI-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
-; VISNI-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
-; VISNI-NEXT: .cfi_restore ra
-; VISNI-NEXT: .cfi_restore s0
-; VISNI-NEXT: addi sp, sp, 384
-; VISNI-NEXT: .cfi_def_cfa_offset 0
-; VISNI-NEXT: ret
%b = insertelement <64 x i32> %a, i32 %y, i32 %idx
ret <64 x i32> %b
}
@@ -309,19 +267,6 @@ define <3 x i64> @insertelt_v3i64(<3 x i64> %a, i64 %y) {
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: vslidedown.vi v8, v8, 1
; RV64-NEXT: ret
-;
-; VISNI-LABEL: insertelt_v3i64:
-; VISNI: # %bb.0:
-; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; VISNI-NEXT: vmv.x.s a1, v8
-; VISNI-NEXT: vmv.v.x v10, a1
-; VISNI-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; VISNI-NEXT: ri.vextract.x.v a1, v8, 1
-; VISNI-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; VISNI-NEXT: vslide1down.vx v8, v10, a1
-; VISNI-NEXT: vslide1down.vx v8, v8, a0
-; VISNI-NEXT: vslidedown.vi v8, v8, 1
-; VISNI-NEXT: ret
%b = insertelement <3 x i64> %a, i64 %y, i32 2
ret <3 x i64> %b
}
@@ -390,18 +335,6 @@ define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) {
; RV64-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; RV64-NEXT: vslideup.vx v8, v12, a1
; RV64-NEXT: ret
-;
-; VISNI-LABEL: insertelt_v32i16:
-; VISNI: # %bb.0:
-; VISNI-NEXT: li a2, 32
-; VISNI-NEXT: vsetvli zero, a2, e16, m1, ta, ma
-; VISNI-NEXT: vmv.s.x v12, a0
-; VISNI-NEXT: slli a1, a1, 32
-; VISNI-NEXT: srli a1, a1, 32
-; VISNI-NEXT: addi a0, a1, 1
-; VISNI-NEXT: vsetvli zero, a0, e16, m4, tu, ma
-; VISNI-NEXT: vslideup.vx v8, v12, a1
-; VISNI-NEXT: ret
%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
ret <32 x i16> %b
}
@@ -834,16 +767,6 @@ define <4 x bfloat> @insertelt_v4bf16_idx(<4 x bfloat> %a, bfloat %y, i32 zeroex
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
-;
-; VISNI-LABEL: insertelt_v4bf16_idx:
-; VISNI: # %bb.0:
-; VISNI-NEXT: fmv.x.h a1, fa0
-; VISNI-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; VISNI-NEXT: vmv.s.x v9, a1
-; VISNI-NEXT: addi a1, a0, 1
-; VISNI-NEXT: vsetvli zero, a1, e16, mf2, tu, ma
-; VISNI-NEXT: vslideup.vx v8, v9, a0
-; VISNI-NEXT: ret
%b = insertelement <4 x bfloat> %a, bfloat %y, i32 %idx
ret <4 x bfloat> %b
}
@@ -905,15 +828,6 @@ define <4 x half> @insertelt_v4f16_idx(<4 x half> %a, half %y, i32 zeroext %idx)
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, mf2, tu, ma
; ZVFHMIN-NEXT: vslideup.vx v8, v9, a0
; ZVFHMIN-NEXT: ret
-;
-; VISNI-LABEL: insertelt_v4f16_idx:
-; VISNI: # %bb.0:
-; VISNI-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; VISNI-NEXT: vfmv.s.f v9, fa0
-; VISNI-NEXT: addi a1, a0, 1
-; VISNI-NEXT: vsetvli zero, a1, e16, mf2, tu, ma
-; VISNI-NEXT: vslideup.vx v8, v9, a0
-; VISNI-NEXT: ret
%b = insertelement <4 x half> %a, half %y, i32 %idx
ret <4 x half> %b
}
@@ -927,15 +841,6 @@ define <2 x i8> @pr169017(<4 x i16> %vecinit, <2 x i8> %dst_vec) {
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
-;
-; VISNI-LABEL: pr169017:
-; VISNI: # %bb.0: # %entry
-; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; VISNI-NEXT: vmv.x.s a0, v8
-; VISNI-NEXT: vmv1r.v v8, v9
-; VISNI-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
-; VISNI-NEXT: vmv.s.x v8, a0
-; VISNI-NEXT: ret
entry:
%cast = bitcast <4 x i16> %vecinit to i64
%trunc = trunc i64 %cast to i8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index dd1f1c9b8a67e..94429ac18dd3d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -1243,14 +1243,6 @@ define void @vnsrl_32_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVZIP-NEXT: vpairo.vv v10, v8, v9
; ZVZIP-NEXT: vse32.v v10, (a2)
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vnsrl_32_i32_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a1)
-; ZIP-NEXT: vle32.v v9, (a0)
-; ZIP-NEXT: ri.vzipodd.vv v10, v9, v8
-; ZIP-NEXT: vse32.v v10, (a2)
-; ZIP-NEXT: ret
entry:
%0 = load <2 x i32>, ptr %in0, align 4
%1 = load <2 x i32>, ptr %in1, align 4
@@ -1323,14 +1315,6 @@ define void @vnsrl_32_float_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVZIP-NEXT: vpairo.vv v10, v8, v9
; ZVZIP-NEXT: vse32.v v10, (a2)
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vnsrl_32_float_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a1)
-; ZIP-NEXT: vle32.v v9, (a0)
-; ZIP-NEXT: ri.vzipodd.vv v10, v9, v8
-; ZIP-NEXT: vse32.v v10, (a2)
-; ZIP-NEXT: ret
entry:
%0 = load <2 x float>, ptr %in0, align 4
%1 = load <2 x float>, ptr %in1, align 4
@@ -1403,14 +1387,6 @@ define void @vnsrl_64_i64_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVZIP-NEXT: vpairo.vv v10, v8, v9
; ZVZIP-NEXT: vse64.v v10, (a2)
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vnsrl_64_i64_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a1)
-; ZIP-NEXT: vle64.v v9, (a0)
-; ZIP-NEXT: ri.vzipodd.vv v10, v9, v8
-; ZIP-NEXT: vse64.v v10, (a2)
-; ZIP-NEXT: ret
entry:
%0 = load <2 x i64>, ptr %in0, align 8
%1 = load <2 x i64>, ptr %in1, align 8
@@ -1480,14 +1456,6 @@ define void @vnsrl_64_double_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVZIP-NEXT: vpairo.vv v10, v8, v9
; ZVZIP-NEXT: vse64.v v10, (a2)
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vnsrl_64_double_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a1)
-; ZIP-NEXT: vle64.v v9, (a0)
-; ZIP-NEXT: ri.vzipodd.vv v10, v9, v8
-; ZIP-NEXT: vse64.v v10, (a2)
-; ZIP-NEXT: ret
entry:
%0 = load <2 x double>, ptr %in0, align 8
%1 = load <2 x double>, ptr %in1, align 8
@@ -1565,14 +1533,6 @@ define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; ZVZIP-NEXT: vslideup.vi v10, v12, 2
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
-; ZIP-LABEL: unzip2a_dual_v4i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v9, v10
-; ZIP-NEXT: ri.vunzip2a.vv v9, v8, v11
-; ZIP-NEXT: vslideup.vi v9, v12, 2
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i64> %c
@@ -1988,14 +1948,6 @@ define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; ZVZIP-NEXT: vslideup.vi v10, v12, 2
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
-; ZIP-LABEL: unzip2b_dual_v4i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2b.vv v12, v9, v10
-; ZIP-NEXT: ri.vunzip2b.vv v9, v8, v11
-; ZIP-NEXT: vslideup.vi v9, v12, 2
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x i64> %c
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
index 63ed63138976b..b4fdd5f9a9d37 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
@@ -628,60 +628,6 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: .cfi_def_cfa_offset 0
; ZVZIP-NEXT: ret
-; ZIP-LABEL: interleave_v32i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: .cfi_def_cfa_offset 16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 24
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 4
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 16
-; ZIP-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; ZIP-NEXT: vmv8r.v v24, v8
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: vslidedown.vi v8, v16, 16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 16
-; ZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: vslidedown.vi v8, v24, 16
-; ZIP-NEXT: lui a0, 699051
-; ZIP-NEXT: addi a0, a0, -1366
-; ZIP-NEXT: vmv.s.x v0, a0
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 16
-; ZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: ri.vzip2a.vv v16, v24, v8, v0.t
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 4
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 16
-; ZIP-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: ri.vzip2a.vv v0, v8, v24
-; ZIP-NEXT: vmv.v.v v8, v0
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 24
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: .cfi_def_cfa sp, 16
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: .cfi_def_cfa_offset 0
-; ZIP-NEXT: ret
%a = shufflevector <32 x i32> %x, <32 x i32> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
ret <64 x i32> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index 1701f95049172..e58ee62d1a90f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -39,22 +39,6 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv
; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: vmsne.vi v8, v14, 0
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv.v.i v8, 0
-; ZIP-NEXT: vmerge.vim v10, v8, 1, v0
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZIP-NEXT: vslidedown.vx v0, v0, a0
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmerge.vim v8, v8, 1, v0
-; ZIP-NEXT: ri.vunzip2a.vv v12, v10, v8
-; ZIP-NEXT: vmsne.vi v0, v12, 0
-; ZIP-NEXT: ri.vunzip2b.vv v12, v10, v8
-; ZIP-NEXT: vmsne.vi v8, v12, 0
-; ZIP-NEXT: ret
%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
}
@@ -273,26 +257,6 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vmsne.vi v8, v24, 0
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv.v.i v24, 0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v24, 1, v0
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmsne.vi v0, v24, 0
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2b.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v24, v8, v12
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmsne.vi v8, v24, 0
-; ZIP-NEXT: ret
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval
}
@@ -3903,15 +3867,6 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
; ZVZIP-NEXT: vzip.vv v8, v14, v12
; ZVZIP-NEXT: ret
-; ZIP-LABEL: deinterleave_interleave2:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vnsrl.wi v12, v8, 0
-; ZIP-NEXT: vnsrl.wx v16, v8, a0
-; ZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v8, v12, v16
-; ZIP-NEXT: ret
entry:
%0 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %arg)
%a = extractvalue { <8 x float>, <8 x float> } %0, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 3d9d84e2d3de3..a56bb463dd2c4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -59,20 +59,6 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_v32i1_v16i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v0, v8, 2
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZIP-NEXT: vmv.v.i v8, 0
-; ZIP-NEXT: vmerge.vim v8, v8, 1, v0
-; ZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v8, 16
-; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v12, v8, v10
-; ZIP-NEXT: vmsne.vi v0, v12, 0
-; ZIP-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
}
@@ -263,32 +249,6 @@ define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave3_v6i32_v2i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg3e32.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle32.v v9, (a2)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <6 x i32> @llvm.vector.interleave3.v6i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)
ret <6 x i32> %res
}
@@ -386,36 +346,6 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave4_v8i32_v2i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vle32.v v9, (a1)
-; ZIP-NEXT: vle32.v v10, (a2)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 2
-; ZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v10, (a3)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
}
@@ -522,39 +452,6 @@ define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave5_v10i16_v2i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg5e16.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a2, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vle16.v v10, (a3)
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v11, v10, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v11, 4
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
ret <10 x i16> %res
}
@@ -676,44 +573,6 @@ define <12 x i16> @vector_interleave6_v12i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave6_v12i16_v2i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a2, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vle16.v v10, (a3)
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: add a3, a3, a1
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v11, v10, 2
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v9, (a1)
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v11, 4
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v10, (a3)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 2
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <12 x i16> @llvm.vector.interleave6.v12i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f)
ret <12 x i16> %res
}
@@ -844,47 +703,6 @@ define <14 x i8> @vector_interleave7_v14i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave7_v14i8_v2i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vsseg7e8.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 3
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vle8.v v9, (a3)
-; ZIP-NEXT: add a3, a3, a1
-; ZIP-NEXT: vle8.v v10, (a2)
-; ZIP-NEXT: add a2, a3, a1
-; ZIP-NEXT: add a4, a2, a1
-; ZIP-NEXT: vle8.v v11, (a4)
-; ZIP-NEXT: vle8.v v8, (a0)
-; ZIP-NEXT: vle8.v v12, (a2)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 2
-; ZIP-NEXT: add a1, a4, a1
-; ZIP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vle8.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 4
-; ZIP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vle8.v v9, (a3)
-; ZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v10, 4
-; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 6
-; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <14 x i8> @llvm.vector.interleave7.v14i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g)
ret <14 x i8> %res
}
@@ -1024,50 +842,6 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave8_v16i8_v2i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vsseg8e8.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 3
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: add a5, a4, a1
-; ZIP-NEXT: add a6, a5, a1
-; ZIP-NEXT: vle8.v v9, (a6)
-; ZIP-NEXT: vle8.v v10, (a5)
-; ZIP-NEXT: add a6, a6, a1
-; ZIP-NEXT: vle8.v v11, (a6)
-; ZIP-NEXT: vle8.v v12, (a2)
-; ZIP-NEXT: vle8.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 2
-; ZIP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vle8.v v9, (a3)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 2
-; ZIP-NEXT: add a1, a6, a1
-; ZIP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vle8.v v12, (a1)
-; ZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v11, 4
-; ZIP-NEXT: vslideup.vi v8, v9, 4
-; ZIP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vle8.v v9, (a4)
-; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v12, 6
-; ZIP-NEXT: vslideup.vi v8, v9, 6
-; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)
ret <16 x i8> %res
}
@@ -1432,32 +1206,6 @@ define <6 x float> @vector_interleave3_v6f32_v2f32(<2 x float> %a, <2 x float> %
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave3_v6f32_v2f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg3e32.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle32.v v9, (a2)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <6 x float> @llvm.vector.interleave3.v6f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
ret <6 x float> %res
}
@@ -1555,36 +1303,6 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave4_v8f32_v2f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vle32.v v9, (a1)
-; ZIP-NEXT: vle32.v v10, (a2)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 2
-; ZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v10, (a3)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)
ret <8 x float> %res
}
@@ -1691,39 +1409,6 @@ define <10 x half> @vector_interleave5_v10f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave5_v10f16_v2f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg5e16.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a2, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vle16.v v10, (a3)
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v11, v10, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v11, 4
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <10 x half> @llvm.vector.interleave5.v10f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e)
ret <10 x half> %res
}
@@ -1951,44 +1636,6 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave6_v12f16_v2f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a2, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vle16.v v10, (a3)
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: add a3, a3, a1
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v11, v10, 2
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v9, (a1)
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v11, 4
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v10, (a3)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 2
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <12 x half> @llvm.vector.interleave6.v12f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f)
ret <12 x half> %res
}
@@ -2246,49 +1893,6 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave7_v7f16_v1f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg7e16.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vle16.v v9, (a3)
-; ZIP-NEXT: add a3, a3, a1
-; ZIP-NEXT: vle16.v v10, (a2)
-; ZIP-NEXT: add a2, a3, a1
-; ZIP-NEXT: add a4, a2, a1
-; ZIP-NEXT: vle16.v v11, (a4)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v12, (a2)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 1
-; ZIP-NEXT: add a1, a4, a1
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 1
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v9, (a3)
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v10, 2
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 3
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <7 x half> @llvm.vector.interleave7.v7f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g)
ret <7 x half> %res
}
@@ -2570,52 +2174,6 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: addi sp, sp, 16
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave8_v8f16_v1f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg8e16.v v8, (a0)
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: add a5, a4, a1
-; ZIP-NEXT: add a6, a5, a1
-; ZIP-NEXT: vle16.v v9, (a6)
-; ZIP-NEXT: vle16.v v10, (a5)
-; ZIP-NEXT: add a6, a6, a1
-; ZIP-NEXT: vle16.v v11, (a6)
-; ZIP-NEXT: vle16.v v12, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 1
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v9, (a3)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 1
-; ZIP-NEXT: add a1, a6, a1
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v12, (a1)
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v9, (a4)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v12, 3
-; ZIP-NEXT: vslideup.vi v8, v9, 3
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave8.v8f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h)
ret <8 x half> %res
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index ab7a1dabe3624..b4053654e42f2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -66,24 +66,6 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZVZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; ZVZIP-NEXT: vslideup.vx v0, v12, a0
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv.v.i v10, 0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmerge.vim v12, v10, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v10, 1, v0
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: vmsne.vi v14, v10, 0
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmsne.vi v0, v10, 0
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZIP-NEXT: vslideup.vx v0, v14, a0
-; ZIP-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
ret <vscale x 32 x i1> %res
}
@@ -285,26 +267,6 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vmsne.vi v8, v24, 0
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv128i1_nxv64i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv.v.i v24, 0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v24, 1, v0
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmsne.vi v0, v24, 0
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v12, v20
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmsne.vi v8, v24, 0
-; ZIP-NEXT: ret
%res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
ret <vscale x 128 x i1> %res
}
@@ -1596,71 +1558,6 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv80i8_nxv16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vsseg5e8.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vsseg5e8.v v17, (a1)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vl1r.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1r.v v11, (a4)
-; ZIP-NEXT: vl1r.v v8, (a0)
-; ZIP-NEXT: vl1r.v v9, (a3)
-; ZIP-NEXT: add a0, a1, a2
-; ZIP-NEXT: vl1r.v v14, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1r.v v15, (a0)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1r.v v12, (a4)
-; ZIP-NEXT: vl1r.v v13, (a1)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1r.v v16, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1r.v v17, (a0)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 10
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8r.v v16, (a2)
-; ZIP-NEXT: vl8r.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 80 x i8> @llvm.vector.interleave5.nxv80i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e)
ret <vscale x 80 x i8> %res
}
@@ -2056,71 +1953,6 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv20i32_nxv4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vsseg5e32.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vsseg5e32.v v17, (a1)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re32.v v11, (a4)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: add a0, a1, a2
-; ZIP-NEXT: vl1re32.v v14, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re32.v v15, (a0)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re32.v v12, (a4)
-; ZIP-NEXT: vl1re32.v v13, (a1)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re32.v v16, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re32.v v17, (a0)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 10
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 20 x i32> @llvm.vector.interleave5.nxv20i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e)
ret <vscale x 20 x i32> %res
}
@@ -2457,71 +2289,6 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv10i64_nxv2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vsseg5e64.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vsseg5e64.v v17, (a1)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re64.v v11, (a4)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: add a0, a1, a2
-; ZIP-NEXT: vl1re64.v v14, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re64.v v15, (a0)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re64.v v12, (a4)
-; ZIP-NEXT: vl1re64.v v13, (a1)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re64.v v16, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re64.v v17, (a0)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 10
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 10 x i64> @llvm.vector.interleave5.nxv10i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e)
ret <vscale x 10 x i64> %res
}
@@ -3058,76 +2825,6 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv96i8_nxv16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v23, v13
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v25, v17
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 6
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vsseg6e8.v v21, (a0)
-; ZIP-NEXT: vmv1r.v v21, v10
-; ZIP-NEXT: vmv1r.v v22, v12
-; ZIP-NEXT: vmv1r.v v23, v14
-; ZIP-NEXT: vmv1r.v v24, v16
-; ZIP-NEXT: vmv1r.v v25, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg6e8.v v20, (a1)
-; ZIP-NEXT: vl1r.v v14, (a0)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1r.v v15, (a0)
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1r.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v13, (a6)
-; ZIP-NEXT: vl1r.v v10, (a4)
-; ZIP-NEXT: vl1r.v v11, (a5)
-; ZIP-NEXT: vl1r.v v8, (a1)
-; ZIP-NEXT: vl1r.v v9, (a3)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a1, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1r.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a2
-; ZIP-NEXT: vl1r.v v19, (a3)
-; ZIP-NEXT: vl1r.v v16, (a0)
-; ZIP-NEXT: vl1r.v v17, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 12
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8r.v v16, (a2)
-; ZIP-NEXT: vl8r.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 96 x i8> @llvm.vector.interleave6.nxv96i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f)
ret <vscale x 96 x i8> %res
}
@@ -3550,76 +3247,6 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv24i32_nxv4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v23, v13
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v25, v17
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 6
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vsseg6e32.v v21, (a0)
-; ZIP-NEXT: vmv1r.v v21, v10
-; ZIP-NEXT: vmv1r.v v22, v12
-; ZIP-NEXT: vmv1r.v v23, v14
-; ZIP-NEXT: vmv1r.v v24, v16
-; ZIP-NEXT: vmv1r.v v25, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg6e32.v v20, (a1)
-; ZIP-NEXT: vl1re32.v v14, (a0)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re32.v v15, (a0)
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v13, (a6)
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: vl1re32.v v11, (a5)
-; ZIP-NEXT: vl1re32.v v8, (a1)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a1, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re32.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a2
-; ZIP-NEXT: vl1re32.v v19, (a3)
-; ZIP-NEXT: vl1re32.v v16, (a0)
-; ZIP-NEXT: vl1re32.v v17, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 12
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 24 x i32> @llvm.vector.interleave6.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f)
ret <vscale x 24 x i32> %res
}
@@ -3980,76 +3607,6 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv12i64_nxv2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v23, v13
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v25, v17
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 6
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vsseg6e64.v v21, (a0)
-; ZIP-NEXT: vmv1r.v v21, v10
-; ZIP-NEXT: vmv1r.v v22, v12
-; ZIP-NEXT: vmv1r.v v23, v14
-; ZIP-NEXT: vmv1r.v v24, v16
-; ZIP-NEXT: vmv1r.v v25, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg6e64.v v20, (a1)
-; ZIP-NEXT: vl1re64.v v14, (a0)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re64.v v15, (a0)
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v13, (a6)
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: vl1re64.v v11, (a5)
-; ZIP-NEXT: vl1re64.v v8, (a1)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a1, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re64.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a2
-; ZIP-NEXT: vl1re64.v v19, (a3)
-; ZIP-NEXT: vl1re64.v v16, (a0)
-; ZIP-NEXT: vl1re64.v v17, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 12
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 12 x i64> @llvm.vector.interleave6.nxv12i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f)
ret <vscale x 12 x i64> %res
}
@@ -4649,86 +4206,6 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv112i8_nxv16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e8.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e8.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1r.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1r.v v11, (a4)
-; ZIP-NEXT: vl1r.v v8, (a1)
-; ZIP-NEXT: vl1r.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1r.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1r.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1r.v v14, (a4)
-; ZIP-NEXT: vl1r.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1r.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1r.v v19, (a3)
-; ZIP-NEXT: vl1r.v v16, (a2)
-; ZIP-NEXT: vl1r.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1r.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1r.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8r.v v16, (a0)
-; ZIP-NEXT: vl8r.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 112 x i8> @llvm.vector.interleave7.nxv112i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g)
ret <vscale x 112 x i8> %res
}
@@ -5140,86 +4617,6 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv56i16_nxv8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e16.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v11, (a4)
-; ZIP-NEXT: vl1re16.v v8, (a1)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v14, (a4)
-; ZIP-NEXT: vl1re16.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1re16.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v19, (a3)
-; ZIP-NEXT: vl1re16.v v16, (a2)
-; ZIP-NEXT: vl1re16.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8re16.v v16, (a0)
-; ZIP-NEXT: vl8re16.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 56 x i16> @llvm.vector.interleave7.nxv56i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g)
ret <vscale x 56 x i16> %res
}
@@ -5631,86 +5028,6 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv28i32_nxv4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e32.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e32.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v11, (a4)
-; ZIP-NEXT: vl1re32.v v8, (a1)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v14, (a4)
-; ZIP-NEXT: vl1re32.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1re32.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re32.v v19, (a3)
-; ZIP-NEXT: vl1re32.v v16, (a2)
-; ZIP-NEXT: vl1re32.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re32.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re32.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8re32.v v16, (a0)
-; ZIP-NEXT: vl8re32.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 28 x i32> @llvm.vector.interleave7.nxv28i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g)
ret <vscale x 28 x i32> %res
}
@@ -6121,86 +5438,6 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv14i64_nxv2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e64.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e64.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v11, (a4)
-; ZIP-NEXT: vl1re64.v v8, (a1)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v14, (a4)
-; ZIP-NEXT: vl1re64.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1re64.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re64.v v19, (a3)
-; ZIP-NEXT: vl1re64.v v16, (a2)
-; ZIP-NEXT: vl1re64.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re64.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re64.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8re64.v v16, (a0)
-; ZIP-NEXT: vl8re64.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 14 x i64> @llvm.vector.interleave7.nxv14i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g)
ret <vscale x 14 x i64> %res
}
@@ -7007,17 +6244,6 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; ZVZIP-NEXT: vslideup.vx v10, v8, a0
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv4bf16_nxv2bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v11, v8, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vx v10, v11, a0
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)
ret <vscale x 4 x bfloat> %res
}
@@ -7092,17 +6318,6 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; ZVZIP-NEXT: vslideup.vx v10, v8, a0
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv4f16_nxv2f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v11, v8, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vx v10, v11, a0
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
%res = call <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
ret <vscale x 4 x half> %res
}
@@ -9110,71 +8325,6 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv40f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vsseg5e16.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vsseg5e16.v v17, (a1)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re16.v v11, (a4)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: add a0, a1, a2
-; ZIP-NEXT: vl1re16.v v14, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re16.v v15, (a0)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re16.v v12, (a4)
-; ZIP-NEXT: vl1re16.v v13, (a1)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re16.v v16, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re16.v v17, (a0)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 10
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 40 x half> @llvm.vector.interleave5.nxv40f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4)
ret <vscale x 40 x half> %res
}
@@ -9641,71 +8791,6 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv40bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vsseg5e16.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vsseg5e16.v v17, (a1)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re16.v v11, (a4)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: add a0, a1, a2
-; ZIP-NEXT: vl1re16.v v14, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re16.v v15, (a0)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re16.v v12, (a4)
-; ZIP-NEXT: vl1re16.v v13, (a1)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re16.v v16, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re16.v v17, (a0)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 10
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 40 x bfloat> @llvm.vector.interleave5.nxv40bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4)
ret <vscale x 40 x bfloat> %res
}
@@ -10172,71 +9257,6 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv20f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vsseg5e32.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vsseg5e32.v v17, (a1)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re32.v v11, (a4)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: add a0, a1, a2
-; ZIP-NEXT: vl1re32.v v14, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re32.v v15, (a0)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re32.v v12, (a4)
-; ZIP-NEXT: vl1re32.v v13, (a1)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re32.v v16, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re32.v v17, (a0)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 10
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 20 x float> @llvm.vector.interleave5.nxv20f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4)
ret <vscale x 20 x float> %res
}
@@ -10629,71 +9649,6 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv10f64_nxv2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vsseg5e64.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vsseg5e64.v v17, (a1)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re64.v v11, (a4)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: add a0, a1, a2
-; ZIP-NEXT: vl1re64.v v14, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re64.v v15, (a0)
-; ZIP-NEXT: add a4, a4, a2
-; ZIP-NEXT: vl1re64.v v12, (a4)
-; ZIP-NEXT: vl1re64.v v13, (a1)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re64.v v16, (a0)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: vl1re64.v v17, (a0)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 10
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 10 x double> @llvm.vector.interleave5.nxv10f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4)
ret <vscale x 10 x double> %res
}
@@ -11197,76 +10152,6 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv48f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v23, v13
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v25, v17
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 6
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vsseg6e16.v v21, (a0)
-; ZIP-NEXT: vmv1r.v v21, v10
-; ZIP-NEXT: vmv1r.v v22, v12
-; ZIP-NEXT: vmv1r.v v23, v14
-; ZIP-NEXT: vmv1r.v v24, v16
-; ZIP-NEXT: vmv1r.v v25, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg6e16.v v20, (a1)
-; ZIP-NEXT: vl1re16.v v14, (a0)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re16.v v15, (a0)
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v13, (a6)
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: vl1re16.v v11, (a5)
-; ZIP-NEXT: vl1re16.v v8, (a1)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a1, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re16.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a2
-; ZIP-NEXT: vl1re16.v v19, (a3)
-; ZIP-NEXT: vl1re16.v v16, (a0)
-; ZIP-NEXT: vl1re16.v v17, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 12
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 48 x half> @llvm.vector.interleave6.nxv48f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5)
ret <vscale x 48 x half> %res
}
@@ -11770,76 +10655,6 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv48bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v23, v13
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v25, v17
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 6
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vsseg6e16.v v21, (a0)
-; ZIP-NEXT: vmv1r.v v21, v10
-; ZIP-NEXT: vmv1r.v v22, v12
-; ZIP-NEXT: vmv1r.v v23, v14
-; ZIP-NEXT: vmv1r.v v24, v16
-; ZIP-NEXT: vmv1r.v v25, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg6e16.v v20, (a1)
-; ZIP-NEXT: vl1re16.v v14, (a0)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re16.v v15, (a0)
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v13, (a6)
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: vl1re16.v v11, (a5)
-; ZIP-NEXT: vl1re16.v v8, (a1)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a1, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re16.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a2
-; ZIP-NEXT: vl1re16.v v19, (a3)
-; ZIP-NEXT: vl1re16.v v16, (a0)
-; ZIP-NEXT: vl1re16.v v17, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 12
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 48 x bfloat> @llvm.vector.interleave6.nxv48bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5)
ret <vscale x 48 x bfloat> %res
}
@@ -12343,76 +11158,6 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv24f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v23, v13
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v25, v17
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 6
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vsseg6e32.v v21, (a0)
-; ZIP-NEXT: vmv1r.v v21, v10
-; ZIP-NEXT: vmv1r.v v22, v12
-; ZIP-NEXT: vmv1r.v v23, v14
-; ZIP-NEXT: vmv1r.v v24, v16
-; ZIP-NEXT: vmv1r.v v25, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg6e32.v v20, (a1)
-; ZIP-NEXT: vl1re32.v v14, (a0)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re32.v v15, (a0)
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v13, (a6)
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: vl1re32.v v11, (a5)
-; ZIP-NEXT: vl1re32.v v8, (a1)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a1, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re32.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a2
-; ZIP-NEXT: vl1re32.v v19, (a3)
-; ZIP-NEXT: vl1re32.v v16, (a0)
-; ZIP-NEXT: vl1re32.v v17, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 12
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 24 x float> @llvm.vector.interleave6.nxv24f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5)
ret <vscale x 24 x float> %res
}
@@ -12834,76 +11579,6 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv12f64_nxv2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v23, v13
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v25, v17
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 6
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vsseg6e64.v v21, (a0)
-; ZIP-NEXT: vmv1r.v v21, v10
-; ZIP-NEXT: vmv1r.v v22, v12
-; ZIP-NEXT: vmv1r.v v23, v14
-; ZIP-NEXT: vmv1r.v v24, v16
-; ZIP-NEXT: vmv1r.v v25, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg6e64.v v20, (a1)
-; ZIP-NEXT: vl1re64.v v14, (a0)
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re64.v v15, (a0)
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v13, (a6)
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: vl1re64.v v11, (a5)
-; ZIP-NEXT: vl1re64.v v8, (a1)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: add a0, a0, a2
-; ZIP-NEXT: add a1, a0, a2
-; ZIP-NEXT: add a3, a1, a2
-; ZIP-NEXT: vl1re64.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a2
-; ZIP-NEXT: vl1re64.v v19, (a3)
-; ZIP-NEXT: vl1re64.v v16, (a0)
-; ZIP-NEXT: vl1re64.v v17, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 12
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 12 x double> @llvm.vector.interleave6.nxv12f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5)
ret <vscale x 12 x double> %res
}
@@ -13461,86 +12136,6 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv56f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e16.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v11, (a4)
-; ZIP-NEXT: vl1re16.v v8, (a1)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v14, (a4)
-; ZIP-NEXT: vl1re16.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1re16.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v19, (a3)
-; ZIP-NEXT: vl1re16.v v16, (a2)
-; ZIP-NEXT: vl1re16.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8re16.v v16, (a0)
-; ZIP-NEXT: vl8re16.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 56 x half> @llvm.vector.interleave7.nxv56f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6)
ret <vscale x 56 x half> %res
}
@@ -14098,86 +12693,6 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv56bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e16.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v11, (a4)
-; ZIP-NEXT: vl1re16.v v8, (a1)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re16.v v14, (a4)
-; ZIP-NEXT: vl1re16.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1re16.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v19, (a3)
-; ZIP-NEXT: vl1re16.v v16, (a2)
-; ZIP-NEXT: vl1re16.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re16.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8re16.v v16, (a0)
-; ZIP-NEXT: vl8re16.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 56 x bfloat> @llvm.vector.interleave7.nxv56bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6)
ret <vscale x 56 x bfloat> %res
}
@@ -14735,86 +13250,6 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv28f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e32.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e32.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v11, (a4)
-; ZIP-NEXT: vl1re32.v v8, (a1)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re32.v v14, (a4)
-; ZIP-NEXT: vl1re32.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1re32.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re32.v v19, (a3)
-; ZIP-NEXT: vl1re32.v v16, (a2)
-; ZIP-NEXT: vl1re32.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re32.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re32.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8re32.v v16, (a0)
-; ZIP-NEXT: vl8re32.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 28 x float> @llvm.vector.interleave7.nxv28f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6)
ret <vscale x 28 x float> %res
}
@@ -15290,86 +13725,6 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: addi sp, sp, 80
; ZVZIP-NEXT: ret
-; ZIP-LABEL: vector_interleave_nxv14f64_nxv2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: addi a1, sp, 64
-; ZIP-NEXT: vsseg7e64.v v1, (a1)
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: slli a0, a2, 3
-; ZIP-NEXT: sub a2, a0, a2
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: vsseg7e64.v v21, (a2)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: add a4, a3, a0
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v11, (a4)
-; ZIP-NEXT: vl1re64.v v8, (a1)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v12, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v13, (a4)
-; ZIP-NEXT: add a4, a4, a0
-; ZIP-NEXT: vl1re64.v v14, (a4)
-; ZIP-NEXT: vl1re64.v v15, (a2)
-; ZIP-NEXT: add a2, a2, a0
-; ZIP-NEXT: add a1, a2, a0
-; ZIP-NEXT: add a3, a1, a0
-; ZIP-NEXT: vl1re64.v v18, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re64.v v19, (a3)
-; ZIP-NEXT: vl1re64.v v16, (a2)
-; ZIP-NEXT: vl1re64.v v17, (a1)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re64.v v20, (a3)
-; ZIP-NEXT: add a3, a3, a0
-; ZIP-NEXT: vl1re64.v v21, (a3)
-; ZIP-NEXT: slli a1, a0, 2
-; ZIP-NEXT: slli a0, a0, 3
-; ZIP-NEXT: add a1, a0, a1
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a2, a2, a3
-; ZIP-NEXT: add a2, sp, a2
-; ZIP-NEXT: addi a2, a2, 64
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vs2r.v v20, (a1)
-; ZIP-NEXT: add a0, a2, a0
-; ZIP-NEXT: vs4r.v v16, (a0)
-; ZIP-NEXT: vs8r.v v8, (a2)
-; ZIP-NEXT: vl8re64.v v16, (a0)
-; ZIP-NEXT: vl8re64.v v8, (a2)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
%res = call <vscale x 14 x double> @llvm.vector.interleave7.nxv14f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6)
ret <vscale x 14 x double> %res
}
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