[llvm] bfca639 - [CodeGen][NFC] Store CPU model index in SubTypeKV (#207351)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 5 08:29:16 PDT 2026
Author: Alexis Engelke
Date: 2026-07-05T17:29:12+02:00
New Revision: bfca639ab943b4b2e16178797ebb01c84675ee65
URL: https://github.com/llvm/llvm-project/commit/bfca639ab943b4b2e16178797ebb01c84675ee65
DIFF: https://github.com/llvm/llvm-project/commit/bfca639ab943b4b2e16178797ebb01c84675ee65.diff
LOG: [CodeGen][NFC] Store CPU model index in SubTypeKV (#207351)
Instead of storing the pointer to the CPU model, store all CPU models in
an array and store the index. This is preliminary work for moving
SubTypeKV to .rodata.
NB: the scheduling models also take a fair amount of space in
.data.rel.ro, with SchedModels ~13kiB, ModelProcResources ~57kiB.
Added:
Modified:
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
llvm/include/llvm/MC/MCSubtargetInfo.h
llvm/lib/CodeGen/TargetSubtargetInfo.cpp
llvm/lib/MC/MCSubtargetInfo.cpp
llvm/unittests/CodeGen/MFCommon.inc
llvm/unittests/CodeGen/MachineInstrTest.cpp
llvm/unittests/CodeGen/MachineOperandTest.cpp
llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp
llvm/utils/TableGen/Common/CodeGenSchedule.h
llvm/utils/TableGen/SubtargetEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 8b8f64f49b595..8f13b0efaa068 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -43,6 +43,7 @@ class LibcallLoweringInfo;
class MachineInstr;
struct MachineSchedPolicy;
struct MCReadAdvanceEntry;
+struct MCSchedModel;
struct MCWriteLatencyEntry;
struct MCWriteProcResEntry;
class RegisterBankInfo;
@@ -70,7 +71,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
StringRef FS, ArrayRef<StringRef> PN,
ArrayRef<SubtargetFeatureKV> PF,
- ArrayRef<SubtargetSubTypeKV> PD,
+ ArrayRef<SubtargetSubTypeKV> PD, const MCSchedModel *PSM,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h b/llvm/include/llvm/MC/MCSubtargetInfo.h
index 652dca7e68a17..493c017830da4 100644
--- a/llvm/include/llvm/MC/MCSubtargetInfo.h
+++ b/llvm/include/llvm/MC/MCSubtargetInfo.h
@@ -77,24 +77,23 @@ struct SubtargetFeatureKVStorage {
struct SubtargetSubTypeKV {
private:
const char *Key; ///< K-V key string
- const MCSchedModel *SchedModel;
public:
FeatureBitArray Implies; ///< K-V bit mask
FeatureBitArray TuneImplies; ///< K-V bit mask
+ unsigned SchedModelIdx;
constexpr SubtargetSubTypeKV(const char *Key, FeatureBitArray Implies,
FeatureBitArray TuneImplies,
- const MCSchedModel *SchedModel)
- : Key(Key), SchedModel(SchedModel), Implies(Implies),
- TuneImplies(TuneImplies) {}
+ unsigned SchedModelIdx)
+ : Key(Key), Implies(Implies), TuneImplies(TuneImplies),
+ SchedModelIdx(SchedModelIdx) {}
// Because of relative string offsets, this type is not copyable.
SubtargetSubTypeKV(const SubtargetSubTypeKV &) = delete;
SubtargetSubTypeKV &operator=(const SubtargetSubTypeKV &) = delete;
const char *key() const { return Key; }
- const MCSchedModel *schedModel() const { return SchedModel; }
/// Compare routine for std::lower_bound
bool operator<(StringRef S) const { return StringRef(key()) < S; }
@@ -116,6 +115,7 @@ class LLVM_ABI MCSubtargetInfo {
ArrayRef<StringRef> ProcNames; // Processor list, including aliases
ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
+ const MCSchedModel *ProcSchedModels; ///< Processor scheduling models.
// Scheduler machine model
const MCWriteProcResEntry *WriteProcResTable;
@@ -134,7 +134,7 @@ class LLVM_ABI MCSubtargetInfo {
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
StringRef FS, ArrayRef<StringRef> PN,
ArrayRef<SubtargetFeatureKV> PF,
- ArrayRef<SubtargetSubTypeKV> PD,
+ ArrayRef<SubtargetSubTypeKV> PD, const MCSchedModel *PSM,
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP);
diff --git a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
index f85d456122780..56757962277b5 100644
--- a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
+++ b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
@@ -18,11 +18,12 @@ using namespace llvm;
TargetSubtargetInfo::TargetSubtargetInfo(
const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
ArrayRef<StringRef> PN, ArrayRef<SubtargetFeatureKV> PF,
- ArrayRef<SubtargetSubTypeKV> PD, const MCWriteProcResEntry *WPR,
- const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
- const InstrStage *IS, const unsigned *OC, const unsigned *FP)
- : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, WPR, WL, RA, IS, OC,
- FP) {}
+ ArrayRef<SubtargetSubTypeKV> PD, const MCSchedModel *PSM,
+ const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
+ const unsigned *FP)
+ : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM, WPR, WL, RA, IS,
+ OC, FP) {}
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp
index 013a2330a96d1..2b6875185c06e 100644
--- a/llvm/lib/MC/MCSubtargetInfo.cpp
+++ b/llvm/lib/MC/MCSubtargetInfo.cpp
@@ -259,13 +259,14 @@ void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU,
MCSubtargetInfo::MCSubtargetInfo(
const Triple &TT, StringRef C, StringRef TC, StringRef FS,
ArrayRef<StringRef> PN, ArrayRef<SubtargetFeatureKV> PF,
- ArrayRef<SubtargetSubTypeKV> PD, const MCWriteProcResEntry *WPR,
- const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
- const InstrStage *IS, const unsigned *OC, const unsigned *FP)
+ ArrayRef<SubtargetSubTypeKV> PD, const MCSchedModel *PSM,
+ const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
+ const unsigned *FP)
: TargetTriple(TT), CPU(std::string(C)), TuneCPU(std::string(TC)),
- ProcNames(PN), ProcFeatures(PF), ProcDesc(PD), WriteProcResTable(WPR),
- WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS),
- OperandCycles(OC), ForwardingPaths(FP) {
+ ProcNames(PN), ProcFeatures(PF), ProcDesc(PD), ProcSchedModels(PSM),
+ WriteProcResTable(WPR), WriteLatencyTable(WL), ReadAdvanceTable(RA),
+ Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
InitMCProcessorInfo(CPU, TuneCPU, FS);
}
@@ -449,8 +450,7 @@ const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
<< " (ignoring processor)\n";
return MCSchedModel::Default;
}
- assert(CPUEntry->schedModel() && "Missing processor SchedModel value");
- return *CPUEntry->schedModel();
+ return ProcSchedModels[CPUEntry->SchedModelIdx];
}
InstrItineraryData
diff --git a/llvm/unittests/CodeGen/MFCommon.inc b/llvm/unittests/CodeGen/MFCommon.inc
index 4499574276421..d773471a8e157 100644
--- a/llvm/unittests/CodeGen/MFCommon.inc
+++ b/llvm/unittests/CodeGen/MFCommon.inc
@@ -89,7 +89,8 @@ class BogusSubtarget : public TargetSubtargetInfo {
public:
BogusSubtarget(TargetMachine &TM)
: TargetSubtargetInfo(Triple(""), "", "", "", {}, {}, {}, nullptr,
- nullptr, nullptr, nullptr, nullptr, nullptr),
+ nullptr, nullptr, nullptr, nullptr, nullptr,
+ nullptr),
FL(), TL(TM, *this) {}
~BogusSubtarget() override = default;
@@ -144,7 +145,7 @@ public:
STI = std::make_unique<MCSubtargetInfo>(
Triple(""), "", "", "", ArrayRef<StringRef>{},
ArrayRef<SubtargetFeatureKV>{}, ArrayRef<SubtargetSubTypeKV>{}, nullptr,
- nullptr, nullptr, nullptr, nullptr, nullptr);
+ nullptr, nullptr, nullptr, nullptr, nullptr, nullptr);
}
~BogusTargetMachine() override = default;
diff --git a/llvm/unittests/CodeGen/MachineInstrTest.cpp b/llvm/unittests/CodeGen/MachineInstrTest.cpp
index 9fd7b1980929c..bdb6a1dfaf42f 100644
--- a/llvm/unittests/CodeGen/MachineInstrTest.cpp
+++ b/llvm/unittests/CodeGen/MachineInstrTest.cpp
@@ -44,7 +44,8 @@ std::unique_ptr<MCContext> createMCContext(const MCAsmInfo &AsmInfo) {
/*EnvironmentStr=*/"elf");
static MCRegisterInfo MRI;
static const MCSubtargetInfo STI(TheTriple, "", "", "", {}, {}, {}, nullptr,
- nullptr, nullptr, nullptr, nullptr, nullptr);
+ nullptr, nullptr, nullptr, nullptr, nullptr,
+ nullptr);
return std::make_unique<MCContext>(TheTriple, AsmInfo, MRI, STI, nullptr,
false);
}
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp
index 585d8f1a82dd3..bff2f86be726a 100644
--- a/llvm/unittests/CodeGen/MachineOperandTest.cpp
+++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp
@@ -354,7 +354,7 @@ TEST(MachineOperandTest, PrintMCSymbol) {
MCRegisterInfo MRI;
Triple T = Triple("unknown-unknown-unknown");
MCSubtargetInfo STI(T, "", "", "", {}, {}, {}, nullptr, nullptr, nullptr,
- nullptr, nullptr, nullptr);
+ nullptr, nullptr, nullptr, nullptr);
MCContext Ctx(T, MAI, MRI, STI);
MCSymbol *Sym = Ctx.getOrCreateSymbol("foo");
diff --git a/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp b/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp
index 6f035a1525d08..912056b1ca560 100644
--- a/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp
@@ -39,7 +39,7 @@ static std::string AArch64InstPrinterTestPrintAlignedLabel(uint64_t value) {
MCInstrInfo MII;
MCRegisterInfo MRI;
MCSubtargetInfo STI(Triple(""), "", "", "", {}, {}, {}, nullptr, nullptr,
- nullptr, nullptr, nullptr, nullptr);
+ nullptr, nullptr, nullptr, nullptr, nullptr);
MCContext Ctx(Triple(""), MAI, MRI, STI);
MCInst MI;
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.h b/llvm/utils/TableGen/Common/CodeGenSchedule.h
index 1d5e953cf70c7..7372d5698c0da 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h
@@ -478,11 +478,11 @@ class CodeGenSchedModels {
return ModelDef;
}
- const CodeGenProcModel &getModelForProc(const Record *ProcDef) const {
+ unsigned getModelIndexForProc(const Record *ProcDef) const {
const Record *ModelDef = getModelOrItinDef(ProcDef);
auto I = ProcModelMap.find(ModelDef);
assert(I != ProcModelMap.end() && "missing machine model");
- return ProcModels[I->second];
+ return I->second;
}
const CodeGenProcModel &getProcModel(const Record *ModelDef) const {
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 312148cb6ba8a..faf36300ada57 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -350,10 +350,8 @@ unsigned SubtargetEmitter::cpuKeyValues(raw_ostream &OS,
OS << ", ";
printFeatureMask(OS, TuneFeatureList, FeatureMap);
- // Emit the scheduler model pointer.
- const std::string &ProcModelName =
- SchedModels.getModelForProc(Processor).ModelName;
- OS << ", &" << ProcModelName << " },\n";
+ // Emit the scheduler model index.
+ OS << ", " << SchedModels.getModelIndexForProc(Processor) << " },\n";
}
// End processor table.
@@ -1470,10 +1468,13 @@ void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
PrintFatalError(PM.ModelDef->getLoc(),
"SchedMachineModel defines "
"ProcResources without defining WriteRes SchedWriteRes");
+ }
+ OS << "\n";
+ OS << "extern const llvm::MCSchedModel " << Target << "SchedModels[] = {\n";
+ for (const CodeGenProcModel &PM : SchedModels.procModels()) {
// Begin processor itinerary properties
- OS << "\n";
- OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";
+ OS << "{ // " << PM.ModelName << "\n";
emitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');
emitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');
emitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');
@@ -1518,8 +1519,9 @@ void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
OS << " &" << PM.ModelName << "ExtraInfo,\n";
else
OS << " nullptr // No extra processor descriptor\n";
- OS << "};\n";
+ OS << " },\n";
}
+ OS << "};\n";
}
//
@@ -2050,11 +2052,12 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
<< " ArrayRef<StringRef> PN,\n"
<< " ArrayRef<SubtargetFeatureKV> PF,\n"
<< " ArrayRef<SubtargetSubTypeKV> PD,\n"
+ << " const MCSchedModel *PSM,\n"
<< " const MCWriteProcResEntry *WPR,\n"
<< " const MCWriteLatencyEntry *WL,\n"
<< " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
<< " const unsigned *OC, const unsigned *FP) :\n"
- << " MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,\n"
+ << " MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,\n"
<< " WPR, WL, RA, IS, OC, FP) { }\n\n"
<< " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
<< " const MCInst *MI, const MCInstrInfo *MCII,\n"
@@ -2140,9 +2143,9 @@ SubtargetEmitter::emitMCDesc(raw_ostream &OS, const FeatureMapTy &FeatureMap) {
else
OS << "{}, ";
if (Res.NumProcs)
- OS << Target << "SubTypeKV, ";
+ OS << Target << "SubTypeKV, " << Target << "SchedModels, ";
else
- OS << "{}, ";
+ OS << "{}, nullptr, ";
OS << '\n';
OS.indent(22);
OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
@@ -2246,6 +2249,7 @@ void SubtargetEmitter::emitCtor(raw_ostream &OS, MCDescInfo DescInfo) {
<< Target << "FeatureKVStorage;\n";
}
OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";
+ OS << "extern const llvm::MCSchedModel " << Target << "SchedModels[];\n";
OS << "extern const llvm::MCWriteProcResEntry " << Target
<< "WriteProcResTable[];\n";
OS << "extern const llvm::MCWriteLatencyEntry " << Target
@@ -2276,10 +2280,12 @@ void SubtargetEmitter::emitCtor(raw_ostream &OS, MCDescInfo DescInfo) {
OS << "ArrayRef(" << Target << "FeatureKVStorage.Features), ";
else
OS << "{}, ";
- if (DescInfo.NumProcs)
- OS << "ArrayRef(" << Target << "SubTypeKV, " << DescInfo.NumProcs << "), ";
- else
- OS << "{}, ";
+ if (DescInfo.NumProcs) {
+ OS << "ArrayRef(" << Target << "SubTypeKV, " << DescInfo.NumProcs << "), "
+ << Target << "SchedModels, ";
+ } else {
+ OS << "{}, nullptr, ";
+ }
OS << '\n';
OS.indent(24);
OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "
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