[llvm] [AArch64][DAG] Port adde and sube combine to AArch64 (PR #202227)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ba17edfc3..2d530163a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -23065,7 +23065,8 @@ static SDValue foldADCToCINC(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond);
 }
 
-static SDValue performAddSubCarryCombine(SDNode *N, SelectionDAG &DAG, unsigned NewOpcode) {
+static SDValue performAddSubCarryCombine(SDNode *N, SelectionDAG &DAG,
+                                         unsigned NewOpcode) {
   SDValue RHS = N->getOperand(1);
   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
     APInt Imm = C->getAPIntValue();

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https://github.com/llvm/llvm-project/pull/202227