[clang] [llvm] [RISCV][P-ext] Improve codegen for packed reverse intrinsics (PR #207575)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 5 03:05:26 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Hongyu Chen (XChy)
<details>
<summary>Changes</summary>
This patch depends on https://github.com/llvm/llvm-project/pull/207574.
---
Full diff: https://github.com/llvm/llvm-project/pull/207575.diff
5 Files Affected:
- (modified) clang/lib/Headers/riscv_packed_simd.h (+32)
- (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+188)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+31)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+24)
- (added) llvm/test/CodeGen/RISCV/rvp-reverse.ll (+87)
``````````diff
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index c61e156ca6a7f..ae6bcfdbdcb3b 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -109,6 +109,21 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
return builtin(__rs1, __rs2); \
}
+/* Packed Reverse: reverse the order of the elements. Lowered to a single
+ * rev8/rev16/ppairoe.* by the backend's packed reverse-shuffle handling. */
+#define __packed_reverse2(name, ty) \
+ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
+ return __builtin_shufflevector(__rs1, __rs1, 1, 0); \
+ }
+#define __packed_reverse4(name, ty) \
+ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
+ return __builtin_shufflevector(__rs1, __rs1, 3, 2, 1, 0); \
+ }
+#define __packed_reverse8(name, ty) \
+ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
+ return __builtin_shufflevector(__rs1, __rs1, 7, 6, 5, 4, 3, 2, 1, 0); \
+ }
+
// clang-format off: macro call sites have no trailing semicolons, which
// confuses clang-format into a deeply nested expression.
@@ -390,6 +405,20 @@ __packed_unary_op(pnot_u16x4, uint16x4_t, ~)
__packed_unary_op(pnot_i32x2, int32x2_t, ~)
__packed_unary_op(pnot_u32x2, uint32x2_t, ~)
+/* Packed Reverse (32-bit) */
+__packed_reverse4(prev_i8x4, int8x4_t)
+__packed_reverse4(prev_u8x4, uint8x4_t)
+__packed_reverse2(prev_i16x2, int16x2_t)
+__packed_reverse2(prev_u16x2, uint16x2_t)
+
+/* Packed Reverse (64-bit) */
+__packed_reverse8(prev_i8x8, int8x8_t)
+__packed_reverse8(prev_u8x8, uint8x8_t)
+__packed_reverse4(prev_i16x4, int16x4_t)
+__packed_reverse4(prev_u16x4, uint16x4_t)
+__packed_reverse2(prev_i32x2, int32x2_t)
+__packed_reverse2(prev_u32x2, uint32x2_t)
+
/* Packed Averaging Addition and Subtraction (32-bit) */
__packed_binary_builtin(paadd_i8x4, int8x4_t, __builtin_riscv_paadd_i8x4)
__packed_binary_builtin(paadd_i16x2, int16x2_t, __builtin_riscv_paadd_i16x2)
@@ -468,6 +497,9 @@ __packed_reduction(predsumu_u32x2_u64, uint64_t, uint32x2_t, __builtin_riscv_pre
#undef __packed_pabs
#undef __packed_binary_builtin_cast
#undef __packed_reduction
+#undef __packed_reverse2
+#undef __packed_reverse4
+#undef __packed_reverse8
#undef __DEFAULT_FN_ATTRS
#if defined(__cplusplus)
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 290f61787ceff..dcb68157d9e6f 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -6143,3 +6143,191 @@ int64_t test_predsum_i32x2_i64(int32x2_t rs1, int64_t rs2) {
uint64_t test_predsumu_u32x2_u64(uint32x2_t rs1, uint64_t rs2) {
return __riscv_predsumu_u32x2_u64(rs1, rs2);
}
+
+// RV32-LABEL: define dso_local i32 @test_prev_i8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_prev_i8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+int8x4_t test_prev_i8x4(int8x4_t rs1) {
+ return __riscv_prev_i8x4(rs1);
+}
+
+// RV32-LABEL: define dso_local i32 @test_prev_u8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
+// RV32-NEXT: ret i32 [[TMP0]]
+//
+// RV64-LABEL: define dso_local i32 @test_prev_u8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
+// RV64-NEXT: ret i32 [[TMP0]]
+//
+uint8x4_t test_prev_u8x4(uint8x4_t rs1) {
+ return __riscv_prev_u8x4(rs1);
+}
+
+// RV32-LABEL: define dso_local i32 @test_prev_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i32 @test_prev_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+int16x2_t test_prev_i16x2(int16x2_t rs1) {
+ return __riscv_prev_i16x2(rs1);
+}
+
+// RV32-LABEL: define dso_local i32 @test_prev_u16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i32 @test_prev_u16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+uint16x2_t test_prev_u16x2(uint16x2_t rs1) {
+ return __riscv_prev_u16x2(rs1);
+}
+
+// RV32-LABEL: define dso_local i64 @test_prev_i8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_prev_i8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[RS1_COERCE]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+int8x8_t test_prev_i8x8(int8x8_t rs1) {
+ return __riscv_prev_i8x8(rs1);
+}
+
+// RV32-LABEL: define dso_local i64 @test_prev_u8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_prev_u8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[RS1_COERCE]])
+// RV64-NEXT: ret i64 [[TMP0]]
+//
+uint8x8_t test_prev_u8x8(uint8x8_t rs1) {
+ return __riscv_prev_u8x8(rs1);
+}
+
+// RV32-LABEL: define dso_local i64 @test_prev_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_prev_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP1]]
+//
+int16x4_t test_prev_i16x4(int16x4_t rs1) {
+ return __riscv_prev_i16x4(rs1);
+}
+
+// RV32-LABEL: define dso_local i64 @test_prev_u16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_prev_u16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP1]]
+//
+uint16x4_t test_prev_u16x4(uint16x4_t rs1) {
+ return __riscv_prev_u16x4(rs1);
+}
+
+// RV32-LABEL: define dso_local i64 @test_prev_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_prev_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP1]]
+//
+int32x2_t test_prev_i32x2(int32x2_t rs1) {
+ return __riscv_prev_i32x2(rs1);
+}
+
+// RV32-LABEL: define dso_local i64 @test_prev_u32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_prev_u32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP1]]
+//
+uint32x2_t test_prev_u32x2(uint32x2_t rs1) {
+ return __riscv_prev_u32x2(rs1);
+}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ea5844dea1dc4..578fe896caeb0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -584,6 +584,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SSUBSAT, VTs, Legal);
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal);
setOperationAction(ISD::BITREVERSE, VTs, Legal);
+ setOperationAction(ISD::VECTOR_SHUFFLE, VTs, Custom);
+ setOperationAction(ISD::VECTOR_REVERSE, VTs, Legal);
for (MVT VT : VTs) {
if (VT != MVT::v2i32)
setOperationAction({ISD::ABS, ISD::ABDS, ISD::ABDU}, VT, Legal);
@@ -647,6 +649,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SSHLSAT, {MVT::v2i32, MVT::v4i16}, Custom);
setOperationAction(ISD::BSWAP, MVT::v4i16, Legal);
setOperationAction(ISD::BITREVERSE, {MVT::v4i16, MVT::v8i8}, Legal);
+ setOperationAction(ISD::VECTOR_SHUFFLE, P64VecVTs, Custom);
+ setOperationAction(ISD::VECTOR_REVERSE, P64VecVTs, Legal);
setOperationAction(ISD::SPLAT_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::BUILD_VECTOR, P64VecVTs, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
@@ -6320,6 +6324,33 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
unsigned NumElts = VT.getVectorNumElements();
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
+ // Select an element reverse shuffle to VECTOR_REVERSE (rev8/rev16/ppairoe.*).
+ if (Subtarget.hasStdExtP() && !Subtarget.hasVInstructions()) {
+ // Reverse of the low L lanes, higher lanes poison. L == NumElts is a plain
+ // reverse; L == NumElts/2 is a widened RV64 v4i8/v2i16 reverse.
+ ArrayRef<int> Mask = SVN->getMask();
+ auto IsLowReverse = [&](unsigned L) {
+ return V2.isUndef() &&
+ ShuffleVectorInst::isReverseMask(Mask.take_front(L), L) &&
+ all_of(Mask.drop_front(L), [](int M) { return M < 0; });
+ };
+ if (IsLowReverse(NumElts))
+ return DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V1);
+ // Widened: reversing sends the low-half lanes to the top half, so shift
+ // them back down by half the register. Only the 64-bit packed types are
+ // legal here, so the register is XLen (i64).
+ if (Subtarget.is64Bit() && VT.getSizeInBits() == 64 &&
+ IsLowReverse(NumElts / 2)) {
+ SDValue Rev = DAG.getBitcast(
+ MVT::i64, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V1));
+ SDValue Srl =
+ DAG.getNode(ISD::SRL, DL, MVT::i64, Rev,
+ DAG.getConstant(VT.getSizeInBits() / 2, DL, MVT::i64));
+ return DAG.getBitcast(VT, Srl);
+ }
+ return SDValue();
+ }
+
if (VT.getVectorElementType() == MVT::i1) {
// Lower to a vror.vi of a larger element type if possible before we promote
// i1s to i8s.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 9114dfbf50a55..4492cb2186e90 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2223,6 +2223,11 @@ let append Predicates = [IsRV32] in {
def : Pat<(v2i16 (bitreverse GPR:$rs)),
(PPAIROE_H (REV_RV32 GPR:$rs), (REV_RV32 GPR:$rs))>;
+ // Element reverse (prev): reverse the byte/halfword order of the register.
+ def : Pat<(v4i8 (vector_reverse (v4i8 GPR:$rs))), (REV8_RV32 GPR:$rs)>;
+ def : Pat<(v2i16 (vector_reverse (v2i16 GPR:$rs))),
+ (PPAIROE_H GPR:$rs, GPR:$rs)>;
+
// Load/Store patterns
def : StPat<store, SW, GPR, v4i8>;
def : StPat<store, SW, GPR, v2i16>;
@@ -2453,6 +2458,19 @@ let append Predicates = [IsRV32] in {
(BuildGPRPair (REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)),
(REV_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd))))>;
+ // Element reverse (prev): swap the two halves and reverse within each.
+ def : Pat<(v8i8 (vector_reverse (v8i8 GPRPair:$rs))),
+ (BuildGPRPair (REV8_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
+ (REV8_RV32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
+ def : Pat<(v4i16 (vector_reverse (v4i16 GPRPair:$rs))),
+ (BuildGPRPair (PPAIROE_H (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd),
+ (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
+ (PPAIROE_H (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even),
+ (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
+ def : Pat<(v2i32 (vector_reverse (v2i32 GPRPair:$rs))),
+ (BuildGPRPair (i32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_odd)),
+ (i32 (EXTRACT_SUBREG GPRPair:$rs, sub_gpr_even)))>;
+
// splat pattern
def : Pat<(v8i8 (splat_vector (XLenVT GPR:$rs2))),
(PADD_DBS (v8i8 X0_Pair), GPR:$rs2)>;
@@ -2671,6 +2689,12 @@ let append Predicates = [IsRV64] in {
def : Pat<(v2i32 (bitreverse GPR:$rs)),
(PPAIROE_W (REV_RV64 GPR:$rs), (REV_RV64 GPR:$rs))>;
+ // Element reverse (prev): reverse the byte/halfword/word order of the register.
+ def : Pat<(v8i8 (vector_reverse (v8i8 GPR:$rs))), (REV8_RV64 GPR:$rs)>;
+ def : Pat<(v4i16 (vector_reverse (v4i16 GPR:$rs))), (REV16_RV64 GPR:$rs)>;
+ def : Pat<(v2i32 (vector_reverse (v2i32 GPR:$rs))),
+ (PPAIROE_W GPR:$rs, GPR:$rs)>;
+
// Load/Store patterns
def : StPat<store, SD, GPR, v8i8>;
def : StPat<store, SD, GPR, v4i16>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-reverse.ll b/llvm/test/CodeGen/RISCV/rvp-reverse.ll
new file mode 100644
index 0000000000000..7490e8f3ab833
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvp-reverse.ll
@@ -0,0 +1,87 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb \
+; RUN: -verify-machineinstrs < %s | \
+; RUN: FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
+; RUN: -verify-machineinstrs < %s | \
+; RUN: FileCheck %s --check-prefixes=CHECK,RV64
+
+define <4 x i8> @test_prev_v4i8(<4 x i8> %a) {
+; RV32-LABEL: test_prev_v4i8:
+; RV32: # %bb.0:
+; RV32-NEXT: rev8 a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_prev_v4i8:
+; RV64: # %bb.0:
+; RV64-NEXT: rev8 a0, a0
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
+ %r = shufflevector <4 x i8> %a, <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i8> %r
+}
+
+define <2 x i16> @test_prev_v2i16(<2 x i16> %a) {
+; RV32-LABEL: test_prev_v2i16:
+; RV32: # %bb.0:
+; RV32-NEXT: ppairoe.h a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_prev_v2i16:
+; RV64: # %bb.0:
+; RV64-NEXT: rev16 a0, a0
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
+ %r = shufflevector <2 x i16> %a, <2 x i16> poison, <2 x i32> <i32 1, i32 0>
+ ret <2 x i16> %r
+}
+
+define <8 x i8> @test_prev_v8i8(<8 x i8> %a) {
+; RV32-LABEL: test_prev_v8i8:
+; RV32: # %bb.0:
+; RV32-NEXT: rev8 a2, a0
+; RV32-NEXT: rev8 a0, a1
+; RV32-NEXT: mv a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_prev_v8i8:
+; RV64: # %bb.0:
+; RV64-NEXT: rev8 a0, a0
+; RV64-NEXT: ret
+ %r = shufflevector <8 x i8> %a, <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i8> %r
+}
+
+define <4 x i16> @test_prev_v4i16(<4 x i16> %a) {
+; RV32-LABEL: test_prev_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: ppairoe.h a2, a0, a0
+; RV32-NEXT: ppairoe.h a0, a1, a1
+; RV32-NEXT: mv a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_prev_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: rev16 a0, a0
+; RV64-NEXT: ret
+ %r = shufflevector <4 x i16> %a, <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i16> %r
+}
+
+define <2 x i32> @test_prev_v2i32(<2 x i32> %a) {
+; RV32-LABEL: test_prev_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mv a2, a0
+; RV32-NEXT: mv a0, a1
+; RV32-NEXT: mv a1, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_prev_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: ppairoe.w a0, a0, a0
+; RV64-NEXT: ret
+ %r = shufflevector <2 x i32> %a, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
+ ret <2 x i32> %r
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
``````````
</details>
https://github.com/llvm/llvm-project/pull/207575
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