[llvm] [SPARC] Don't combine misaligned memory ops with BSWAP (PR #206345)

[Sergei Barannikov via llvm-commits]

================
@@ -3264,11 +3264,18 @@ SDValue SparcTargetLowering::PerformBSWAPCombine(SDNode *N,
   SelectionDAG &DAG = DCI.DAG;
   SDValue Op = N->getOperand(0);
   EVT VT = N->getValueType(0);
-  bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
+  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
+  LoadSDNode *LN = dyn_cast<LoadSDNode>(Op.getNode());
 
-  // Turn BSWAP (LOAD) -> ld*a #ASI_P(_L) on V9.
-  if (Subtarget->isV9() && ISD::isNormalLoad(Op.getNode()) &&
-      Op.getNode()->hasOneUse() &&
+  bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
+  bool IsAlignedLoad =
+      LN && ISD::isNormalLoad(Op.getNode()) &&
+      (VT.isZeroSized() ||
+       LN->getAlign() >= DAG.getDataLayout().getABITypeAlign(Ty)) &&
+      (LN->getAlign() >= VT.getScalarStoreSize());
----------------
s-barannikov wrote:

```suggestion
  bool IsAlignedLoad =
      LN && ISD::isNormalLoad(Op.getNode()) &&
      LN->getAlign() >= VT.getScalarStoreSize();
```
isZeroSized check is redundant here since VT should be one of i16/i32/i64 (checked below).
The two alignment checks are doing the same thing, with the second one being more precise (I guess).


https://github.com/llvm/llvm-project/pull/206345