[llvm] [PowerPC] Generalize combineADDToADDZE to support i32 operands (PR #207553)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/PowerPC/PPCISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 949e3de8a..142fb462a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -20068,7 +20068,7 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
 
   if (Z.getValueType() != NativeVT)
     Z = DAG.getNode(ISD::SIGN_EXTEND, DL, NativeVT, Z);
-  
+
   SDValue ExtLHS = LHS;
   if (ExtLHS.getValueType() != NativeVT)
     ExtLHS = DAG.getNode(ISD::SIGN_EXTEND, DL, NativeVT, ExtLHS);
@@ -20087,13 +20087,14 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
     //                            \    when -32768 <= -C <= 32767 && C != 0
     //                             --> addze X, (addic (addi Z, -C), -1).carry
     SDValue Add = DAG.getNode(ISD::ADD, DL, NativeVT, Z,
-                              DAG.getConstant(NativeVT == MVT::i32 ? (uint32_t)NegConstant : (uint64_t)NegConstant,
+                              DAG.getConstant(NativeVT == MVT::i32
+                                                  ? (uint32_t)NegConstant
+                                                  : (uint64_t)NegConstant,
                                               DL, NativeVT));
     SDValue AddOrZ = NegConstant != 0 ? Add : Z;
-    SDValue Addc =
-        DAG.getNode(ISD::UADDO_CARRY, DL, VTs,
-                    AddOrZ, DAG.getAllOnesConstant(DL, NativeVT),
-                    DAG.getConstant(0, DL, CarryType));
+    SDValue Addc = DAG.getNode(ISD::UADDO_CARRY, DL, VTs, AddOrZ,
+                               DAG.getAllOnesConstant(DL, NativeVT),
+                               DAG.getConstant(0, DL, CarryType));
     Result = DAG.getNode(ISD::UADDO_CARRY, DL, VTs, ExtLHS,
                          DAG.getConstant(0, DL, NativeVT),
                          SDValue(Addc.getNode(), 1));
@@ -20107,13 +20108,14 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
     //                            \    when -32768 <= -C <= 32767 && C != 0
     //                             --> addze X, (subfic (addi Z, -C), 0).carry
     SDValue Add = DAG.getNode(ISD::ADD, DL, NativeVT, Z,
-                              DAG.getConstant(NativeVT == MVT::i32 ? (uint32_t)NegConstant : (uint64_t)NegConstant,
+                              DAG.getConstant(NativeVT == MVT::i32
+                                                  ? (uint32_t)NegConstant
+                                                  : (uint64_t)NegConstant,
                                               DL, NativeVT));
     SDValue AddOrZ = NegConstant != 0 ? Add : Z;
     SDValue Subc =
-        DAG.getNode(ISD::USUBO_CARRY, DL, VTs,
-                    DAG.getConstant(0, DL, NativeVT), AddOrZ,
-                    DAG.getConstant(0, DL, CarryType));
+        DAG.getNode(ISD::USUBO_CARRY, DL, VTs, DAG.getConstant(0, DL, NativeVT),
+                    AddOrZ, DAG.getConstant(0, DL, CarryType));
     SDValue Invert = DAG.getNode(ISD::XOR, DL, CarryType, Subc.getValue(1),
                                  DAG.getConstant(1UL, DL, CarryType));
     Result = DAG.getNode(ISD::UADDO_CARRY, DL, VTs, ExtLHS,

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https://github.com/llvm/llvm-project/pull/207553