[llvm] [PowerPC] Lower UCMP and SCMP directly to setb instead of matching the DAG shape (PR #206282)
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llvm-commits at lists.llvm.org
Sat Jul 4 11:48:07 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/206282
>From 8974e3f6c5bba0ef1ad92131999f5b133ba4d603 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 27 Jun 2026 15:43:47 -0400
Subject: [PATCH 1/2] [PowerPC] Lower UCMP and SCMP directly to setb instead of
matching the DAG shape
The old code had no scmp or ucmp so we had no choice but to match the shapes and then output setb clumsily. Now, however, opt will turn the tested llvm-ir to scmp intrinsics anyway, and while scmp does decompose into the shapes needed for cmpld on Power9, we can do this directly.
---
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 76 +-
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 +-
llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll | 1258 -------------------
llvm/test/CodeGen/PowerPC/scmp.ll | 62 +-
llvm/test/CodeGen/PowerPC/ucmp.ll | 76 +-
5 files changed, 180 insertions(+), 1307 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 016c547821f7a..b8ae3d69563a8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -85,8 +85,6 @@ STATISTIC(NumLogicOpsOnComparison,
"Number of logical ops on i1 values calculated in GPR.");
STATISTIC(OmittedForNonExtendUses,
"Number of compares not eliminated as they have non-extending uses.");
-STATISTIC(NumP9Setb,
- "Number of compares lowered to setb.");
// FIXME: Remove this once the bug has been fixed!
cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
@@ -4693,14 +4691,15 @@ void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
CurDAG->setNodeMemRefs(cast<MachineSDNode>(Result), {MemOp});
}
-
-static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
- bool &NeedSwapOps, bool &IsUnCmp) {
-
+static bool mayUseP9SetbForFloat(SDNode *N, const ISD::CondCode &CC,
+ bool &NeedSwapOps) {
assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here.");
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
+ if (!LHS.getValueType().isFloatingPoint())
+ return false;
+
SDValue TrueRes = N->getOperand(2);
SDValue FalseRes = N->getOperand(3);
ConstantSDNode *TrueConst = dyn_cast<ConstantSDNode>(TrueRes);
@@ -4762,12 +4761,6 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
return false;
}
- // Canonicalize unsigned case
- if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) {
- IsUnCmp = true;
- InnerCC = (InnerCC == ISD::SETULT) ? ISD::SETLT : ISD::SETGT;
- }
-
bool InnerSwapped = false;
if (LHS == InnerRHS && RHS == InnerLHS)
InnerSwapped = true;
@@ -4785,17 +4778,12 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
NeedSwapOps = (InnerCC == ISD::SETGT) ? InnerSwapped : !InnerSwapped;
break;
- // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setu?lt)
- // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setu?lt)
- // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setu?lt)
- // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setu?lt)
- // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setu?lt)
- // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setu?lt)
- case ISD::SETULT:
- if (!IsUnCmp && InnerCC != ISD::SETNE)
- return false;
- IsUnCmp = true;
- [[fallthrough]];
+ // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setlt)
+ // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt)
+ // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt)
+ // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setlt)
+ // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt)
+ // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt)
case ISD::SETLT:
if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETGT && !InnerSwapped) ||
(InnerCC == ISD::SETLT && InnerSwapped))
@@ -4804,17 +4792,12 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
return false;
break;
- // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setu?gt)
- // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setu?gt)
- // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setu?gt)
- // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setu?gt)
- // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setu?gt)
- // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setu?gt)
- case ISD::SETUGT:
- if (!IsUnCmp && InnerCC != ISD::SETNE)
- return false;
- IsUnCmp = true;
- [[fallthrough]];
+ // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setgt)
+ // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt)
+ // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt)
+ // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setgt)
+ // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt)
+ // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt)
case ISD::SETGT:
if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETLT && !InnerSwapped) ||
(InnerCC == ISD::SETGT && InnerSwapped))
@@ -4827,9 +4810,6 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
return false;
}
- LLVM_DEBUG(dbgs() << "Found a node that can be lowered to a SETB: ");
- LLVM_DEBUG(N->dump());
-
return true;
}
@@ -5276,6 +5256,17 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
switch (N->getOpcode()) {
default: break;
+ case ISD::UCMP:
+ case ISD::SCMP: {
+ bool IsUnsigned = N->getOpcode() == ISD::UCMP;
+ ISD::CondCode CC = IsUnsigned ? ISD::SETUGT : ISD::SETGT;
+ SDValue CRVal = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
+ unsigned SetBOpc =
+ N->getSimpleValueType(0) == MVT::i64 ? PPC::SETB8 : PPC::SETB;
+ CurDAG->SelectNodeTo(N, SetBOpc, N->getValueType(0), CRVal);
+ return;
+ }
+
case ISD::Constant:
if (N->getValueType(0) == MVT::i64) {
ReplaceNode(N, selectI64Imm(CurDAG, N));
@@ -5866,10 +5857,9 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
if (Subtarget->useCRBits() && N->getOperand(0).getValueType() == MVT::i1)
break;
- if (Subtarget->isISA3_0() && Subtarget->isPPC64()) {
+ if (Subtarget->isISA3_0()) {
bool NeedSwapOps = false;
- bool IsUnCmp = false;
- if (mayUseP9Setb(N, CC, CurDAG, NeedSwapOps, IsUnCmp)) {
+ if (mayUseP9SetbForFloat(N, CC, NeedSwapOps)) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
if (NeedSwapOps)
@@ -5880,13 +5870,11 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
// doesn't need to materialize the whole literal and just use xoris to
// check it first, it leads the following comparison result can't
// exactly represent GT/LT relationship. So to avoid this we specify
- // SETGT/SETUGT here instead of SETEQ.
- SDValue GenCC =
- SelectCC(LHS, RHS, IsUnCmp ? ISD::SETUGT : ISD::SETGT, dl);
+ // SETGT here instead of SETEQ.
+ SDValue GenCC = SelectCC(LHS, RHS, ISD::SETGT, dl);
CurDAG->SelectNodeTo(
N, N->getSimpleValueType(0) == MVT::i64 ? PPC::SETB8 : PPC::SETB,
N->getValueType(0), GenCC);
- NumP9Setb++;
return;
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 9a4943aad6289..bdbb5aeaf2802 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -603,9 +603,18 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- // Custom handling for PowerPC ucmp instruction
- setOperationAction(ISD::UCMP, MVT::i32, Custom);
- setOperationAction(ISD::UCMP, MVT::i64, isPPC64 ? Custom : Expand);
+ if (Subtarget.isISA3_0()) {
+ // Power9 SETB produces -1/0/1 directly from a compare.
+ setOperationAction(ISD::UCMP, MVT::i32, Legal);
+ setOperationAction(ISD::UCMP, MVT::i64, isPPC64 ? Legal : Expand);
+ setOperationAction(ISD::SCMP, MVT::i32, Legal);
+ setOperationAction(ISD::SCMP, MVT::i64, isPPC64 ? Legal : Expand);
+ } else {
+ // Custom handling for PowerPC ucmp instruction
+ setOperationAction(ISD::UCMP, MVT::i32, Custom);
+ setOperationAction(ISD::UCMP, MVT::i64, isPPC64 ? Custom : Expand);
+ }
+
setOperationAction(ISD::ABDU, MVT::i32, Custom);
setOperationAction(ISD::ABDU, MVT::i64, isPPC64 ? Custom : Expand);
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
index a2a5c6c5eafb7..c2d01e9fb6fbe 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
@@ -8,1135 +8,6 @@
; Test different patterns with type i64
; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
-define i64 @setb1(i64 %a, i64 %b) {
-; CHECK-LABEL: setb1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb1:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %a, %b
- %t2 = icmp ne i64 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
-define i64 @setb2(i64 %a, i64 %b) {
-; CHECK-LABEL: setb2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb2:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %b, %a
- %t2 = icmp ne i64 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
-define i64 @setb3(i64 %a, i64 %b) {
-; CHECK-LABEL: setb3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb3:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %a, %b
- %t2 = icmp ne i64 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
-define i64 @setb4(i64 %a, i64 %b) {
-; CHECK-LABEL: setb4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb4:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %b, %a
- %t2 = icmp ne i64 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
-define i64 @setb5(i64 %a, i64 %b) {
-; CHECK-LABEL: setb5:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb5:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r4, 63
-; CHECK-PWR8-NEXT: rldicl r6, r3, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r4, r3
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %a, %b
- %t2 = icmp sgt i64 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
-define i64 @setb6(i64 %a, i64 %b) {
-; CHECK-LABEL: setb6:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb6:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r4, 63
-; CHECK-PWR8-NEXT: rldicl r6, r3, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r4, r3
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %b, %a
- %t2 = icmp sgt i64 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
-define i64 @setb7(i64 %a, i64 %b) {
-; CHECK-LABEL: setb7:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb7:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r4, 63
-; CHECK-PWR8-NEXT: rldicl r6, r3, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r4, r3
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %a, %b
- %t2 = icmp slt i64 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
-define i64 @setb8(i64 %a, i64 %b) {
-; CHECK-LABEL: setb8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb8:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r4, 63
-; CHECK-PWR8-NEXT: rldicl r6, r3, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r4, r3
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %b, %a
- %t2 = icmp slt i64 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt
-define i64 @setb9(i64 %a, i64 %b) {
-; CHECK-LABEL: setb9:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb9:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: subfic r5, r5, 0
-; CHECK-PWR8-NEXT: subfe r5, r5, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %a, %b
- %t2 = icmp ne i64 %a, %b
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setlt
-define i64 @setb10(i64 %a, i64 %b) {
-; CHECK-LABEL: setb10:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb10:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: subfic r5, r5, 0
-; CHECK-PWR8-NEXT: subfe r5, r5, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %b, %a
- %t2 = icmp ne i64 %a, %b
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setgt
-define i64 @setb11(i64 %a, i64 %b) {
-; CHECK-LABEL: setb11:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb11:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: subfic r5, r5, 0
-; CHECK-PWR8-NEXT: subfe r5, r5, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %a, %b
- %t2 = icmp ne i64 %b, %a
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setlt
-define i64 @setb12(i64 %a, i64 %b) {
-; CHECK-LABEL: setb12:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb12:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: subfic r5, r5, 0
-; CHECK-PWR8-NEXT: subfe r5, r5, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %b, %a
- %t2 = icmp ne i64 %b, %a
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt
-define i64 @setb13(i64 %a, i64 %b) {
-; CHECK-LABEL: setb13:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb13:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r3, 63
-; CHECK-PWR8-NEXT: rldicl r6, r4, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r3, r4
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %a, %b
- %t2 = icmp slt i64 %a, %b
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt
-define i64 @setb14(i64 %a, i64 %b) {
-; CHECK-LABEL: setb14:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb14:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r3, 63
-; CHECK-PWR8-NEXT: rldicl r6, r4, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r3, r4
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %b, %a
- %t2 = icmp slt i64 %a, %b
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt
-define i64 @setb15(i64 %a, i64 %b) {
-; CHECK-LABEL: setb15:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb15:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r3, 63
-; CHECK-PWR8-NEXT: rldicl r6, r4, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r3, r4
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %a, %b
- %t2 = icmp sgt i64 %b, %a
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
-define i64 @setb16(i64 %a, i64 %b) {
-; CHECK-LABEL: setb16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb16:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r3, 63
-; CHECK-PWR8-NEXT: rldicl r6, r4, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r3, r4
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %b, %a
- %t2 = icmp sgt i64 %b, %a
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setgt), seteq
-define i64 @setb17(i64 %a, i64 %b) {
-; CHECK-LABEL: setb17:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb17:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: li r6, 1
-; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %a, %b
- %t2 = icmp sgt i64 %a, %b
- %t3 = select i1 %t2, i64 1, i64 -1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setgt), seteq
-define i64 @setb18(i64 %a, i64 %b) {
-; CHECK-LABEL: setb18:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb18:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: li r6, 1
-; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %b, %a
- %t2 = icmp sgt i64 %a, %b
- %t3 = select i1 %t2, i64 1, i64 -1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setlt), seteq
-define i64 @setb19(i64 %a, i64 %b) {
-; CHECK-LABEL: setb19:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb19:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: li r6, 1
-; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %a, %b
- %t2 = icmp slt i64 %b, %a
- %t3 = select i1 %t2, i64 1, i64 -1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setlt), seteq
-define i64 @setb20(i64 %a, i64 %b) {
-; CHECK-LABEL: setb20:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb20:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: li r6, 1
-; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %b, %a
- %t2 = icmp slt i64 %b, %a
- %t3 = select i1 %t2, i64 1, i64 -1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setlt), seteq
-define i64 @setb21(i64 %a, i64 %b) {
-; CHECK-LABEL: setb21:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb21:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r5, 1
-; CHECK-PWR8-NEXT: li r6, -1
-; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %a, %b
- %t2 = icmp slt i64 %a, %b
- %t3 = select i1 %t2, i64 -1, i64 1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setlt), seteq
-define i64 @setb22(i64 %a, i64 %b) {
-; CHECK-LABEL: setb22:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb22:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r5, 1
-; CHECK-PWR8-NEXT: li r6, -1
-; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %b, %a
- %t2 = icmp slt i64 %a, %b
- %t3 = select i1 %t2, i64 -1, i64 1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
-define i64 @setb23(i64 %a, i64 %b) {
-; CHECK-LABEL: setb23:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb23:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r5, 1
-; CHECK-PWR8-NEXT: li r6, -1
-; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %a, %b
- %t2 = icmp sgt i64 %b, %a
- %t3 = select i1 %t2, i64 -1, i64 1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
-define i64 @setb24(i64 %a, i64 %b) {
-; CHECK-LABEL: setb24:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb24:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r5, 1
-; CHECK-PWR8-NEXT: li r6, -1
-; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %b, %a
- %t2 = icmp sgt i64 %b, %a
- %t3 = select i1 %t2, i64 -1, i64 1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-; end all patterns testing for i64
-
-; Test with swapping the input parameters
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
-define i64 @setb25(i64 %a, i64 %b) {
-; CHECK-LABEL: setb25:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r4, r3
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb25:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %b, %a
- %t2 = icmp ne i64 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
-define i64 @setb26(i64 %a, i64 %b) {
-; CHECK-LABEL: setb26:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r4, r3
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb26:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %a, %b
- %t2 = icmp ne i64 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; Test with different scalar integer type for selected value
-; i32/i16/i8 rather than i64 above
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
-define i64 @setb27(i64 %a, i64 %b) {
-; CHECK-LABEL: setb27:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb27:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: extsw r3, r3
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %a, %b
- %t2 = icmp ne i64 %b, %a
- %t3 = zext i1 %t2 to i32
- %t4 = select i1 %t1, i32 -1, i32 %t3
- %t5 = sext i32 %t4 to i64
- ret i64 %t5
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
-define i64 @setb28(i64 %a, i64 %b) {
-; CHECK-LABEL: setb28:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb28:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpd r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: addic r6, r5, -1
-; CHECK-PWR8-NEXT: subfe r5, r6, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: extsw r3, r3
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i64 %b, %a
- %t2 = icmp ne i64 %b, %a
- %t3 = zext i1 %t2 to i16
- %t4 = select i1 %t1, i16 -1, i16 %t3
- %t5 = sext i16 %t4 to i64
- ret i64 %t5
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
-define i64 @setb29(i64 %a, i64 %b) {
-; CHECK-LABEL: setb29:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: clrldi r3, r3, 56
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setb29:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: sradi r5, r4, 63
-; CHECK-PWR8-NEXT: rldicl r6, r3, 1, 63
-; CHECK-PWR8-NEXT: subc r7, r4, r3
-; CHECK-PWR8-NEXT: adde r5, r6, r5
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: clrldi r3, r3, 56
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %a, %b
- %t2 = icmp sgt i64 %a, %b
- %t3 = zext i1 %t2 to i8
- %t4 = select i1 %t1, i8 -1, i8 %t3
- %t5 = zext i8 %t4 to i64
- ret i64 %t5
-}
-
-; Testings to cover different comparison opcodes
-; Test with integer type i32/i16/i8 for input parameter
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
-define i64 @setbsw1(i32 %a, i32 %b) {
-; CHECK-LABEL: setbsw1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsw1:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpw r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: cntlzw r5, r5
-; CHECK-PWR8-NEXT: srwi r5, r5, 5
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i32 %a, %b
- %t2 = icmp ne i32 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
-define i64 @setbsw2(i32 %a, i32 %b) {
-; CHECK-LABEL: setbsw2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsw2:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpw r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: cntlzw r5, r5
-; CHECK-PWR8-NEXT: srwi r5, r5, 5
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i32 %b, %a
- %t2 = icmp ne i32 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
-define i64 @setbsw3(i32 %a, i32 %b) {
-; CHECK-LABEL: setbsw3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsw3:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpw r4, r3
-; CHECK-PWR8-NEXT: li r5, 1
-; CHECK-PWR8-NEXT: li r6, -1
-; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmplw r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i32 %a, %b
- %t2 = icmp sgt i32 %b, %a
- %t3 = select i1 %t2, i64 -1, i64 1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
-define i64 @setbsh1(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: setbsh1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsh1:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpw r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: cntlzw r5, r5
-; CHECK-PWR8-NEXT: srwi r5, r5, 5
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i16 %a, %b
- %t2 = icmp ne i16 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
-define i64 @setbsh2(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: setbsh2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsh2:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmpw r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: cntlzw r5, r5
-; CHECK-PWR8-NEXT: srwi r5, r5, 5
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i16 %b, %a
- %t2 = icmp ne i16 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
-define i64 @setbsc1(i8 %a, i8 %b) {
-; CHECK-LABEL: setbsc1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: extsb r4, r4
-; CHECK-NEXT: extsb r3, r3
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsc1:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: extsb r4, r4
-; CHECK-PWR8-NEXT: extsb r3, r3
-; CHECK-PWR8-NEXT: sub r5, r4, r3
-; CHECK-PWR8-NEXT: cmpw r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: rldicl r5, r5, 1, 63
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i8 %a, %b
- %t2 = icmp sgt i8 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
-define i64 @setbsc2(i8 %a, i8 %b) {
-; CHECK-LABEL: setbsc2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: extsb r4, r4
-; CHECK-NEXT: extsb r3, r3
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsc2:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: extsb r4, r4
-; CHECK-PWR8-NEXT: extsb r3, r3
-; CHECK-PWR8-NEXT: sub r5, r4, r3
-; CHECK-PWR8-NEXT: cmpw r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: rldicl r5, r5, 1, 63
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp sgt i8 %b, %a
- %t2 = icmp sgt i8 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
-define i64 @setbsc3(i4 %a, i4 %b) {
-; CHECK-LABEL: setbsc3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: slwi r4, r4, 28
-; CHECK-NEXT: slwi r3, r3, 28
-; CHECK-NEXT: srawi r4, r4, 28
-; CHECK-NEXT: srawi r3, r3, 28
-; CHECK-NEXT: cmpw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbsc3:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: slwi r4, r4, 28
-; CHECK-PWR8-NEXT: slwi r3, r3, 28
-; CHECK-PWR8-NEXT: srawi r4, r4, 28
-; CHECK-PWR8-NEXT: srawi r3, r3, 28
-; CHECK-PWR8-NEXT: cmpw r3, r4
-; CHECK-PWR8-NEXT: sub r5, r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: rldicl r5, r5, 1, 63
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i4 %a, %b
- %t2 = icmp slt i4 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; Test with unsigned integer type i64/i32/i16/i8 for input parameter
-
-; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setult)), setugt
-define i64 @setbud1(i64 %a, i64 %b) {
-; CHECK-LABEL: setbud1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpld r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbud1:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: subc r5, r4, r3
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: subfe r5, r4, r4
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp ugt i64 %b, %a
- %t2 = icmp ult i64 %b, %a
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setugt
-define i64 @setbud2(i64 %a, i64 %b) {
-; CHECK-LABEL: setbud2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpld r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbud2:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: subfic r5, r5, 0
-; CHECK-PWR8-NEXT: subfe r5, r5, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp ugt i64 %a, %b
- %t2 = icmp ne i64 %a, %b
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setugt), seteq
-define i64 @setbud3(i64 %a, i64 %b) {
-; CHECK-LABEL: setbud3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmpld r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbud3:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: li r4, -1
-; CHECK-PWR8-NEXT: iselgt r3, r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r3
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp eq i64 %b, %a
- %t2 = icmp ugt i64 %b, %a
- %t3 = select i1 %t2, i64 -1, i64 1
- %t4 = select i1 %t1, i64 0, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setult
-define i64 @setbuw1(i32 %a, i32 %b) {
-; CHECK-LABEL: setbuw1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbuw1:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmplw r4, r3
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: cntlzw r5, r5
-; CHECK-PWR8-NEXT: srwi r5, r5, 5
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp ult i32 %b, %a
- %t2 = icmp ne i32 %a, %b
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setugt
-define i64 @setbuw2(i32 %a, i32 %b) {
-; CHECK-LABEL: setbuw2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbuw2:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmplw r3, r4
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: cntlzw r5, r5
-; CHECK-PWR8-NEXT: srwi r5, r5, 5
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp ugt i32 %a, %b
- %t2 = icmp ne i32 %b, %a
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setult
-define i64 @setbuh(i16 %a, i16 %b) {
-; CHECK-LABEL: setbuh:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi r4, r4, 16
-; CHECK-NEXT: clrlwi r3, r3, 16
-; CHECK-NEXT: cmplw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbuh:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: clrlwi r3, r3, 16
-; CHECK-PWR8-NEXT: clrlwi r4, r4, 16
-; CHECK-PWR8-NEXT: xor r5, r4, r3
-; CHECK-PWR8-NEXT: cmplw r4, r3
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: cntlzw r5, r5
-; CHECK-PWR8-NEXT: srwi r5, r5, 5
-; CHECK-PWR8-NEXT: xori r5, r5, 1
-; CHECK-PWR8-NEXT: neg r5, r5
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp ult i16 %b, %a
- %t2 = icmp ne i16 %b, %a
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setult)), setugt
-define i64 @setbuc(i8 %a, i8 %b) {
-; CHECK-LABEL: setbuc:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi r4, r4, 24
-; CHECK-NEXT: clrlwi r3, r3, 24
-; CHECK-NEXT: cmplw r3, r4
-; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbuc:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: clrlwi r3, r3, 24
-; CHECK-PWR8-NEXT: clrlwi r4, r4, 24
-; CHECK-PWR8-NEXT: clrldi r5, r3, 32
-; CHECK-PWR8-NEXT: clrldi r6, r4, 32
-; CHECK-PWR8-NEXT: cmplw r3, r4
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: sub r5, r5, r6
-; CHECK-PWR8-NEXT: sradi r5, r5, 63
-; CHECK-PWR8-NEXT: iselgt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp ugt i8 %a, %b
- %t2 = icmp ult i8 %a, %b
- %t3 = sext i1 %t2 to i64
- %t4 = select i1 %t1, i64 1, i64 %t3
- ret i64 %t4
-}
-
-; Test with float/double/float128 for input parameter
-
-; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
define i64 @setbf1(float %a, float %b) {
; CHECK-LABEL: setbf1:
; CHECK: # %bb.0:
@@ -1282,132 +153,3 @@ define i64 @setbf128(fp128 %a, fp128 %b) {
%t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4
}
-
-; Some cases we can't leverage setb
-
-define i64 @setbn1(i64 %a, i64 %b) {
-; CHECK-LABEL: setbn1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xor r5, r3, r4
-; CHECK-NEXT: cmpd r3, r4
-; CHECK-NEXT: li r3, -1
-; CHECK-NEXT: cntlzd r5, r5
-; CHECK-NEXT: rldicl r5, r5, 58, 63
-; CHECK-NEXT: isellt r3, r3, r5
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbn1:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: xor r5, r3, r4
-; CHECK-PWR8-NEXT: cmpd r3, r4
-; CHECK-PWR8-NEXT: li r3, -1
-; CHECK-PWR8-NEXT: cntlzd r5, r5
-; CHECK-PWR8-NEXT: rldicl r5, r5, 58, 63
-; CHECK-PWR8-NEXT: isellt r3, r3, r5
-; CHECK-PWR8-NEXT: blr
- %t1 = icmp slt i64 %a, %b
- %t2 = icmp eq i64 %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-define i64 @setbn2(double %a, double %b) {
-; CHECK-LABEL: setbn2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fcmpu cr0, f1, f2
-; CHECK-NEXT: li r3, 1
-; CHECK-NEXT: li r4, -1
-; CHECK-NEXT: cror 4*cr5+lt, un, eq
-; CHECK-NEXT: xscmpudp cr0, f1, f2
-; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
-; CHECK-NEXT: isellt r3, r4, r3
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbn2:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: fcmpu cr0, f1, f2
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: li r4, -1
-; CHECK-PWR8-NEXT: cror 4*cr5+lt, un, eq
-; CHECK-PWR8-NEXT: xscmpudp cr0, f1, f2
-; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt
-; CHECK-PWR8-NEXT: isellt r3, r4, r3
-; CHECK-PWR8-NEXT: blr
- %t1 = fcmp olt double %a, %b
- %t2 = fcmp one double %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-define i64 @setbn3(float %a, float %b) {
-; CHECK-LABEL: setbn3:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fcmpu cr0, f1, f2
-; CHECK-NEXT: li r3, 1
-; CHECK-NEXT: li r4, -1
-; CHECK-NEXT: iseleq r3, 0, r3
-; CHECK-NEXT: cror 4*cr5+lt, lt, un
-; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbn3:
-; CHECK-PWR8: # %bb.0:
-; CHECK-PWR8-NEXT: fcmpu cr0, f1, f2
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: li r4, -1
-; CHECK-PWR8-NEXT: iseleq r3, 0, r3
-; CHECK-PWR8-NEXT: cror 4*cr5+lt, lt, un
-; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr5+lt
-; CHECK-PWR8-NEXT: blr
- %t1 = fcmp ult float %a, %b
- %t2 = fcmp une float %a, %b
- %t3 = zext i1 %t2 to i64
- %t4 = select i1 %t1, i64 -1, i64 %t3
- ret i64 %t4
-}
-
-; Verify this case doesn't crash
-define void @setbn4(i128 %0, ptr %sel.out) {
-; CHECK-LABEL: setbn4:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li r6, 1
-; CHECK-NEXT: cmpdi cr1, r3, 0
-; CHECK-NEXT: li r3, 1
-; CHECK-NEXT: rldic r6, r6, 48, 15
-; CHECK-NEXT: cmpld r4, r6
-; CHECK-NEXT: crandc 4*cr5+lt, gt, eq
-; CHECK-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq
-; CHECK-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; CHECK-NEXT: rldicl. r4, r4, 16, 48
-; CHECK-NEXT: li r4, -1
-; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
-; CHECK-NEXT: iseleq r3, r4, r3
-; CHECK-NEXT: stw r3, 0(r5)
-; CHECK-NEXT: blr
-;
-; CHECK-PWR8-LABEL: setbn4:
-; CHECK-PWR8: # %bb.0: # %entry
-; CHECK-PWR8-NEXT: li r6, 1
-; CHECK-PWR8-NEXT: cmpdi cr1, r3, 0
-; CHECK-PWR8-NEXT: li r3, 1
-; CHECK-PWR8-NEXT: rldic r6, r6, 48, 15
-; CHECK-PWR8-NEXT: cmpld r4, r6
-; CHECK-PWR8-NEXT: crandc 4*cr5+lt, gt, eq
-; CHECK-PWR8-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq
-; CHECK-PWR8-NEXT: rldicl. r4, r4, 16, 48
-; CHECK-PWR8-NEXT: li r4, -1
-; CHECK-PWR8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt
-; CHECK-PWR8-NEXT: iseleq r3, r4, r3
-; CHECK-PWR8-NEXT: stw r3, 0(r5)
-; CHECK-PWR8-NEXT: blr
-entry:
- %c1 = icmp ult i128 %0, 5192296858534827628530496329220096
- %c2 = icmp ugt i128 %0, 5192296858534827628530496329220096
- %ext = zext i1 %c2 to i32
- %sel = select i1 %c1, i32 -1, i32 %ext
- store i32 %sel, ptr %sel.out, align 4
- ret void
-}
diff --git a/llvm/test/CodeGen/PowerPC/scmp.ll b/llvm/test/CodeGen/PowerPC/scmp.ll
index 107137c0bea7c..f42bd7903ce27 100644
--- a/llvm/test/CodeGen/PowerPC/scmp.ll
+++ b/llvm/test/CodeGen/PowerPC/scmp.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=ppc64le-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -mtriple=ppc64le-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=ppc64le-unknown-unknown -mcpu=pwr9 %s -o - | FileCheck %s --check-prefix=P9
define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-LABEL: scmp_8_8:
@@ -10,6 +11,12 @@ define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-NEXT: rldicl 5, 5, 1, 63
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_8_8:
+; P9: # %bb.0:
+; P9-NEXT: cmpw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
ret i8 %1
}
@@ -23,6 +30,12 @@ define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-NEXT: rldicl 5, 5, 1, 63
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_8_16:
+; P9: # %bb.0:
+; P9-NEXT: cmpw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
ret i8 %1
}
@@ -38,6 +51,12 @@ define i8 @scmp_8_32(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_8_32:
+; P9: # %bb.0:
+; P9-NEXT: cmpw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.scmp(i32 %x, i32 %y)
ret i8 %1
}
@@ -54,6 +73,12 @@ define i8 @scmp_8_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: xori 5, 5, 1
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_8_64:
+; P9: # %bb.0:
+; P9-NEXT: cmpd 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.scmp(i64 %x, i64 %y)
ret i8 %1
}
@@ -75,6 +100,23 @@ define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK-NEXT: cror 20, 20, 21
; CHECK-NEXT: isel 3, 4, 3, 20
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_8_128:
+; P9: # %bb.0:
+; P9-NEXT: cmpld 4, 6
+; P9-NEXT: cmpd 1, 4, 6
+; P9-NEXT: cmpld 6, 3, 5
+; P9-NEXT: li 3, 1
+; P9-NEXT: li 4, -1
+; P9-NEXT: crandc 20, 5, 2
+; P9-NEXT: crand 21, 2, 25
+; P9-NEXT: crnor 20, 21, 20
+; P9-NEXT: crand 21, 2, 24
+; P9-NEXT: isel 3, 0, 3, 20
+; P9-NEXT: crandc 20, 4, 2
+; P9-NEXT: cror 20, 21, 20
+; P9-NEXT: isel 3, 4, 3, 20
+; P9-NEXT: blr
%1 = call i8 @llvm.scmp(i128 %x, i128 %y)
ret i8 %1
}
@@ -90,6 +132,12 @@ define i32 @scmp_32_32(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_32_32:
+; P9: # %bb.0:
+; P9-NEXT: cmpw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i32 @llvm.scmp(i32 %x, i32 %y)
ret i32 %1
}
@@ -106,6 +154,12 @@ define i32 @scmp_32_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: xori 5, 5, 1
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_32_64:
+; P9: # %bb.0:
+; P9-NEXT: cmpd 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i32 @llvm.scmp(i64 %x, i64 %y)
ret i32 %1
}
@@ -122,6 +176,12 @@ define i64 @scmp_64_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: xori 5, 5, 1
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: scmp_64_64:
+; P9: # %bb.0:
+; P9-NEXT: cmpd 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
ret i64 %1
}
diff --git a/llvm/test/CodeGen/PowerPC/ucmp.ll b/llvm/test/CodeGen/PowerPC/ucmp.ll
index a299fbbba3422..750182ff9ab63 100644
--- a/llvm/test/CodeGen/PowerPC/ucmp.ll
+++ b/llvm/test/CodeGen/PowerPC/ucmp.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=ppc64le-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -mtriple=ppc64le-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=ppc64le-unknown-unknown -mcpu=pwr9 %s -o - | FileCheck %s --check-prefix=P9
define i8 @ucmp_8_8(i8 zeroext %x, i8 zeroext %y) nounwind {
; CHECK-LABEL: ucmp_8_8:
@@ -11,6 +12,12 @@ define i8 @ucmp_8_8(i8 zeroext %x, i8 zeroext %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_8_8:
+; P9: # %bb.0:
+; P9-NEXT: cmplw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
ret i8 %1
}
@@ -25,6 +32,12 @@ define i8 @ucmp_8_16(i16 zeroext %x, i16 zeroext %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_8_16:
+; P9: # %bb.0:
+; P9-NEXT: cmplw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
ret i8 %1
}
@@ -39,6 +52,12 @@ define i8 @ucmp_8_32(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_8_32:
+; P9: # %bb.0:
+; P9-NEXT: cmplw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
ret i8 %1
}
@@ -51,6 +70,12 @@ define i8 @ucmp_8_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_8_64:
+; P9: # %bb.0:
+; P9-NEXT: cmpld 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
ret i8 %1
}
@@ -71,6 +96,22 @@ define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK-NEXT: cror 20, 21, 20
; CHECK-NEXT: isel 3, 4, 3, 20
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_8_128:
+; P9: # %bb.0:
+; P9-NEXT: cmpld 4, 6
+; P9-NEXT: cmpld 1, 3, 5
+; P9-NEXT: li 3, 1
+; P9-NEXT: li 4, -1
+; P9-NEXT: crandc 20, 1, 2
+; P9-NEXT: crand 21, 2, 5
+; P9-NEXT: crnor 20, 21, 20
+; P9-NEXT: crand 21, 2, 4
+; P9-NEXT: isel 3, 0, 3, 20
+; P9-NEXT: crandc 20, 0, 2
+; P9-NEXT: cror 20, 21, 20
+; P9-NEXT: isel 3, 4, 3, 20
+; P9-NEXT: blr
%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
ret i8 %1
}
@@ -85,6 +126,12 @@ define i32 @ucmp_32_32(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_32_32:
+; P9: # %bb.0:
+; P9-NEXT: cmplw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
ret i32 %1
}
@@ -97,6 +144,12 @@ define i32 @ucmp_32_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_32_64:
+; P9: # %bb.0:
+; P9-NEXT: cmpld 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
ret i32 %1
}
@@ -109,6 +162,12 @@ define i64 @ucmp_64_64(i64 %x, i64 %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_64_64:
+; P9: # %bb.0:
+; P9-NEXT: cmpld 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
ret i64 %1
}
@@ -122,6 +181,13 @@ define i64 @ucmp_64_8_zero(i8 %x) nounwind {
; CHECK-NEXT: subfe 4, 4, 3
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_64_8_zero:
+; P9: # %bb.0:
+; P9-NEXT: clrlwi 3, 3, 24
+; P9-NEXT: cmplwi 3, 0
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i64 @llvm.ucmp(i8 %x, i8 0)
ret i64 %1
}
@@ -136,6 +202,14 @@ define i64 @ucmp_64_8(i8 %x, i8 %y) nounwind {
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: subfe 3, 3, 5
; CHECK-NEXT: blr
+;
+; P9-LABEL: ucmp_64_8:
+; P9: # %bb.0:
+; P9-NEXT: clrlwi 4, 4, 24
+; P9-NEXT: clrlwi 3, 3, 24
+; P9-NEXT: cmplw 3, 4
+; P9-NEXT: setb 3, 0
+; P9-NEXT: blr
%1 = call i64 @llvm.ucmp(i8 %x, i8 %y)
ret i64 %1
}
>From a330261a971811a9a6e408a9741d75e45399cdf3 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Wed, 1 Jul 2026 18:10:47 -0400
Subject: [PATCH 2/2] Fix blank line
---
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index b8ae3d69563a8..307f4f3d1ed74 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -4691,6 +4691,7 @@ void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
CurDAG->setNodeMemRefs(cast<MachineSDNode>(Result), {MemOp});
}
+
static bool mayUseP9SetbForFloat(SDNode *N, const ISD::CondCode &CC,
bool &NeedSwapOps) {
assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here.");
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