[llvm] [CodeGen] Expand fmaximum/fminimum reductions (PR #195169)
Prajwal KP via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 4 01:50:24 PDT 2026
https://github.com/Prajwal-kp-18 updated https://github.com/llvm/llvm-project/pull/195169
>From 1ad069078bd29e691ae2ac6ecf09e5612268bc43 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Fri, 1 May 2026 01:32:42 +0530
Subject: [PATCH 1/5] [CodeGen] Expand fmaximum/fminimum reductions
---
llvm/lib/CodeGen/ExpandReductions.cpp | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp
index 30c1a8f9fa0e5..398b4f35a30aa 100644
--- a/llvm/lib/CodeGen/ExpandReductions.cpp
+++ b/llvm/lib/CodeGen/ExpandReductions.cpp
@@ -49,6 +49,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
case Intrinsic::vector_reduce_umin:
case Intrinsic::vector_reduce_fmax:
case Intrinsic::vector_reduce_fmin:
+ case Intrinsic::vector_reduce_fmaximum:
+ case Intrinsic::vector_reduce_fminimum:
if (TTI->shouldExpandReduction(II))
Worklist.push_back(II);
@@ -157,6 +159,19 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
break;
}
+ case Intrinsic::vector_reduce_fmaximum:
+ case Intrinsic::vector_reduce_fminimum: {
+ // We require "nnan" to use a shuffle reduction; "nsz" is implied by the
+ // semantics of the reduction.
+ Value *Vec = II->getArgOperand(0);
+ if (!isPowerOf2_32(
+ cast<FixedVectorType>(Vec->getType())->getNumElements()) ||
+ !FMF.noNaNs())
+ continue;
+ unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+ Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
+ break;
+ }
}
II->replaceAllUsesWith(Rdx);
II->eraseFromParent();
>From 7397f381ecc61a45c0a6261722eec82b5e6adf4b Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Fri, 1 May 2026 17:26:23 +0530
Subject: [PATCH 2/5] [CodeGen] Fix getArithmeticReductionInstruction for
fmaximum/fminimum
---
llvm/lib/Transforms/Utils/LoopUtils.cpp | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp
index 39032f710eadb..5d5e33c4c2585 100644
--- a/llvm/lib/Transforms/Utils/LoopUtils.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp
@@ -1180,6 +1180,8 @@ unsigned llvm::getArithmeticReductionInstruction(Intrinsic::ID RdxID) {
return Instruction::ICmp;
case Intrinsic::vector_reduce_fmax:
case Intrinsic::vector_reduce_fmin:
+ case Intrinsic::vector_reduce_fmaximum:
+ case Intrinsic::vector_reduce_fminimum:
return Instruction::FCmp;
default:
llvm_unreachable("Unexpected ID");
@@ -1275,6 +1277,10 @@ RecurKind llvm::getMinMaxReductionRecurKind(Intrinsic::ID RdxID) {
return RecurKind::FMax;
case Intrinsic::vector_reduce_fmin:
return RecurKind::FMin;
+ case Intrinsic::vector_reduce_fmaximum:
+ return RecurKind::FMaximum;
+ case Intrinsic::vector_reduce_fminimum:
+ return RecurKind::FMinimum;
default:
return RecurKind::None;
}
>From b7abd68203177dfd092766c3f6d078e4bcea9699 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Fri, 1 May 2026 18:54:58 +0530
Subject: [PATCH 3/5] [WebAssembly] Return false from shouldExpandReduction for
fmaximum/fminimum
---
.../WebAssembly/WebAssemblyTargetTransformInfo.cpp | 10 ++++++++++
.../WebAssembly/WebAssemblyTargetTransformInfo.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
index 7249d54cc7a9f..3a8668465563e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
@@ -480,6 +480,16 @@ InstructionCost WebAssemblyTTIImpl::getPartialReductionCost(
return Invalid;
}
+bool WebAssemblyTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
+ switch (II->getIntrinsicID()) {
+ case Intrinsic::vector_reduce_fmaximum:
+ case Intrinsic::vector_reduce_fminimum:
+ return false;
+ default:
+ return BaseT::shouldExpandReduction(II);
+ }
+}
+
TTI::ReductionShuffle WebAssemblyTTIImpl::getPreferredExpandedReductionShuffle(
const IntrinsicInst *II) const {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
index 221f32609b2de..af2529c3d82e1 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
@@ -105,6 +105,8 @@ class WebAssemblyTTIImpl final : public BasicTTIImplBase<WebAssemblyTTIImpl> {
TTI::TargetCostKind CostKind,
std::optional<FastMathFlags> FMF) const override;
+ bool shouldExpandReduction(const IntrinsicInst *II) const override;
+
TTI::ReductionShuffle
getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const override;
>From c003f412776aacaee21371e28015370f9e6848c8 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Thu, 21 May 2026 04:15:02 +0530
Subject: [PATCH 4/5] [CodeGen] Fix fmaximum/fminimum expansion and update
tests
---
llvm/lib/CodeGen/ExpandReductions.cpp | 16 +--
.../WebAssemblyTargetTransformInfo.cpp | 10 --
.../WebAssemblyTargetTransformInfo.h | 2 -
.../test/CodeGen/WebAssembly/vector-reduce.ll | 114 +++++++++---------
.../X86/vector-reductions-expanded.ll | 33 +++++
5 files changed, 95 insertions(+), 80 deletions(-)
diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp
index 398b4f35a30aa..98e900591bba1 100644
--- a/llvm/lib/CodeGen/ExpandReductions.cpp
+++ b/llvm/lib/CodeGen/ExpandReductions.cpp
@@ -35,7 +35,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
for (auto &I : instructions(F)) {
if (auto *II = dyn_cast<IntrinsicInst>(&I)) {
switch (II->getIntrinsicID()) {
- default: break;
+ default:
+ break;
case Intrinsic::vector_reduce_fadd:
case Intrinsic::vector_reduce_fmul:
case Intrinsic::vector_reduce_add:
@@ -50,12 +51,13 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
case Intrinsic::vector_reduce_fmax:
case Intrinsic::vector_reduce_fmin:
case Intrinsic::vector_reduce_fmaximum:
- case Intrinsic::vector_reduce_fminimum:
+ case Intrinsic::vector_reduce_fminimum: {
+ // Only expand if the target doesn't support this operation natively
if (TTI->shouldExpandReduction(II))
Worklist.push_back(II);
-
break;
}
+ }
}
}
@@ -71,7 +73,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
IRBuilder<>::FastMathFlagGuard FMFGuard(Builder);
Builder.setFastMathFlags(FMF);
switch (ID) {
- default: llvm_unreachable("Unexpected intrinsic!");
+ default:
+ llvm_unreachable("Unexpected intrinsic!");
case Intrinsic::vector_reduce_fadd:
case Intrinsic::vector_reduce_fmul: {
// FMFs must be attached to the call, otherwise it's an ordered reduction
@@ -161,12 +164,9 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
}
case Intrinsic::vector_reduce_fmaximum:
case Intrinsic::vector_reduce_fminimum: {
- // We require "nnan" to use a shuffle reduction; "nsz" is implied by the
- // semantics of the reduction.
Value *Vec = II->getArgOperand(0);
if (!isPowerOf2_32(
- cast<FixedVectorType>(Vec->getType())->getNumElements()) ||
- !FMF.noNaNs())
+ cast<FixedVectorType>(Vec->getType())->getNumElements()))
continue;
unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
index 3a8668465563e..7249d54cc7a9f 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
@@ -480,16 +480,6 @@ InstructionCost WebAssemblyTTIImpl::getPartialReductionCost(
return Invalid;
}
-bool WebAssemblyTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
- switch (II->getIntrinsicID()) {
- case Intrinsic::vector_reduce_fmaximum:
- case Intrinsic::vector_reduce_fminimum:
- return false;
- default:
- return BaseT::shouldExpandReduction(II);
- }
-}
-
TTI::ReductionShuffle WebAssemblyTTIImpl::getPreferredExpandedReductionShuffle(
const IntrinsicInst *II) const {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
index af2529c3d82e1..221f32609b2de 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
@@ -105,8 +105,6 @@ class WebAssemblyTTIImpl final : public BasicTTIImplBase<WebAssemblyTTIImpl> {
TTI::TargetCostKind CostKind,
std::optional<FastMathFlags> FMF) const override;
- bool shouldExpandReduction(const IntrinsicInst *II) const override;
-
TTI::ReductionShuffle
getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const override;
diff --git a/llvm/test/CodeGen/WebAssembly/vector-reduce.ll b/llvm/test/CodeGen/WebAssembly/vector-reduce.ll
index 4c30a3adf2378..d0ac1c86dd8d8 100644
--- a/llvm/test/CodeGen/WebAssembly/vector-reduce.ll
+++ b/llvm/test/CodeGen/WebAssembly/vector-reduce.ll
@@ -909,9 +909,9 @@ define double @pairwise_maximum_v2f64(<2 x double> %arg) {
; SIMD128-LABEL: pairwise_maximum_v2f64:
; SIMD128: .functype pairwise_maximum_v2f64 (v128) -> (f64)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f64x2.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f64x2.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f64.max $push2=, $pop1, $pop0
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7
+; SIMD128-NEXT: f64x2.max $push1=, $0, $pop0
+; SIMD128-NEXT: f64x2.extract_lane $push2=, $pop1, 0
; SIMD128-NEXT: return $pop2
%res = tail call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %arg)
ret double%res
@@ -921,9 +921,9 @@ define double @pairwise_maximum_v2f64_fast(<2 x double> %arg) {
; SIMD128-LABEL: pairwise_maximum_v2f64_fast:
; SIMD128: .functype pairwise_maximum_v2f64_fast (v128) -> (f64)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f64x2.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f64x2.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f64.max $push2=, $pop1, $pop0
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7
+; SIMD128-NEXT: f64x2.max $push1=, $0, $pop0
+; SIMD128-NEXT: f64x2.extract_lane $push2=, $pop1, 0
; SIMD128-NEXT: return $pop2
%res = tail call fast double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %arg)
ret double%res
@@ -933,14 +933,13 @@ define float @pairwise_maximum_v4f32(<4 x float> %arg) {
; SIMD128-LABEL: pairwise_maximum_v4f32:
; SIMD128: .functype pairwise_maximum_v4f32 (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f32.max $push2=, $pop1, $pop0
-; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 2
-; SIMD128-NEXT: f32.max $push4=, $pop2, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push5=, $0, 3
-; SIMD128-NEXT: f32.max $push6=, $pop4, $pop5
-; SIMD128-NEXT: return $pop6
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.max $push5=, $0, $pop0
+; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
+; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.max $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
+; SIMD128-NEXT: return $pop3
%res = tail call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %arg)
ret float %res
}
@@ -949,14 +948,13 @@ define float @pairwise_maximum_v4f32_fast(<4 x float> %arg) {
; SIMD128-LABEL: pairwise_maximum_v4f32_fast:
; SIMD128: .functype pairwise_maximum_v4f32_fast (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f32.max $push2=, $pop1, $pop0
-; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 2
-; SIMD128-NEXT: f32.max $push4=, $pop2, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push5=, $0, 3
-; SIMD128-NEXT: f32.max $push6=, $pop4, $pop5
-; SIMD128-NEXT: return $pop6
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.max $push5=, $0, $pop0
+; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
+; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.max $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
+; SIMD128-NEXT: return $pop3
%res = tail call fast float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %arg)
ret float %res
}
@@ -965,14 +963,13 @@ define float @pairwise_maximum_v4f32_reassoc(<4 x float> %arg) {
; SIMD128-LABEL: pairwise_maximum_v4f32_reassoc:
; SIMD128: .functype pairwise_maximum_v4f32_reassoc (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f32.max $push2=, $pop1, $pop0
-; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 2
-; SIMD128-NEXT: f32.max $push4=, $pop2, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push5=, $0, 3
-; SIMD128-NEXT: f32.max $push6=, $pop4, $pop5
-; SIMD128-NEXT: return $pop6
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.max $push5=, $0, $pop0
+; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
+; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.max $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
+; SIMD128-NEXT: return $pop3
%res = tail call reassoc float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %arg)
ret float %res
}
@@ -981,9 +978,9 @@ define double @pairwise_minimum_v2f64(<2 x double> %arg) {
; SIMD128-LABEL: pairwise_minimum_v2f64:
; SIMD128: .functype pairwise_minimum_v2f64 (v128) -> (f64)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f64x2.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f64x2.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f64.min $push2=, $pop1, $pop0
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7
+; SIMD128-NEXT: f64x2.min $push1=, $0, $pop0
+; SIMD128-NEXT: f64x2.extract_lane $push2=, $pop1, 0
; SIMD128-NEXT: return $pop2
%res = tail call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %arg)
ret double%res
@@ -993,9 +990,9 @@ define double @pairwise_minimum_v2f64_fast(<2 x double> %arg) {
; SIMD128-LABEL: pairwise_minimum_v2f64_fast:
; SIMD128: .functype pairwise_minimum_v2f64_fast (v128) -> (f64)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f64x2.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f64x2.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f64.min $push2=, $pop1, $pop0
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7
+; SIMD128-NEXT: f64x2.min $push1=, $0, $pop0
+; SIMD128-NEXT: f64x2.extract_lane $push2=, $pop1, 0
; SIMD128-NEXT: return $pop2
%res = tail call fast double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %arg)
ret double%res
@@ -1005,14 +1002,13 @@ define float @pairwise_minimum_v4f32(<4 x float> %arg) {
; SIMD128-LABEL: pairwise_minimum_v4f32:
; SIMD128: .functype pairwise_minimum_v4f32 (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f32.min $push2=, $pop1, $pop0
-; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 2
-; SIMD128-NEXT: f32.min $push4=, $pop2, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push5=, $0, 3
-; SIMD128-NEXT: f32.min $push6=, $pop4, $pop5
-; SIMD128-NEXT: return $pop6
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.min $push5=, $0, $pop0
+; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
+; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.min $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
+; SIMD128-NEXT: return $pop3
%res = tail call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %arg)
ret float %res
}
@@ -1021,14 +1017,13 @@ define float @pairwise_minimum_v4f32_fast(<4 x float> %arg) {
; SIMD128-LABEL: pairwise_minimum_v4f32_fast:
; SIMD128: .functype pairwise_minimum_v4f32_fast (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f32.min $push2=, $pop1, $pop0
-; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 2
-; SIMD128-NEXT: f32.min $push4=, $pop2, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push5=, $0, 3
-; SIMD128-NEXT: f32.min $push6=, $pop4, $pop5
-; SIMD128-NEXT: return $pop6
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.min $push5=, $0, $pop0
+; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
+; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.min $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
+; SIMD128-NEXT: return $pop3
%res = tail call fast float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %arg)
ret float %res
}
@@ -1037,14 +1032,13 @@ define float @pairwise_minimum_v4f32_reassoc(<4 x float> %arg) {
; SIMD128-LABEL: pairwise_minimum_v4f32_reassoc:
; SIMD128: .functype pairwise_minimum_v4f32_reassoc (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 0
-; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
-; SIMD128-NEXT: f32.min $push2=, $pop1, $pop0
-; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 2
-; SIMD128-NEXT: f32.min $push4=, $pop2, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push5=, $0, 3
-; SIMD128-NEXT: f32.min $push6=, $pop4, $pop5
-; SIMD128-NEXT: return $pop6
+; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.min $push5=, $0, $pop0
+; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
+; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
+; SIMD128-NEXT: f32x4.min $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
+; SIMD128-NEXT: return $pop3
%res = tail call reassoc float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %arg)
ret float %res
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
index acddf254c2998..62e69c2c3204e 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
@@ -360,6 +360,36 @@ for.end:
ret float %r.0
}
+define float @fmaximum_v4f32(<4 x float> %arg) {
+; CHECK-LABEL: @fmaximum_v4f32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> %arg, <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
+; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.maximum.v4f32(<4 x float> %arg, <4 x float> [[RDX_SHUF]])
+; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[RDX_MINMAX]], <4 x float> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[RDX_MINMAX2:%.*]] = call <4 x float> @llvm.maximum.v4f32(<4 x float> [[RDX_MINMAX]], <4 x float> [[RDX_SHUF3]])
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[RDX_MINMAX2]], i32 0
+; CHECK-NEXT: ret float [[TMP2]]
+;
+entry:
+ %res = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %arg)
+ ret float %res
+}
+
+define float @fminimum_v4f32(<4 x float> %arg) {
+; CHECK-LABEL: @fminimum_v4f32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> %arg, <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
+; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.minimum.v4f32(<4 x float> %arg, <4 x float> [[RDX_SHUF]])
+; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[RDX_MINMAX]], <4 x float> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[RDX_MINMAX2:%.*]] = call <4 x float> @llvm.minimum.v4f32(<4 x float> [[RDX_MINMAX]], <4 x float> [[RDX_SHUF3]])
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[RDX_MINMAX2]], i32 0
+; CHECK-NEXT: ret float [[TMP2]]
+;
+entry:
+ %res = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %arg)
+ ret float %res
+}
+
define available_externally float @max(float %a, float %b) {
entry:
%a.addr = alloca float, align 4
@@ -432,6 +462,9 @@ entry:
ret float %call13
}
+declare float @llvm.vector.reduce.fmaximum.v4f32(<4 x float>)
+declare float @llvm.vector.reduce.fminimum.v4f32(<4 x float>)
+
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"PIC Level", i32 2}
!2 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git a9fe69c359de653015c39e413e48630d069abe27)"}
>From ca76ae9ab72d0340b55d2f72adb3c2c9c535ddc7 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Sat, 4 Jul 2026 05:08:27 +0530
Subject: [PATCH 5/5] [CodeGen] Regenerate X86/AMDGPU fmaximum/fminimum
reduction tests
---
.../CodeGen/AMDGPU/vector-reduce-fmaximum.ll | 2977 +++++++--------
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 3359 ++++++++---------
.../llvm-vector-reduce/fmaximum.ll | 24 +-
.../llvm-vector-reduce/fminimum.ll | 24 +-
.../CodeGen/X86/vector-reduce-fmaximum.ll | 1517 ++++----
.../CodeGen/X86/vector-reduce-fminimum.ll | 1513 ++++----
6 files changed, 4758 insertions(+), 4656 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
index c7d6f7cd97d1e..cf5d74eca9025 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
@@ -256,39 +256,41 @@ define half @test_vector_reduce_fmaximum_v4half(<4 x half> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX7-NEXT: v_max_f32_e32 v4, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v4, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX7-NEXT: v_max_f32_e32 v4, v2, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v3, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v4half:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX8-NEXT: v_max_f16_e32 v4, v0, v3
+; GFX8-NEXT: v_max_f16_e32 v4, v3, v2
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
; GFX8-NEXT: v_max_f16_e32 v1, v0, v2
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
@@ -298,69 +300,66 @@ define half @test_vector_reduce_fmaximum_v4half(<4 x half> %v) {
; GFX9-LABEL: test_vector_reduce_fmaximum_v4half:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_f16_sdwa v2, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_pk_max_f16 v2, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
-; GFX9-NEXT: v_max_f16_e32 v2, v0, v1
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
-; GFX9-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v3, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_max_f16_e32 v1, v4, v0
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v4, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v4half:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f16_sdwa v2, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v0 src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX10-NEXT: v_pk_max_f16 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x7e00
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v2, s4
; GFX10-NEXT: v_max_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v4half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v4half:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v3, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v3
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v1, v0, v3
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v4half:
@@ -414,83 +413,83 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5
; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_mov_b32_e32 v6, 0x7fc00000
-; GFX7-NEXT: v_max_f32_e32 v5, v0, v4
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v5, v0, v4
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v4, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v4, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v8, v4, v5
+; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v4, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v8, vcc
+; GFX7-NEXT: v_max_f32_e32 v5, v6, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v6, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX7-NEXT: v_max_f32_e32 v6, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX7-NEXT: v_max_f32_e32 v2, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v2, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v5
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v4
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_max_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v3, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v8half:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX8-NEXT: v_max_f16_e32 v8, v0, v7
-; GFX8-NEXT: v_mov_b32_e32 v9, 0x7e00
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX8-NEXT: v_max_f16_e32 v7, v0, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_max_f16_e32 v6, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0x7e00
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX8-NEXT: v_max_f16_e32 v8, v6, v5
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v6, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc
+; GFX8-NEXT: v_max_f16_e32 v6, v1, v3
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc
+; GFX8-NEXT: v_max_f16_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc
+; GFX8-NEXT: v_max_f16_e32 v2, v5, v4
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v7, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc
; GFX8-NEXT: v_max_f16_e32 v1, v0, v2
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v4
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v8half:
@@ -499,54 +498,57 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
; GFX9-NEXT: v_pk_max_f16 v4, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: s_mov_b32 s0, 0x5040100
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX9-NEXT: v_max_f16_e32 v2, v6, v0
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v0
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
-; GFX9-NEXT: v_pk_max_f16 v2, v1, v3
+; GFX9-NEXT: v_pk_max_f16 v4, v1, v3
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v2, vcc
-; GFX9-NEXT: v_max_f16_e32 v6, v0, v4
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
+; GFX9-NEXT: v_perm_b32 v2, v0, v6, s0
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc
; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_max_f16_e32 v2, v0, v1
+; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v3, v1, v7, s0
+; GFX9-NEXT: v_pk_max_f16 v2, v2, v3
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v7
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_max_f16_e32 v1, v3, v0
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v8half:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_pk_max_f16 v4, v0, v2
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v4, 0x7e00
+; GFX10-NEXT: v_pk_max_f16 v5, v0, v2
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_pk_max_f16 v2, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
+; GFX10-NEXT: v_pk_max_f16 v6, v1, v3
+; GFX10-NEXT: v_cmp_o_f16_sdwa s4, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e64 s5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_max_f16_e32 v5, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
-; GFX10-NEXT: v_max_f16_e32 v4, v0, v6
-; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v6
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_perm_b32 v5, v2, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_sdwa v3, v4, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
+; GFX10-NEXT: v_perm_b32 v6, v3, v1, 0x5040100
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v3
+; GFX10-NEXT: v_pk_max_f16 v5, v5, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_max_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
@@ -558,22 +560,21 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v0, v2
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v1, v3
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v0.h, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v1, v0
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
@@ -587,27 +588,29 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v7, v1, v3
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v4, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v10, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v5, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v4, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v3, v0, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v6
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9, v8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v3, v4, v0, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v5, v2, v1, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v3, v3, v5
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
@@ -674,285 +677,282 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX7-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v12, v12
+; GFX7-NEXT: v_cvt_f32_f16_e32 v11, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v4
+; GFX7-NEXT: v_cvt_f32_f16_e32 v15, v15
+; GFX7-NEXT: v_cvt_f32_f16_e32 v10, v10
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v14, v14
+; GFX7-NEXT: v_cvt_f32_f16_e32 v9, v9
+; GFX7-NEXT: v_cvt_f32_f16_e32 v13, v13
; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v8
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_mov_b32_e32 v10, 0x7fc00000
-; GFX7-NEXT: v_max_f32_e32 v9, v0, v8
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v9, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v9, v0, v8
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v9, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v8, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v8, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v4
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX7-NEXT: v_max_f32_e32 v16, v11, v12
+; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v11, v12
+; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v17, v16, vcc
+; GFX7-NEXT: v_max_f32_e32 v12, v10, v15
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v10, v15
+; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v10, v17, v12, vcc
+; GFX7-NEXT: v_max_f32_e32 v12, v9, v14
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v9, v14
+; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v9, v17, v12, vcc
+; GFX7-NEXT: v_max_f32_e32 v12, v8, v13
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v8, v13
+; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v12, vcc
+; GFX7-NEXT: v_max_f32_e32 v12, v1, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v12, vcc
+; GFX7-NEXT: v_max_f32_e32 v5, v3, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v5, vcc
+; GFX7-NEXT: v_max_f32_e32 v5, v0, v4
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX7-NEXT: v_cvt_f16_f32_e32 v9, v9
+; GFX7-NEXT: v_cvt_f16_f32_e32 v8, v8
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v5, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v2, v6
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX7-NEXT: v_cvt_f16_f32_e32 v11, v11
+; GFX7-NEXT: v_cvt_f16_f32_e32 v10, v10
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v4, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v5
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v8
+; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v9
+; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v10
+; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v11
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v6
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v7, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v7, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v17, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v5, v8, v6
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v8, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
+; GFX7-NEXT: v_max_f32_e32 v6, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX7-NEXT: v_max_f32_e32 v2, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v5
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v4
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v7
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_max_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v3, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v0
-; GFX8-NEXT: v_max_f16_e32 v16, v0, v15
-; GFX8-NEXT: v_mov_b32_e32 v17, 0x7e00
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX8-NEXT: v_max_f16_e32 v15, v0, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX8-NEXT: v_max_f16_e32 v10, v9, v8
+; GFX8-NEXT: v_mov_b32_e32 v11, 0x7e00
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v9, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v10, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v0
+; GFX8-NEXT: v_max_f16_e32 v12, v10, v9
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v10, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; GFX8-NEXT: v_max_f16_e32 v13, v12, v10
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v12, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; GFX8-NEXT: v_max_f16_e32 v14, v13, v12
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v13, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v14, vcc
+; GFX8-NEXT: v_max_f16_e32 v13, v2, v6
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v2, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v13, vcc
+; GFX8-NEXT: v_max_f16_e32 v6, v0, v4
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v6, vcc
+; GFX8-NEXT: v_max_f16_e32 v4, v3, v7
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
+; GFX8-NEXT: v_max_f16_e32 v4, v1, v5
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v4, vcc
+; GFX8-NEXT: v_max_f16_e32 v4, v12, v10
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v12, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc
+; GFX8-NEXT: v_max_f16_e32 v5, v9, v8
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v9, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
+; GFX8-NEXT: v_max_f16_e32 v6, v1, v3
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v6, vcc
+; GFX8-NEXT: v_max_f16_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v3, vcc
+; GFX8-NEXT: v_max_f16_e32 v2, v5, v4
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc
+; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v14
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v14
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v3, vcc
; GFX8-NEXT: v_max_f16_e32 v1, v0, v2
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v13
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v13
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v12
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v12
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v4
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v11
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v11
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v10
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v10
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v6
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v9
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v9
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v7
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v7
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f16_e32 v1, v0, v8
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_f16 v8, v2, v6
+; GFX9-NEXT: v_pk_max_f16 v8, v1, v5
; GFX9-NEXT: v_mov_b32_e32 v9, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5
; GFX9-NEXT: s_mov_b32 s0, 0x5040100
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
; GFX9-NEXT: v_pk_max_f16 v8, v0, v4
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX9-NEXT: v_perm_b32 v6, v2, v10, s0
+; GFX9-NEXT: v_perm_b32 v5, v1, v10, s0
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v9, v8, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_pk_max_f16 v8, v3, v7
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7
; GFX9-NEXT: v_perm_b32 v4, v0, v11, s0
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_pk_max_f16 v7, v2, v6
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_sdwa v3, v9, v8, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v7, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_sdwa v2, v9, v7, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v6, v2, v8, s0
; GFX9-NEXT: v_pk_max_f16 v4, v4, v6
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v11, v10
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v11, v8
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v4, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v4, vcc
-; GFX9-NEXT: v_max_f16_e32 v2, v6, v0
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v0
-; GFX9-NEXT: v_pk_max_f16 v6, v1, v5
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
-; GFX9-NEXT: v_pk_max_f16 v2, v3, v7
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5
-; GFX9-NEXT: v_perm_b32 v3, v2, v4, s0
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v9, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v4, v3, v12, s0
+; GFX9-NEXT: v_pk_max_f16 v4, v5, v4
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v10, v12
+; GFX9-NEXT: v_perm_b32 v2, v0, v6, s0
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v6, vcc
-; GFX9-NEXT: v_perm_b32 v5, v1, v7, s0
-; GFX9-NEXT: v_pk_max_f16 v3, v5, v3
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v7, v4
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v3, vcc
-; GFX9-NEXT: v_max_f16_e32 v5, v0, v4
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v4, vcc
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v5, vcc
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_sdwa v1, v9, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v3, v1, v5, s0
+; GFX9-NEXT: v_pk_max_f16 v2, v2, v3
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v5
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_sdwa v1, v9, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_max_f16_e32 v2, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v2, vcc
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v9, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_max_f16_e32 v1, v3, v0
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_pk_max_f16 v8, v2, v6
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
-; GFX10-NEXT: v_pk_max_f16 v9, v0, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v10, vcc_lo
+; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_pk_max_f16 v8, v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v9, 0x7e00
+; GFX10-NEXT: v_pk_max_f16 v10, v0, v4
+; GFX10-NEXT: v_cmp_o_f16_sdwa s4, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_sdwa s5, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_pk_max_f16 v12, v2, v6
+; GFX10-NEXT: v_cndmask_b32_sdwa v11, v9, v8, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v9, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_pk_max_f16 v9, v3, v7
-; GFX10-NEXT: v_perm_b32 v4, v2, v8, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v9
-; GFX10-NEXT: v_pk_max_f16 v11, v1, v5
-; GFX10-NEXT: v_perm_b32 v10, v0, v6, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v9, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_pk_max_f16 v4, v10, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v10, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cmp_o_f16_sdwa s4, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_cndmask_b32_sdwa v4, v9, v10, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_pk_max_f16 v10, v3, v7
+; GFX10-NEXT: s_mov_b32 vcc_lo, s5
+; GFX10-NEXT: v_cndmask_b32_sdwa v13, v9, v10, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v12, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v6, v9, v12, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v11, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v10, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v8
-; GFX10-NEXT: v_perm_b32 v6, v3, v9, 0x5040100
-; GFX10-NEXT: v_perm_b32 v8, v1, v7, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_pk_max_f16 v2, v8, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v9
-; GFX10-NEXT: v_max_f16_e32 v5, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
+; GFX10-NEXT: v_perm_b32 v5, v4, v0, 0x5040100
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
+; GFX10-NEXT: v_perm_b32 v8, v6, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v7, v11, v1, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v10, vcc_lo
+; GFX10-NEXT: v_pk_max_f16 v5, v5, v8
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v6
+; GFX10-NEXT: v_perm_b32 v8, v13, v3, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s4
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v11, v13
+; GFX10-NEXT: v_cndmask_b32_sdwa v4, v9, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
-; GFX10-NEXT: v_max_f16_e32 v4, v0, v6
-; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v6
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_pk_max_f16 v2, v7, v8
+; GFX10-NEXT: v_perm_b32 v3, v4, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v2, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v9, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
+; GFX10-NEXT: v_perm_b32 v5, v2, v1, 0x5040100
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v2
+; GFX10-NEXT: v_pk_max_f16 v3, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v3, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v9, v3, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_max_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
@@ -961,116 +961,117 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v8, v2, v6
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v6.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v0, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.h, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v8, v1, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v9, v0, v4
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v2, v6
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.h, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v7.l
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v2.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v2.h, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v3.h, v7.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v1.h, v5.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v2, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v5.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v9.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v9.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.h, v6.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v3.l, v7.l
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v3, v7
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v3, v1, v5
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v2.l, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v2.h, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v3.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v3.h, s3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v3.h, v7.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v4.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v2.l, s2
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v2.h, s3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v1, v0, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.h, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v3, v2, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v1.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.h, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v1.h, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v8, v2, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v8, v1, v5
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v10, v0, v4
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v8, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v5, v3, v7
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v8, v2, v6
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v5
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v10, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v12, v1, v5
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v6, v2, v9, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v10, v3, v7
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v8
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v13, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v12
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v8, v4, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v6, v8, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v10, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v10, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v12, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v14, v13
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v14, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v7, v4, v0, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v10, v1, v9, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v15, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v9
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v6, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v2
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v4, v3, v8, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v6, v5, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v11, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v4, v6, v4
-; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v7, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v8, v6, v2, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v11, v5, v3, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v7, v7, v8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v8, v10, v11
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v8
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v2, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v6
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v10, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9, v3
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v2, v4, v0, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v5, v1, v3, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_pk_max_f16 v2, v2, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v5, v3
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_max_f16_e32 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1080,11 +1081,11 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v3, v3, v7
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v1, v1, v5
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v4
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v1, v1, v3
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1095,11 +1096,11 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX1170-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v3, v3, v7
; GFX1170-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v1, v1, v5
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX1170-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v4
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v1, v1, v3
; GFX1170-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1116,11 +1117,11 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v3, v3, v7
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v1, v1, v5
-; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v1, v1, v3
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1135,11 +1136,11 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v3, v3, v7
; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v1, v1, v5
-; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v2, v2, v6
; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v4
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v1, v1, v3
; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1306,88 +1307,86 @@ define float @test_vector_reduce_fmaximum_v4float(<4 x float> %v) {
; GFX7-LABEL: test_vector_reduce_fmaximum_v4float:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_max_f32_e32 v4, v0, v1
+; GFX7-NEXT: v_max_f32_e32 v4, v1, v3
; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v3, v0, v2
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v4float:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f32_e32 v4, v0, v1
+; GFX8-NEXT: v_max_f32_e32 v4, v1, v3
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7fc00000
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
+; GFX8-NEXT: v_max_f32_e32 v3, v0, v2
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX8-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v4float:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_f32_e32 v4, v0, v1
+; GFX9-NEXT: v_max_f32_e32 v4, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v5, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX9-NEXT: v_max_f32_e32 v3, v0, v2
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX9-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v4float:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f32_e32 v4, v0, v1
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX10-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX10-NEXT: v_max_f32_e32 v5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX10-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v4float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f32_e32 v4, v0, v1
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX11-NEXT: v_dual_max_f32 v4, v1, v3 :: v_dual_max_f32 v5, v0, v2
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_vector_reduce_fmaximum_v4float:
; GFX1170: ; %bb.0: ; %entry
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_maximum_f32 v0, v0, v1
+; GFX1170-NEXT: v_maximum3_f32 v0, v0, v2, v1
; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v2, v3
+; GFX1170-NEXT: v_maximum_f32 v0, v0, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v4float:
@@ -1397,9 +1396,9 @@ define float @test_vector_reduce_fmaximum_v4float(<4 x float> %v) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_maximum_f32 v0, v0, v1
+; GFX12-NEXT: v_maximum3_f32 v0, v0, v2, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v2, v3
+; GFX12-NEXT: v_maximum_f32 v0, v0, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmaximum.v4float(<4 x float> %v)
@@ -1410,159 +1409,154 @@ define float @test_vector_reduce_fmaximum_v8float(<8 x float> %v) {
; GFX7-LABEL: test_vector_reduce_fmaximum_v8float:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_max_f32_e32 v8, v0, v1
+; GFX7-NEXT: v_max_f32_e32 v8, v2, v6
; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v4
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
+; GFX7-NEXT: v_max_f32_e32 v6, v0, v4
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v3, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v1, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v3, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v8float:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f32_e32 v8, v0, v1
+; GFX8-NEXT: v_max_f32_e32 v8, v2, v6
; GFX8-NEXT: v_mov_b32_e32 v9, 0x7fc00000
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v4
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
+; GFX8-NEXT: v_max_f32_e32 v6, v0, v4
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX8-NEXT: v_max_f32_e32 v4, v3, v7
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc
+; GFX8-NEXT: v_max_f32_e32 v4, v1, v5
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_max_f32_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX8-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v8float:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_f32_e32 v8, v0, v1
+; GFX9-NEXT: v_max_f32_e32 v8, v2, v6
; GFX9-NEXT: v_mov_b32_e32 v9, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v4
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX9-NEXT: v_max_f32_e32 v6, v0, v4
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX9-NEXT: v_max_f32_e32 v4, v3, v7
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc
+; GFX9-NEXT: v_max_f32_e32 v4, v1, v5
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX9-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX9-NEXT: v_max_f32_e32 v3, v0, v2
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX9-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v8float:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f32_e32 v8, v0, v1
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_max_f32_e32 v8, v2, v6
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX10-NEXT: v_max_f32_e32 v9, v3, v7
+; GFX10-NEXT: v_max_f32_e32 v6, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX10-NEXT: v_max_f32_e32 v8, v0, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX10-NEXT: v_max_f32_e32 v4, v1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX10-NEXT: v_max_f32_e32 v5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v4
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX10-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v8float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f32_e32 v8, v0, v1
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_max_f32 v8, v2, v6 :: v_dual_max_f32 v9, v3, v7
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_max_f32_e32 v6, v1, v5
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_max_f32 v8, v0, v4 :: v_dual_cndmask_b32 v1, 0x7fc00000, v6
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v2
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: v_max_f32_e32 v5, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v4
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_vector_reduce_fmaximum_v8float:
; GFX1170: ; %bb.0: ; %entry
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_maximum_f32 v0, v0, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v2, v3
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v4, v5
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v6, v7
+; GFX1170-NEXT: v_maximum_f32 v2, v2, v6
+; GFX1170-NEXT: v_maximum3_f32 v1, v1, v5, v3
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum3_f32 v0, v0, v4, v2
+; GFX1170-NEXT: v_maximum3_f32 v0, v0, v1, v7
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v8float:
@@ -1572,12 +1566,11 @@ define float @test_vector_reduce_fmaximum_v8float(<8 x float> %v) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_maximum_f32 v0, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v2, v3
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v4, v5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v6, v7
+; GFX12-NEXT: v_maximum_f32 v2, v2, v6
+; GFX12-NEXT: v_maximum3_f32 v1, v1, v5, v3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_maximum3_f32 v0, v0, v4, v2
+; GFX12-NEXT: v_maximum3_f32 v0, v0, v1, v7
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmaximum.v8float(<8 x float> %v)
@@ -1588,301 +1581,288 @@ define float @test_vector_reduce_fmaximum_v16float(<16 x float> %v) {
; GFX7-LABEL: test_vector_reduce_fmaximum_v16float:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_max_f32_e32 v16, v0, v1
+; GFX7-NEXT: v_max_f32_e32 v16, v5, v13
; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v4
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v8
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v5, v13
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc
+; GFX7-NEXT: v_max_f32_e32 v13, v1, v9
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v9
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v13, vcc
+; GFX7-NEXT: v_max_f32_e32 v9, v7, v15
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v7, v15
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v17, v9, vcc
+; GFX7-NEXT: v_max_f32_e32 v9, v3, v11
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v11
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v9, vcc
+; GFX7-NEXT: v_max_f32_e32 v9, v4, v12
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v4, v12
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v17, v9, vcc
+; GFX7-NEXT: v_max_f32_e32 v9, v0, v8
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v9
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v9
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v10
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v10
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v11
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v11
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v12
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v12
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v13
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v13
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v14
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v14
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_max_f32_e32 v1, v0, v15
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v15
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc
+; GFX7-NEXT: v_max_f32_e32 v8, v6, v14
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v6, v14
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v17, v8, vcc
+; GFX7-NEXT: v_max_f32_e32 v8, v2, v10
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v10
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX7-NEXT: v_max_f32_e32 v8, v2, v6
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX7-NEXT: v_max_f32_e32 v6, v0, v4
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v3, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v1, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX7-NEXT: v_max_f32_e32 v3, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v16float:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f32_e32 v16, v0, v1
+; GFX8-NEXT: v_max_f32_e32 v16, v5, v13
; GFX8-NEXT: v_mov_b32_e32 v17, 0x7fc00000
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v4
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v8
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v5, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc
+; GFX8-NEXT: v_max_f32_e32 v13, v1, v9
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v13, vcc
+; GFX8-NEXT: v_max_f32_e32 v9, v7, v15
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v7, v15
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v17, v9, vcc
+; GFX8-NEXT: v_max_f32_e32 v9, v3, v11
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v3, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v9, vcc
+; GFX8-NEXT: v_max_f32_e32 v9, v4, v12
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v4, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v17, v9, vcc
+; GFX8-NEXT: v_max_f32_e32 v9, v0, v8
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v9
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v9
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v10
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v10
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v11
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v11
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v12
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v12
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v13
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v13
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v14
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v14
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_max_f32_e32 v1, v0, v15
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc
+; GFX8-NEXT: v_max_f32_e32 v8, v6, v14
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v6, v14
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v17, v8, vcc
+; GFX8-NEXT: v_max_f32_e32 v8, v2, v10
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v2, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX8-NEXT: v_max_f32_e32 v8, v2, v6
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX8-NEXT: v_max_f32_e32 v6, v0, v4
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX8-NEXT: v_max_f32_e32 v4, v3, v7
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc
+; GFX8-NEXT: v_max_f32_e32 v4, v1, v5
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX8-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX8-NEXT: v_max_f32_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX8-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v16float:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_f32_e32 v16, v0, v1
+; GFX9-NEXT: v_max_f32_e32 v16, v5, v13
; GFX9-NEXT: v_mov_b32_e32 v17, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v4
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v5, v13
+; GFX9-NEXT: v_max_f32_e32 v13, v1, v9
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v9
+; GFX9-NEXT: v_max_f32_e32 v9, v7, v15
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v13, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v7, v15
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v9, vcc
+; GFX9-NEXT: v_max_f32_e32 v9, v3, v11
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v11
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v9, vcc
+; GFX9-NEXT: v_max_f32_e32 v9, v4, v12
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v4, v12
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v9, vcc
+; GFX9-NEXT: v_max_f32_e32 v9, v0, v8
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
+; GFX9-NEXT: v_max_f32_e32 v8, v6, v14
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v6, v14
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v9
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v9
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v10
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v10
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v11
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v8, vcc
+; GFX9-NEXT: v_max_f32_e32 v8, v2, v10
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v10
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v12
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v12
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX9-NEXT: v_max_f32_e32 v8, v2, v6
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX9-NEXT: v_max_f32_e32 v6, v0, v4
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX9-NEXT: v_max_f32_e32 v4, v3, v7
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v13
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v13
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc
+; GFX9-NEXT: v_max_f32_e32 v4, v1, v5
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v14
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v14
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX9-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX9-NEXT: v_max_f32_e32 v3, v0, v2
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_max_f32_e32 v1, v0, v15
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v15
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX9-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v16float:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f32_e32 v16, v0, v1
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v16, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v4
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v8
+; GFX10-NEXT: v_max_f32_e32 v16, v5, v13
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v13
+; GFX10-NEXT: v_max_f32_e32 v17, v1, v9
+; GFX10-NEXT: v_max_f32_e32 v18, v7, v15
+; GFX10-NEXT: v_max_f32_e32 v13, v3, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7fc00000, v16, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v9
+; GFX10-NEXT: v_max_f32_e32 v9, v6, v14
+; GFX10-NEXT: v_max_f32_e32 v16, v4, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v7, v15
+; GFX10-NEXT: v_max_f32_e32 v15, v2, v10
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7fc00000, v18, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v14
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v10
+; GFX10-NEXT: v_max_f32_e32 v9, v0, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v15, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v11
+; GFX10-NEXT: v_max_f32_e32 v10, v2, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v13, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v4, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7fc00000, v16, vcc_lo
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v9
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v10
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v10
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v11
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v12
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v12
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v13
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v13
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v14
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v14
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_max_f32_e32 v1, v0, v15
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v15
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: v_max_f32_e32 v8, v3, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX10-NEXT: v_max_f32_e32 v6, v1, v5
+; GFX10-NEXT: v_max_f32_e32 v9, v0, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v8, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX10-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX10-NEXT: v_max_f32_e32 v5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX10-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v16float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f32_e32 v16, v0, v1
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v16, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v2
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v3
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v4
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v5
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v6
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v7
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v8
+; GFX11-NEXT: v_dual_max_f32 v17, v1, v9 :: v_dual_max_f32 v18, v7, v15
+; GFX11-NEXT: v_max_f32_e32 v16, v5, v13
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7fc00000, v16, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v9
+; GFX11-NEXT: v_dual_max_f32 v16, v4, v12 :: v_dual_max_f32 v13, v3, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v7, v15
+; GFX11-NEXT: v_max_f32_e32 v15, v2, v10
+; GFX11-NEXT: v_max_f32_e32 v9, v6, v14
+; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7fc00000, v18, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v15, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v11
+; GFX11-NEXT: v_dual_max_f32 v10, v2, v6 :: v_dual_cndmask_b32 v3, 0x7fc00000, v13
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v4, v12
+; GFX11-NEXT: v_max_f32_e32 v9, v0, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v9
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v10
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v11
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v12
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v13
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v14
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_max_f32_e32 v1, v0, v15
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v15
+; GFX11-NEXT: v_max_f32_e32 v8, v3, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX11-NEXT: v_dual_max_f32 v9, v0, v4 :: v_dual_cndmask_b32 v2, 0x7fc00000, v10
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX11-NEXT: v_dual_max_f32 v6, v1, v5 :: v_dual_cndmask_b32 v3, 0x7fc00000, v8
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_max_f32_e32 v4, v1, v3
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_max_f32_e32 v5, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX11-NEXT: v_max_f32_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_vector_reduce_fmaximum_v16float:
; GFX1170: ; %bb.0: ; %entry
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_maximum_f32 v0, v0, v1
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v2, v3
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v4, v5
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v6, v7
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v8, v9
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v10, v11
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v12, v13
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum3_f32 v0, v0, v14, v15
+; GFX1170-NEXT: v_maximum3_f32 v2, v2, v10, v6
+; GFX1170-NEXT: v_maximum_f32 v4, v4, v12
+; GFX1170-NEXT: v_maximum_f32 v0, v0, v8
+; GFX1170-NEXT: v_maximum3_f32 v3, v3, v11, v7
+; GFX1170-NEXT: v_maximum3_f32 v1, v1, v9, v5
+; GFX1170-NEXT: v_maximum_f32 v2, v2, v14
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1170-NEXT: v_maximum_f32 v3, v3, v15
+; GFX1170-NEXT: v_maximum_f32 v1, v1, v13
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum3_f32 v0, v0, v4, v2
+; GFX1170-NEXT: v_maximum3_f32 v0, v0, v1, v3
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v16float:
@@ -1892,18 +1872,18 @@ define float @test_vector_reduce_fmaximum_v16float(<16 x float> %v) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_maximum_f32 v0, v0, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v2, v3
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v4, v5
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v6, v7
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v8, v9
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v10, v11
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v12, v13
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_maximum3_f32 v0, v0, v14, v15
+; GFX12-NEXT: v_maximum3_f32 v2, v2, v10, v6
+; GFX12-NEXT: v_maximum_f32 v4, v4, v12
+; GFX12-NEXT: v_maximum_f32 v0, v0, v8
+; GFX12-NEXT: v_maximum3_f32 v3, v3, v11, v7
+; GFX12-NEXT: v_maximum3_f32 v1, v1, v9, v5
+; GFX12-NEXT: v_maximum_f32 v2, v2, v14
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_maximum_f32 v3, v3, v15
+; GFX12-NEXT: v_maximum_f32 v1, v1, v13
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_maximum3_f32 v0, v0, v4, v2
+; GFX12-NEXT: v_maximum3_f32 v0, v0, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fmaximum.v16float(<16 x float> %v)
@@ -2084,105 +2064,104 @@ define double @test_vector_reduce_fmaximum_v4double(<4 x double> %v) {
; GFX7-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_max_f64 v[8:9], v[2:3], v[6:7]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
; GFX7-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v10, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_max_f64 v[8:9], v[2:3], v[6:7]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
; GFX8-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v10, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
+; GFX9-NEXT: v_max_f64 v[8:9], v[2:3], v[6:7]
; GFX9-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[4:5]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v10, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_max_f64 v[8:9], v[2:3], v[6:7]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[0:1], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s4
+; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_max_f64 v[8:9], v[2:3], v[6:7]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[0:1], v[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_vector_reduce_fmaximum_v4double:
; GFX1170: ; %bb.0: ; %entry
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum_f64 v[2:3], v[2:3], v[6:7]
; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v4double:
@@ -2192,10 +2171,10 @@ define double @test_vector_reduce_fmaximum_v4double(<4 x double> %v) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_maximum_f64 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[6:7]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call double @llvm.vector.reduce.fmaximum.v4double(<4 x double> %v)
@@ -2206,201 +2185,194 @@ define double @test_vector_reduce_fmaximum_v8double(<8 x double> %v) {
; GFX7-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_max_f64 v[16:17], v[4:5], v[12:13]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[8:9]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[8:9]
+; GFX7-NEXT: v_max_f64 v[0:1], v[6:7], v[14:15]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[14:15]
+; GFX7-NEXT: v_max_f64 v[6:7], v[2:3], v[10:11]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[2:3], v[10:11]
; GFX7-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v18, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v18, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX7-NEXT: v_max_f64 v[8:9], v[6:7], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[0:1]
+; GFX7-NEXT: v_max_f64 v[0:1], v[4:5], v[2:3]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[2:3]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_max_f64 v[16:17], v[4:5], v[12:13]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[8:9]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[8:9]
+; GFX8-NEXT: v_max_f64 v[0:1], v[6:7], v[14:15]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[14:15]
+; GFX8-NEXT: v_max_f64 v[6:7], v[2:3], v[10:11]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[2:3], v[10:11]
; GFX8-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v18, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v18, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX8-NEXT: v_max_f64 v[8:9], v[6:7], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[0:1]
+; GFX8-NEXT: v_max_f64 v[0:1], v[4:5], v[2:3]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
+; GFX9-NEXT: v_max_f64 v[16:17], v[4:5], v[12:13]
; GFX9-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX9-NEXT: v_max_f64 v[12:13], v[0:1], v[8:9]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX9-NEXT: v_max_f64 v[8:9], v[6:7], v[14:15]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v13, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc
+; GFX9-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX9-NEXT: v_max_f64 v[8:9], v[2:3], v[6:7]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[4:5]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_max_f64 v[16:17], v[4:5], v[12:13]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-NEXT: v_max_f64 v[4:5], v[6:7], v[14:15]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[6:7], v[14:15]
+; GFX10-NEXT: v_max_f64 v[6:7], v[2:3], v[10:11]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[2:3], v[10:11]
+; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
+; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[0:1], v[8:9]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, 0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s6
+; GFX10-NEXT: v_max_f64 v[8:9], v[6:7], v[4:5]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[4:5]
+; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
+; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[16:17], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_max_f64 v[16:17], v[4:5], v[12:13]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[14:15]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[6:7], v[14:15]
+; GFX11-NEXT: v_max_f64 v[6:7], v[2:3], v[10:11]
+; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[2:3], v[10:11]
+; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[0:1], v[8:9]
; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_max_f64 v[8:9], v[6:7], v[4:5]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[4:5]
+; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_vector_reduce_fmaximum_v8double:
; GFX1170: ; %bb.0: ; %entry
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11]
; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[10:11]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[12:13]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-NEXT: v_maximum_f64 v[2:3], v[2:3], v[6:7]
+; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v8double:
@@ -2410,16 +2382,15 @@ define double @test_vector_reduce_fmaximum_v8double(<8 x double> %v) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13]
+; GFX12-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15]
+; GFX12-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11]
; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[10:11]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[12:13]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[14:15]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_maximum_f64 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call double @llvm.vector.reduce.fmaximum.v8double(<8 x double> %v)
@@ -2430,405 +2401,377 @@ define double @test_vector_reduce_fmaximum_v16double(<16 x double> %v) {
; GFX7-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_max_f64 v[32:33], v[8:9], v[24:25]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX7-NEXT: v_max_f64 v[8:9], v[0:1], v[16:17]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[16:17]
+; GFX7-NEXT: v_max_f64 v[0:1], v[12:13], v[28:29]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[12:13], v[28:29]
+; GFX7-NEXT: v_max_f64 v[12:13], v[10:11], v[26:27]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[10:11], v[26:27]
+; GFX7-NEXT: v_max_f64 v[10:11], v[2:3], v[18:19]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[2:3], v[18:19]
+; GFX7-NEXT: v_mov_b32_e32 v34, 0x7ff80000
+; GFX7-NEXT: v_max_f64 v[2:3], v[4:5], v[20:21]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[4:5], v[20:21]
+; GFX7-NEXT: v_max_f64 v[4:5], v[6:7], v[22:23]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[6:7], v[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v34, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v34, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v12, v32, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[4:5]
+; GFX7-NEXT: v_max_f64 v[16:17], v[10:11], v[6:7]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v34, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v34, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[14:15]
+; GFX7-NEXT: v_max_f64 v[10:11], v[2:3], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[2:3], v[0:1]
+; GFX7-NEXT: v_max_f64 v[0:1], v[8:9], v[12:13]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX7-NEXT: v_max_f64 v[6:7], v[14:15], v[30:31]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[14:15], v[30:31]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5]
+; GFX7-NEXT: v_max_f64 v[8:9], v[4:5], v[6:7]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v34, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
+; GFX7-NEXT: v_max_f64 v[6:7], v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX7-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v7, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v5, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
+; GFX7-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v34, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_max_f64 v[32:33], v[8:9], v[24:25]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX8-NEXT: v_max_f64 v[8:9], v[0:1], v[16:17]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[16:17]
+; GFX8-NEXT: v_max_f64 v[0:1], v[12:13], v[28:29]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[12:13], v[28:29]
+; GFX8-NEXT: v_max_f64 v[12:13], v[10:11], v[26:27]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[10:11], v[26:27]
+; GFX8-NEXT: v_max_f64 v[10:11], v[2:3], v[18:19]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[2:3], v[18:19]
+; GFX8-NEXT: v_mov_b32_e32 v34, 0x7ff80000
+; GFX8-NEXT: v_max_f64 v[2:3], v[4:5], v[20:21]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[4:5], v[20:21]
+; GFX8-NEXT: v_max_f64 v[4:5], v[6:7], v[22:23]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[6:7], v[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v34, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v34, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v32, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[4:5]
+; GFX8-NEXT: v_max_f64 v[16:17], v[10:11], v[6:7]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v34, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v34, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[14:15]
+; GFX8-NEXT: v_max_f64 v[10:11], v[2:3], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[2:3], v[0:1]
+; GFX8-NEXT: v_max_f64 v[0:1], v[8:9], v[12:13]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX8-NEXT: v_max_f64 v[6:7], v[14:15], v[30:31]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[14:15], v[30:31]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5]
+; GFX8-NEXT: v_max_f64 v[8:9], v[4:5], v[6:7]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v34, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
+; GFX8-NEXT: v_max_f64 v[6:7], v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX8-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
+; GFX8-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v34, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v31, off, s32
-; GFX9-NEXT: v_max_f64 v[32:33], v[0:1], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v34, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
+; GFX9-NEXT: v_mov_b32_e32 v36, 0x7ff80000
+; GFX9-NEXT: v_max_f64 v[32:33], v[8:9], v[24:25]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX9-NEXT: v_max_f64 v[34:35], v[0:1], v[16:17]
+; GFX9-NEXT: v_max_f64 v[38:39], v[12:13], v[28:29]
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v33, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v32, 0, vcc
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX9-NEXT: v_max_f64 v[48:49], v[4:5], v[20:21]
+; GFX9-NEXT: v_max_f64 v[50:51], v[6:7], v[22:23]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v35, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v34, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX9-NEXT: v_max_f64 v[52:53], v[10:11], v[26:27]
+; GFX9-NEXT: v_max_f64 v[54:55], v[2:3], v[18:19]
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v39, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v38, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[20:21]
+; GFX9-NEXT: v_max_f64 v[20:21], v[0:1], v[8:9]
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cmp_u_f64_e64 s[0:1], v[14:15], v[30:31]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v49, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v48, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[22:23]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v51, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v50, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v53, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v52, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[18:19]
+; GFX9-NEXT: v_max_f64 v[18:19], v[4:5], v[12:13]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v55, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v54, 0, vcc
+; GFX9-NEXT: v_max_f64 v[16:17], v[2:3], v[10:11]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v19, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v18, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v21, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v20, 0, vcc
+; GFX9-NEXT: v_max_f64 v[8:9], v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_max_f64 v[4:5], v[14:15], v[30:31]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v36, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[0:1]
+; GFX9-NEXT: v_max_f64 v[10:11], v[6:7], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e64 s[0:1], v[6:7], v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v11, v36, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[0:1]
+; GFX9-NEXT: v_max_f64 v[6:7], v[2:3], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v36, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_max_f64 v[32:33], v[8:9], v[24:25]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[16:17]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[0:1], v[16:17]
+; GFX10-NEXT: v_max_f64 v[0:1], v[12:13], v[28:29]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[28:29]
+; GFX10-NEXT: v_max_f64 v[12:13], v[10:11], v[26:27]
+; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[10:11], v[26:27]
+; GFX10-NEXT: v_max_f64 v[10:11], v[2:3], v[18:19]
+; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[2:3], v[18:19]
+; GFX10-NEXT: v_max_f64 v[2:3], v[4:5], v[20:21]
+; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[4:5], v[20:21]
+; GFX10-NEXT: v_max_f64 v[4:5], v[6:7], v[22:23]
+; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[6:7], v[22:23]
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, 0, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, 0x7ff80000, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, 0, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, s9
+; GFX10-NEXT: v_max_f64 v[16:17], v[10:11], v[12:13]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[0:1]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_max_f64 v[6:7], v[14:15], v[30:31]
+; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v33, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v32, 0, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[12:13]
+; GFX10-NEXT: v_max_f64 v[10:11], v[2:3], v[0:1]
+; GFX10-NEXT: v_max_f64 v[0:1], v[8:9], v[14:15]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[8:9], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, 0, s10
+; GFX10-NEXT: v_max_f64 v[2:3], v[4:5], v[6:7]
+; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[4:5], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX10-NEXT: v_max_f64 v[8:9], v[0:1], v[6:7]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s6
+; GFX10-NEXT: v_max_f64 v[0:1], v[4:5], v[2:3]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[4:5], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s4
+; GFX10-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[31:32], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[6:7]
+; GFX11-NEXT: v_max_f64 v[32:33], v[8:9], v[24:25]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[16:17]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[0:1], v[16:17]
+; GFX11-NEXT: v_max_f64 v[0:1], v[12:13], v[28:29]
+; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[12:13], v[28:29]
+; GFX11-NEXT: v_max_f64 v[12:13], v[10:11], v[26:27]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[10:11], v[26:27]
+; GFX11-NEXT: v_max_f64 v[10:11], v[2:3], v[18:19]
+; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[2:3], v[18:19]
+; GFX11-NEXT: v_max_f64 v[2:3], v[4:5], v[20:21]
+; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[4:5], v[20:21]
+; GFX11-NEXT: v_max_f64 v[4:5], v[6:7], v[22:23]
+; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[6:7], v[22:23]
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, 0, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, 0x7ff80000, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, 0, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, s5
+; GFX11-NEXT: v_max_f64 v[16:17], v[10:11], v[12:13]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[0:1]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_max_f64 v[6:7], v[14:15], v[30:31]
+; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[30:31]
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v33, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v32, 0, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[12:13]
+; GFX11-NEXT: v_max_f64 v[10:11], v[2:3], v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_max_f64 v[0:1], v[8:9], v[14:15]
+; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[8:9], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, s6
+; GFX11-NEXT: v_max_f64 v[2:3], v[4:5], v[6:7]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[4:5], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v11, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_max_f64 v[8:9], v[0:1], v[6:7]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s2
+; GFX11-NEXT: v_max_f64 v[0:1], v[4:5], v[2:3]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[4:5], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX11-NEXT: v_max_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[16:17]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f64 v[2:3], v[0:1], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_vector_reduce_fmaximum_v16double:
; GFX1170: ; %bb.0: ; %entry
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[10:11]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[12:13]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-NEXT: v_maximum_f64 v[10:11], v[10:11], v[26:27]
+; GFX1170-NEXT: v_maximum_f64 v[2:3], v[2:3], v[18:19]
+; GFX1170-NEXT: v_maximum_f64 v[8:9], v[8:9], v[24:25]
+; GFX1170-NEXT: v_maximum_f64 v[12:13], v[12:13], v[28:29]
+; GFX1170-NEXT: v_maximum_f64 v[4:5], v[4:5], v[20:21]
; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[16:17]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[18:19]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[20:21]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[22:23]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[24:25]
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[26:27]
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[28:29]
+; GFX1170-NEXT: v_maximum_f64 v[6:7], v[6:7], v[22:23]
+; GFX1170-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[30:31]
+; GFX1170-NEXT: v_maximum_f64 v[14:15], v[14:15], v[30:31]
+; GFX1170-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-NEXT: v_maximum_f64 v[2:3], v[2:3], v[6:7]
+; GFX1170-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_vector_reduce_fmaximum_v16double:
@@ -2838,30 +2781,26 @@ define double @test_vector_reduce_fmaximum_v16double(<16 x double> %v) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[6:7]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[10:11]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[12:13]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[14:15]
+; GFX12-NEXT: v_maximum_f64 v[10:11], v[10:11], v[26:27]
+; GFX12-NEXT: v_maximum_f64 v[2:3], v[2:3], v[18:19]
+; GFX12-NEXT: v_maximum_f64 v[8:9], v[8:9], v[24:25]
+; GFX12-NEXT: v_maximum_f64 v[12:13], v[12:13], v[28:29]
+; GFX12-NEXT: v_maximum_f64 v[4:5], v[4:5], v[20:21]
; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[16:17]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[18:19]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[20:21]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[22:23]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[24:25]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[26:27]
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[28:29]
+; GFX12-NEXT: v_maximum_f64 v[6:7], v[6:7], v[22:23]
+; GFX12-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13]
+; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[30:31]
+; GFX12-NEXT: v_maximum_f64 v[14:15], v[14:15], v[30:31]
+; GFX12-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_maximum_f64 v[2:3], v[2:3], v[6:7]
+; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call double @llvm.vector.reduce.fmaximum.v16double(<16 x double> %v)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 2d9dc5bd56f24..4d0a25e516022 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -92,15 +92,17 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v2half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1170-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v2half:
@@ -132,7 +134,9 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
@@ -142,9 +146,9 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fminimum.v2half(<2 x half> %v)
@@ -332,39 +336,41 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
-; GFX7-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; GFX7-NEXT: v_min_f32_e32 v4, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v4, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000
+; GFX7-NEXT: v_min_f32_e32 v4, v2, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v3, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v4half:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX8-NEXT: v_min_f16_e32 v4, v0, v3
+; GFX8-NEXT: v_min_f16_e32 v4, v3, v2
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
; GFX8-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
; GFX8-NEXT: v_min_f16_e32 v1, v0, v2
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
@@ -374,69 +380,66 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX9-LABEL: test_vector_reduce_fminimum_v4half:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_f16_sdwa v2, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_pk_min_f16 v2, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
-; GFX9-NEXT: v_min_f16_e32 v2, v0, v1
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
-; GFX9-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v3, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_min_f16_e32 v1, v4, v0
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v4, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v4half:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_min_f16_sdwa v2, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v0 src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX10-NEXT: v_pk_min_f16 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x7e00
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v2, s4
; GFX10-NEXT: v_min_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v1 src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v3, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v3
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v1, v0, v3
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
@@ -459,19 +462,19 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v3, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
@@ -506,9 +509,10 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
@@ -518,11 +522,10 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v2
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v3, v1
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fminimum.v4half(<4 x half> %v)
@@ -534,83 +537,83 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5
; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_mov_b32_e32 v6, 0x7fc00000
-; GFX7-NEXT: v_min_f32_e32 v5, v0, v4
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v5, v0, v4
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v4, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v4, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v8, v4, v5
+; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v4, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v9, v8, vcc
+; GFX7-NEXT: v_min_f32_e32 v5, v6, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v6, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX7-NEXT: v_min_f32_e32 v6, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX7-NEXT: v_min_f32_e32 v2, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v2, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v5
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v4
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_min_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v3, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v8half:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX8-NEXT: v_min_f16_e32 v8, v0, v7
-; GFX8-NEXT: v_mov_b32_e32 v9, 0x7e00
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX8-NEXT: v_min_f16_e32 v7, v0, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_min_f16_e32 v6, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0x7e00
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX8-NEXT: v_min_f16_e32 v8, v6, v5
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v6, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc
+; GFX8-NEXT: v_min_f16_e32 v6, v1, v3
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc
+; GFX8-NEXT: v_min_f16_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc
+; GFX8-NEXT: v_min_f16_e32 v2, v5, v4
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX8-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v7, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v3, vcc
; GFX8-NEXT: v_min_f16_e32 v1, v0, v2
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v4
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v8half:
@@ -619,54 +622,57 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX9-NEXT: v_pk_min_f16 v4, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: s_mov_b32 s0, 0x5040100
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX9-NEXT: v_min_f16_e32 v2, v6, v0
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v0
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
-; GFX9-NEXT: v_pk_min_f16 v2, v1, v3
+; GFX9-NEXT: v_pk_min_f16 v4, v1, v3
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v2, vcc
-; GFX9-NEXT: v_min_f16_e32 v6, v0, v4
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
+; GFX9-NEXT: v_perm_b32 v2, v0, v6, s0
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc
; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_min_f16_e32 v2, v0, v1
+; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v3, v1, v7, s0
+; GFX9-NEXT: v_pk_min_f16 v2, v2, v3
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v7
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_min_f16_e32 v1, v3, v0
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v8half:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_pk_min_f16 v4, v0, v2
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v4, 0x7e00
+; GFX10-NEXT: v_pk_min_f16 v5, v0, v2
; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_pk_min_f16 v2, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
+; GFX10-NEXT: v_pk_min_f16 v6, v1, v3
+; GFX10-NEXT: v_cmp_o_f16_sdwa s4, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e64 s5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_min_f16_e32 v5, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
-; GFX10-NEXT: v_min_f16_e32 v4, v0, v6
-; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v6
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v6, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_perm_b32 v5, v2, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_sdwa v3, v4, v6, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
+; GFX10-NEXT: v_perm_b32 v6, v3, v1, 0x5040100
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v3
+; GFX10-NEXT: v_pk_min_f16 v5, v5, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v4, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_min_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
@@ -678,22 +684,21 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v0, v2
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v1, v3
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v0.h, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v1, v0
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
@@ -707,27 +712,29 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v7, v1, v3
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v5
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v4, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v10, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v5, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v4, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v3, v0, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v6
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9, v8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v3, v4, v0, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v5, v2, v1, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v3, v3, v5
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v2
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
@@ -759,30 +766,25 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v8half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.h, v2.l, v2.h, v1.h
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v3, v3, v5
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v6, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v1, v2, v7, v3
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v8half:
@@ -822,13 +824,13 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.h, v2.l, v2.h, v1.h
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
@@ -838,18 +840,13 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v4
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v3, v3, v5
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v6, v1
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v1, v2, v7, v3
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fminimum.v8half(<8 x half> %v)
@@ -860,285 +857,282 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v16half:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v12, v12
+; GFX7-NEXT: v_cvt_f32_f16_e32 v11, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v4
+; GFX7-NEXT: v_cvt_f32_f16_e32 v15, v15
+; GFX7-NEXT: v_cvt_f32_f16_e32 v10, v10
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v14, v14
+; GFX7-NEXT: v_cvt_f32_f16_e32 v9, v9
+; GFX7-NEXT: v_cvt_f32_f16_e32 v13, v13
; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v8
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_mov_b32_e32 v10, 0x7fc00000
-; GFX7-NEXT: v_min_f32_e32 v9, v0, v8
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v9, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v9, v0, v8
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v9, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v8, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v8, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v4
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX7-NEXT: v_min_f32_e32 v16, v11, v12
+; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v11, v12
+; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v17, v16, vcc
+; GFX7-NEXT: v_min_f32_e32 v12, v10, v15
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v10, v15
+; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v10, v17, v12, vcc
+; GFX7-NEXT: v_min_f32_e32 v12, v9, v14
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v9, v14
+; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v4
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v9, v17, v12, vcc
+; GFX7-NEXT: v_min_f32_e32 v12, v8, v13
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v8, v13
+; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v8, v17, v12, vcc
+; GFX7-NEXT: v_min_f32_e32 v12, v1, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v12, vcc
+; GFX7-NEXT: v_min_f32_e32 v5, v3, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v5, vcc
+; GFX7-NEXT: v_min_f32_e32 v5, v0, v4
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX7-NEXT: v_cvt_f16_f32_e32 v9, v9
+; GFX7-NEXT: v_cvt_f16_f32_e32 v8, v8
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v5, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v2, v6
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX7-NEXT: v_cvt_f16_f32_e32 v11, v11
+; GFX7-NEXT: v_cvt_f16_f32_e32 v10, v10
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v4, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v5
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX7-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v8
+; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v9
+; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v10
+; GFX7-NEXT: v_cvt_f32_f16_e32 v8, v11
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v6
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v7, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v7, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v17, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v5, v8, v6
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v8, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc
+; GFX7-NEXT: v_min_f32_e32 v6, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX7-NEXT: v_min_f32_e32 v2, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cvt_f16_f32_e32 v4, v4
+; GFX7-NEXT: v_cvt_f16_f32_e32 v5, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v5
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v4
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v7
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_min_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v3, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v10, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v16half:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v0
-; GFX8-NEXT: v_min_f16_e32 v16, v0, v15
-; GFX8-NEXT: v_mov_b32_e32 v17, 0x7e00
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX8-NEXT: v_min_f16_e32 v15, v0, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX8-NEXT: v_min_f16_e32 v10, v9, v8
+; GFX8-NEXT: v_mov_b32_e32 v11, 0x7e00
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v9, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v10, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v0
+; GFX8-NEXT: v_min_f16_e32 v12, v10, v9
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v10, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v3
+; GFX8-NEXT: v_min_f16_e32 v13, v12, v10
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v12, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; GFX8-NEXT: v_min_f16_e32 v14, v13, v12
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v13, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v14, vcc
+; GFX8-NEXT: v_min_f16_e32 v13, v2, v6
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v2, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v13, vcc
+; GFX8-NEXT: v_min_f16_e32 v6, v0, v4
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v6, vcc
+; GFX8-NEXT: v_min_f16_e32 v4, v3, v7
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v3, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc
+; GFX8-NEXT: v_min_f16_e32 v4, v1, v5
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v4, vcc
+; GFX8-NEXT: v_min_f16_e32 v4, v12, v10
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v12, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc
+; GFX8-NEXT: v_min_f16_e32 v5, v9, v8
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v9, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
+; GFX8-NEXT: v_min_f16_e32 v6, v1, v3
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v11, v6, vcc
+; GFX8-NEXT: v_min_f16_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v3, vcc
+; GFX8-NEXT: v_min_f16_e32 v2, v5, v4
+; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v5, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc
+; GFX8-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v14
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v14
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v3, vcc
; GFX8-NEXT: v_min_f16_e32 v1, v0, v2
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v13
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v13
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v12
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v12
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v4
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v11
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v11
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v10
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v10
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v6
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v9
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v9
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v7
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v7
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f16_e32 v1, v0, v8
-; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v11, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v16half:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_f16 v8, v2, v6
+; GFX9-NEXT: v_pk_min_f16 v8, v1, v5
; GFX9-NEXT: v_mov_b32_e32 v9, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5
; GFX9-NEXT: s_mov_b32 s0, 0x5040100
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
; GFX9-NEXT: v_pk_min_f16 v8, v0, v4
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
-; GFX9-NEXT: v_perm_b32 v6, v2, v10, s0
+; GFX9-NEXT: v_perm_b32 v5, v1, v10, s0
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v9, v8, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_pk_min_f16 v8, v3, v7
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7
; GFX9-NEXT: v_perm_b32 v4, v0, v11, s0
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_pk_min_f16 v7, v2, v6
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_sdwa v3, v9, v8, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v2, v6
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v7, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_sdwa v2, v9, v7, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v6, v2, v8, s0
; GFX9-NEXT: v_pk_min_f16 v4, v4, v6
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v11, v10
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v11, v8
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v4, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v4, vcc
-; GFX9-NEXT: v_min_f16_e32 v2, v6, v0
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v0
-; GFX9-NEXT: v_pk_min_f16 v6, v1, v5
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
-; GFX9-NEXT: v_pk_min_f16 v2, v3, v7
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v7
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v5
-; GFX9-NEXT: v_perm_b32 v3, v2, v4, s0
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v9, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v4, v3, v12, s0
+; GFX9-NEXT: v_pk_min_f16 v4, v5, v4
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v10, v12
+; GFX9-NEXT: v_perm_b32 v2, v0, v6, s0
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v6, vcc
-; GFX9-NEXT: v_perm_b32 v5, v1, v7, s0
-; GFX9-NEXT: v_pk_min_f16 v3, v5, v3
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v7, v4
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v3, vcc
-; GFX9-NEXT: v_min_f16_e32 v5, v0, v4
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v4, vcc
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v5, vcc
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v2
+; GFX9-NEXT: v_cndmask_b32_sdwa v1, v9, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_perm_b32 v3, v1, v5, s0
+; GFX9-NEXT: v_pk_min_f16 v2, v2, v3
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v6, v5
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_sdwa v1, v9, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_min_f16_e32 v2, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v2, vcc
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v9, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_min_f16_e32 v1, v3, v0
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v3, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v16half:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_pk_min_f16 v8, v2, v6
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
-; GFX10-NEXT: v_pk_min_f16 v9, v0, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v8, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v10, vcc_lo
+; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_pk_min_f16 v8, v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v9, 0x7e00
+; GFX10-NEXT: v_pk_min_f16 v10, v0, v4
+; GFX10-NEXT: v_cmp_o_f16_sdwa s4, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_sdwa s5, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_pk_min_f16 v12, v2, v6
+; GFX10-NEXT: v_cndmask_b32_sdwa v11, v9, v8, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v9, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v4 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_pk_min_f16 v9, v3, v7
-; GFX10-NEXT: v_perm_b32 v4, v2, v8, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v11, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v9
-; GFX10-NEXT: v_pk_min_f16 v11, v1, v5
-; GFX10-NEXT: v_perm_b32 v10, v0, v6, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v9, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v3, v7 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_pk_min_f16 v4, v10, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v10, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cmp_o_f16_sdwa s4, v2, v6 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-NEXT: v_cndmask_b32_sdwa v4, v9, v10, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_pk_min_f16 v10, v3, v7
+; GFX10-NEXT: s_mov_b32 vcc_lo, s5
+; GFX10-NEXT: v_cndmask_b32_sdwa v13, v9, v10, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v12, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v6, v9, v12, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7e00, v11, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v1, v5 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v10, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v6, v8
-; GFX10-NEXT: v_perm_b32 v6, v3, v9, 0x5040100
-; GFX10-NEXT: v_perm_b32 v8, v1, v7, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v4, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_pk_min_f16 v2, v8, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v7, v9
-; GFX10-NEXT: v_min_f16_e32 v5, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
+; GFX10-NEXT: v_perm_b32 v5, v4, v0, 0x5040100
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
+; GFX10-NEXT: v_perm_b32 v8, v6, v2, 0x5040100
+; GFX10-NEXT: v_perm_b32 v7, v11, v1, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v10, vcc_lo
+; GFX10-NEXT: v_pk_min_f16 v5, v5, v8
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v6
+; GFX10-NEXT: v_perm_b32 v8, v13, v3, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v5, s4
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v11, v13
+; GFX10-NEXT: v_cndmask_b32_sdwa v4, v9, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_mov_b32_e32 v1, 0x7e00
-; GFX10-NEXT: v_min_f16_e32 v4, v0, v6
-; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v6
-; GFX10-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v4, s4
+; GFX10-NEXT: v_pk_min_f16 v2, v7, v8
+; GFX10-NEXT: v_perm_b32 v3, v4, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v2, vcc_lo
+; GFX10-NEXT: s_mov_b32 vcc_lo, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v2, v9, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX10-NEXT: v_cmp_o_f16_e64 s4, v0, v1
+; GFX10-NEXT: v_perm_b32 v5, v2, v1, 0x5040100
+; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v2
+; GFX10-NEXT: v_pk_min_f16 v3, v3, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0x7e00, v3, s4
+; GFX10-NEXT: v_cndmask_b32_sdwa v1, v9, v3, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX10-NEXT: v_min_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
@@ -1147,116 +1141,117 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v8, v2, v6
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v6.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v0, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.h, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v8, v1, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v9, v0, v4
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v2, v6
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.h, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v7.l
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v2.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v2.h, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v3.h, v7.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v1.h, v5.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v2, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v5.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v9.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v9.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.h, v6.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v3.l, v7.l
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v3, v7
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v3, v1, v5
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v2.l, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v2.h, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v3.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v3.h, s3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v3.h, v7.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v4.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v2.l, s2
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v2.h, s3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v1, v0, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.h, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v3, v2, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v1.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.h, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v1.h, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v8, v2, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v8, v1, v5
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v10, v0, v4
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v9, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v10
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v8, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v5, v3, v7
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v8, v2, v6
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v5
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v10, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v12, v11
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v12, v1, v5
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v6, v2, v9, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v10, v3, v7
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v8
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v13, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v12
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v8, v4, v0, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v6, v8, v6
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v8, 0x7e00, v10, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v2, v6
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v8, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v10, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v12, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v14, v13
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v13, v12
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7e00, v14, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v7
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v7, v4, v0, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v11, v10
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v10, v1, v9, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7e00, v15, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v9
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v6, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v2
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v4, v3, v8, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v6, v5, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v11, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v4, v6, v4
-; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v7, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v8, v6, v2, 0x5040100
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v11, v5, v3, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v7, v7, v8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v8, v10, v11
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v7, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v8
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v2, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v6
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v10, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9, v3
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v8, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v5
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v2, v4, v0, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v5, v1, v3, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_pk_min_f16 v2, v2, v5
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v5, v3
-; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7e00, v5, vcc_lo
; GFX11-SDAG-FAKE16-NEXT: v_min_f16_e32 v2, v0, v1
; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1266,11 +1261,11 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v3, v3, v7
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v5
-; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v4
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v3
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1281,11 +1276,11 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
; GFX1170-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX1170-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX1170-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v3, v3, v7
; GFX1170-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v5
-; GFX1170-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX1170-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v4
-; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1170-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v3
; GFX1170-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX1170-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1298,44 +1293,35 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX1170-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v5.l, v5.l, v5.h
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v5.h, v7.l, v7.h
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.h, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v3.l, v4.l, v4.h, v5.l
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v3.h, v6.l, v6.h, v5.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.h, v2.l, v2.h, v1.h
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v3.l, v3.h
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v4
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v5
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v2, v2, v6
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v3, v3, v7
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
; GFX1170-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX1170-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v4
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v5, v5, v10
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v7, v7, v11
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX1170-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v9
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v3, v3, v12
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v4, v4, v13, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v5, v6, v14, v7
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v8, v1
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v1, v2, v10, v3
-; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum_f16 v2, v4, v5
-; GFX1170-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v1, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v4
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v5
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v2, v2, v6
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v3, v3, v7
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX1170-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
+; GFX1170-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX1170-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
@@ -1345,11 +1331,11 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v3, v3, v7
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v5
-; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v3
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1364,11 +1350,11 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v3, v3, v7
; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v5
-; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v2, v2, v6
; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v4
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v3
; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1385,19 +1371,18 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v5.l, v5.l, v5.h
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v5.h, v7.l, v7.h
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.h, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v3.l, v4.l, v4.h, v5.l
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v3.h, v6.l, v6.h, v5.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.h, v2.l, v2.h, v1.h
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v3.l, v3.h
-; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v4
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v5
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v2, v2, v6
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v3, v3, v7
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
@@ -1407,26 +1392,18 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX12-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v4
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v5, v5, v10
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v7, v7, v11
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v1, v1, v9
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v3, v3, v12
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v4, v4, v13, v5
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v5, v6, v14, v7
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v8, v1
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v1, v2, v10, v3
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-FAKE16-NEXT: v_minimum_f16 v2, v4, v5
-; GFX12-GISEL-FAKE16-NEXT: v_minimum3_f16 v0, v0, v1, v2
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v5
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v2, v2, v6
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v3, v3, v7
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT: v_alignbit_b32 v1, s0, v0, 16
+; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call half @llvm.vector.reduce.fminimum.v16half(<16 x half> %v)
@@ -1586,96 +1563,94 @@ define float @test_vector_reduce_fminimum_v4float(<4 x float> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v4float:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_min_f32_e32 v4, v0, v1
+; GFX7-NEXT: v_min_f32_e32 v4, v1, v3
; GFX7-NEXT: v_mov_b32_e32 v5, 0x7fc00000
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v3, v0, v2
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v4float:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_f32_e32 v4, v0, v1
+; GFX8-NEXT: v_min_f32_e32 v4, v1, v3
; GFX8-NEXT: v_mov_b32_e32 v5, 0x7fc00000
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
+; GFX8-NEXT: v_min_f32_e32 v3, v0, v2
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX8-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v4float:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_f32_e32 v4, v0, v1
+; GFX9-NEXT: v_min_f32_e32 v4, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v5, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX9-NEXT: v_min_f32_e32 v3, v0, v2
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
+; GFX9-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v4float:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_min_f32_e32 v4, v0, v1
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX10-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX10-NEXT: v_min_f32_e32 v5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX10-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v4float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f32_e32 v4, v0, v1
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX11-NEXT: v_dual_min_f32 v4, v1, v3 :: v_dual_min_f32 v5, v0, v2
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fminimum_v4float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_minimum_f32 v0, v0, v1
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v1
; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v3
+; GFX1170-SDAG-NEXT: v_minimum_f32 v0, v0, v3
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fminimum_v4float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_minimum_f32 v2, v2, v3
+; GFX1170-GISEL-NEXT: v_minimum_f32 v1, v1, v3
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v2, v1
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v4float:
@@ -1685,9 +1660,9 @@ define float @test_vector_reduce_fminimum_v4float(<4 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_minimum_f32 v0, v0, v1
+; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v1
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v3
+; GFX12-SDAG-NEXT: v_minimum_f32 v0, v0, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v4float:
@@ -1697,9 +1672,9 @@ define float @test_vector_reduce_fminimum_v4float(<4 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_minimum_f32 v2, v2, v3
+; GFX12-GISEL-NEXT: v_minimum_f32 v1, v1, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
+; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fminimum.v4float(<4 x float> %v)
@@ -1710,169 +1685,164 @@ define float @test_vector_reduce_fminimum_v8float(<8 x float> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v8float:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_min_f32_e32 v8, v0, v1
+; GFX7-NEXT: v_min_f32_e32 v8, v2, v6
; GFX7-NEXT: v_mov_b32_e32 v9, 0x7fc00000
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v4
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
+; GFX7-NEXT: v_min_f32_e32 v6, v0, v4
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v3, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v1, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v3, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v8float:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_f32_e32 v8, v0, v1
+; GFX8-NEXT: v_min_f32_e32 v8, v2, v6
; GFX8-NEXT: v_mov_b32_e32 v9, 0x7fc00000
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v4
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
+; GFX8-NEXT: v_min_f32_e32 v6, v0, v4
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX8-NEXT: v_min_f32_e32 v4, v3, v7
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc
+; GFX8-NEXT: v_min_f32_e32 v4, v1, v5
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX8-NEXT: v_min_f32_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX8-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v8float:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_f32_e32 v8, v0, v1
+; GFX9-NEXT: v_min_f32_e32 v8, v2, v6
; GFX9-NEXT: v_mov_b32_e32 v9, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v4
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX9-NEXT: v_min_f32_e32 v6, v0, v4
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v8, vcc
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX9-NEXT: v_min_f32_e32 v4, v3, v7
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc
+; GFX9-NEXT: v_min_f32_e32 v4, v1, v5
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX9-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX9-NEXT: v_min_f32_e32 v3, v0, v2
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v3, vcc
+; GFX9-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v8float:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_min_f32_e32 v8, v0, v1
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_min_f32_e32 v8, v2, v6
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX10-NEXT: v_min_f32_e32 v9, v3, v7
+; GFX10-NEXT: v_min_f32_e32 v6, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX10-NEXT: v_min_f32_e32 v8, v0, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX10-NEXT: v_min_f32_e32 v4, v1, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX10-NEXT: v_min_f32_e32 v5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v4
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX10-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v8float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f32_e32 v8, v0, v1
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_min_f32 v8, v2, v6 :: v_dual_min_f32 v9, v3, v7
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_min_f32_e32 v6, v1, v5
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_min_f32 v8, v0, v4 :: v_dual_cndmask_b32 v1, 0x7fc00000, v6
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v2
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: v_min_f32_e32 v5, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v4
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fminimum_v8float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_minimum_f32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v3
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v5
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v6, v7
+; GFX1170-SDAG-NEXT: v_minimum_f32 v2, v2, v6
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v1, v1, v5, v3
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v2
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v1, v7
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fminimum_v8float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_minimum_f32 v2, v2, v3
-; GFX1170-GISEL-NEXT: v_minimum_f32 v3, v6, v7
+; GFX1170-GISEL-NEXT: v_minimum_f32 v2, v2, v6
+; GFX1170-GISEL-NEXT: v_minimum_f32 v3, v3, v7
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v1, v4, v5, v3
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v4, v2
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v1, v1, v5, v3
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_minimum_f32 v0, v0, v1
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1884,12 +1854,11 @@ define float @test_vector_reduce_fminimum_v8float(<8 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_minimum_f32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v3
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v5
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v6, v7
+; GFX12-SDAG-NEXT: v_minimum_f32 v2, v2, v6
+; GFX12-SDAG-NEXT: v_minimum3_f32 v1, v1, v5, v3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v2
+; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v1, v7
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v8float:
@@ -1899,11 +1868,11 @@ define float @test_vector_reduce_fminimum_v8float(<8 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_minimum_f32 v2, v2, v3
-; GFX12-GISEL-NEXT: v_minimum_f32 v3, v6, v7
+; GFX12-GISEL-NEXT: v_minimum_f32 v2, v2, v6
+; GFX12-GISEL-NEXT: v_minimum_f32 v3, v3, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: v_minimum3_f32 v1, v4, v5, v3
+; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v4, v2
+; GFX12-GISEL-NEXT: v_minimum3_f32 v1, v1, v5, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_minimum_f32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1916,319 +1885,306 @@ define float @test_vector_reduce_fminimum_v16float(<16 x float> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v16float:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_min_f32_e32 v16, v0, v1
+; GFX7-NEXT: v_min_f32_e32 v16, v5, v13
; GFX7-NEXT: v_mov_b32_e32 v17, 0x7fc00000
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v4
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v8
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v5, v13
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc
+; GFX7-NEXT: v_min_f32_e32 v13, v1, v9
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v9
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v13, vcc
+; GFX7-NEXT: v_min_f32_e32 v9, v7, v15
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v7, v15
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v17, v9, vcc
+; GFX7-NEXT: v_min_f32_e32 v9, v3, v11
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v11
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v9, vcc
+; GFX7-NEXT: v_min_f32_e32 v9, v4, v12
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v4, v12
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v17, v9, vcc
+; GFX7-NEXT: v_min_f32_e32 v9, v0, v8
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v9
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v9
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v10
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v10
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v11
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v11
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v12
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v12
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v13
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v13
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v14
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v14
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX7-NEXT: v_min_f32_e32 v1, v0, v15
-; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v15
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc
+; GFX7-NEXT: v_min_f32_e32 v8, v6, v14
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v6, v14
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v17, v8, vcc
+; GFX7-NEXT: v_min_f32_e32 v8, v2, v10
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v10
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX7-NEXT: v_min_f32_e32 v8, v2, v6
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX7-NEXT: v_min_f32_e32 v6, v0, v4
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v3, v7
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v1, v5
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX7-NEXT: v_min_f32_e32 v3, v0, v2
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX7-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v16float:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_f32_e32 v16, v0, v1
+; GFX8-NEXT: v_min_f32_e32 v16, v5, v13
; GFX8-NEXT: v_mov_b32_e32 v17, 0x7fc00000
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v4
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v8
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v5, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc
+; GFX8-NEXT: v_min_f32_e32 v13, v1, v9
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v13, vcc
+; GFX8-NEXT: v_min_f32_e32 v9, v7, v15
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v7, v15
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v17, v9, vcc
+; GFX8-NEXT: v_min_f32_e32 v9, v3, v11
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v3, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v9, vcc
+; GFX8-NEXT: v_min_f32_e32 v9, v4, v12
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v4, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v17, v9, vcc
+; GFX8-NEXT: v_min_f32_e32 v9, v0, v8
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v9
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v9
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v10
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v10
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v11
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v11
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v12
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v12
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v13
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v13
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v14
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v14
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_min_f32_e32 v1, v0, v15
-; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc
+; GFX8-NEXT: v_min_f32_e32 v8, v6, v14
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v6, v14
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v17, v8, vcc
+; GFX8-NEXT: v_min_f32_e32 v8, v2, v10
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v2, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX8-NEXT: v_min_f32_e32 v8, v2, v6
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX8-NEXT: v_min_f32_e32 v6, v0, v4
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX8-NEXT: v_min_f32_e32 v4, v3, v7
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc
+; GFX8-NEXT: v_min_f32_e32 v4, v1, v5
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX8-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX8-NEXT: v_min_f32_e32 v3, v0, v2
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX8-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v16float:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_f32_e32 v16, v0, v1
+; GFX9-NEXT: v_min_f32_e32 v16, v5, v13
; GFX9-NEXT: v_mov_b32_e32 v17, 0x7fc00000
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v16, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v3
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v4
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v5
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v5, v13
+; GFX9-NEXT: v_min_f32_e32 v13, v1, v9
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v9
+; GFX9-NEXT: v_min_f32_e32 v9, v7, v15
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v13, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v7, v15
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v9, vcc
+; GFX9-NEXT: v_min_f32_e32 v9, v3, v11
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v11
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v9, vcc
+; GFX9-NEXT: v_min_f32_e32 v9, v4, v12
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v4, v12
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v9, vcc
+; GFX9-NEXT: v_min_f32_e32 v9, v0, v8
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v8
+; GFX9-NEXT: v_min_f32_e32 v8, v6, v14
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v9, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v6, v14
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v9
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v9
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v10
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v10
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v11
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v8, vcc
+; GFX9-NEXT: v_min_f32_e32 v8, v2, v10
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v10
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v12
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v12
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX9-NEXT: v_min_f32_e32 v8, v2, v6
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v6
+; GFX9-NEXT: v_min_f32_e32 v6, v0, v4
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v8, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v4
+; GFX9-NEXT: v_min_f32_e32 v4, v3, v7
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v6, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v7
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v13
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v13
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc
+; GFX9-NEXT: v_min_f32_e32 v4, v1, v5
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v5
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v14
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v14
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX9-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v3
+; GFX9-NEXT: v_min_f32_e32 v3, v0, v2
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_min_f32_e32 v1, v0, v15
-; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v15
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v3, vcc
+; GFX9-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v16float:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_min_f32_e32 v16, v0, v1
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v16, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v4
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v8
+; GFX10-NEXT: v_min_f32_e32 v16, v5, v13
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v13
+; GFX10-NEXT: v_min_f32_e32 v17, v1, v9
+; GFX10-NEXT: v_min_f32_e32 v18, v7, v15
+; GFX10-NEXT: v_min_f32_e32 v13, v3, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v5, 0x7fc00000, v16, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v9
+; GFX10-NEXT: v_min_f32_e32 v9, v6, v14
+; GFX10-NEXT: v_min_f32_e32 v16, v4, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v7, v15
+; GFX10-NEXT: v_min_f32_e32 v15, v2, v10
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0x7fc00000, v18, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v14
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v10
+; GFX10-NEXT: v_min_f32_e32 v9, v0, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v15, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v11
+; GFX10-NEXT: v_min_f32_e32 v10, v2, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v13, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v4, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v4, 0x7fc00000, v16, vcc_lo
; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v9
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v10
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v10
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v11
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v12
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v12
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v13
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v13
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v14
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v14
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX10-NEXT: v_min_f32_e32 v1, v0, v15
-; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v15
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX10-NEXT: v_min_f32_e32 v8, v3, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX10-NEXT: v_min_f32_e32 v6, v1, v5
+; GFX10-NEXT: v_min_f32_e32 v9, v0, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v8, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX10-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX10-NEXT: v_min_f32_e32 v5, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX10-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v16float:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f32_e32 v16, v0, v1
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v16, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v2
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v3
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v4
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v5
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v6
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v7
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v8
+; GFX11-NEXT: v_dual_min_f32 v17, v1, v9 :: v_dual_min_f32 v18, v7, v15
+; GFX11-NEXT: v_min_f32_e32 v16, v5, v13
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, 0x7fc00000, v16, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v9
+; GFX11-NEXT: v_dual_min_f32 v16, v4, v12 :: v_dual_min_f32 v13, v3, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v17, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v7, v15
+; GFX11-NEXT: v_min_f32_e32 v15, v2, v10
+; GFX11-NEXT: v_min_f32_e32 v9, v6, v14
+; GFX11-NEXT: v_cndmask_b32_e32 v7, 0x7fc00000, v18, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v6, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v6, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v15, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v11
+; GFX11-NEXT: v_dual_min_f32 v10, v2, v6 :: v_dual_cndmask_b32 v3, 0x7fc00000, v13
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v4, v12
+; GFX11-NEXT: v_min_f32_e32 v9, v0, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v4, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v9
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v10
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v11
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v12
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v13
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v14
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX11-NEXT: v_min_f32_e32 v1, v0, v15
-; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v15
+; GFX11-NEXT: v_min_f32_e32 v8, v3, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v2, v6
+; GFX11-NEXT: v_dual_min_f32 v9, v0, v4 :: v_dual_cndmask_b32 v2, 0x7fc00000, v10
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v7
+; GFX11-NEXT: v_dual_min_f32 v6, v1, v5 :: v_dual_cndmask_b32 v3, 0x7fc00000, v8
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v6, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT: v_min_f32_e32 v4, v1, v3
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_min_f32_e32 v5, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v5, vcc_lo
+; GFX11-NEXT: v_min_f32_e32 v2, v0, v1
+; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fminimum_v16float:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_minimum_f32 v0, v0, v1
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v3
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v5
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v6, v7
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v8, v9
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v10, v11
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v12, v13
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v14, v15
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v2, v2, v10, v6
+; GFX1170-SDAG-NEXT: v_minimum_f32 v4, v4, v12
+; GFX1170-SDAG-NEXT: v_minimum_f32 v0, v0, v8
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v3, v3, v11, v7
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v1, v1, v9, v5
+; GFX1170-SDAG-NEXT: v_minimum_f32 v2, v2, v14
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1170-SDAG-NEXT: v_minimum_f32 v3, v3, v15
+; GFX1170-SDAG-NEXT: v_minimum_f32 v1, v1, v13
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v2
+; GFX1170-SDAG-NEXT: v_minimum3_f32 v0, v0, v1, v3
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fminimum_v16float:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_minimum_f32 v10, v10, v11
-; GFX1170-GISEL-NEXT: v_minimum_f32 v11, v14, v15
-; GFX1170-GISEL-NEXT: v_minimum_f32 v2, v2, v3
-; GFX1170-GISEL-NEXT: v_minimum_f32 v3, v6, v7
+; GFX1170-GISEL-NEXT: v_minimum_f32 v5, v5, v13
+; GFX1170-GISEL-NEXT: v_minimum_f32 v7, v7, v15
+; GFX1170-GISEL-NEXT: v_minimum_f32 v4, v4, v12
+; GFX1170-GISEL-NEXT: v_minimum_f32 v6, v6, v14
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v6, v8, v9, v10
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v7, v12, v13, v11
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v1, v1, v9, v5
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v3, v3, v11, v7
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v1, v4, v5, v3
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v8, v4
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v2, v2, v10, v6
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_minimum_f32 v2, v6, v7
-; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
+; GFX1170-GISEL-NEXT: v_minimum_f32 v1, v1, v3
+; GFX1170-GISEL-NEXT: v_minimum3_f32 v0, v0, v2, v1
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v16float:
@@ -2238,18 +2194,18 @@ define float @test_vector_reduce_fminimum_v16float(<16 x float> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_minimum_f32 v0, v0, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v2, v3
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v5
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v6, v7
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v8, v9
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v10, v11
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v12, v13
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v14, v15
+; GFX12-SDAG-NEXT: v_minimum3_f32 v2, v2, v10, v6
+; GFX12-SDAG-NEXT: v_minimum_f32 v4, v4, v12
+; GFX12-SDAG-NEXT: v_minimum_f32 v0, v0, v8
+; GFX12-SDAG-NEXT: v_minimum3_f32 v3, v3, v11, v7
+; GFX12-SDAG-NEXT: v_minimum3_f32 v1, v1, v9, v5
+; GFX12-SDAG-NEXT: v_minimum_f32 v2, v2, v14
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_minimum_f32 v3, v3, v15
+; GFX12-SDAG-NEXT: v_minimum_f32 v1, v1, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v4, v2
+; GFX12-SDAG-NEXT: v_minimum3_f32 v0, v0, v1, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v16float:
@@ -2259,19 +2215,19 @@ define float @test_vector_reduce_fminimum_v16float(<16 x float> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_minimum_f32 v10, v10, v11
-; GFX12-GISEL-NEXT: v_minimum_f32 v11, v14, v15
-; GFX12-GISEL-NEXT: v_minimum_f32 v2, v2, v3
-; GFX12-GISEL-NEXT: v_minimum_f32 v3, v6, v7
+; GFX12-GISEL-NEXT: v_minimum_f32 v5, v5, v13
+; GFX12-GISEL-NEXT: v_minimum_f32 v7, v7, v15
+; GFX12-GISEL-NEXT: v_minimum_f32 v4, v4, v12
+; GFX12-GISEL-NEXT: v_minimum_f32 v6, v6, v14
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_minimum3_f32 v6, v8, v9, v10
-; GFX12-GISEL-NEXT: v_minimum3_f32 v7, v12, v13, v11
+; GFX12-GISEL-NEXT: v_minimum3_f32 v1, v1, v9, v5
+; GFX12-GISEL-NEXT: v_minimum3_f32 v3, v3, v11, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
-; GFX12-GISEL-NEXT: v_minimum3_f32 v1, v4, v5, v3
+; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v8, v4
+; GFX12-GISEL-NEXT: v_minimum3_f32 v2, v2, v10, v6
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_minimum_f32 v2, v6, v7
-; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v1, v2
+; GFX12-GISEL-NEXT: v_minimum_f32 v1, v1, v3
+; GFX12-GISEL-NEXT: v_minimum3_f32 v0, v0, v2, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%res = call float @llvm.vector.reduce.fminimum.v16float(<16 x float> %v)
@@ -2452,112 +2408,111 @@ define double @test_vector_reduce_fminimum_v4double(<4 x double> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v4double:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_min_f64 v[8:9], v[2:3], v[6:7]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
; GFX7-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX7-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v10, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v4double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_min_f64 v[8:9], v[2:3], v[6:7]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
; GFX8-NEXT: v_mov_b32_e32 v10, 0x7ff80000
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
+; GFX8-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v10, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v4double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
+; GFX9-NEXT: v_min_f64 v[8:9], v[2:3], v[6:7]
; GFX9-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[4:5]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v10, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v4double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_min_f64 v[8:9], v[2:3], v[6:7]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[0:1], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s4
+; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v4double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_min_f64 v[8:9], v[2:3], v[6:7]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[6:7]
+; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[0:1], v[4:5]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fminimum_v4double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[6:7]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fminimum_v4double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2569,10 +2524,10 @@ define double @test_vector_reduce_fminimum_v4double(<4 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[6:7]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v4double:
@@ -2582,8 +2537,8 @@ define double @test_vector_reduce_fminimum_v4double(<4 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2596,213 +2551,206 @@ define double @test_vector_reduce_fminimum_v8double(<8 x double> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v8double:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_min_f64 v[16:17], v[4:5], v[12:13]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[8:9]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[8:9]
+; GFX7-NEXT: v_min_f64 v[0:1], v[6:7], v[14:15]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[14:15]
+; GFX7-NEXT: v_min_f64 v[6:7], v[2:3], v[10:11]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[2:3], v[10:11]
; GFX7-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v18, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v18, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX7-NEXT: v_min_f64 v[8:9], v[6:7], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[0:1]
+; GFX7-NEXT: v_min_f64 v[0:1], v[4:5], v[2:3]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[2:3]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v8double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_min_f64 v[16:17], v[4:5], v[12:13]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[8:9]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[8:9]
+; GFX8-NEXT: v_min_f64 v[0:1], v[6:7], v[14:15]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[6:7], v[14:15]
+; GFX8-NEXT: v_min_f64 v[6:7], v[2:3], v[10:11]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[2:3], v[10:11]
; GFX8-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v18, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v18, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[8:9]
+; GFX8-NEXT: v_min_f64 v[8:9], v[6:7], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[0:1]
+; GFX8-NEXT: v_min_f64 v[0:1], v[4:5], v[2:3]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[4:5], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[4:5]
+; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v8double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
+; GFX9-NEXT: v_min_f64 v[16:17], v[4:5], v[12:13]
; GFX9-NEXT: v_mov_b32_e32 v18, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
+; GFX9-NEXT: v_min_f64 v[12:13], v[0:1], v[8:9]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
+; GFX9-NEXT: v_min_f64 v[8:9], v[6:7], v[14:15]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v13, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v12, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[14:15]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, 0, vcc
+; GFX9-NEXT: v_min_f64 v[8:9], v[2:3], v[10:11]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX9-NEXT: v_min_f64 v[8:9], v[2:3], v[6:7]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[6:7]
+; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[4:5]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
+; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v8double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX10-NEXT: v_min_f64 v[16:17], v[4:5], v[12:13]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-NEXT: v_min_f64 v[4:5], v[6:7], v[14:15]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[6:7], v[14:15]
+; GFX10-NEXT: v_min_f64 v[6:7], v[2:3], v[10:11]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[2:3], v[10:11]
+; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
+; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[0:1], v[8:9]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, 0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s6
+; GFX10-NEXT: v_min_f64 v[8:9], v[6:7], v[4:5]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[4:5]
+; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, s4
+; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v8double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f64 v[16:17], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_min_f64 v[16:17], v[4:5], v[12:13]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_min_f64 v[4:5], v[6:7], v[14:15]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[6:7], v[14:15]
+; GFX11-NEXT: v_min_f64 v[6:7], v[2:3], v[10:11]
+; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[2:3], v[10:11]
+; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[0:1], v[8:9]
; GFX11-NEXT: v_cndmask_b32_e64 v1, v17, 0x7ff80000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_min_f64 v[8:9], v[6:7], v[4:5]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[4:5]
+; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fminimum_v8double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[10:11]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[12:13]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fminimum_v8double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[4:5], v[8:9], v[10:11]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[6:7], v[12:13], v[14:15]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2814,16 +2762,15 @@ define double @test_vector_reduce_fminimum_v8double(<8 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[6:7]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[10:11]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[12:13]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[14:15]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v8double:
@@ -2833,13 +2780,13 @@ define double @test_vector_reduce_fminimum_v8double(<8 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], v[8:9], v[10:11]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], v[12:13], v[14:15]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2852,428 +2799,401 @@ define double @test_vector_reduce_fminimum_v16double(<16 x double> %v) {
; GFX7-LABEL: test_vector_reduce_fminimum_v16double:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX7-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX7-NEXT: v_min_f64 v[32:33], v[8:9], v[24:25]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX7-NEXT: v_min_f64 v[8:9], v[0:1], v[16:17]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[16:17]
+; GFX7-NEXT: v_min_f64 v[0:1], v[12:13], v[28:29]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[12:13], v[28:29]
+; GFX7-NEXT: v_min_f64 v[12:13], v[10:11], v[26:27]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[10:11], v[26:27]
+; GFX7-NEXT: v_min_f64 v[10:11], v[2:3], v[18:19]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[10:11], v[2:3], v[18:19]
+; GFX7-NEXT: v_mov_b32_e32 v34, 0x7ff80000
+; GFX7-NEXT: v_min_f64 v[2:3], v[4:5], v[20:21]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[12:13], v[4:5], v[20:21]
+; GFX7-NEXT: v_min_f64 v[4:5], v[6:7], v[22:23]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[14:15], v[6:7], v[22:23]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v13, v34, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v34, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v12, v32, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[4:5]
+; GFX7-NEXT: v_min_f64 v[16:17], v[10:11], v[6:7]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v34, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v34, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[14:15]
+; GFX7-NEXT: v_min_f64 v[10:11], v[2:3], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[6:7], v[2:3], v[0:1]
+; GFX7-NEXT: v_min_f64 v[0:1], v[8:9], v[12:13]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v17, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9]
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX7-NEXT: v_min_f64 v[6:7], v[14:15], v[30:31]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[14:15], v[30:31]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5]
+; GFX7-NEXT: v_min_f64 v[8:9], v[4:5], v[6:7]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v11, v34, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
+; GFX7-NEXT: v_min_f64 v[6:7], v[0:1], v[4:5]
+; GFX7-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX7-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v7, v34, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v6, 0, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v5, v34, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
+; GFX7-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v34, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_fminimum_v16double:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-NEXT: v_mov_b32_e32 v33, 0x7ff80000
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
+; GFX8-NEXT: v_min_f64 v[32:33], v[8:9], v[24:25]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX8-NEXT: v_min_f64 v[8:9], v[0:1], v[16:17]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[16:17]
+; GFX8-NEXT: v_min_f64 v[0:1], v[12:13], v[28:29]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[12:13], v[28:29]
+; GFX8-NEXT: v_min_f64 v[12:13], v[10:11], v[26:27]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[10:11], v[26:27]
+; GFX8-NEXT: v_min_f64 v[10:11], v[2:3], v[18:19]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[10:11], v[2:3], v[18:19]
+; GFX8-NEXT: v_mov_b32_e32 v34, 0x7ff80000
+; GFX8-NEXT: v_min_f64 v[2:3], v[4:5], v[20:21]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[12:13], v[4:5], v[20:21]
+; GFX8-NEXT: v_min_f64 v[4:5], v[6:7], v[22:23]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[14:15], v[6:7], v[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v13, v34, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v34, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v32, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, 0, s[4:5]
+; GFX8-NEXT: v_min_f64 v[16:17], v[10:11], v[6:7]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v34, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v34, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[14:15]
+; GFX8-NEXT: v_min_f64 v[10:11], v[2:3], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[6:7], v[2:3], v[0:1]
+; GFX8-NEXT: v_min_f64 v[0:1], v[8:9], v[12:13]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[8:9], v[8:9], v[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v34, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v33, vcc
+; GFX8-NEXT: v_min_f64 v[6:7], v[14:15], v[30:31]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[14:15], v[30:31]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5]
+; GFX8-NEXT: v_min_f64 v[8:9], v[4:5], v[6:7]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v11, v34, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[6:7]
+; GFX8-NEXT: v_min_f64 v[6:7], v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_u_f64_e64 s[4:5], v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX8-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v34, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, 0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v34, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc
+; GFX8-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v34, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_vector_reduce_fminimum_v16double:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v31, off, s32
-; GFX9-NEXT: v_min_f64 v[32:33], v[0:1], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v34, 0x7ff80000
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v32, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[6:7]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[10:11]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[12:13]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[14:15]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
+; GFX9-NEXT: v_mov_b32_e32 v36, 0x7ff80000
+; GFX9-NEXT: v_min_f64 v[32:33], v[8:9], v[24:25]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[8:9], v[24:25]
+; GFX9-NEXT: v_min_f64 v[34:35], v[0:1], v[16:17]
+; GFX9-NEXT: v_min_f64 v[38:39], v[12:13], v[28:29]
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v33, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v32, 0, vcc
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[16:17]
+; GFX9-NEXT: v_min_f64 v[48:49], v[4:5], v[20:21]
+; GFX9-NEXT: v_min_f64 v[50:51], v[6:7], v[22:23]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v35, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v34, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[12:13], v[28:29]
+; GFX9-NEXT: v_min_f64 v[52:53], v[10:11], v[26:27]
+; GFX9-NEXT: v_min_f64 v[54:55], v[2:3], v[18:19]
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v39, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v38, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[20:21]
+; GFX9-NEXT: v_min_f64 v[20:21], v[0:1], v[8:9]
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cmp_u_f64_e64 s[0:1], v[14:15], v[30:31]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v49, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v48, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[6:7], v[22:23]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v51, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v50, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[10:11], v[26:27]
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v53, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v52, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[18:19]
+; GFX9-NEXT: v_min_f64 v[18:19], v[4:5], v[12:13]
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v55, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v54, 0, vcc
+; GFX9-NEXT: v_min_f64 v[16:17], v[2:3], v[10:11]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[10:11]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[18:19]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[20:21]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[22:23]
-; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[24:25]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v16, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[4:5], v[12:13]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[26:27]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v19, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v18, 0, vcc
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[28:29]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v21, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v20, 0, vcc
+; GFX9-NEXT: v_min_f64 v[8:9], v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_min_f64 v[4:5], v[14:15], v[30:31]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v36, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[0:1]
+; GFX9-NEXT: v_min_f64 v[10:11], v[6:7], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e64 s[0:1], v[6:7], v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v8, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v11, v36, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[0:1]
+; GFX9-NEXT: v_min_f64 v[6:7], v[2:3], v[4:5]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[4:5]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[30:31]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v36, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc
+; GFX9-NEXT: v_min_f64 v[4:5], v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: s_nop 1
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v34, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v36, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_vector_reduce_fminimum_v16double:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GFX10-NEXT: v_min_f64 v[32:33], v[8:9], v[24:25]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[16:17]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[0:1], v[16:17]
+; GFX10-NEXT: v_min_f64 v[0:1], v[12:13], v[28:29]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[12:13], v[28:29]
+; GFX10-NEXT: v_min_f64 v[12:13], v[10:11], v[26:27]
+; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[10:11], v[26:27]
+; GFX10-NEXT: v_min_f64 v[10:11], v[2:3], v[18:19]
+; GFX10-NEXT: v_cmp_u_f64_e64 s7, v[2:3], v[18:19]
+; GFX10-NEXT: v_min_f64 v[2:3], v[4:5], v[20:21]
+; GFX10-NEXT: v_cmp_u_f64_e64 s8, v[4:5], v[20:21]
+; GFX10-NEXT: v_min_f64 v[4:5], v[6:7], v[22:23]
+; GFX10-NEXT: v_cmp_u_f64_e64 s9, v[6:7], v[22:23]
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, 0, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, 0x7ff80000, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, 0, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, s9
+; GFX10-NEXT: v_min_f64 v[16:17], v[10:11], v[12:13]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[2:3], v[0:1]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_min_f64 v[6:7], v[14:15], v[30:31]
+; GFX10-NEXT: v_cmp_u_f64_e64 s10, v[14:15], v[30:31]
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v33, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v32, 0, vcc_lo
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[12:13]
+; GFX10-NEXT: v_min_f64 v[10:11], v[2:3], v[0:1]
+; GFX10-NEXT: v_min_f64 v[0:1], v[8:9], v[14:15]
+; GFX10-NEXT: v_cmp_u_f64_e64 s5, v[8:9], v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, 0, s10
+; GFX10-NEXT: v_min_f64 v[2:3], v[4:5], v[6:7]
+; GFX10-NEXT: v_cmp_u_f64_e64 s6, v[4:5], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, 0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s5
+; GFX10-NEXT: v_min_f64 v[8:9], v[0:1], v[6:7]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s6
+; GFX10-NEXT: v_min_f64 v[0:1], v[4:5], v[2:3]
+; GFX10-NEXT: v_cmp_u_f64_e64 s4, v[4:5], v[2:3]
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, s4
+; GFX10-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX10-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_vector_reduce_fminimum_v16double:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f64 v[31:32], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v32, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v31, 0, vcc_lo
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[6:7]
+; GFX11-NEXT: v_min_f64 v[32:33], v[8:9], v[24:25]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[8:9], v[24:25]
+; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[16:17]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[0:1], v[16:17]
+; GFX11-NEXT: v_min_f64 v[0:1], v[12:13], v[28:29]
+; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[12:13], v[28:29]
+; GFX11-NEXT: v_min_f64 v[12:13], v[10:11], v[26:27]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[10:11], v[26:27]
+; GFX11-NEXT: v_min_f64 v[10:11], v[2:3], v[18:19]
+; GFX11-NEXT: v_cmp_u_f64_e64 s3, v[2:3], v[18:19]
+; GFX11-NEXT: v_min_f64 v[2:3], v[4:5], v[20:21]
+; GFX11-NEXT: v_cmp_u_f64_e64 s4, v[4:5], v[20:21]
+; GFX11-NEXT: v_min_f64 v[4:5], v[6:7], v[22:23]
+; GFX11-NEXT: v_cmp_u_f64_e64 s5, v[6:7], v[22:23]
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, 0x7ff80000, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, 0, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, 0x7ff80000, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, 0, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0x7ff80000, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, s5
+; GFX11-NEXT: v_min_f64 v[16:17], v[10:11], v[12:13]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[2:3], v[0:1]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_min_f64 v[6:7], v[14:15], v[30:31]
+; GFX11-NEXT: v_cmp_u_f64_e64 s6, v[14:15], v[30:31]
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v33, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v32, 0, vcc_lo
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[10:11], v[12:13]
+; GFX11-NEXT: v_min_f64 v[10:11], v[2:3], v[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_min_f64 v[0:1], v[8:9], v[14:15]
+; GFX11-NEXT: v_cmp_u_f64_e64 s1, v[8:9], v[14:15]
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0x7ff80000, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, s6
+; GFX11-NEXT: v_min_f64 v[2:3], v[4:5], v[6:7]
+; GFX11-NEXT: v_cmp_u_f64_e64 s2, v[4:5], v[6:7]
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v11, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v10, 0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_min_f64 v[8:9], v[0:1], v[6:7]
; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[8:9]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[10:11]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[12:13]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[12:13]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[14:15]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[16:17]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[18:19]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[18:19]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[20:21]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[20:21]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[22:23]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[22:23]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[24:25]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[24:25]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[26:27]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[26:27]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[28:29]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[28:29]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7ff80000, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s2
+; GFX11-NEXT: v_min_f64 v[0:1], v[4:5], v[2:3]
+; GFX11-NEXT: v_cmp_u_f64_e64 s0, v[4:5], v[2:3]
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v9, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0x7ff80000, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX11-NEXT: v_min_f64 v[4:5], v[2:3], v[0:1]
+; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f64 v[2:3], v[0:1], v[30:31]
-; GFX11-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[30:31]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, 0x7ff80000, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, 0x7ff80000, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-LABEL: test_vector_reduce_fminimum_v16double:
; GFX1170-SDAG: ; %bb.0: ; %entry
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[6:7]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[10:11]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[12:13]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[14:15]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[10:11], v[10:11], v[26:27]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[18:19]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[8:9], v[8:9], v[24:25]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[12:13], v[12:13], v[28:29]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[4:5], v[4:5], v[20:21]
; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[16:17]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[18:19]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[20:21]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[22:23]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[24:25]
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[26:27]
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[28:29]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[6:7], v[6:7], v[22:23]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[30:31]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[14:15], v[14:15], v[30:31]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
+; GFX1170-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-LABEL: test_vector_reduce_fminimum_v16double:
; GFX1170-GISEL: ; %bb.0: ; %entry
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[4:5], v[8:9], v[10:11]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[6:7], v[12:13], v[14:15]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[8:9], v[16:17], v[18:19]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[10:11], v[20:21], v[22:23]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[12:13], v[24:25], v[26:27]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
-; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[4:5], v[8:9], v[10:11]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[16:17]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[18:19]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[4:5], v[4:5], v[20:21]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[6:7], v[6:7], v[22:23]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[8:9], v[8:9], v[24:25]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[10:11], v[10:11], v[26:27]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[12:13], v[12:13], v[28:29]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[14:15], v[28:29], v[30:31]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[14:15], v[14:15], v[30:31]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[6:7], v[12:13], v[14:15]
-; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX1170-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -3285,30 +3205,26 @@ define double @test_vector_reduce_fminimum_v16double(<16 x double> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[6:7]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[10:11]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[12:13]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[14:15]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[10:11], v[10:11], v[26:27]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[18:19]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[8:9], v[8:9], v[24:25]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[12:13], v[12:13], v[28:29]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[4:5], v[4:5], v[20:21]
; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[16:17]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[18:19]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[20:21]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[22:23]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[24:25]
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[26:27]
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[28:29]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[6:7], v[6:7], v[22:23]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[30:31]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[14:15], v[14:15], v[30:31]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
+; GFX12-SDAG-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v16double:
@@ -3319,23 +3235,24 @@ define double @test_vector_reduce_fminimum_v16double(<16 x double> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], v[8:9], v[10:11]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], v[12:13], v[14:15]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[8:9], v[16:17], v[18:19]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[10:11], v[20:21], v[22:23]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[12:13], v[24:25], v[26:27]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], v[8:9], v[10:11]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[16:17]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[18:19]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], v[4:5], v[20:21]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], v[6:7], v[22:23]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[8:9], v[8:9], v[24:25]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[10:11], v[10:11], v[26:27]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[12:13], v[12:13], v[28:29]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11]
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[4:5]
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_minimum_f64 v[14:15], v[28:29], v[30:31]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[14:15], v[14:15], v[30:31]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], v[12:13], v[14:15]
-; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[4:5], v[6:7]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15]
+; GFX12-GISEL-NEXT: v_minimum_f64 v[2:3], v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
index 418cafaf80a16..d28f26cd62aa6 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
@@ -17,10 +17,10 @@ target triple = "spir64-unknown-unknown"
; CHECK: OpFunction
; CHECK: %[[ParamVec2Half:.*]] = OpFunctionParameter %[[HalfVec2]]
-; CHECK: %[[Vec2HalfItem0:.*]] = OpCompositeExtract %[[Half]] %[[ParamVec2Half]] 0
-; CHECK: %[[Vec2HalfItem1:.*]] = OpCompositeExtract %[[Half]] %[[ParamVec2Half]] 1
-; CHECK: %[[Vec2HalfR1:.*]] = OpExtInst %[[Half]] %[[#]] fmax %[[Vec2HalfItem0]] %[[Vec2HalfItem1]]
-; CHECK: OpReturnValue %[[Vec2HalfR1]]
+; CHECK: %[[Vec2HalfShuf:.*]] = OpVectorShuffle %[[HalfVec2]] %[[ParamVec2Half]] %[[#]] 1 0xFFFFFFFF
+; CHECK: %[[Vec2HalfR1:.*]] = OpExtInst %[[HalfVec2]] %[[#]] fmax %[[ParamVec2Half]] %[[Vec2HalfShuf]]
+; CHECK: %[[Vec2HalfR2:.*]] = OpCompositeExtract %[[Half]] %[[Vec2HalfR1]] 0
+; CHECK: OpReturnValue %[[Vec2HalfR2]]
; CHECK: OpFunctionEnd
; CHECK: OpFunction
@@ -35,10 +35,10 @@ target triple = "spir64-unknown-unknown"
; CHECK: OpFunction
; CHECK: %[[ParamVec2Float:.*]] = OpFunctionParameter %[[FloatVec2]]
-; CHECK: %[[Vec2FloatItem0:.*]] = OpCompositeExtract %[[Float]] %[[ParamVec2Float]] 0
-; CHECK: %[[Vec2FloatItem1:.*]] = OpCompositeExtract %[[Float]] %[[ParamVec2Float]] 1
-; CHECK: %[[Vec2FloatR1:.*]] = OpExtInst %[[Float]] %[[#]] fmax %[[Vec2FloatItem0]] %[[Vec2FloatItem1]]
-; CHECK: OpReturnValue %[[Vec2FloatR1]]
+; CHECK: %[[Vec2FloatShuf:.*]] = OpVectorShuffle %[[FloatVec2]] %[[ParamVec2Float]] %[[#]] 1 0xFFFFFFFF
+; CHECK: %[[Vec2FloatR1:.*]] = OpExtInst %[[FloatVec2]] %[[#]] fmax %[[ParamVec2Float]] %[[Vec2FloatShuf]]
+; CHECK: %[[Vec2FloatR2:.*]] = OpCompositeExtract %[[Float]] %[[Vec2FloatR1]] 0
+; CHECK: OpReturnValue %[[Vec2FloatR2]]
; CHECK: OpFunctionEnd
; CHECK: OpFunction
@@ -53,10 +53,10 @@ target triple = "spir64-unknown-unknown"
; CHECK: OpFunction
; CHECK: %[[ParamVec2Double:.*]] = OpFunctionParameter %[[DoubleVec2]]
-; CHECK: %[[Vec2DoubleItem0:.*]] = OpCompositeExtract %[[Double]] %[[ParamVec2Double]] 0
-; CHECK: %[[Vec2DoubleItem1:.*]] = OpCompositeExtract %[[Double]] %[[ParamVec2Double]] 1
-; CHECK: %[[Vec2DoubleR1:.*]] = OpExtInst %[[Double]] %[[#]] fmax %[[Vec2DoubleItem0]] %[[Vec2DoubleItem1]]
-; CHECK: OpReturnValue %[[Vec2DoubleR1]]
+; CHECK: %[[Vec2DoubleShuf:.*]] = OpVectorShuffle %[[DoubleVec2]] %[[ParamVec2Double]] %[[#]] 1 0xFFFFFFFF
+; CHECK: %[[Vec2DoubleR1:.*]] = OpExtInst %[[DoubleVec2]] %[[#]] fmax %[[ParamVec2Double]] %[[Vec2DoubleShuf]]
+; CHECK: %[[Vec2DoubleR2:.*]] = OpCompositeExtract %[[Double]] %[[Vec2DoubleR1]] 0
+; CHECK: OpReturnValue %[[Vec2DoubleR2]]
; CHECK: OpFunctionEnd
; CHECK: OpFunction
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
index 26bb7796957eb..53ef537ac3385 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
@@ -17,10 +17,10 @@ target triple = "spir64-unknown-unknown"
; CHECK: OpFunction
; CHECK: %[[ParamVec2Half:.*]] = OpFunctionParameter %[[HalfVec2]]
-; CHECK: %[[Vec2HalfItem0:.*]] = OpCompositeExtract %[[Half]] %[[ParamVec2Half]] 0
-; CHECK: %[[Vec2HalfItem1:.*]] = OpCompositeExtract %[[Half]] %[[ParamVec2Half]] 1
-; CHECK: %[[Vec2HalfR1:.*]] = OpExtInst %[[Half]] %[[#]] fmin %[[Vec2HalfItem0]] %[[Vec2HalfItem1]]
-; CHECK: OpReturnValue %[[Vec2HalfR1]]
+; CHECK: %[[Vec2HalfShuf:.*]] = OpVectorShuffle %[[HalfVec2]] %[[ParamVec2Half]] %[[#]] 1 0xFFFFFFFF
+; CHECK: %[[Vec2HalfR1:.*]] = OpExtInst %[[HalfVec2]] %[[#]] fmin %[[ParamVec2Half]] %[[Vec2HalfShuf]]
+; CHECK: %[[Vec2HalfR2:.*]] = OpCompositeExtract %[[Half]] %[[Vec2HalfR1]] 0
+; CHECK: OpReturnValue %[[Vec2HalfR2]]
; CHECK: OpFunctionEnd
; CHECK: OpFunction
@@ -35,10 +35,10 @@ target triple = "spir64-unknown-unknown"
; CHECK: OpFunction
; CHECK: %[[ParamVec2Float:.*]] = OpFunctionParameter %[[FloatVec2]]
-; CHECK: %[[Vec2FloatItem0:.*]] = OpCompositeExtract %[[Float]] %[[ParamVec2Float]] 0
-; CHECK: %[[Vec2FloatItem1:.*]] = OpCompositeExtract %[[Float]] %[[ParamVec2Float]] 1
-; CHECK: %[[Vec2FloatR1:.*]] = OpExtInst %[[Float]] %[[#]] fmin %[[Vec2FloatItem0]] %[[Vec2FloatItem1]]
-; CHECK: OpReturnValue %[[Vec2FloatR1]]
+; CHECK: %[[Vec2FloatShuf:.*]] = OpVectorShuffle %[[FloatVec2]] %[[ParamVec2Float]] %[[#]] 1 0xFFFFFFFF
+; CHECK: %[[Vec2FloatR1:.*]] = OpExtInst %[[FloatVec2]] %[[#]] fmin %[[ParamVec2Float]] %[[Vec2FloatShuf]]
+; CHECK: %[[Vec2FloatR2:.*]] = OpCompositeExtract %[[Float]] %[[Vec2FloatR1]] 0
+; CHECK: OpReturnValue %[[Vec2FloatR2]]
; CHECK: OpFunctionEnd
; CHECK: OpFunction
@@ -53,10 +53,10 @@ target triple = "spir64-unknown-unknown"
; CHECK: OpFunction
; CHECK: %[[ParamVec2Double:.*]] = OpFunctionParameter %[[DoubleVec2]]
-; CHECK: %[[Vec2DoubleItem0:.*]] = OpCompositeExtract %[[Double]] %[[ParamVec2Double]] 0
-; CHECK: %[[Vec2DoubleItem1:.*]] = OpCompositeExtract %[[Double]] %[[ParamVec2Double]] 1
-; CHECK: %[[Vec2DoubleR1:.*]] = OpExtInst %[[Double]] %[[#]] fmin %[[Vec2DoubleItem0]] %[[Vec2DoubleItem1]]
-; CHECK: OpReturnValue %[[Vec2DoubleR1]]
+; CHECK: %[[Vec2DoubleShuf:.*]] = OpVectorShuffle %[[DoubleVec2]] %[[ParamVec2Double]] %[[#]] 1 0xFFFFFFFF
+; CHECK: %[[Vec2DoubleR1:.*]] = OpExtInst %[[DoubleVec2]] %[[#]] fmin %[[ParamVec2Double]] %[[Vec2DoubleShuf]]
+; CHECK: %[[Vec2DoubleR2:.*]] = OpCompositeExtract %[[Double]] %[[Vec2DoubleR1]] 0
+; CHECK: OpReturnValue %[[Vec2DoubleR2]]
; CHECK: OpFunctionEnd
; CHECK: OpFunction
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
index 813539b7d3b88..d0271a8081dc9 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
@@ -97,101 +97,176 @@ define float @test_v2f32(<2 x float> %a0) {
ret float %1
}
+define float @test_v3f32(<3 x float> %a0) {
+; SSE2-LABEL: test_v3f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: orps %xmm2, %xmm1
+; SSE2-NEXT: movaps %xmm0, %xmm3
+; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1]
+; SSE2-NEXT: movaps %xmm0, %xmm4
+; SSE2-NEXT: maxss %xmm3, %xmm4
+; SSE2-NEXT: andps %xmm1, %xmm4
+; SSE2-NEXT: movaps %xmm0, %xmm3
+; SSE2-NEXT: cmpunordss %xmm0, %xmm3
+; SSE2-NEXT: movaps %xmm3, %xmm1
+; SSE2-NEXT: andnps %xmm4, %xmm1
+; SSE2-NEXT: andps %xmm0, %xmm3
+; SSE2-NEXT: orps %xmm1, %xmm3
+; SSE2-NEXT: movaps %xmm3, %xmm1
+; SSE2-NEXT: cmpunordss %xmm3, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm4
+; SSE2-NEXT: andps %xmm3, %xmm4
+; SSE2-NEXT: orps %xmm3, %xmm2
+; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; SSE2-NEXT: maxss %xmm0, %xmm3
+; SSE2-NEXT: andps %xmm2, %xmm3
+; SSE2-NEXT: andnps %xmm3, %xmm1
+; SSE2-NEXT: orps %xmm4, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_v3f32:
+; SSE41: # %bb.0:
+; SSE41-NEXT: movaps %xmm0, %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
+; SSE41-NEXT: orps %xmm3, %xmm0
+; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; SSE41-NEXT: movaps %xmm1, %xmm4
+; SSE41-NEXT: maxss %xmm2, %xmm4
+; SSE41-NEXT: andps %xmm0, %xmm4
+; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: cmpunordss %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm4
+; SSE41-NEXT: orps %xmm4, %xmm3
+; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
+; SSE41-NEXT: movaps %xmm4, %xmm2
+; SSE41-NEXT: maxss %xmm1, %xmm2
+; SSE41-NEXT: andps %xmm3, %xmm2
+; SSE41-NEXT: movaps %xmm4, %xmm0
+; SSE41-NEXT: cmpunordss %xmm4, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm2
+; SSE41-NEXT: movaps %xmm2, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_v3f32:
+; AVX: # %bb.0:
+; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
+; AVX-NEXT: vorps %xmm1, %xmm0, %xmm2
+; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; AVX-NEXT: vmaxss %xmm3, %xmm0, %xmm3
+; AVX-NEXT: vandps %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
+; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm2, %xmm2
+; AVX-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT: vmaxss %xmm0, %xmm2, %xmm0
+; AVX-NEXT: vandps %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vcmpunordss %xmm2, %xmm2, %xmm1
+; AVX-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; AVX512BW-LABEL: test_v3f32:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
+; AVX512BW-NEXT: vorps %xmm1, %xmm0, %xmm2
+; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; AVX512BW-NEXT: vmaxss %xmm3, %xmm0, %xmm3
+; AVX512BW-NEXT: vandps %xmm3, %xmm2, %xmm2
+; AVX512BW-NEXT: vcmpunordss %xmm0, %xmm0, %k1
+; AVX512BW-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512BW-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX512BW-NEXT: vmaxss %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vandps %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vcmpunordss %xmm2, %xmm2, %k1
+; AVX512BW-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: retq
+;
+; AVX512VL-LABEL: test_v3f32:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX512VL-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm1 & (xmm0 | xmm2)
+; AVX512VL-NEXT: vcmpunordss %xmm0, %xmm0, %k1
+; AVX512VL-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX512VL-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 & (xmm1 | xmm2)
+; AVX512VL-NEXT: vcmpunordss %xmm1, %xmm1, %k1
+; AVX512VL-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: retq
+ %1 = call float @llvm.vector.reduce.fmaximum.v3f32(<3 x float> %a0)
+ ret float %1
+}
+
define float @test_v4f32(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
+; SSE2-NEXT: movaps {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
; SSE2-NEXT: movaps %xmm0, %xmm3
+; SSE2-NEXT: orps %xmm2, %xmm3
; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: movaps %xmm0, %xmm5
-; SSE2-NEXT: movaps %xmm0, %xmm6
-; SSE2-NEXT: cmpunordss %xmm0, %xmm6
-; SSE2-NEXT: movaps %xmm6, %xmm7
-; SSE2-NEXT: andps %xmm0, %xmm6
-; SSE2-NEXT: movaps %xmm0, %xmm2
-; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm0[3,3]
-; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
-; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1]
-; SSE2-NEXT: maxss %xmm3, %xmm5
-; SSE2-NEXT: movaps {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
-; SSE2-NEXT: orps %xmm3, %xmm4
-; SSE2-NEXT: andps %xmm4, %xmm5
-; SSE2-NEXT: andnps %xmm5, %xmm7
-; SSE2-NEXT: orps %xmm7, %xmm6
-; SSE2-NEXT: movaps %xmm6, %xmm4
-; SSE2-NEXT: cmpunordss %xmm6, %xmm4
-; SSE2-NEXT: movaps %xmm4, %xmm0
-; SSE2-NEXT: andps %xmm6, %xmm0
-; SSE2-NEXT: movaps %xmm6, %xmm5
-; SSE2-NEXT: orps %xmm3, %xmm5
-; SSE2-NEXT: maxss %xmm1, %xmm6
-; SSE2-NEXT: andps %xmm5, %xmm6
-; SSE2-NEXT: andnps %xmm6, %xmm4
-; SSE2-NEXT: orps %xmm0, %xmm4
-; SSE2-NEXT: movaps %xmm4, %xmm0
-; SSE2-NEXT: cmpunordss %xmm4, %xmm0
-; SSE2-NEXT: movaps %xmm0, %xmm1
-; SSE2-NEXT: andps %xmm4, %xmm1
-; SSE2-NEXT: orps %xmm4, %xmm3
-; SSE2-NEXT: maxss %xmm2, %xmm4
+; SSE2-NEXT: maxps %xmm1, %xmm4
; SSE2-NEXT: andps %xmm3, %xmm4
-; SSE2-NEXT: andnps %xmm4, %xmm0
-; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: cmpunordps %xmm0, %xmm1
+; SSE2-NEXT: andps %xmm1, %xmm0
+; SSE2-NEXT: andnps %xmm4, %xmm1
+; SSE2-NEXT: orps %xmm0, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: cmpunordss %xmm1, %xmm0
+; SSE2-NEXT: movaps %xmm0, %xmm3
+; SSE2-NEXT: andps %xmm1, %xmm3
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
+; SSE2-NEXT: movaps %xmm1, %xmm5
+; SSE2-NEXT: maxss %xmm4, %xmm5
+; SSE2-NEXT: orps %xmm2, %xmm1
+; SSE2-NEXT: andps %xmm5, %xmm1
+; SSE2-NEXT: andnps %xmm1, %xmm0
+; SSE2-NEXT: orps %xmm3, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1
-; SSE41-NEXT: movaps %xmm0, %xmm3
-; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE41-NEXT: movaps {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; SSE41-NEXT: movaps %xmm1, %xmm3
+; SSE41-NEXT: orps %xmm2, %xmm3
; SSE41-NEXT: movaps %xmm1, %xmm4
-; SSE41-NEXT: orps %xmm2, %xmm4
-; SSE41-NEXT: movaps %xmm1, %xmm5
-; SSE41-NEXT: maxss %xmm0, %xmm5
-; SSE41-NEXT: andps %xmm4, %xmm5
-; SSE41-NEXT: movaps %xmm1, %xmm0
-; SSE41-NEXT: cmpunordss %xmm1, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm5
-; SSE41-NEXT: movaps %xmm1, %xmm4
-; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm1[3,3]
-; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1]
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: orps %xmm2, %xmm0
-; SSE41-NEXT: movaps %xmm5, %xmm6
-; SSE41-NEXT: maxss %xmm3, %xmm6
-; SSE41-NEXT: andps %xmm0, %xmm6
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: cmpunordss %xmm5, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm6
-; SSE41-NEXT: orps %xmm6, %xmm2
-; SSE41-NEXT: movaps %xmm6, %xmm1
-; SSE41-NEXT: maxss %xmm4, %xmm1
-; SSE41-NEXT: andps %xmm2, %xmm1
-; SSE41-NEXT: movaps %xmm6, %xmm0
-; SSE41-NEXT: cmpunordss %xmm6, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm6, %xmm1
+; SSE41-NEXT: maxps %xmm0, %xmm4
+; SSE41-NEXT: andps %xmm3, %xmm4
; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: cmpunordps %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm4
+; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE41-NEXT: movaps %xmm4, %xmm1
+; SSE41-NEXT: maxss %xmm0, %xmm1
+; SSE41-NEXT: orps %xmm4, %xmm2
+; SSE41-NEXT: andps %xmm1, %xmm2
+; SSE41-NEXT: movaps %xmm4, %xmm0
+; SSE41-NEXT: cmpunordss %xmm4, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm2
+; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: retq
;
; AVX-LABEL: test_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX-NEXT: vbroadcastss {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN]
-; AVX-NEXT: vorps %xmm4, %xmm0, %xmm5
-; AVX-NEXT: vmaxss %xmm3, %xmm0, %xmm3
-; AVX-NEXT: vandps %xmm3, %xmm5, %xmm3
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm5
-; AVX-NEXT: vblendvps %xmm5, %xmm0, %xmm3, %xmm0
-; AVX-NEXT: vorps %xmm4, %xmm0, %xmm3
-; AVX-NEXT: vmaxss %xmm2, %xmm0, %xmm2
-; AVX-NEXT: vandps %xmm2, %xmm3, %xmm2
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm2, %xmm0
-; AVX-NEXT: vorps %xmm4, %xmm0, %xmm2
+; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX-NEXT: vorpd %xmm2, %xmm0, %xmm3
+; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm1
+; AVX-NEXT: vandpd %xmm1, %xmm3, %xmm1
+; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
+; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; AVX-NEXT: vorps %xmm2, %xmm0, %xmm2
; AVX-NEXT: vandps %xmm1, %xmm2, %xmm1
; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
@@ -199,45 +274,34 @@ define float @test_v4f32(<4 x float> %a0) {
;
; AVX512BW-LABEL: test_v4f32:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX512BW-NEXT: vbroadcastss {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN]
-; AVX512BW-NEXT: vorps %xmm4, %xmm0, %xmm5
-; AVX512BW-NEXT: vmaxss %xmm3, %xmm0, %xmm3
-; AVX512BW-NEXT: vandps %xmm3, %xmm5, %xmm3
-; AVX512BW-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512BW-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k1}
-; AVX512BW-NEXT: vorps %xmm4, %xmm3, %xmm0
-; AVX512BW-NEXT: vmaxss %xmm2, %xmm3, %xmm2
-; AVX512BW-NEXT: vandps %xmm2, %xmm0, %xmm2
-; AVX512BW-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512BW-NEXT: vmovss %xmm3, %xmm2, %xmm2 {%k1}
-; AVX512BW-NEXT: vorps %xmm4, %xmm2, %xmm0
-; AVX512BW-NEXT: vmaxss %xmm1, %xmm2, %xmm1
-; AVX512BW-NEXT: vandps %xmm1, %xmm0, %xmm0
-; AVX512BW-NEXT: vcmpunordss %xmm2, %xmm2, %k1
-; AVX512BW-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX512BW-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX512BW-NEXT: vorpd %xmm2, %xmm0, %xmm3
+; AVX512BW-NEXT: vmaxps %xmm1, %xmm0, %xmm1
+; AVX512BW-NEXT: vandpd %xmm1, %xmm3, %xmm1
+; AVX512BW-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
+; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; AVX512BW-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vorps %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vandps %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vcmpunordss %xmm1, %xmm1, %k1
+; AVX512BW-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: retq
;
; AVX512VL-LABEL: test_v4f32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX512VL-NEXT: vmaxss %xmm3, %xmm0, %xmm3
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN]
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm3 = xmm3 & (xmm0 | xmm4)
-; AVX512VL-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k1}
-; AVX512VL-NEXT: vmaxss %xmm2, %xmm3, %xmm2
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm2 = xmm2 & (xmm3 | xmm4)
-; AVX512VL-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovss %xmm3, %xmm2, %xmm2 {%k1}
-; AVX512VL-NEXT: vmaxss %xmm1, %xmm2, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 & (xmm2 | xmm4)
-; AVX512VL-NEXT: vcmpunordss %xmm2, %xmm2, %k1
-; AVX512VL-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX512VL-NEXT: vmaxps %xmm1, %xmm0, %xmm1
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm1 & (xmm0 | xmm2)
+; AVX512VL-NEXT: vcmpunordps %xmm0, %xmm0, %k1
+; AVX512VL-NEXT: vmovaps %xmm0, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; AVX512VL-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 & (xmm1 | xmm2)
+; AVX512VL-NEXT: vcmpunordss %xmm1, %xmm1, %k1
+; AVX512VL-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; AVX512VL-NEXT: retq
%1 = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %a0)
ret float %1
@@ -257,164 +321,154 @@ define float @test_v8f32(<8 x float> %a0) {
; SSE2-NEXT: andps %xmm2, %xmm0
; SSE2-NEXT: andnps %xmm3, %xmm2
; SSE2-NEXT: orps %xmm0, %xmm2
-; SSE2-NEXT: movaps %xmm2, %xmm0
-; SSE2-NEXT: cmpunordss %xmm2, %xmm0
-; SSE2-NEXT: movaps %xmm0, %xmm3
-; SSE2-NEXT: andps %xmm2, %xmm3
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
+; SSE2-NEXT: movaps %xmm2, %xmm3
+; SSE2-NEXT: cmpunordps %xmm2, %xmm3
+; SSE2-NEXT: movaps %xmm2, %xmm4
+; SSE2-NEXT: andps %xmm3, %xmm4
; SSE2-NEXT: movaps %xmm2, %xmm5
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm2[2,3,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm2[3,3,3,3]
-; SSE2-NEXT: maxss %xmm4, %xmm2
-; SSE2-NEXT: orps %xmm1, %xmm5
-; SSE2-NEXT: andps %xmm2, %xmm5
-; SSE2-NEXT: andnps %xmm5, %xmm0
-; SSE2-NEXT: orps %xmm3, %xmm0
+; SSE2-NEXT: maxps %xmm0, %xmm5
+; SSE2-NEXT: orps %xmm1, %xmm2
+; SSE2-NEXT: andps %xmm5, %xmm2
+; SSE2-NEXT: andnps %xmm2, %xmm3
+; SSE2-NEXT: orps %xmm4, %xmm3
+; SSE2-NEXT: movaps %xmm3, %xmm0
+; SSE2-NEXT: cmpunordss %xmm3, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm2
-; SSE2-NEXT: cmpunordss %xmm0, %xmm2
-; SSE2-NEXT: movaps %xmm2, %xmm3
-; SSE2-NEXT: andps %xmm0, %xmm3
-; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: orps %xmm1, %xmm4
-; SSE2-NEXT: maxss %xmm6, %xmm0
-; SSE2-NEXT: andps %xmm4, %xmm0
-; SSE2-NEXT: andnps %xmm0, %xmm2
-; SSE2-NEXT: orps %xmm3, %xmm2
-; SSE2-NEXT: movaps %xmm2, %xmm0
-; SSE2-NEXT: cmpunordss %xmm2, %xmm0
-; SSE2-NEXT: movaps %xmm0, %xmm3
-; SSE2-NEXT: andps %xmm2, %xmm3
-; SSE2-NEXT: orps %xmm2, %xmm1
-; SSE2-NEXT: maxss %xmm7, %xmm2
-; SSE2-NEXT: andps %xmm1, %xmm2
-; SSE2-NEXT: andnps %xmm2, %xmm0
-; SSE2-NEXT: orps %xmm3, %xmm0
+; SSE2-NEXT: andps %xmm3, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,1,1]
+; SSE2-NEXT: movaps %xmm3, %xmm5
+; SSE2-NEXT: maxss %xmm4, %xmm5
+; SSE2-NEXT: orps %xmm1, %xmm3
+; SSE2-NEXT: andps %xmm5, %xmm3
+; SSE2-NEXT: andnps %xmm3, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: test_v8f32:
; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm2
; SSE41-NEXT: maxps %xmm1, %xmm0
-; SSE41-NEXT: movaps {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
-; SSE41-NEXT: movaps %xmm2, %xmm4
-; SSE41-NEXT: orps %xmm3, %xmm4
-; SSE41-NEXT: andps %xmm0, %xmm4
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
+; SSE41-NEXT: movaps %xmm2, %xmm3
+; SSE41-NEXT: orps %xmm1, %xmm3
+; SSE41-NEXT: andps %xmm0, %xmm3
; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: cmpunordps %xmm2, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm4
+; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
+; SSE41-NEXT: movaps %xmm3, %xmm0
+; SSE41-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1]
+; SSE41-NEXT: movaps %xmm3, %xmm2
+; SSE41-NEXT: maxps %xmm0, %xmm2
+; SSE41-NEXT: movaps %xmm3, %xmm4
+; SSE41-NEXT: orps %xmm1, %xmm4
+; SSE41-NEXT: andps %xmm2, %xmm4
+; SSE41-NEXT: movaps %xmm3, %xmm0
+; SSE41-NEXT: cmpunordps %xmm3, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm3, %xmm4
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3]
-; SSE41-NEXT: movaps %xmm4, %xmm1
-; SSE41-NEXT: maxss %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm4, %xmm2
-; SSE41-NEXT: orps %xmm3, %xmm2
-; SSE41-NEXT: andps %xmm1, %xmm2
+; SSE41-NEXT: maxss %xmm0, %xmm2
+; SSE41-NEXT: orps %xmm4, %xmm1
+; SSE41-NEXT: andps %xmm2, %xmm1
; SSE41-NEXT: movaps %xmm4, %xmm0
; SSE41-NEXT: cmpunordss %xmm4, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm2
-; SSE41-NEXT: movaps %xmm2, %xmm0
-; SSE41-NEXT: orps %xmm3, %xmm0
-; SSE41-NEXT: movaps %xmm4, %xmm1
-; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1]
-; SSE41-NEXT: movaps %xmm2, %xmm5
-; SSE41-NEXT: maxss %xmm1, %xmm5
-; SSE41-NEXT: andps %xmm0, %xmm5
-; SSE41-NEXT: movaps %xmm2, %xmm0
-; SSE41-NEXT: cmpunordss %xmm2, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm5
-; SSE41-NEXT: orps %xmm5, %xmm3
-; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
-; SSE41-NEXT: movaps %xmm5, %xmm1
-; SSE41-NEXT: maxss %xmm4, %xmm1
-; SSE41-NEXT: andps %xmm3, %xmm1
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: cmpunordss %xmm5, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm1
+; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v8f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
-; AVX-NEXT: vorps %xmm2, %xmm1, %xmm3
-; AVX-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX-NEXT: vmaxss %xmm4, %xmm1, %xmm4
-; AVX-NEXT: vandps %xmm4, %xmm3, %xmm3
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm4
-; AVX-NEXT: vblendvps %xmm4, %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vorps %xmm2, %xmm1, %xmm2
-; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vandps %xmm0, %xmm2, %xmm0
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm2
-; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v8f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vmaxps %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vandps %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vmaxps %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vorps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX1-NEXT: vorps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8f32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX2-NEXT: vorps %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vmaxps %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vandps %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vmaxps %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vorps %xmm2, %xmm0, %xmm4
+; AVX2-NEXT: vandps %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX2-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vorps %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v8f32:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512BW-NEXT: vorps %ymm2, %ymm0, %ymm3
+; AVX512BW-NEXT: vmaxps %ymm1, %ymm0, %ymm1
+; AVX512BW-NEXT: vandps %ymm1, %ymm3, %ymm1
+; AVX512BW-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX512BW-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512BW-NEXT: vmaxps %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512BW-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512BW-NEXT: vmaxss %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512BW-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512BW-NEXT: vorps %xmm2, %xmm1, %xmm3
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX512BW-NEXT: vmaxss %xmm4, %xmm1, %xmm4
-; AVX512BW-NEXT: vandps %xmm4, %xmm3, %xmm3
+; AVX512BW-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX512BW-NEXT: vorps %xmm2, %xmm0, %xmm4
+; AVX512BW-NEXT: vandps %xmm1, %xmm4, %xmm1
+; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; AVX512BW-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vorps %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vandps %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vcmpunordss %xmm1, %xmm1, %k1
-; AVX512BW-NEXT: vmovss %xmm1, %xmm3, %xmm3 {%k1}
-; AVX512BW-NEXT: vorps %xmm2, %xmm3, %xmm1
-; AVX512BW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512BW-NEXT: vmaxss %xmm0, %xmm3, %xmm0
-; AVX512BW-NEXT: vandps %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512BW-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
; AVX512VL-LABEL: test_v8f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX512VL-NEXT: vmaxps %xmm1, %xmm0, %xmm1
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm1 & (xmm0 | xmm2)
-; AVX512VL-NEXT: vcmpunordps %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovaps %xmm0, %xmm1 {%k1}
-; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
-; AVX512VL-NEXT: vmaxss %xmm0, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 & (xmm1 | xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm3 = xmm1[1,0]
-; AVX512VL-NEXT: vmaxss %xmm3, %xmm0, %xmm3
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm3 = xmm3 & (xmm0 | xmm2)
+; AVX512VL-NEXT: vmaxps %ymm1, %ymm0, %ymm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm1 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512VL-NEXT: vpternlogd {{.*#+}} ymm2 = ymm2 & (ymm0 | ymm1)
+; AVX512VL-NEXT: vcmpunordps %ymm0, %ymm0, %k1
+; AVX512VL-NEXT: vmovaps %ymm0, %ymm2 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
+; AVX512VL-NEXT: vmaxps %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 & (ymm2 | ymm1)
+; AVX512VL-NEXT: vcmpunordps %ymm2, %ymm2, %k1
+; AVX512VL-NEXT: vmovaps %ymm2, %ymm0 {%k1}
+; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX512VL-NEXT: vmaxss %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm2 & (xmm1 | xmm0)
; AVX512VL-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k1}
-; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,3,3,3]
-; AVX512VL-NEXT: vmaxss %xmm0, %xmm3, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 & (xmm3 | xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovaps %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %a0)
@@ -424,68 +478,58 @@ define float @test_v8f32(<8 x float> %a0) {
define float @test_v16f32(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0:
-; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: maxps %xmm2, %xmm4
-; SSE2-NEXT: movaps {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; SSE2-NEXT: movaps %xmm0, %xmm5
-; SSE2-NEXT: orps %xmm2, %xmm5
+; SSE2-NEXT: movaps %xmm1, %xmm4
+; SSE2-NEXT: maxps %xmm3, %xmm4
+; SSE2-NEXT: movaps {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
+; SSE2-NEXT: movaps %xmm1, %xmm5
+; SSE2-NEXT: orps %xmm3, %xmm5
; SSE2-NEXT: andps %xmm4, %xmm5
-; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: cmpunordps %xmm0, %xmm4
-; SSE2-NEXT: andps %xmm4, %xmm0
+; SSE2-NEXT: movaps %xmm1, %xmm4
+; SSE2-NEXT: cmpunordps %xmm1, %xmm4
+; SSE2-NEXT: andps %xmm4, %xmm1
; SSE2-NEXT: andnps %xmm5, %xmm4
-; SSE2-NEXT: orps %xmm0, %xmm4
-; SSE2-NEXT: movaps %xmm4, %xmm0
-; SSE2-NEXT: cmpunordps %xmm4, %xmm0
-; SSE2-NEXT: movaps %xmm4, %xmm5
-; SSE2-NEXT: andps %xmm0, %xmm5
-; SSE2-NEXT: movaps %xmm1, %xmm6
-; SSE2-NEXT: maxps %xmm3, %xmm6
-; SSE2-NEXT: movaps %xmm1, %xmm3
-; SSE2-NEXT: orps %xmm2, %xmm3
-; SSE2-NEXT: andps %xmm6, %xmm3
-; SSE2-NEXT: movaps %xmm1, %xmm6
-; SSE2-NEXT: cmpunordps %xmm1, %xmm6
-; SSE2-NEXT: andps %xmm6, %xmm1
-; SSE2-NEXT: andnps %xmm3, %xmm6
-; SSE2-NEXT: orps %xmm1, %xmm6
-; SSE2-NEXT: movaps %xmm4, %xmm1
-; SSE2-NEXT: maxps %xmm6, %xmm1
-; SSE2-NEXT: orps %xmm2, %xmm4
-; SSE2-NEXT: andps %xmm1, %xmm4
-; SSE2-NEXT: andnps %xmm4, %xmm0
-; SSE2-NEXT: orps %xmm5, %xmm0
+; SSE2-NEXT: orps %xmm1, %xmm4
; SSE2-NEXT: movaps %xmm0, %xmm1
-; SSE2-NEXT: cmpunordss %xmm0, %xmm1
-; SSE2-NEXT: movaps %xmm1, %xmm3
-; SSE2-NEXT: andps %xmm0, %xmm3
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
-; SSE2-NEXT: movaps %xmm0, %xmm5
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm0[3,3,3,3]
-; SSE2-NEXT: maxss %xmm4, %xmm0
-; SSE2-NEXT: orps %xmm2, %xmm5
-; SSE2-NEXT: andps %xmm0, %xmm5
-; SSE2-NEXT: andnps %xmm5, %xmm1
-; SSE2-NEXT: orps %xmm3, %xmm1
-; SSE2-NEXT: movaps %xmm1, %xmm3
-; SSE2-NEXT: cmpunordss %xmm1, %xmm3
-; SSE2-NEXT: movaps %xmm3, %xmm0
+; SSE2-NEXT: maxps %xmm2, %xmm1
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: orps %xmm3, %xmm2
+; SSE2-NEXT: andps %xmm1, %xmm2
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: cmpunordps %xmm0, %xmm1
; SSE2-NEXT: andps %xmm1, %xmm0
-; SSE2-NEXT: movaps %xmm1, %xmm4
-; SSE2-NEXT: orps %xmm2, %xmm4
-; SSE2-NEXT: maxss %xmm6, %xmm1
-; SSE2-NEXT: andps %xmm4, %xmm1
-; SSE2-NEXT: andnps %xmm1, %xmm3
-; SSE2-NEXT: orps %xmm0, %xmm3
-; SSE2-NEXT: movaps %xmm3, %xmm0
-; SSE2-NEXT: cmpunordss %xmm3, %xmm0
+; SSE2-NEXT: andnps %xmm2, %xmm1
+; SSE2-NEXT: orps %xmm0, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: cmpunordps %xmm1, %xmm0
+; SSE2-NEXT: movaps %xmm1, %xmm2
+; SSE2-NEXT: andps %xmm0, %xmm2
+; SSE2-NEXT: movaps %xmm1, %xmm5
+; SSE2-NEXT: maxps %xmm4, %xmm5
+; SSE2-NEXT: orps %xmm3, %xmm1
+; SSE2-NEXT: andps %xmm5, %xmm1
+; SSE2-NEXT: andnps %xmm1, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: cmpunordps %xmm0, %xmm2
+; SSE2-NEXT: movaps %xmm0, %xmm4
+; SSE2-NEXT: andps %xmm2, %xmm4
+; SSE2-NEXT: movaps %xmm0, %xmm5
+; SSE2-NEXT: maxps %xmm1, %xmm5
+; SSE2-NEXT: orps %xmm3, %xmm0
+; SSE2-NEXT: andps %xmm5, %xmm0
+; SSE2-NEXT: andnps %xmm0, %xmm2
+; SSE2-NEXT: orps %xmm4, %xmm2
+; SSE2-NEXT: movaps %xmm2, %xmm0
+; SSE2-NEXT: cmpunordss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1
-; SSE2-NEXT: andps %xmm3, %xmm1
+; SSE2-NEXT: andps %xmm2, %xmm1
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; SSE2-NEXT: movaps %xmm2, %xmm5
+; SSE2-NEXT: maxss %xmm4, %xmm5
; SSE2-NEXT: orps %xmm3, %xmm2
-; SSE2-NEXT: maxss %xmm7, %xmm3
-; SSE2-NEXT: andps %xmm2, %xmm3
-; SSE2-NEXT: andnps %xmm3, %xmm0
+; SSE2-NEXT: andps %xmm5, %xmm2
+; SSE2-NEXT: andnps %xmm2, %xmm0
; SSE2-NEXT: orps %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -517,135 +561,137 @@ define float @test_v16f32(<16 x float> %a0) {
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: cmpunordps %xmm1, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm2
-; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; SSE41-NEXT: movaps %xmm2, %xmm0
+; SSE41-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1]
; SSE41-NEXT: movaps %xmm2, %xmm1
-; SSE41-NEXT: maxss %xmm0, %xmm1
+; SSE41-NEXT: maxps %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm2, %xmm4
; SSE41-NEXT: orps %xmm3, %xmm4
; SSE41-NEXT: andps %xmm1, %xmm4
; SSE41-NEXT: movaps %xmm2, %xmm0
-; SSE41-NEXT: cmpunordss %xmm2, %xmm0
+; SSE41-NEXT: cmpunordps %xmm2, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm4
-; SSE41-NEXT: movaps %xmm4, %xmm0
-; SSE41-NEXT: orps %xmm3, %xmm0
-; SSE41-NEXT: movaps %xmm2, %xmm1
-; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]
-; SSE41-NEXT: movaps %xmm4, %xmm5
-; SSE41-NEXT: maxss %xmm1, %xmm5
-; SSE41-NEXT: andps %xmm0, %xmm5
+; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE41-NEXT: movaps %xmm4, %xmm1
+; SSE41-NEXT: maxss %xmm0, %xmm1
+; SSE41-NEXT: orps %xmm4, %xmm3
+; SSE41-NEXT: andps %xmm1, %xmm3
; SSE41-NEXT: movaps %xmm4, %xmm0
; SSE41-NEXT: cmpunordss %xmm4, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm5
-; SSE41-NEXT: orps %xmm5, %xmm3
-; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
-; SSE41-NEXT: movaps %xmm5, %xmm1
-; SSE41-NEXT: maxss %xmm2, %xmm1
-; SSE41-NEXT: andps %xmm3, %xmm1
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: cmpunordss %xmm5, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm1
-; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm3
+; SSE41-NEXT: movaps %xmm3, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v16f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm1
-; AVX-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
-; AVX-NEXT: vorps %ymm2, %ymm0, %ymm3
-; AVX-NEXT: vandps %ymm1, %ymm3, %ymm1
-; AVX-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
-; AVX-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
-; AVX-NEXT: vorps %xmm2, %xmm1, %xmm3
-; AVX-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX-NEXT: vmaxss %xmm4, %xmm1, %xmm4
-; AVX-NEXT: vandps %xmm4, %xmm3, %xmm3
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm4
-; AVX-NEXT: vblendvps %xmm4, %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vorps %xmm2, %xmm1, %xmm2
-; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vandps %xmm0, %xmm2, %xmm0
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm2
-; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v16f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxps %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vandps %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vmaxps %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vandps %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vmaxps %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vorps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX1-NEXT: vorps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v16f32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmaxps %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX2-NEXT: vorps %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vandps %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vmaxps %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vorps %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vandps %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vmaxps %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vorps %xmm2, %xmm0, %xmm4
+; AVX2-NEXT: vandps %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX2-NEXT: vmaxss %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vorps %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v16f32:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vmaxps %ymm1, %ymm0, %ymm1
-; AVX512BW-NEXT: vbroadcastss {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
-; AVX512BW-NEXT: vorps %ymm2, %ymm0, %ymm3
-; AVX512BW-NEXT: vandps %ymm1, %ymm3, %ymm1
-; AVX512BW-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
-; AVX512BW-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vmaxps %zmm1, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastd {{.*#+}} zmm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm1 & (zmm0 | zmm2)
+; AVX512BW-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovaps %zmm0, %zmm1 {%k1}
+; AVX512BW-NEXT: vextractf128 $1, %ymm1, %xmm0
+; AVX512BW-NEXT: vmaxps %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 & (zmm1 | zmm2)
+; AVX512BW-NEXT: vcmpunordps %zmm1, %zmm1, %k1
+; AVX512BW-NEXT: vmovaps %zmm1, %zmm0 {%k1}
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512BW-NEXT: vmaxps %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512BW-NEXT: vmaxss %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vorps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vandps %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512BW-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512BW-NEXT: vorps %xmm2, %xmm1, %xmm3
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX512BW-NEXT: vmaxss %xmm4, %xmm1, %xmm4
-; AVX512BW-NEXT: vandps %xmm4, %xmm3, %xmm3
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm1 & (zmm0 | zmm2)
+; AVX512BW-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovaps %zmm0, %zmm1 {%k1}
+; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; AVX512BW-NEXT: vmaxss %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vorps %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vandps %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vcmpunordss %xmm1, %xmm1, %k1
-; AVX512BW-NEXT: vmovss %xmm1, %xmm3, %xmm3 {%k1}
-; AVX512BW-NEXT: vorps %xmm2, %xmm3, %xmm1
-; AVX512BW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512BW-NEXT: vmaxss %xmm0, %xmm3, %xmm0
-; AVX512BW-NEXT: vandps %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512BW-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
; AVX512VL-LABEL: test_v16f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512VL-NEXT: vmaxps %ymm1, %ymm0, %ymm1
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
-; AVX512VL-NEXT: vpternlogd {{.*#+}} ymm1 = ymm1 & (ymm0 | ymm2)
-; AVX512VL-NEXT: vcmpunordps %ymm0, %ymm0, %k1
-; AVX512VL-NEXT: vmovaps %ymm0, %ymm1 {%k1}
-; AVX512VL-NEXT: vextractf128 $1, %ymm1, %xmm0
-; AVX512VL-NEXT: vmaxps %xmm0, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 & (xmm1 | xmm2)
-; AVX512VL-NEXT: vcmpunordps %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovaps %xmm1, %xmm0 {%k1}
-; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512VL-NEXT: vmaxss %xmm1, %xmm0, %xmm1
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm1 & (xmm0 | xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
-; AVX512VL-NEXT: vmaxss %xmm3, %xmm1, %xmm3
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm3 = xmm3 & (xmm1 | xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovss %xmm1, %xmm3, %xmm3 {%k1}
-; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512VL-NEXT: vmaxss %xmm0, %xmm3, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 & (xmm3 | xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmaxps %zmm1, %zmm0, %zmm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm1 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm2 = zmm2 & (zmm0 | zmm1)
+; AVX512VL-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovaps %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vextractf128 $1, %ymm2, %xmm0
+; AVX512VL-NEXT: vmaxps %zmm0, %zmm2, %zmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 & (zmm2 | zmm1)
+; AVX512VL-NEXT: vcmpunordps %zmm2, %zmm2, %k1
+; AVX512VL-NEXT: vmovaps %zmm2, %zmm0 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX512VL-NEXT: vmaxps %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm2 = zmm2 & (zmm0 | zmm1)
+; AVX512VL-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovaps %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; AVX512VL-NEXT: vmaxss %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm0 & (xmm1 | xmm2)
+; AVX512VL-NEXT: vcmpunordss %xmm2, %xmm2, %k1
+; AVX512VL-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovaps %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %a0)
@@ -659,18 +705,18 @@ define float @test_v16f32(<16 x float> %a0) {
define double @test_v2f64(<2 x double> %a0) {
; SSE2-LABEL: test_v2f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movapd %xmm0, %xmm2
-; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: movapd %xmm0, %xmm1
; SSE2-NEXT: cmpunordsd %xmm0, %xmm1
-; SSE2-NEXT: movapd %xmm1, %xmm3
-; SSE2-NEXT: andpd %xmm0, %xmm3
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: andpd %xmm0, %xmm2
+; SSE2-NEXT: movapd %xmm0, %xmm3
+; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: movapd %xmm0, %xmm4
-; SSE2-NEXT: maxsd %xmm2, %xmm4
+; SSE2-NEXT: maxsd %xmm3, %xmm4
; SSE2-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: andpd %xmm4, %xmm0
; SSE2-NEXT: andnpd %xmm0, %xmm1
-; SSE2-NEXT: orpd %xmm3, %xmm1
+; SSE2-NEXT: orpd %xmm2, %xmm1
; SSE2-NEXT: movapd %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -773,38 +819,57 @@ define double @test_v4f64(<4 x double> %a0) {
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v4f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [NaN,NaN]
-; AVX-NEXT: # xmm2 = mem[0,0]
-; AVX-NEXT: vorpd %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vandpd %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorpd %xmm2, %xmm0, %xmm2
-; AVX-NEXT: vandpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v4f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX1-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
+; AVX1-NEXT: vandpd %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [NaN,NaN]
+; AVX1-NEXT: # xmm2 = mem[0,0]
+; AVX1-NEXT: vorpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v4f64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vmovddup {{.*#+}} xmm3 = [NaN,NaN]
+; AVX2-NEXT: # xmm3 = mem[0,0]
+; AVX2-NEXT: vorpd %xmm3, %xmm0, %xmm4
+; AVX2-NEXT: vandpd %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vorpd %xmm3, %xmm0, %xmm2
+; AVX2-NEXT: vandpd %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v4f64:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512BW-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vmovddup {{.*#+}} xmm2 = [NaN,NaN]
-; AVX512BW-NEXT: # xmm2 = mem[0,0]
-; AVX512BW-NEXT: vorpd %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vandpd %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX512BW-NEXT: vmovddup {{.*#+}} xmm3 = [NaN,NaN]
+; AVX512BW-NEXT: # xmm3 = mem[0,0]
+; AVX512BW-NEXT: vorpd %xmm3, %xmm0, %xmm4
+; AVX512BW-NEXT: vandpd %xmm1, %xmm4, %xmm1
+; AVX512BW-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
; AVX512BW-NEXT: vmaxsd %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vorpd %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vorpd %xmm3, %xmm1, %xmm2
; AVX512BW-NEXT: vandpd %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
; AVX512BW-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
@@ -814,16 +879,17 @@ define double @test_v4f64(<4 x double> %a0) {
; AVX512VL-LABEL: test_v4f64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX512VL-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
-; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm2 = [NaN,NaN]
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = xmm1 & (xmm0 | xmm2)
-; AVX512VL-NEXT: vcmpunordpd %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovapd %xmm0, %xmm1 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
-; AVX512VL-NEXT: vmaxsd %xmm0, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm0 & (xmm1 | xmm2)
-; AVX512VL-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmaxpd %xmm1, %xmm0, %xmm2
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [NaN,NaN,NaN,NaN]
+; AVX512VL-NEXT: vpternlogq {{.*#+}} ymm2 = ymm2 & (ymm0 | ymm1)
+; AVX512VL-NEXT: vcmpunordpd %ymm0, %ymm0, %k1
+; AVX512VL-NEXT: vmovapd %ymm0, %ymm2 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
+; AVX512VL-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = xmm0 & (xmm1 | xmm2)
+; AVX512VL-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512VL-NEXT: vmovsd %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovapd %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %a0)
@@ -833,47 +899,47 @@ define double @test_v4f64(<4 x double> %a0) {
define double @test_v8f64(<8 x double> %a0) {
; SSE2-LABEL: test_v8f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movapd %xmm0, %xmm4
-; SSE2-NEXT: maxpd %xmm2, %xmm4
-; SSE2-NEXT: movapd {{.*#+}} xmm2 = [NaN,NaN]
-; SSE2-NEXT: movapd %xmm0, %xmm6
-; SSE2-NEXT: orpd %xmm2, %xmm6
-; SSE2-NEXT: andpd %xmm4, %xmm6
-; SSE2-NEXT: movapd %xmm0, %xmm5
-; SSE2-NEXT: cmpunordpd %xmm0, %xmm5
-; SSE2-NEXT: andpd %xmm5, %xmm0
-; SSE2-NEXT: andnpd %xmm6, %xmm5
-; SSE2-NEXT: orpd %xmm0, %xmm5
-; SSE2-NEXT: movapd %xmm5, %xmm4
-; SSE2-NEXT: cmpunordpd %xmm5, %xmm4
-; SSE2-NEXT: movapd %xmm5, %xmm0
-; SSE2-NEXT: andpd %xmm4, %xmm0
-; SSE2-NEXT: movapd %xmm1, %xmm6
-; SSE2-NEXT: maxpd %xmm3, %xmm6
-; SSE2-NEXT: movapd %xmm1, %xmm3
-; SSE2-NEXT: orpd %xmm2, %xmm3
-; SSE2-NEXT: andpd %xmm6, %xmm3
-; SSE2-NEXT: movapd %xmm1, %xmm6
-; SSE2-NEXT: cmpunordpd %xmm1, %xmm6
-; SSE2-NEXT: andpd %xmm6, %xmm1
-; SSE2-NEXT: andnpd %xmm3, %xmm6
-; SSE2-NEXT: orpd %xmm1, %xmm6
-; SSE2-NEXT: movapd %xmm5, %xmm1
-; SSE2-NEXT: maxpd %xmm6, %xmm1
-; SSE2-NEXT: orpd %xmm2, %xmm5
-; SSE2-NEXT: andpd %xmm1, %xmm5
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: maxpd %xmm3, %xmm4
+; SSE2-NEXT: movapd {{.*#+}} xmm3 = [NaN,NaN]
+; SSE2-NEXT: movapd %xmm1, %xmm5
+; SSE2-NEXT: orpd %xmm3, %xmm5
+; SSE2-NEXT: andpd %xmm4, %xmm5
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm4
+; SSE2-NEXT: andpd %xmm4, %xmm1
; SSE2-NEXT: andnpd %xmm5, %xmm4
-; SSE2-NEXT: orpd %xmm0, %xmm4
-; SSE2-NEXT: movapd %xmm4, %xmm0
-; SSE2-NEXT: cmpunordsd %xmm4, %xmm0
+; SSE2-NEXT: orpd %xmm1, %xmm4
; SSE2-NEXT: movapd %xmm0, %xmm1
-; SSE2-NEXT: andpd %xmm4, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[2,3,2,3]
-; SSE2-NEXT: movapd %xmm4, %xmm5
-; SSE2-NEXT: maxsd %xmm3, %xmm5
-; SSE2-NEXT: orpd %xmm2, %xmm4
-; SSE2-NEXT: andpd %xmm5, %xmm4
-; SSE2-NEXT: andnpd %xmm4, %xmm0
+; SSE2-NEXT: maxpd %xmm2, %xmm1
+; SSE2-NEXT: movapd %xmm0, %xmm2
+; SSE2-NEXT: orpd %xmm3, %xmm2
+; SSE2-NEXT: andpd %xmm1, %xmm2
+; SSE2-NEXT: movapd %xmm0, %xmm1
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm1
+; SSE2-NEXT: andpd %xmm1, %xmm0
+; SSE2-NEXT: andnpd %xmm2, %xmm1
+; SSE2-NEXT: orpd %xmm0, %xmm1
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm2
+; SSE2-NEXT: movapd %xmm1, %xmm0
+; SSE2-NEXT: andpd %xmm2, %xmm0
+; SSE2-NEXT: movapd %xmm1, %xmm5
+; SSE2-NEXT: maxpd %xmm4, %xmm5
+; SSE2-NEXT: orpd %xmm3, %xmm1
+; SSE2-NEXT: andpd %xmm5, %xmm1
+; SSE2-NEXT: andnpd %xmm1, %xmm2
+; SSE2-NEXT: orpd %xmm0, %xmm2
+; SSE2-NEXT: movapd %xmm2, %xmm0
+; SSE2-NEXT: cmpunordsd %xmm2, %xmm0
+; SSE2-NEXT: movapd %xmm0, %xmm1
+; SSE2-NEXT: andpd %xmm2, %xmm1
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[2,3,2,3]
+; SSE2-NEXT: movapd %xmm2, %xmm5
+; SSE2-NEXT: maxsd %xmm4, %xmm5
+; SSE2-NEXT: orpd %xmm3, %xmm2
+; SSE2-NEXT: andpd %xmm5, %xmm2
+; SSE2-NEXT: andnpd %xmm2, %xmm0
; SSE2-NEXT: orpd %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -917,71 +983,95 @@ define double @test_v8f64(<8 x double> %a0) {
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v8f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
-; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
-; AVX-NEXT: vorpd %ymm2, %ymm0, %ymm3
-; AVX-NEXT: vandpd %ymm1, %ymm3, %ymm1
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
-; AVX-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorpd %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vandpd %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorpd %xmm2, %xmm0, %xmm2
-; AVX-NEXT: vandpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v8f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
+; AVX1-NEXT: vorpd %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vandpd %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vorpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [NaN,NaN]
+; AVX1-NEXT: # xmm2 = mem[0,0]
+; AVX1-NEXT: vorpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8f64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
+; AVX2-NEXT: vorpd %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vandpd %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vorpd %xmm2, %xmm0, %xmm4
+; AVX2-NEXT: vandpd %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vorpd %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vandpd %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v8f64:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
-; AVX512BW-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
-; AVX512BW-NEXT: vorpd %ymm2, %ymm0, %ymm3
-; AVX512BW-NEXT: vandpd %ymm1, %ymm3, %ymm1
-; AVX512BW-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
-; AVX512BW-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX512BW-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vorpd %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vandpd %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
-; AVX512BW-NEXT: vmaxsd %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vorpd %xmm2, %xmm1, %xmm2
-; AVX512BW-NEXT: vandpd %xmm0, %xmm2, %xmm0
-; AVX512BW-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512BW-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: vmaxpd %zmm1, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} zmm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 & (zmm0 | zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovapd %zmm0, %zmm1 {%k1}
+; AVX512BW-NEXT: vextractf128 $1, %ymm1, %xmm0
+; AVX512BW-NEXT: vmaxpd %xmm0, %xmm1, %xmm3
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm3 = zmm3 & (zmm1 | zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm1, %zmm1, %k1
+; AVX512BW-NEXT: vmovapd %zmm1, %zmm3 {%k1}
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm3[1,0]
+; AVX512BW-NEXT: vmaxsd %xmm0, %xmm3, %xmm0
+; AVX512BW-NEXT: vorpd %xmm2, %xmm3, %xmm1
+; AVX512BW-NEXT: vandpd %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vcmpunordsd %xmm3, %xmm3, %k1
+; AVX512BW-NEXT: vmovsd %xmm3, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
; AVX512VL-LABEL: test_v8f64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512VL-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
-; AVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
-; AVX512VL-NEXT: vpternlogq {{.*#+}} ymm1 = ymm1 & (ymm0 | ymm2)
-; AVX512VL-NEXT: vcmpunordpd %ymm0, %ymm0, %k1
-; AVX512VL-NEXT: vmovapd %ymm0, %ymm1 {%k1}
-; AVX512VL-NEXT: vextractf128 $1, %ymm1, %xmm0
-; AVX512VL-NEXT: vmaxpd %xmm0, %xmm1, %xmm3
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm3 = xmm3 & (xmm1 | xmm2)
-; AVX512VL-NEXT: vcmpunordpd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovapd %xmm1, %xmm3 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm3[1,0]
-; AVX512VL-NEXT: vmaxsd %xmm0, %xmm3, %xmm0
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm0 & (xmm3 | xmm2)
-; AVX512VL-NEXT: vcmpunordsd %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovsd %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmaxpd %zmm1, %zmm0, %zmm2
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm1 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm2 = zmm2 & (zmm0 | zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovapd %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vextractf128 $1, %ymm2, %xmm0
+; AVX512VL-NEXT: vmaxpd %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm0 = zmm0 & (zmm2 | zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm2, %zmm2, %k1
+; AVX512VL-NEXT: vmovapd %zmm2, %zmm0 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX512VL-NEXT: vmaxsd %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = xmm2 & (xmm1 | xmm0)
+; AVX512VL-NEXT: vcmpunordsd %xmm0, %xmm0, %k1
+; AVX512VL-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovapd %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> %a0)
@@ -991,86 +1081,86 @@ define double @test_v8f64(<8 x double> %a0) {
define double @test_v16f64(<16 x double> %a0) {
; SSE2-LABEL: test_v16f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movapd %xmm0, %xmm8
-; SSE2-NEXT: maxpd %xmm4, %xmm8
-; SSE2-NEXT: movapd {{.*#+}} xmm4 = [NaN,NaN]
-; SSE2-NEXT: movapd %xmm0, %xmm9
-; SSE2-NEXT: orpd %xmm4, %xmm9
+; SSE2-NEXT: movapd %xmm2, %xmm8
+; SSE2-NEXT: maxpd %xmm6, %xmm8
+; SSE2-NEXT: movapd {{.*#+}} xmm6 = [NaN,NaN]
+; SSE2-NEXT: movapd %xmm2, %xmm9
+; SSE2-NEXT: orpd %xmm6, %xmm9
; SSE2-NEXT: andpd %xmm8, %xmm9
-; SSE2-NEXT: movapd %xmm0, %xmm8
-; SSE2-NEXT: cmpunordpd %xmm0, %xmm8
-; SSE2-NEXT: andpd %xmm8, %xmm0
+; SSE2-NEXT: movapd %xmm2, %xmm8
+; SSE2-NEXT: cmpunordpd %xmm2, %xmm8
+; SSE2-NEXT: andpd %xmm8, %xmm2
; SSE2-NEXT: andnpd %xmm9, %xmm8
-; SSE2-NEXT: orpd %xmm0, %xmm8
-; SSE2-NEXT: movapd %xmm8, %xmm0
-; SSE2-NEXT: cmpunordpd %xmm8, %xmm0
-; SSE2-NEXT: movapd %xmm8, %xmm9
-; SSE2-NEXT: andpd %xmm0, %xmm9
-; SSE2-NEXT: movapd %xmm2, %xmm10
-; SSE2-NEXT: maxpd %xmm6, %xmm10
-; SSE2-NEXT: movapd %xmm2, %xmm6
-; SSE2-NEXT: orpd %xmm4, %xmm6
-; SSE2-NEXT: andpd %xmm10, %xmm6
-; SSE2-NEXT: movapd %xmm2, %xmm10
-; SSE2-NEXT: cmpunordpd %xmm2, %xmm10
-; SSE2-NEXT: andpd %xmm10, %xmm2
-; SSE2-NEXT: andnpd %xmm6, %xmm10
-; SSE2-NEXT: orpd %xmm2, %xmm10
-; SSE2-NEXT: movapd %xmm8, %xmm2
-; SSE2-NEXT: maxpd %xmm10, %xmm2
-; SSE2-NEXT: orpd %xmm4, %xmm8
-; SSE2-NEXT: andpd %xmm2, %xmm8
-; SSE2-NEXT: andnpd %xmm8, %xmm0
-; SSE2-NEXT: orpd %xmm9, %xmm0
+; SSE2-NEXT: orpd %xmm2, %xmm8
+; SSE2-NEXT: movapd %xmm0, %xmm2
+; SSE2-NEXT: maxpd %xmm4, %xmm2
+; SSE2-NEXT: movapd %xmm0, %xmm4
+; SSE2-NEXT: orpd %xmm6, %xmm4
+; SSE2-NEXT: andpd %xmm2, %xmm4
; SSE2-NEXT: movapd %xmm0, %xmm2
; SSE2-NEXT: cmpunordpd %xmm0, %xmm2
-; SSE2-NEXT: movapd %xmm0, %xmm6
-; SSE2-NEXT: andpd %xmm2, %xmm6
-; SSE2-NEXT: movapd %xmm1, %xmm8
-; SSE2-NEXT: maxpd %xmm5, %xmm8
-; SSE2-NEXT: movapd %xmm1, %xmm9
-; SSE2-NEXT: orpd %xmm4, %xmm9
-; SSE2-NEXT: andpd %xmm8, %xmm9
-; SSE2-NEXT: movapd %xmm1, %xmm5
-; SSE2-NEXT: cmpunordpd %xmm1, %xmm5
-; SSE2-NEXT: andpd %xmm5, %xmm1
-; SSE2-NEXT: andnpd %xmm9, %xmm5
-; SSE2-NEXT: orpd %xmm1, %xmm5
-; SSE2-NEXT: movapd %xmm5, %xmm1
-; SSE2-NEXT: cmpunordpd %xmm5, %xmm1
-; SSE2-NEXT: movapd %xmm5, %xmm8
-; SSE2-NEXT: andpd %xmm1, %xmm8
-; SSE2-NEXT: movapd %xmm3, %xmm9
-; SSE2-NEXT: maxpd %xmm7, %xmm9
+; SSE2-NEXT: andpd %xmm2, %xmm0
+; SSE2-NEXT: andnpd %xmm4, %xmm2
+; SSE2-NEXT: orpd %xmm0, %xmm2
+; SSE2-NEXT: movapd %xmm3, %xmm0
+; SSE2-NEXT: maxpd %xmm7, %xmm0
+; SSE2-NEXT: movapd %xmm3, %xmm4
+; SSE2-NEXT: orpd %xmm6, %xmm4
+; SSE2-NEXT: andpd %xmm0, %xmm4
; SSE2-NEXT: movapd %xmm3, %xmm7
-; SSE2-NEXT: orpd %xmm4, %xmm7
-; SSE2-NEXT: andpd %xmm9, %xmm7
-; SSE2-NEXT: movapd %xmm3, %xmm9
-; SSE2-NEXT: cmpunordpd %xmm3, %xmm9
-; SSE2-NEXT: andpd %xmm9, %xmm3
-; SSE2-NEXT: andnpd %xmm7, %xmm9
-; SSE2-NEXT: orpd %xmm3, %xmm9
-; SSE2-NEXT: movapd %xmm5, %xmm3
-; SSE2-NEXT: maxpd %xmm9, %xmm3
-; SSE2-NEXT: orpd %xmm4, %xmm5
-; SSE2-NEXT: andpd %xmm3, %xmm5
-; SSE2-NEXT: andnpd %xmm5, %xmm1
-; SSE2-NEXT: orpd %xmm8, %xmm1
-; SSE2-NEXT: movapd %xmm0, %xmm3
-; SSE2-NEXT: maxpd %xmm1, %xmm3
-; SSE2-NEXT: orpd %xmm4, %xmm0
-; SSE2-NEXT: andpd %xmm3, %xmm0
-; SSE2-NEXT: andnpd %xmm0, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm3, %xmm7
+; SSE2-NEXT: andpd %xmm7, %xmm3
+; SSE2-NEXT: andnpd %xmm4, %xmm7
+; SSE2-NEXT: orpd %xmm3, %xmm7
+; SSE2-NEXT: movapd %xmm1, %xmm0
+; SSE2-NEXT: maxpd %xmm5, %xmm0
+; SSE2-NEXT: movapd %xmm1, %xmm3
+; SSE2-NEXT: orpd %xmm6, %xmm3
+; SSE2-NEXT: andpd %xmm0, %xmm3
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm4
+; SSE2-NEXT: andpd %xmm4, %xmm1
+; SSE2-NEXT: andnpd %xmm3, %xmm4
+; SSE2-NEXT: orpd %xmm1, %xmm4
+; SSE2-NEXT: movapd %xmm4, %xmm0
+; SSE2-NEXT: cmpunordpd %xmm4, %xmm0
+; SSE2-NEXT: movapd %xmm4, %xmm1
+; SSE2-NEXT: andpd %xmm0, %xmm1
+; SSE2-NEXT: movapd %xmm4, %xmm3
+; SSE2-NEXT: maxpd %xmm7, %xmm3
+; SSE2-NEXT: orpd %xmm6, %xmm4
+; SSE2-NEXT: andpd %xmm3, %xmm4
+; SSE2-NEXT: andnpd %xmm4, %xmm0
+; SSE2-NEXT: orpd %xmm1, %xmm0
+; SSE2-NEXT: movapd %xmm2, %xmm1
+; SSE2-NEXT: cmpunordpd %xmm2, %xmm1
+; SSE2-NEXT: movapd %xmm2, %xmm3
+; SSE2-NEXT: andpd %xmm1, %xmm3
+; SSE2-NEXT: movapd %xmm2, %xmm4
+; SSE2-NEXT: maxpd %xmm8, %xmm4
; SSE2-NEXT: orpd %xmm6, %xmm2
+; SSE2-NEXT: andpd %xmm4, %xmm2
+; SSE2-NEXT: andnpd %xmm2, %xmm1
+; SSE2-NEXT: orpd %xmm3, %xmm1
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm2
+; SSE2-NEXT: movapd %xmm1, %xmm3
+; SSE2-NEXT: andpd %xmm2, %xmm3
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: maxpd %xmm0, %xmm4
+; SSE2-NEXT: orpd %xmm6, %xmm1
+; SSE2-NEXT: andpd %xmm4, %xmm1
+; SSE2-NEXT: andnpd %xmm1, %xmm2
+; SSE2-NEXT: orpd %xmm3, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm0
; SSE2-NEXT: cmpunordsd %xmm2, %xmm0
; SSE2-NEXT: movapd %xmm0, %xmm1
; SSE2-NEXT: andpd %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
-; SSE2-NEXT: movapd %xmm2, %xmm5
-; SSE2-NEXT: maxsd %xmm3, %xmm5
-; SSE2-NEXT: orpd %xmm4, %xmm2
-; SSE2-NEXT: andpd %xmm5, %xmm2
+; SSE2-NEXT: movapd %xmm2, %xmm4
+; SSE2-NEXT: maxsd %xmm3, %xmm4
+; SSE2-NEXT: orpd %xmm6, %xmm2
+; SSE2-NEXT: andpd %xmm4, %xmm2
; SSE2-NEXT: andnpd %xmm2, %xmm0
; SSE2-NEXT: orpd %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -1078,51 +1168,51 @@ define double @test_v16f64(<16 x double> %a0) {
; SSE41-LABEL: test_v16f64:
; SSE41: # %bb.0:
; SSE41-NEXT: movapd %xmm0, %xmm8
+; SSE41-NEXT: movapd %xmm2, %xmm0
+; SSE41-NEXT: maxpd %xmm6, %xmm0
+; SSE41-NEXT: movapd {{.*#+}} xmm6 = [NaN,NaN]
+; SSE41-NEXT: movapd %xmm2, %xmm9
+; SSE41-NEXT: orpd %xmm6, %xmm9
+; SSE41-NEXT: andpd %xmm0, %xmm9
+; SSE41-NEXT: movapd %xmm2, %xmm0
+; SSE41-NEXT: cmpunordpd %xmm2, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm9
+; SSE41-NEXT: movapd %xmm8, %xmm0
+; SSE41-NEXT: maxpd %xmm4, %xmm0
+; SSE41-NEXT: movapd %xmm8, %xmm2
+; SSE41-NEXT: orpd %xmm6, %xmm2
+; SSE41-NEXT: andpd %xmm0, %xmm2
+; SSE41-NEXT: movapd %xmm8, %xmm0
+; SSE41-NEXT: cmpunordpd %xmm8, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm8, %xmm2
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: maxpd %xmm7, %xmm0
-; SSE41-NEXT: movapd {{.*#+}} xmm7 = [NaN,NaN]
-; SSE41-NEXT: movapd %xmm3, %xmm9
-; SSE41-NEXT: orpd %xmm7, %xmm9
-; SSE41-NEXT: andpd %xmm0, %xmm9
+; SSE41-NEXT: movapd %xmm3, %xmm4
+; SSE41-NEXT: orpd %xmm6, %xmm4
+; SSE41-NEXT: andpd %xmm0, %xmm4
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: cmpunordpd %xmm3, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm9
+; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm4
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: maxpd %xmm5, %xmm0
; SSE41-NEXT: movapd %xmm1, %xmm3
-; SSE41-NEXT: orpd %xmm7, %xmm3
+; SSE41-NEXT: orpd %xmm6, %xmm3
; SSE41-NEXT: andpd %xmm0, %xmm3
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordpd %xmm1, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3
; SSE41-NEXT: movapd %xmm3, %xmm0
-; SSE41-NEXT: maxpd %xmm9, %xmm0
+; SSE41-NEXT: maxpd %xmm4, %xmm0
; SSE41-NEXT: movapd %xmm3, %xmm1
-; SSE41-NEXT: orpd %xmm7, %xmm1
+; SSE41-NEXT: orpd %xmm6, %xmm1
; SSE41-NEXT: andpd %xmm0, %xmm1
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: cmpunordpd %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1
; SSE41-NEXT: movapd %xmm2, %xmm0
-; SSE41-NEXT: maxpd %xmm6, %xmm0
-; SSE41-NEXT: movapd %xmm2, %xmm3
-; SSE41-NEXT: orpd %xmm7, %xmm3
-; SSE41-NEXT: andpd %xmm0, %xmm3
-; SSE41-NEXT: movapd %xmm2, %xmm0
-; SSE41-NEXT: cmpunordpd %xmm2, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm3
-; SSE41-NEXT: movapd %xmm8, %xmm0
-; SSE41-NEXT: maxpd %xmm4, %xmm0
-; SSE41-NEXT: movapd %xmm8, %xmm2
-; SSE41-NEXT: orpd %xmm7, %xmm2
-; SSE41-NEXT: andpd %xmm0, %xmm2
-; SSE41-NEXT: movapd %xmm8, %xmm0
-; SSE41-NEXT: cmpunordpd %xmm8, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm8, %xmm2
-; SSE41-NEXT: movapd %xmm2, %xmm0
-; SSE41-NEXT: maxpd %xmm3, %xmm0
+; SSE41-NEXT: maxpd %xmm9, %xmm0
; SSE41-NEXT: movapd %xmm2, %xmm3
-; SSE41-NEXT: orpd %xmm7, %xmm3
+; SSE41-NEXT: orpd %xmm6, %xmm3
; SSE41-NEXT: andpd %xmm0, %xmm3
; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: cmpunordpd %xmm2, %xmm0
@@ -1130,7 +1220,7 @@ define double @test_v16f64(<16 x double> %a0) {
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: maxpd %xmm1, %xmm0
; SSE41-NEXT: movapd %xmm3, %xmm1
-; SSE41-NEXT: orpd %xmm7, %xmm1
+; SSE41-NEXT: orpd %xmm6, %xmm1
; SSE41-NEXT: andpd %xmm0, %xmm1
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: cmpunordpd %xmm3, %xmm0
@@ -1139,46 +1229,81 @@ define double @test_v16f64(<16 x double> %a0) {
; SSE41-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE41-NEXT: movapd %xmm1, %xmm2
; SSE41-NEXT: maxsd %xmm0, %xmm2
-; SSE41-NEXT: orpd %xmm1, %xmm7
-; SSE41-NEXT: andpd %xmm2, %xmm7
+; SSE41-NEXT: orpd %xmm1, %xmm6
+; SSE41-NEXT: andpd %xmm2, %xmm6
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordsd %xmm1, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm7
-; SSE41-NEXT: movapd %xmm7, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm6
+; SSE41-NEXT: movapd %xmm6, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v16f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxpd %ymm3, %ymm1, %ymm3
-; AVX-NEXT: vbroadcastsd {{.*#+}} ymm4 = [NaN,NaN,NaN,NaN]
-; AVX-NEXT: vorpd %ymm4, %ymm1, %ymm5
-; AVX-NEXT: vandpd %ymm3, %ymm5, %ymm3
-; AVX-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm5
-; AVX-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
-; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm2
-; AVX-NEXT: vorpd %ymm4, %ymm0, %ymm3
-; AVX-NEXT: vandpd %ymm2, %ymm3, %ymm2
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
-; AVX-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
-; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
-; AVX-NEXT: vorpd %ymm4, %ymm0, %ymm2
-; AVX-NEXT: vandpd %ymm1, %ymm2, %ymm1
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
-; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorpd %xmm4, %xmm0, %xmm2
-; AVX-NEXT: vandpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorpd %xmm4, %xmm0, %xmm2
-; AVX-NEXT: vandpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v16f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxpd %ymm3, %ymm1, %ymm3
+; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm4 = [NaN,NaN,NaN,NaN]
+; AVX1-NEXT: vorpd %ymm4, %ymm1, %ymm5
+; AVX1-NEXT: vandpd %ymm3, %ymm5, %ymm3
+; AVX1-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm5
+; AVX1-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vmaxpd %ymm2, %ymm0, %ymm2
+; AVX1-NEXT: vorpd %ymm4, %ymm0, %ymm3
+; AVX1-NEXT: vandpd %ymm2, %ymm3, %ymm2
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
+; AVX1-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vorpd %ymm4, %ymm0, %ymm2
+; AVX1-NEXT: vandpd %ymm1, %ymm2, %ymm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX1-NEXT: vorpd %xmm4, %xmm0, %xmm3
+; AVX1-NEXT: vandpd %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [NaN,NaN]
+; AVX1-NEXT: # xmm2 = mem[0,0]
+; AVX1-NEXT: vorpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vandpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v16f64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmaxpd %ymm3, %ymm1, %ymm3
+; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm4 = [NaN,NaN,NaN,NaN]
+; AVX2-NEXT: vorpd %ymm4, %ymm1, %ymm5
+; AVX2-NEXT: vandpd %ymm3, %ymm5, %ymm3
+; AVX2-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm5
+; AVX2-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vmaxpd %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vorpd %ymm4, %ymm0, %ymm3
+; AVX2-NEXT: vandpd %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
+; AVX2-NEXT: vmaxpd %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vorpd %ymm4, %ymm0, %ymm2
+; AVX2-NEXT: vandpd %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vorpd %xmm4, %xmm0, %xmm3
+; AVX2-NEXT: vandpd %xmm1, %xmm3, %xmm1
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vorpd %xmm4, %xmm0, %xmm2
+; AVX2-NEXT: vandpd %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v16f64:
; AVX512BW: # %bb.0:
@@ -1188,17 +1313,15 @@ define double @test_v16f64(<16 x double> %a0) {
; AVX512BW-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
; AVX512BW-NEXT: vmovapd %zmm0, %zmm1 {%k1}
; AVX512BW-NEXT: vextractf64x4 $1, %zmm1, %ymm0
-; AVX512BW-NEXT: vmaxpd %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vorpd %ymm2, %ymm1, %ymm3
-; AVX512BW-NEXT: vandpd %ymm0, %ymm3, %ymm0
-; AVX512BW-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm3
-; AVX512BW-NEXT: vblendvpd %ymm3, %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vmaxpd %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm0 = zmm0 & (zmm1 | zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm1, %zmm1, %k1
+; AVX512BW-NEXT: vmovapd %zmm1, %zmm0 {%k1}
; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512BW-NEXT: vmaxpd %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vorpd %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vandpd %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 & (zmm0 | zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovapd %zmm0, %zmm1 {%k1}
; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
; AVX512BW-NEXT: vmaxsd %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vorpd %xmm2, %xmm1, %xmm2
@@ -1210,27 +1333,27 @@ define double @test_v16f64(<16 x double> %a0) {
;
; AVX512VL-LABEL: test_v16f64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmaxpd %zmm1, %zmm0, %zmm1
-; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
-; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 & (zmm0 | zmm2)
+; AVX512VL-NEXT: vmaxpd %zmm1, %zmm0, %zmm2
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm1 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm2 = zmm2 & (zmm0 | zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovapd %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vextractf64x4 $1, %zmm2, %ymm0
+; AVX512VL-NEXT: vmaxpd %zmm0, %zmm2, %zmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm0 = zmm0 & (zmm2 | zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm2, %zmm2, %k1
+; AVX512VL-NEXT: vmovapd %zmm2, %zmm0 {%k1}
+; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX512VL-NEXT: vmaxpd %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm2 = zmm2 & (zmm0 | zmm1)
; AVX512VL-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
-; AVX512VL-NEXT: vmovapd %zmm0, %zmm1 {%k1}
-; AVX512VL-NEXT: vextractf64x4 $1, %zmm1, %ymm0
-; AVX512VL-NEXT: vmaxpd %ymm0, %ymm1, %ymm0
-; AVX512VL-NEXT: vmovdqa %ymm2, %ymm3
-; AVX512VL-NEXT: vpternlogq {{.*#+}} ymm3 = ymm0 & (ymm3 | ymm1)
-; AVX512VL-NEXT: vcmpunordpd %ymm1, %ymm1, %k1
-; AVX512VL-NEXT: vmovapd %ymm1, %ymm3 {%k1}
-; AVX512VL-NEXT: vextractf128 $1, %ymm3, %xmm0
-; AVX512VL-NEXT: vmaxpd %xmm0, %xmm3, %xmm1
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = xmm1 & (xmm3 | xmm2)
-; AVX512VL-NEXT: vcmpunordpd %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovapd %xmm3, %xmm1 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
-; AVX512VL-NEXT: vmaxsd %xmm0, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm0 & (xmm1 | xmm2)
-; AVX512VL-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmovapd %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
+; AVX512VL-NEXT: vmaxsd %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = xmm0 & (xmm1 | xmm2)
+; AVX512VL-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512VL-NEXT: vmovsd %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovapd %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> %a0)
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fminimum.ll b/llvm/test/CodeGen/X86/vector-reduce-fminimum.ll
index 2c85839f3a266..b80a1fa68bafd 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fminimum.ll
@@ -97,304 +97,201 @@ define float @test_v2f32(<2 x float> %a0) {
ret float %1
}
-define float @test_v4f32(<4 x float> %a0) {
-; SSE2-LABEL: test_v4f32:
+define float @test_v3f32(<3 x float> %a0) {
+; SSE2-LABEL: test_v3f32:
; SSE2: # %bb.0:
+; SSE2-NEXT: movaps {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: andps %xmm2, %xmm1
; SSE2-NEXT: movaps %xmm0, %xmm3
-; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: movaps %xmm0, %xmm5
-; SSE2-NEXT: movaps %xmm0, %xmm6
-; SSE2-NEXT: cmpunordss %xmm0, %xmm6
-; SSE2-NEXT: movaps %xmm6, %xmm7
-; SSE2-NEXT: andps %xmm0, %xmm6
-; SSE2-NEXT: movaps %xmm0, %xmm2
-; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm0[3,3]
-; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[1,1]
-; SSE2-NEXT: minss %xmm3, %xmm5
-; SSE2-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; SSE2-NEXT: movaps %xmm0, %xmm4
+; SSE2-NEXT: minss %xmm3, %xmm4
+; SSE2-NEXT: orps %xmm1, %xmm4
+; SSE2-NEXT: movaps %xmm0, %xmm3
+; SSE2-NEXT: cmpunordss %xmm0, %xmm3
+; SSE2-NEXT: movaps %xmm3, %xmm1
+; SSE2-NEXT: andnps %xmm4, %xmm1
+; SSE2-NEXT: andps %xmm0, %xmm3
+; SSE2-NEXT: orps %xmm1, %xmm3
+; SSE2-NEXT: movaps %xmm3, %xmm1
+; SSE2-NEXT: cmpunordss %xmm3, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm4
; SSE2-NEXT: andps %xmm3, %xmm4
-; SSE2-NEXT: orps %xmm4, %xmm5
-; SSE2-NEXT: andnps %xmm5, %xmm7
-; SSE2-NEXT: orps %xmm7, %xmm6
-; SSE2-NEXT: movaps %xmm6, %xmm4
-; SSE2-NEXT: cmpunordss %xmm6, %xmm4
-; SSE2-NEXT: movaps %xmm4, %xmm0
-; SSE2-NEXT: andps %xmm6, %xmm0
-; SSE2-NEXT: movaps %xmm6, %xmm5
-; SSE2-NEXT: andps %xmm3, %xmm5
-; SSE2-NEXT: minss %xmm1, %xmm6
-; SSE2-NEXT: orps %xmm5, %xmm6
-; SSE2-NEXT: andnps %xmm6, %xmm4
-; SSE2-NEXT: orps %xmm0, %xmm4
-; SSE2-NEXT: movaps %xmm4, %xmm0
-; SSE2-NEXT: cmpunordss %xmm4, %xmm0
-; SSE2-NEXT: movaps %xmm0, %xmm1
-; SSE2-NEXT: andps %xmm4, %xmm1
-; SSE2-NEXT: andps %xmm4, %xmm3
-; SSE2-NEXT: minss %xmm2, %xmm4
-; SSE2-NEXT: orps %xmm3, %xmm4
-; SSE2-NEXT: andnps %xmm4, %xmm0
-; SSE2-NEXT: orps %xmm1, %xmm0
+; SSE2-NEXT: andps %xmm3, %xmm2
+; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; SSE2-NEXT: minss %xmm0, %xmm3
+; SSE2-NEXT: orps %xmm2, %xmm3
+; SSE2-NEXT: andnps %xmm3, %xmm1
+; SSE2-NEXT: orps %xmm4, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: test_v4f32:
+; SSE41-LABEL: test_v3f32:
; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1
-; SSE41-NEXT: movaps %xmm0, %xmm3
-; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE41-NEXT: movaps {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; SSE41-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; SSE41-NEXT: andps %xmm3, %xmm0
+; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; SSE41-NEXT: movaps %xmm1, %xmm4
-; SSE41-NEXT: andps %xmm2, %xmm4
-; SSE41-NEXT: movaps %xmm1, %xmm5
-; SSE41-NEXT: minss %xmm0, %xmm5
-; SSE41-NEXT: orps %xmm4, %xmm5
+; SSE41-NEXT: minss %xmm2, %xmm4
+; SSE41-NEXT: orps %xmm0, %xmm4
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: cmpunordss %xmm1, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm5
-; SSE41-NEXT: movaps %xmm1, %xmm4
-; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm1[3,3]
-; SSE41-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1]
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: andps %xmm2, %xmm0
-; SSE41-NEXT: movaps %xmm5, %xmm6
-; SSE41-NEXT: minss %xmm3, %xmm6
-; SSE41-NEXT: orps %xmm0, %xmm6
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: cmpunordss %xmm5, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm6
-; SSE41-NEXT: andps %xmm6, %xmm2
-; SSE41-NEXT: movaps %xmm6, %xmm1
-; SSE41-NEXT: minss %xmm4, %xmm1
-; SSE41-NEXT: orps %xmm2, %xmm1
-; SSE41-NEXT: movaps %xmm6, %xmm0
-; SSE41-NEXT: cmpunordss %xmm6, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm6, %xmm1
-; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm4
+; SSE41-NEXT: andps %xmm4, %xmm3
+; SSE41-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
+; SSE41-NEXT: movaps %xmm4, %xmm2
+; SSE41-NEXT: minss %xmm1, %xmm2
+; SSE41-NEXT: orps %xmm3, %xmm2
+; SSE41-NEXT: movaps %xmm4, %xmm0
+; SSE41-NEXT: cmpunordss %xmm4, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm2
+; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v4f32:
+; AVX-LABEL: test_v3f32:
; AVX: # %bb.0:
-; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX-NEXT: vandps %xmm1, %xmm0, %xmm2
; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX-NEXT: vbroadcastss {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX-NEXT: vandps %xmm4, %xmm0, %xmm5
; AVX-NEXT: vminss %xmm3, %xmm0, %xmm3
-; AVX-NEXT: vorps %xmm3, %xmm5, %xmm3
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm5
-; AVX-NEXT: vblendvps %xmm5, %xmm0, %xmm3, %xmm0
-; AVX-NEXT: vandps %xmm4, %xmm0, %xmm3
-; AVX-NEXT: vminss %xmm2, %xmm0, %xmm2
-; AVX-NEXT: vorps %xmm2, %xmm3, %xmm2
+; AVX-NEXT: vorps %xmm3, %xmm2, %xmm2
; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm2, %xmm0
-; AVX-NEXT: vandps %xmm4, %xmm0, %xmm2
-; AVX-NEXT: vminss %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vorps %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm2, %xmm2
+; AVX-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT: vminss %xmm0, %xmm2, %xmm0
+; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vcmpunordss %xmm2, %xmm2, %xmm1
+; AVX-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq
;
-; AVX512BW-LABEL: test_v4f32:
+; AVX512BW-LABEL: test_v3f32:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX512BW-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512BW-NEXT: vandps %xmm1, %xmm0, %xmm2
; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX512BW-NEXT: vbroadcastss {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512BW-NEXT: vandps %xmm4, %xmm0, %xmm5
; AVX512BW-NEXT: vminss %xmm3, %xmm0, %xmm3
-; AVX512BW-NEXT: vorps %xmm3, %xmm5, %xmm3
+; AVX512BW-NEXT: vorps %xmm3, %xmm2, %xmm2
; AVX512BW-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512BW-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k1}
-; AVX512BW-NEXT: vandps %xmm4, %xmm3, %xmm0
-; AVX512BW-NEXT: vminss %xmm2, %xmm3, %xmm2
-; AVX512BW-NEXT: vorps %xmm2, %xmm0, %xmm2
-; AVX512BW-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512BW-NEXT: vmovss %xmm3, %xmm2, %xmm2 {%k1}
-; AVX512BW-NEXT: vandps %xmm4, %xmm2, %xmm0
-; AVX512BW-NEXT: vminss %xmm1, %xmm2, %xmm1
-; AVX512BW-NEXT: vorps %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512BW-NEXT: vandps %xmm1, %xmm2, %xmm1
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX512BW-NEXT: vminss %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vcmpunordss %xmm2, %xmm2, %k1
; AVX512BW-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: retq
;
-; AVX512VL-LABEL: test_v4f32:
+; AVX512VL-LABEL: test_v3f32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX512VL-NEXT: vminss %xmm3, %xmm0, %xmm3
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm3 = xmm3 | (xmm0 & xmm4)
+; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX512VL-NEXT: vminss %xmm1, %xmm0, %xmm1
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm1 | (xmm0 & xmm2)
; AVX512VL-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k1}
-; AVX512VL-NEXT: vminss %xmm2, %xmm3, %xmm2
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm2 = xmm2 | (xmm3 & xmm4)
-; AVX512VL-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovss %xmm3, %xmm2, %xmm2 {%k1}
-; AVX512VL-NEXT: vminss %xmm1, %xmm2, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 | (xmm2 & xmm4)
-; AVX512VL-NEXT: vcmpunordss %xmm2, %xmm2, %k1
-; AVX512VL-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX512VL-NEXT: vminss %xmm0, %xmm1, %xmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 | (xmm1 & xmm2)
+; AVX512VL-NEXT: vcmpunordss %xmm1, %xmm1, %k1
+; AVX512VL-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; AVX512VL-NEXT: retq
- %1 = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %a0)
+ %1 = call float @llvm.vector.reduce.fminimum.v3f32(<3 x float> %a0)
ret float %1
}
-define float @test_v8f32(<8 x float> %a0) {
-; SSE2-LABEL: test_v8f32:
+define float @test_v4f32(<4 x float> %a0) {
+; SSE2-LABEL: test_v4f32:
; SSE2: # %bb.0:
-; SSE2-NEXT: movaps %xmm0, %xmm2
-; SSE2-NEXT: minps %xmm1, %xmm2
-; SSE2-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; SSE2-NEXT: movaps %xmm0, %xmm3
-; SSE2-NEXT: andps %xmm1, %xmm3
-; SSE2-NEXT: orps %xmm2, %xmm3
-; SSE2-NEXT: movaps %xmm0, %xmm2
-; SSE2-NEXT: cmpunordps %xmm0, %xmm2
-; SSE2-NEXT: andps %xmm2, %xmm0
-; SSE2-NEXT: andnps %xmm3, %xmm2
-; SSE2-NEXT: orps %xmm0, %xmm2
-; SSE2-NEXT: movaps %xmm2, %xmm0
-; SSE2-NEXT: cmpunordss %xmm2, %xmm0
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
+; SSE2-NEXT: movaps {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: andps %xmm2, %xmm3
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
-; SSE2-NEXT: movaps %xmm2, %xmm5
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm2[2,3,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm2[3,3,3,3]
-; SSE2-NEXT: minss %xmm4, %xmm2
-; SSE2-NEXT: andps %xmm1, %xmm5
-; SSE2-NEXT: orps %xmm2, %xmm5
-; SSE2-NEXT: andnps %xmm5, %xmm0
-; SSE2-NEXT: orps %xmm3, %xmm0
-; SSE2-NEXT: movaps %xmm0, %xmm2
-; SSE2-NEXT: cmpunordss %xmm0, %xmm2
-; SSE2-NEXT: movaps %xmm2, %xmm3
-; SSE2-NEXT: andps %xmm0, %xmm3
; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: andps %xmm1, %xmm4
-; SSE2-NEXT: minss %xmm6, %xmm0
-; SSE2-NEXT: orps %xmm4, %xmm0
-; SSE2-NEXT: andnps %xmm0, %xmm2
-; SSE2-NEXT: orps %xmm3, %xmm2
-; SSE2-NEXT: movaps %xmm2, %xmm0
-; SSE2-NEXT: cmpunordss %xmm2, %xmm0
+; SSE2-NEXT: minps %xmm1, %xmm4
+; SSE2-NEXT: orps %xmm3, %xmm4
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: cmpunordps %xmm0, %xmm1
+; SSE2-NEXT: andps %xmm1, %xmm0
+; SSE2-NEXT: andnps %xmm4, %xmm1
+; SSE2-NEXT: orps %xmm0, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: cmpunordss %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm3
-; SSE2-NEXT: andps %xmm2, %xmm3
+; SSE2-NEXT: andps %xmm1, %xmm3
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
+; SSE2-NEXT: movaps %xmm1, %xmm5
+; SSE2-NEXT: minss %xmm4, %xmm5
; SSE2-NEXT: andps %xmm2, %xmm1
-; SSE2-NEXT: minss %xmm7, %xmm2
-; SSE2-NEXT: orps %xmm1, %xmm2
-; SSE2-NEXT: andnps %xmm2, %xmm0
+; SSE2-NEXT: orps %xmm5, %xmm1
+; SSE2-NEXT: andnps %xmm1, %xmm0
; SSE2-NEXT: orps %xmm3, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: test_v8f32:
+; SSE41-LABEL: test_v4f32:
; SSE41: # %bb.0:
-; SSE41-NEXT: movaps %xmm0, %xmm2
-; SSE41-NEXT: minps %xmm1, %xmm0
-; SSE41-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; SSE41-NEXT: movaps %xmm2, %xmm4
-; SSE41-NEXT: andps %xmm3, %xmm4
-; SSE41-NEXT: orps %xmm0, %xmm4
-; SSE41-NEXT: movaps %xmm2, %xmm0
-; SSE41-NEXT: cmpunordps %xmm2, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm4
+; SSE41-NEXT: movaps %xmm0, %xmm1
+; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; SSE41-NEXT: movaps {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; SSE41-NEXT: movaps %xmm1, %xmm3
+; SSE41-NEXT: andps %xmm2, %xmm3
+; SSE41-NEXT: movaps %xmm1, %xmm4
+; SSE41-NEXT: minps %xmm0, %xmm4
+; SSE41-NEXT: orps %xmm3, %xmm4
+; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: cmpunordps %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm4
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSE41-NEXT: movaps %xmm4, %xmm1
; SSE41-NEXT: minss %xmm0, %xmm1
-; SSE41-NEXT: movaps %xmm4, %xmm2
-; SSE41-NEXT: andps %xmm3, %xmm2
+; SSE41-NEXT: andps %xmm4, %xmm2
; SSE41-NEXT: orps %xmm1, %xmm2
; SSE41-NEXT: movaps %xmm4, %xmm0
; SSE41-NEXT: cmpunordss %xmm4, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm2
; SSE41-NEXT: movaps %xmm2, %xmm0
-; SSE41-NEXT: andps %xmm3, %xmm0
-; SSE41-NEXT: movaps %xmm4, %xmm1
-; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1]
-; SSE41-NEXT: movaps %xmm2, %xmm5
-; SSE41-NEXT: minss %xmm1, %xmm5
-; SSE41-NEXT: orps %xmm0, %xmm5
-; SSE41-NEXT: movaps %xmm2, %xmm0
-; SSE41-NEXT: cmpunordss %xmm2, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm5
-; SSE41-NEXT: andps %xmm5, %xmm3
-; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3]
-; SSE41-NEXT: movaps %xmm5, %xmm1
-; SSE41-NEXT: minss %xmm4, %xmm1
-; SSE41-NEXT: orps %xmm3, %xmm1
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: cmpunordss %xmm5, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm1
-; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v8f32:
+; AVX-LABEL: test_v4f32:
; AVX: # %bb.0:
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vorps %xmm1, %xmm3, %xmm1
+; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm3
+; AVX-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX-NEXT: vorpd %xmm1, %xmm3, %xmm1
; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-NEXT: vminss %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vorps %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
-; AVX-NEXT: vandps %xmm2, %xmm1, %xmm3
-; AVX-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX-NEXT: vminss %xmm4, %xmm1, %xmm4
-; AVX-NEXT: vorps %xmm4, %xmm3, %xmm3
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm4
-; AVX-NEXT: vblendvps %xmm4, %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vandps %xmm2, %xmm1, %xmm2
-; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX-NEXT: vminss %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vorps %xmm0, %xmm2, %xmm0
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm2
-; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vzeroupper
+; AVX-NEXT: vandps %xmm2, %xmm0, %xmm2
+; AVX-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
;
-; AVX512BW-LABEL: test_v8f32:
+; AVX512BW-LABEL: test_v4f32:
; AVX512BW: # %bb.0:
-; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX512BW-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512BW-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512BW-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vorps %xmm1, %xmm3, %xmm1
+; AVX512BW-NEXT: vandpd %xmm2, %xmm0, %xmm3
+; AVX512BW-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX512BW-NEXT: vorpd %xmm1, %xmm3, %xmm1
; AVX512BW-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512BW-NEXT: vminss %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vorps %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512BW-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512BW-NEXT: vandps %xmm2, %xmm1, %xmm3
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX512BW-NEXT: vminss %xmm4, %xmm1, %xmm4
-; AVX512BW-NEXT: vorps %xmm4, %xmm3, %xmm3
+; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; AVX512BW-NEXT: vminss %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vandps %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vorps %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vcmpunordss %xmm1, %xmm1, %k1
-; AVX512BW-NEXT: vmovss %xmm1, %xmm3, %xmm3 {%k1}
-; AVX512BW-NEXT: vandps %xmm2, %xmm3, %xmm1
-; AVX512BW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512BW-NEXT: vminss %xmm0, %xmm3, %xmm0
-; AVX512BW-NEXT: vorps %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512BW-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
-; AVX512BW-NEXT: vzeroupper
+; AVX512BW-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: retq
;
-; AVX512VL-LABEL: test_v8f32:
+; AVX512VL-LABEL: test_v4f32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512VL-NEXT: vminps %xmm1, %xmm0, %xmm1
; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm1 | (xmm0 & xmm2)
@@ -405,16 +302,173 @@ define float @test_v8f32(<8 x float> %a0) {
; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 | (xmm1 & xmm2)
; AVX512VL-NEXT: vcmpunordss %xmm1, %xmm1, %k1
; AVX512VL-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm3 = xmm1[1,0]
-; AVX512VL-NEXT: vminss %xmm3, %xmm0, %xmm3
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm3 = xmm3 | (xmm0 & xmm2)
+; AVX512VL-NEXT: retq
+ %1 = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %a0)
+ ret float %1
+}
+
+define float @test_v8f32(<8 x float> %a0) {
+; SSE2-LABEL: test_v8f32:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: minps %xmm1, %xmm2
+; SSE2-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; SSE2-NEXT: movaps %xmm0, %xmm3
+; SSE2-NEXT: andps %xmm1, %xmm3
+; SSE2-NEXT: orps %xmm2, %xmm3
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: cmpunordps %xmm0, %xmm2
+; SSE2-NEXT: andps %xmm2, %xmm0
+; SSE2-NEXT: andnps %xmm3, %xmm2
+; SSE2-NEXT: orps %xmm0, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
+; SSE2-NEXT: movaps %xmm2, %xmm3
+; SSE2-NEXT: cmpunordps %xmm2, %xmm3
+; SSE2-NEXT: movaps %xmm2, %xmm4
+; SSE2-NEXT: andps %xmm3, %xmm4
+; SSE2-NEXT: movaps %xmm2, %xmm5
+; SSE2-NEXT: minps %xmm0, %xmm5
+; SSE2-NEXT: andps %xmm1, %xmm2
+; SSE2-NEXT: orps %xmm5, %xmm2
+; SSE2-NEXT: andnps %xmm2, %xmm3
+; SSE2-NEXT: orps %xmm4, %xmm3
+; SSE2-NEXT: movaps %xmm3, %xmm0
+; SSE2-NEXT: cmpunordss %xmm3, %xmm0
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: andps %xmm3, %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,1,1]
+; SSE2-NEXT: movaps %xmm3, %xmm5
+; SSE2-NEXT: minss %xmm4, %xmm5
+; SSE2-NEXT: andps %xmm1, %xmm3
+; SSE2-NEXT: orps %xmm5, %xmm3
+; SSE2-NEXT: andnps %xmm3, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_v8f32:
+; SSE41: # %bb.0:
+; SSE41-NEXT: movaps %xmm0, %xmm2
+; SSE41-NEXT: minps %xmm1, %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; SSE41-NEXT: movaps %xmm2, %xmm3
+; SSE41-NEXT: andps %xmm1, %xmm3
+; SSE41-NEXT: orps %xmm0, %xmm3
+; SSE41-NEXT: movaps %xmm2, %xmm0
+; SSE41-NEXT: cmpunordps %xmm2, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
+; SSE41-NEXT: movaps %xmm3, %xmm0
+; SSE41-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1]
+; SSE41-NEXT: movaps %xmm3, %xmm2
+; SSE41-NEXT: minps %xmm0, %xmm2
+; SSE41-NEXT: movaps %xmm3, %xmm4
+; SSE41-NEXT: andps %xmm1, %xmm4
+; SSE41-NEXT: orps %xmm2, %xmm4
+; SSE41-NEXT: movaps %xmm3, %xmm0
+; SSE41-NEXT: cmpunordps %xmm3, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm3, %xmm4
+; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE41-NEXT: movaps %xmm4, %xmm2
+; SSE41-NEXT: minss %xmm0, %xmm2
+; SSE41-NEXT: andps %xmm4, %xmm1
+; SSE41-NEXT: orps %xmm2, %xmm1
+; SSE41-NEXT: movaps %xmm4, %xmm0
+; SSE41-NEXT: cmpunordss %xmm4, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm1
+; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX1-LABEL: test_v8f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vminps %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vandps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX1-NEXT: vminss %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX1-NEXT: vandps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8f32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vminps %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm4
+; AVX2-NEXT: vorps %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX2-NEXT: vminss %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
+;
+; AVX512BW-LABEL: test_v8f32:
+; AVX512BW: # %bb.0:
+; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512BW-NEXT: vandps %ymm2, %ymm0, %ymm3
+; AVX512BW-NEXT: vminps %ymm1, %ymm0, %ymm1
+; AVX512BW-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX512BW-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX512BW-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX512BW-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX512BW-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX512BW-NEXT: vandps %xmm2, %xmm0, %xmm4
+; AVX512BW-NEXT: vorps %xmm1, %xmm4, %xmm1
+; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; AVX512BW-NEXT: vminss %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vandps %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vorps %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vcmpunordss %xmm1, %xmm1, %k1
+; AVX512BW-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: vzeroupper
+; AVX512BW-NEXT: retq
+;
+; AVX512VL-LABEL: test_v8f32:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX512VL-NEXT: vminps %ymm1, %ymm0, %ymm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512VL-NEXT: vpternlogd {{.*#+}} ymm2 = ymm2 | (ymm0 & ymm1)
+; AVX512VL-NEXT: vcmpunordps %ymm0, %ymm0, %k1
+; AVX512VL-NEXT: vmovaps %ymm0, %ymm2 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
+; AVX512VL-NEXT: vminps %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 | (ymm2 & ymm1)
+; AVX512VL-NEXT: vcmpunordps %ymm2, %ymm2, %k1
+; AVX512VL-NEXT: vmovaps %ymm2, %ymm0 {%k1}
+; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX512VL-NEXT: vminss %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = (xmm1 & xmm0) | xmm2
; AVX512VL-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k1}
-; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,3,3,3]
-; AVX512VL-NEXT: vminss %xmm0, %xmm3, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 | (xmm3 & xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovaps %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %a0)
@@ -424,68 +478,58 @@ define float @test_v8f32(<8 x float> %a0) {
define float @test_v16f32(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32:
; SSE2: # %bb.0:
-; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: minps %xmm2, %xmm4
-; SSE2-NEXT: movaps {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; SSE2-NEXT: movaps %xmm0, %xmm5
-; SSE2-NEXT: andps %xmm2, %xmm5
+; SSE2-NEXT: movaps %xmm1, %xmm4
+; SSE2-NEXT: minps %xmm3, %xmm4
+; SSE2-NEXT: movaps {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; SSE2-NEXT: movaps %xmm1, %xmm5
+; SSE2-NEXT: andps %xmm3, %xmm5
; SSE2-NEXT: orps %xmm4, %xmm5
-; SSE2-NEXT: movaps %xmm0, %xmm4
-; SSE2-NEXT: cmpunordps %xmm0, %xmm4
-; SSE2-NEXT: andps %xmm4, %xmm0
+; SSE2-NEXT: movaps %xmm1, %xmm4
+; SSE2-NEXT: cmpunordps %xmm1, %xmm4
+; SSE2-NEXT: andps %xmm4, %xmm1
; SSE2-NEXT: andnps %xmm5, %xmm4
-; SSE2-NEXT: orps %xmm0, %xmm4
-; SSE2-NEXT: movaps %xmm4, %xmm0
-; SSE2-NEXT: cmpunordps %xmm4, %xmm0
-; SSE2-NEXT: movaps %xmm4, %xmm5
-; SSE2-NEXT: andps %xmm0, %xmm5
-; SSE2-NEXT: movaps %xmm1, %xmm6
-; SSE2-NEXT: minps %xmm3, %xmm6
-; SSE2-NEXT: movaps %xmm1, %xmm3
-; SSE2-NEXT: andps %xmm2, %xmm3
-; SSE2-NEXT: orps %xmm6, %xmm3
-; SSE2-NEXT: movaps %xmm1, %xmm6
-; SSE2-NEXT: cmpunordps %xmm1, %xmm6
-; SSE2-NEXT: andps %xmm6, %xmm1
-; SSE2-NEXT: andnps %xmm3, %xmm6
-; SSE2-NEXT: orps %xmm1, %xmm6
-; SSE2-NEXT: movaps %xmm4, %xmm1
-; SSE2-NEXT: minps %xmm6, %xmm1
-; SSE2-NEXT: andps %xmm2, %xmm4
; SSE2-NEXT: orps %xmm1, %xmm4
-; SSE2-NEXT: andnps %xmm4, %xmm0
-; SSE2-NEXT: orps %xmm5, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1
-; SSE2-NEXT: cmpunordss %xmm0, %xmm1
-; SSE2-NEXT: movaps %xmm1, %xmm3
-; SSE2-NEXT: andps %xmm0, %xmm3
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
-; SSE2-NEXT: movaps %xmm0, %xmm5
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
-; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm0[3,3,3,3]
-; SSE2-NEXT: minss %xmm4, %xmm0
-; SSE2-NEXT: andps %xmm2, %xmm5
-; SSE2-NEXT: orps %xmm0, %xmm5
-; SSE2-NEXT: andnps %xmm5, %xmm1
-; SSE2-NEXT: orps %xmm3, %xmm1
-; SSE2-NEXT: movaps %xmm1, %xmm3
-; SSE2-NEXT: cmpunordss %xmm1, %xmm3
-; SSE2-NEXT: movaps %xmm3, %xmm0
+; SSE2-NEXT: minps %xmm2, %xmm1
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: andps %xmm3, %xmm2
+; SSE2-NEXT: orps %xmm1, %xmm2
+; SSE2-NEXT: movaps %xmm0, %xmm1
+; SSE2-NEXT: cmpunordps %xmm0, %xmm1
; SSE2-NEXT: andps %xmm1, %xmm0
-; SSE2-NEXT: movaps %xmm1, %xmm4
+; SSE2-NEXT: andnps %xmm2, %xmm1
+; SSE2-NEXT: orps %xmm0, %xmm1
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: cmpunordps %xmm1, %xmm0
+; SSE2-NEXT: movaps %xmm1, %xmm2
+; SSE2-NEXT: andps %xmm0, %xmm2
+; SSE2-NEXT: movaps %xmm1, %xmm5
+; SSE2-NEXT: minps %xmm4, %xmm5
+; SSE2-NEXT: andps %xmm3, %xmm1
+; SSE2-NEXT: orps %xmm5, %xmm1
+; SSE2-NEXT: andnps %xmm1, %xmm0
+; SSE2-NEXT: orps %xmm2, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE2-NEXT: movaps %xmm0, %xmm2
+; SSE2-NEXT: cmpunordps %xmm0, %xmm2
+; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: andps %xmm2, %xmm4
-; SSE2-NEXT: minss %xmm6, %xmm1
-; SSE2-NEXT: orps %xmm4, %xmm1
-; SSE2-NEXT: andnps %xmm1, %xmm3
-; SSE2-NEXT: orps %xmm0, %xmm3
-; SSE2-NEXT: movaps %xmm3, %xmm0
-; SSE2-NEXT: cmpunordss %xmm3, %xmm0
+; SSE2-NEXT: movaps %xmm0, %xmm5
+; SSE2-NEXT: minps %xmm1, %xmm5
+; SSE2-NEXT: andps %xmm3, %xmm0
+; SSE2-NEXT: orps %xmm5, %xmm0
+; SSE2-NEXT: andnps %xmm0, %xmm2
+; SSE2-NEXT: orps %xmm4, %xmm2
+; SSE2-NEXT: movaps %xmm2, %xmm0
+; SSE2-NEXT: cmpunordss %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1
-; SSE2-NEXT: andps %xmm3, %xmm1
+; SSE2-NEXT: andps %xmm2, %xmm1
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; SSE2-NEXT: movaps %xmm2, %xmm5
+; SSE2-NEXT: minss %xmm4, %xmm5
; SSE2-NEXT: andps %xmm3, %xmm2
-; SSE2-NEXT: minss %xmm7, %xmm3
-; SSE2-NEXT: orps %xmm2, %xmm3
-; SSE2-NEXT: andnps %xmm3, %xmm0
+; SSE2-NEXT: orps %xmm5, %xmm2
+; SSE2-NEXT: andnps %xmm2, %xmm0
; SSE2-NEXT: orps %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -517,135 +561,137 @@ define float @test_v16f32(<16 x float> %a0) {
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: cmpunordps %xmm1, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm2
-; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; SSE41-NEXT: movaps %xmm2, %xmm0
+; SSE41-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1]
; SSE41-NEXT: movaps %xmm2, %xmm1
-; SSE41-NEXT: minss %xmm0, %xmm1
+; SSE41-NEXT: minps %xmm0, %xmm1
; SSE41-NEXT: movaps %xmm2, %xmm4
; SSE41-NEXT: andps %xmm3, %xmm4
; SSE41-NEXT: orps %xmm1, %xmm4
; SSE41-NEXT: movaps %xmm2, %xmm0
-; SSE41-NEXT: cmpunordss %xmm2, %xmm0
+; SSE41-NEXT: cmpunordps %xmm2, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm4
-; SSE41-NEXT: movaps %xmm4, %xmm0
-; SSE41-NEXT: andps %xmm3, %xmm0
-; SSE41-NEXT: movaps %xmm2, %xmm1
-; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]
-; SSE41-NEXT: movaps %xmm4, %xmm5
-; SSE41-NEXT: minss %xmm1, %xmm5
-; SSE41-NEXT: orps %xmm0, %xmm5
+; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3]
+; SSE41-NEXT: movaps %xmm4, %xmm1
+; SSE41-NEXT: minss %xmm0, %xmm1
+; SSE41-NEXT: andps %xmm4, %xmm3
+; SSE41-NEXT: orps %xmm1, %xmm3
; SSE41-NEXT: movaps %xmm4, %xmm0
; SSE41-NEXT: cmpunordss %xmm4, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm5
-; SSE41-NEXT: andps %xmm5, %xmm3
-; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
-; SSE41-NEXT: movaps %xmm5, %xmm1
-; SSE41-NEXT: minss %xmm2, %xmm1
-; SSE41-NEXT: orps %xmm3, %xmm1
-; SSE41-NEXT: movaps %xmm5, %xmm0
-; SSE41-NEXT: cmpunordss %xmm5, %xmm0
-; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm1
-; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm3
+; SSE41-NEXT: movaps %xmm3, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v16f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vminps %ymm1, %ymm0, %ymm1
-; AVX-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX-NEXT: vandps %ymm2, %ymm0, %ymm3
-; AVX-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
-; AVX-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vminps %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vorps %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX-NEXT: vminss %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vorps %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm1
-; AVX-NEXT: vandps %xmm2, %xmm1, %xmm3
-; AVX-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX-NEXT: vminss %xmm4, %xmm1, %xmm4
-; AVX-NEXT: vorps %xmm4, %xmm3, %xmm3
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm4
-; AVX-NEXT: vblendvps %xmm4, %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vandps %xmm2, %xmm1, %xmm2
-; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX-NEXT: vminss %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vorps %xmm0, %xmm2, %xmm0
-; AVX-NEXT: vcmpunordss %xmm1, %xmm1, %xmm2
-; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v16f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminps %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vminps %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vandps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX1-NEXT: vminss %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX1-NEXT: vandps %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v16f32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vminps %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vminps %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vminps %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm4
+; AVX2-NEXT: vorps %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; AVX2-NEXT: vminss %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vorps %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordss %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v16f32:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vminps %ymm1, %ymm0, %ymm1
-; AVX512BW-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512BW-NEXT: vandps %ymm2, %ymm0, %ymm3
-; AVX512BW-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX512BW-NEXT: vcmpunordps %ymm0, %ymm0, %ymm3
-; AVX512BW-NEXT: vblendvps %ymm3, %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX512BW-NEXT: vminps %zmm1, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastd {{.*#+}} zmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm1 | (zmm0 & zmm2)
+; AVX512BW-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovaps %zmm0, %zmm1 {%k1}
+; AVX512BW-NEXT: vextractf128 $1, %ymm1, %xmm0
+; AVX512BW-NEXT: vminps %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 | (zmm1 & zmm2)
+; AVX512BW-NEXT: vcmpunordps %zmm1, %zmm1, %k1
+; AVX512BW-NEXT: vmovaps %zmm1, %zmm0 {%k1}
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512BW-NEXT: vminps %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vorps %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordps %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvps %xmm3, %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512BW-NEXT: vminss %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vandps %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vorps %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512BW-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512BW-NEXT: vandps %xmm2, %xmm1, %xmm3
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX512BW-NEXT: vminss %xmm4, %xmm1, %xmm4
-; AVX512BW-NEXT: vorps %xmm4, %xmm3, %xmm3
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm1 | (zmm0 & zmm2)
+; AVX512BW-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovaps %zmm0, %zmm1 {%k1}
+; AVX512BW-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; AVX512BW-NEXT: vminss %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vandps %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vorps %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vcmpunordss %xmm1, %xmm1, %k1
-; AVX512BW-NEXT: vmovss %xmm1, %xmm3, %xmm3 {%k1}
-; AVX512BW-NEXT: vandps %xmm2, %xmm3, %xmm1
-; AVX512BW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512BW-NEXT: vminss %xmm0, %xmm3, %xmm0
-; AVX512BW-NEXT: vorps %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512BW-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
; AVX512VL-LABEL: test_v16f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512VL-NEXT: vminps %ymm1, %ymm0, %ymm1
-; AVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512VL-NEXT: vpternlogd {{.*#+}} ymm1 = ymm1 | (ymm0 & ymm2)
-; AVX512VL-NEXT: vcmpunordps %ymm0, %ymm0, %k1
-; AVX512VL-NEXT: vmovaps %ymm0, %ymm1 {%k1}
-; AVX512VL-NEXT: vextractf128 $1, %ymm1, %xmm0
-; AVX512VL-NEXT: vminps %xmm0, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 | (xmm1 & xmm2)
-; AVX512VL-NEXT: vcmpunordps %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovaps %xmm1, %xmm0 {%k1}
-; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; AVX512VL-NEXT: vminss %xmm1, %xmm0, %xmm1
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = xmm1 | (xmm0 & xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
-; AVX512VL-NEXT: vminss %xmm3, %xmm1, %xmm3
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm3 = xmm3 | (xmm1 & xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovss %xmm1, %xmm3, %xmm3 {%k1}
-; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512VL-NEXT: vminss %xmm0, %xmm3, %xmm0
-; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm0 | (xmm3 & xmm2)
-; AVX512VL-NEXT: vcmpunordss %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vminps %zmm1, %zmm0, %zmm2
+; AVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm2 = zmm2 | (zmm0 & zmm1)
+; AVX512VL-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovaps %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vextractf128 $1, %ymm2, %xmm0
+; AVX512VL-NEXT: vminps %zmm0, %zmm2, %zmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 | (zmm2 & zmm1)
+; AVX512VL-NEXT: vcmpunordps %zmm2, %zmm2, %k1
+; AVX512VL-NEXT: vmovaps %zmm2, %zmm0 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX512VL-NEXT: vminps %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm2 = zmm2 | (zmm0 & zmm1)
+; AVX512VL-NEXT: vcmpunordps %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovaps %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; AVX512VL-NEXT: vminss %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogd {{.*#+}} xmm1 = (xmm1 & xmm2) | xmm0
+; AVX512VL-NEXT: vcmpunordss %xmm2, %xmm2, %k1
+; AVX512VL-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovaps %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %a0)
@@ -659,18 +705,18 @@ define float @test_v16f32(<16 x float> %a0) {
define double @test_v2f64(<2 x double> %a0) {
; SSE2-LABEL: test_v2f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movapd %xmm0, %xmm2
-; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: movapd %xmm0, %xmm1
; SSE2-NEXT: cmpunordsd %xmm0, %xmm1
-; SSE2-NEXT: movapd %xmm1, %xmm3
-; SSE2-NEXT: andpd %xmm0, %xmm3
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: andpd %xmm0, %xmm2
+; SSE2-NEXT: movapd %xmm0, %xmm3
+; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE2-NEXT: movapd %xmm0, %xmm4
-; SSE2-NEXT: minsd %xmm2, %xmm4
+; SSE2-NEXT: minsd %xmm3, %xmm4
; SSE2-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: orpd %xmm4, %xmm0
; SSE2-NEXT: andnpd %xmm0, %xmm1
-; SSE2-NEXT: orpd %xmm3, %xmm1
+; SSE2-NEXT: orpd %xmm2, %xmm1
; SSE2-NEXT: movapd %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -773,38 +819,57 @@ define double @test_v4f64(<4 x double> %a0) {
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v4f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
-; AVX-NEXT: # xmm2 = mem[0,0]
-; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vorpd %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm2
-; AVX-NEXT: vorpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v4f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vminpd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX1-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
+; AVX1-NEXT: vorpd %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vminsd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
+; AVX1-NEXT: # xmm2 = mem[0,0]
+; AVX1-NEXT: vandpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v4f64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vminpd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vmovddup {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0]
+; AVX2-NEXT: # xmm3 = mem[0,0]
+; AVX2-NEXT: vandpd %xmm3, %xmm0, %xmm4
+; AVX2-NEXT: vorpd %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vminsd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vandpd %xmm3, %xmm0, %xmm2
+; AVX2-NEXT: vorpd %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v4f64:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512BW-NEXT: vminpd %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vmovddup {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
-; AVX512BW-NEXT: # xmm2 = mem[0,0]
-; AVX512BW-NEXT: vandpd %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vorpd %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX512BW-NEXT: vmovddup {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0]
+; AVX512BW-NEXT: # xmm3 = mem[0,0]
+; AVX512BW-NEXT: vandpd %xmm3, %xmm0, %xmm4
+; AVX512BW-NEXT: vorpd %xmm1, %xmm4, %xmm1
+; AVX512BW-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
; AVX512BW-NEXT: vminsd %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vandpd %xmm2, %xmm1, %xmm2
+; AVX512BW-NEXT: vandpd %xmm3, %xmm1, %xmm2
; AVX512BW-NEXT: vorpd %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
; AVX512BW-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
@@ -814,16 +879,17 @@ define double @test_v4f64(<4 x double> %a0) {
; AVX512VL-LABEL: test_v4f64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX512VL-NEXT: vminpd %xmm1, %xmm0, %xmm1
-; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = xmm1 | (xmm0 & xmm2)
-; AVX512VL-NEXT: vcmpunordpd %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovapd %xmm0, %xmm1 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
-; AVX512VL-NEXT: vminsd %xmm0, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm0 | (xmm1 & xmm2)
-; AVX512VL-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vminpd %xmm1, %xmm0, %xmm2
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512VL-NEXT: vpternlogq {{.*#+}} ymm2 = ymm2 | (ymm0 & ymm1)
+; AVX512VL-NEXT: vcmpunordpd %ymm0, %ymm0, %k1
+; AVX512VL-NEXT: vmovapd %ymm0, %ymm2 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
+; AVX512VL-NEXT: vminsd %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = (xmm1 & xmm2) | xmm0
+; AVX512VL-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512VL-NEXT: vmovsd %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovapd %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %a0)
@@ -833,47 +899,47 @@ define double @test_v4f64(<4 x double> %a0) {
define double @test_v8f64(<8 x double> %a0) {
; SSE2-LABEL: test_v8f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movapd %xmm0, %xmm4
-; SSE2-NEXT: minpd %xmm2, %xmm4
-; SSE2-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
-; SSE2-NEXT: movapd %xmm0, %xmm6
-; SSE2-NEXT: andpd %xmm2, %xmm6
-; SSE2-NEXT: orpd %xmm4, %xmm6
-; SSE2-NEXT: movapd %xmm0, %xmm5
-; SSE2-NEXT: cmpunordpd %xmm0, %xmm5
-; SSE2-NEXT: andpd %xmm5, %xmm0
-; SSE2-NEXT: andnpd %xmm6, %xmm5
-; SSE2-NEXT: orpd %xmm0, %xmm5
-; SSE2-NEXT: movapd %xmm5, %xmm4
-; SSE2-NEXT: cmpunordpd %xmm5, %xmm4
-; SSE2-NEXT: movapd %xmm5, %xmm0
-; SSE2-NEXT: andpd %xmm4, %xmm0
-; SSE2-NEXT: movapd %xmm1, %xmm6
-; SSE2-NEXT: minpd %xmm3, %xmm6
-; SSE2-NEXT: movapd %xmm1, %xmm3
-; SSE2-NEXT: andpd %xmm2, %xmm3
-; SSE2-NEXT: orpd %xmm6, %xmm3
-; SSE2-NEXT: movapd %xmm1, %xmm6
-; SSE2-NEXT: cmpunordpd %xmm1, %xmm6
-; SSE2-NEXT: andpd %xmm6, %xmm1
-; SSE2-NEXT: andnpd %xmm3, %xmm6
-; SSE2-NEXT: orpd %xmm1, %xmm6
-; SSE2-NEXT: movapd %xmm5, %xmm1
-; SSE2-NEXT: minpd %xmm6, %xmm1
-; SSE2-NEXT: andpd %xmm2, %xmm5
-; SSE2-NEXT: orpd %xmm1, %xmm5
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: minpd %xmm3, %xmm4
+; SSE2-NEXT: movapd {{.*#+}} xmm3 = [-0.0E+0,-0.0E+0]
+; SSE2-NEXT: movapd %xmm1, %xmm5
+; SSE2-NEXT: andpd %xmm3, %xmm5
+; SSE2-NEXT: orpd %xmm4, %xmm5
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm4
+; SSE2-NEXT: andpd %xmm4, %xmm1
; SSE2-NEXT: andnpd %xmm5, %xmm4
-; SSE2-NEXT: orpd %xmm0, %xmm4
-; SSE2-NEXT: movapd %xmm4, %xmm0
-; SSE2-NEXT: cmpunordsd %xmm4, %xmm0
+; SSE2-NEXT: orpd %xmm1, %xmm4
; SSE2-NEXT: movapd %xmm0, %xmm1
-; SSE2-NEXT: andpd %xmm4, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[2,3,2,3]
-; SSE2-NEXT: movapd %xmm4, %xmm5
-; SSE2-NEXT: minsd %xmm3, %xmm5
-; SSE2-NEXT: andpd %xmm2, %xmm4
-; SSE2-NEXT: orpd %xmm5, %xmm4
-; SSE2-NEXT: andnpd %xmm4, %xmm0
+; SSE2-NEXT: minpd %xmm2, %xmm1
+; SSE2-NEXT: movapd %xmm0, %xmm2
+; SSE2-NEXT: andpd %xmm3, %xmm2
+; SSE2-NEXT: orpd %xmm1, %xmm2
+; SSE2-NEXT: movapd %xmm0, %xmm1
+; SSE2-NEXT: cmpunordpd %xmm0, %xmm1
+; SSE2-NEXT: andpd %xmm1, %xmm0
+; SSE2-NEXT: andnpd %xmm2, %xmm1
+; SSE2-NEXT: orpd %xmm0, %xmm1
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm2
+; SSE2-NEXT: movapd %xmm1, %xmm0
+; SSE2-NEXT: andpd %xmm2, %xmm0
+; SSE2-NEXT: movapd %xmm1, %xmm5
+; SSE2-NEXT: minpd %xmm4, %xmm5
+; SSE2-NEXT: andpd %xmm3, %xmm1
+; SSE2-NEXT: orpd %xmm5, %xmm1
+; SSE2-NEXT: andnpd %xmm1, %xmm2
+; SSE2-NEXT: orpd %xmm0, %xmm2
+; SSE2-NEXT: movapd %xmm2, %xmm0
+; SSE2-NEXT: cmpunordsd %xmm2, %xmm0
+; SSE2-NEXT: movapd %xmm0, %xmm1
+; SSE2-NEXT: andpd %xmm2, %xmm1
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[2,3,2,3]
+; SSE2-NEXT: movapd %xmm2, %xmm5
+; SSE2-NEXT: minsd %xmm4, %xmm5
+; SSE2-NEXT: andpd %xmm3, %xmm2
+; SSE2-NEXT: orpd %xmm5, %xmm2
+; SSE2-NEXT: andnpd %xmm2, %xmm0
; SSE2-NEXT: orpd %xmm1, %xmm0
; SSE2-NEXT: retq
;
@@ -917,71 +983,95 @@ define double @test_v8f64(<8 x double> %a0) {
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v8f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm1
-; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX-NEXT: vandpd %ymm2, %ymm0, %ymm3
-; AVX-NEXT: vorpd %ymm1, %ymm3, %ymm1
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
-; AVX-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm3
-; AVX-NEXT: vorpd %xmm1, %xmm3, %xmm1
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm2
-; AVX-NEXT: vorpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v8f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminpd %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX1-NEXT: vandpd %ymm2, %ymm0, %ymm3
+; AVX1-NEXT: vorpd %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vminpd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vandpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vminsd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
+; AVX1-NEXT: # xmm2 = mem[0,0]
+; AVX1-NEXT: vandpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8f64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vminpd %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX2-NEXT: vandpd %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vorpd %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vminpd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vandpd %xmm2, %xmm0, %xmm4
+; AVX2-NEXT: vorpd %xmm1, %xmm4, %xmm1
+; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vminsd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vandpd %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vorpd %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v8f64:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vminpd %ymm1, %ymm0, %ymm1
-; AVX512BW-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512BW-NEXT: vandpd %ymm2, %ymm0, %ymm3
-; AVX512BW-NEXT: vorpd %ymm1, %ymm3, %ymm1
-; AVX512BW-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
-; AVX512BW-NEXT: vblendvpd %ymm3, %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX512BW-NEXT: vminpd %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vandpd %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vorpd %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
-; AVX512BW-NEXT: vminsd %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vandpd %xmm2, %xmm1, %xmm2
-; AVX512BW-NEXT: vorpd %xmm0, %xmm2, %xmm0
-; AVX512BW-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512BW-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512BW-NEXT: vminpd %zmm1, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastq {{.*#+}} zmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 | (zmm0 & zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovapd %zmm0, %zmm1 {%k1}
+; AVX512BW-NEXT: vextractf128 $1, %ymm1, %xmm0
+; AVX512BW-NEXT: vminpd %xmm0, %xmm1, %xmm3
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm3 = zmm3 | (zmm1 & zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm1, %zmm1, %k1
+; AVX512BW-NEXT: vmovapd %zmm1, %zmm3 {%k1}
+; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm3[1,0]
+; AVX512BW-NEXT: vminsd %xmm0, %xmm3, %xmm0
+; AVX512BW-NEXT: vandpd %xmm2, %xmm3, %xmm1
+; AVX512BW-NEXT: vorpd %xmm0, %xmm1, %xmm0
+; AVX512BW-NEXT: vcmpunordsd %xmm3, %xmm3, %k1
+; AVX512BW-NEXT: vmovsd %xmm3, %xmm0, %xmm0 {%k1}
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
; AVX512VL-LABEL: test_v8f64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextractf64x4 $1, %zmm0, %ymm1
-; AVX512VL-NEXT: vminpd %ymm1, %ymm0, %ymm1
-; AVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512VL-NEXT: vpternlogq {{.*#+}} ymm1 = ymm1 | (ymm0 & ymm2)
-; AVX512VL-NEXT: vcmpunordpd %ymm0, %ymm0, %k1
-; AVX512VL-NEXT: vmovapd %ymm0, %ymm1 {%k1}
-; AVX512VL-NEXT: vextractf128 $1, %ymm1, %xmm0
-; AVX512VL-NEXT: vminpd %xmm0, %xmm1, %xmm3
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm3 = xmm3 | (xmm1 & xmm2)
-; AVX512VL-NEXT: vcmpunordpd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovapd %xmm1, %xmm3 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm3[1,0]
-; AVX512VL-NEXT: vminsd %xmm0, %xmm3, %xmm0
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm0 | (xmm3 & xmm2)
-; AVX512VL-NEXT: vcmpunordsd %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovsd %xmm3, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vminpd %zmm1, %zmm0, %zmm2
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm2 = zmm2 | (zmm0 & zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovapd %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vextractf128 $1, %ymm2, %xmm0
+; AVX512VL-NEXT: vminpd %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm0 = zmm0 | (zmm2 & zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm2, %zmm2, %k1
+; AVX512VL-NEXT: vmovapd %zmm2, %zmm0 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
+; AVX512VL-NEXT: vminsd %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = (xmm1 & xmm0) | xmm2
+; AVX512VL-NEXT: vcmpunordsd %xmm0, %xmm0, %k1
+; AVX512VL-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovapd %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call double @llvm.vector.reduce.fminimum.v8f64(<8 x double> %a0)
@@ -991,86 +1081,86 @@ define double @test_v8f64(<8 x double> %a0) {
define double @test_v16f64(<16 x double> %a0) {
; SSE2-LABEL: test_v16f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movapd %xmm0, %xmm8
-; SSE2-NEXT: minpd %xmm4, %xmm8
-; SSE2-NEXT: movapd {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0]
-; SSE2-NEXT: movapd %xmm0, %xmm9
-; SSE2-NEXT: andpd %xmm4, %xmm9
+; SSE2-NEXT: movapd %xmm2, %xmm8
+; SSE2-NEXT: minpd %xmm6, %xmm8
+; SSE2-NEXT: movapd {{.*#+}} xmm6 = [-0.0E+0,-0.0E+0]
+; SSE2-NEXT: movapd %xmm2, %xmm9
+; SSE2-NEXT: andpd %xmm6, %xmm9
; SSE2-NEXT: orpd %xmm8, %xmm9
-; SSE2-NEXT: movapd %xmm0, %xmm8
-; SSE2-NEXT: cmpunordpd %xmm0, %xmm8
-; SSE2-NEXT: andpd %xmm8, %xmm0
+; SSE2-NEXT: movapd %xmm2, %xmm8
+; SSE2-NEXT: cmpunordpd %xmm2, %xmm8
+; SSE2-NEXT: andpd %xmm8, %xmm2
; SSE2-NEXT: andnpd %xmm9, %xmm8
-; SSE2-NEXT: orpd %xmm0, %xmm8
-; SSE2-NEXT: movapd %xmm8, %xmm0
-; SSE2-NEXT: cmpunordpd %xmm8, %xmm0
-; SSE2-NEXT: movapd %xmm8, %xmm9
-; SSE2-NEXT: andpd %xmm0, %xmm9
-; SSE2-NEXT: movapd %xmm2, %xmm10
-; SSE2-NEXT: minpd %xmm6, %xmm10
-; SSE2-NEXT: movapd %xmm2, %xmm6
-; SSE2-NEXT: andpd %xmm4, %xmm6
-; SSE2-NEXT: orpd %xmm10, %xmm6
-; SSE2-NEXT: movapd %xmm2, %xmm10
-; SSE2-NEXT: cmpunordpd %xmm2, %xmm10
-; SSE2-NEXT: andpd %xmm10, %xmm2
-; SSE2-NEXT: andnpd %xmm6, %xmm10
-; SSE2-NEXT: orpd %xmm2, %xmm10
-; SSE2-NEXT: movapd %xmm8, %xmm2
-; SSE2-NEXT: minpd %xmm10, %xmm2
-; SSE2-NEXT: andpd %xmm4, %xmm8
; SSE2-NEXT: orpd %xmm2, %xmm8
-; SSE2-NEXT: andnpd %xmm8, %xmm0
-; SSE2-NEXT: orpd %xmm9, %xmm0
+; SSE2-NEXT: movapd %xmm0, %xmm2
+; SSE2-NEXT: minpd %xmm4, %xmm2
+; SSE2-NEXT: movapd %xmm0, %xmm4
+; SSE2-NEXT: andpd %xmm6, %xmm4
+; SSE2-NEXT: orpd %xmm2, %xmm4
; SSE2-NEXT: movapd %xmm0, %xmm2
; SSE2-NEXT: cmpunordpd %xmm0, %xmm2
-; SSE2-NEXT: movapd %xmm0, %xmm6
-; SSE2-NEXT: andpd %xmm2, %xmm6
-; SSE2-NEXT: movapd %xmm1, %xmm8
-; SSE2-NEXT: minpd %xmm5, %xmm8
-; SSE2-NEXT: movapd %xmm1, %xmm9
-; SSE2-NEXT: andpd %xmm4, %xmm9
-; SSE2-NEXT: orpd %xmm8, %xmm9
-; SSE2-NEXT: movapd %xmm1, %xmm5
-; SSE2-NEXT: cmpunordpd %xmm1, %xmm5
-; SSE2-NEXT: andpd %xmm5, %xmm1
-; SSE2-NEXT: andnpd %xmm9, %xmm5
-; SSE2-NEXT: orpd %xmm1, %xmm5
-; SSE2-NEXT: movapd %xmm5, %xmm1
-; SSE2-NEXT: cmpunordpd %xmm5, %xmm1
-; SSE2-NEXT: movapd %xmm5, %xmm8
-; SSE2-NEXT: andpd %xmm1, %xmm8
-; SSE2-NEXT: movapd %xmm3, %xmm9
-; SSE2-NEXT: minpd %xmm7, %xmm9
+; SSE2-NEXT: andpd %xmm2, %xmm0
+; SSE2-NEXT: andnpd %xmm4, %xmm2
+; SSE2-NEXT: orpd %xmm0, %xmm2
+; SSE2-NEXT: movapd %xmm3, %xmm0
+; SSE2-NEXT: minpd %xmm7, %xmm0
+; SSE2-NEXT: movapd %xmm3, %xmm4
+; SSE2-NEXT: andpd %xmm6, %xmm4
+; SSE2-NEXT: orpd %xmm0, %xmm4
; SSE2-NEXT: movapd %xmm3, %xmm7
-; SSE2-NEXT: andpd %xmm4, %xmm7
-; SSE2-NEXT: orpd %xmm9, %xmm7
-; SSE2-NEXT: movapd %xmm3, %xmm9
-; SSE2-NEXT: cmpunordpd %xmm3, %xmm9
-; SSE2-NEXT: andpd %xmm9, %xmm3
-; SSE2-NEXT: andnpd %xmm7, %xmm9
-; SSE2-NEXT: orpd %xmm3, %xmm9
-; SSE2-NEXT: movapd %xmm5, %xmm3
-; SSE2-NEXT: minpd %xmm9, %xmm3
-; SSE2-NEXT: andpd %xmm4, %xmm5
-; SSE2-NEXT: orpd %xmm3, %xmm5
-; SSE2-NEXT: andnpd %xmm5, %xmm1
-; SSE2-NEXT: orpd %xmm8, %xmm1
-; SSE2-NEXT: movapd %xmm0, %xmm3
-; SSE2-NEXT: minpd %xmm1, %xmm3
-; SSE2-NEXT: andpd %xmm4, %xmm0
-; SSE2-NEXT: orpd %xmm3, %xmm0
-; SSE2-NEXT: andnpd %xmm0, %xmm2
-; SSE2-NEXT: orpd %xmm6, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm3, %xmm7
+; SSE2-NEXT: andpd %xmm7, %xmm3
+; SSE2-NEXT: andnpd %xmm4, %xmm7
+; SSE2-NEXT: orpd %xmm3, %xmm7
+; SSE2-NEXT: movapd %xmm1, %xmm0
+; SSE2-NEXT: minpd %xmm5, %xmm0
+; SSE2-NEXT: movapd %xmm1, %xmm3
+; SSE2-NEXT: andpd %xmm6, %xmm3
+; SSE2-NEXT: orpd %xmm0, %xmm3
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm4
+; SSE2-NEXT: andpd %xmm4, %xmm1
+; SSE2-NEXT: andnpd %xmm3, %xmm4
+; SSE2-NEXT: orpd %xmm1, %xmm4
+; SSE2-NEXT: movapd %xmm4, %xmm0
+; SSE2-NEXT: cmpunordpd %xmm4, %xmm0
+; SSE2-NEXT: movapd %xmm4, %xmm1
+; SSE2-NEXT: andpd %xmm0, %xmm1
+; SSE2-NEXT: movapd %xmm4, %xmm3
+; SSE2-NEXT: minpd %xmm7, %xmm3
+; SSE2-NEXT: andpd %xmm6, %xmm4
+; SSE2-NEXT: orpd %xmm3, %xmm4
+; SSE2-NEXT: andnpd %xmm4, %xmm0
+; SSE2-NEXT: orpd %xmm1, %xmm0
+; SSE2-NEXT: movapd %xmm2, %xmm1
+; SSE2-NEXT: cmpunordpd %xmm2, %xmm1
+; SSE2-NEXT: movapd %xmm2, %xmm3
+; SSE2-NEXT: andpd %xmm1, %xmm3
+; SSE2-NEXT: movapd %xmm2, %xmm4
+; SSE2-NEXT: minpd %xmm8, %xmm4
+; SSE2-NEXT: andpd %xmm6, %xmm2
+; SSE2-NEXT: orpd %xmm4, %xmm2
+; SSE2-NEXT: andnpd %xmm2, %xmm1
+; SSE2-NEXT: orpd %xmm3, %xmm1
+; SSE2-NEXT: movapd %xmm1, %xmm2
+; SSE2-NEXT: cmpunordpd %xmm1, %xmm2
+; SSE2-NEXT: movapd %xmm1, %xmm3
+; SSE2-NEXT: andpd %xmm2, %xmm3
+; SSE2-NEXT: movapd %xmm1, %xmm4
+; SSE2-NEXT: minpd %xmm0, %xmm4
+; SSE2-NEXT: andpd %xmm6, %xmm1
+; SSE2-NEXT: orpd %xmm4, %xmm1
+; SSE2-NEXT: andnpd %xmm1, %xmm2
+; SSE2-NEXT: orpd %xmm3, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm0
; SSE2-NEXT: cmpunordsd %xmm2, %xmm0
; SSE2-NEXT: movapd %xmm0, %xmm1
; SSE2-NEXT: andpd %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
-; SSE2-NEXT: movapd %xmm2, %xmm5
-; SSE2-NEXT: minsd %xmm3, %xmm5
-; SSE2-NEXT: andpd %xmm4, %xmm2
-; SSE2-NEXT: orpd %xmm5, %xmm2
+; SSE2-NEXT: movapd %xmm2, %xmm4
+; SSE2-NEXT: minsd %xmm3, %xmm4
+; SSE2-NEXT: andpd %xmm6, %xmm2
+; SSE2-NEXT: orpd %xmm4, %xmm2
; SSE2-NEXT: andnpd %xmm2, %xmm0
; SSE2-NEXT: orpd %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -1078,51 +1168,51 @@ define double @test_v16f64(<16 x double> %a0) {
; SSE41-LABEL: test_v16f64:
; SSE41: # %bb.0:
; SSE41-NEXT: movapd %xmm0, %xmm8
+; SSE41-NEXT: movapd %xmm2, %xmm0
+; SSE41-NEXT: minpd %xmm6, %xmm0
+; SSE41-NEXT: movapd {{.*#+}} xmm6 = [-0.0E+0,-0.0E+0]
+; SSE41-NEXT: movapd %xmm2, %xmm9
+; SSE41-NEXT: andpd %xmm6, %xmm9
+; SSE41-NEXT: orpd %xmm0, %xmm9
+; SSE41-NEXT: movapd %xmm2, %xmm0
+; SSE41-NEXT: cmpunordpd %xmm2, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm9
+; SSE41-NEXT: movapd %xmm8, %xmm0
+; SSE41-NEXT: minpd %xmm4, %xmm0
+; SSE41-NEXT: movapd %xmm8, %xmm2
+; SSE41-NEXT: andpd %xmm6, %xmm2
+; SSE41-NEXT: orpd %xmm0, %xmm2
+; SSE41-NEXT: movapd %xmm8, %xmm0
+; SSE41-NEXT: cmpunordpd %xmm8, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm8, %xmm2
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: minpd %xmm7, %xmm0
-; SSE41-NEXT: movapd {{.*#+}} xmm7 = [-0.0E+0,-0.0E+0]
-; SSE41-NEXT: movapd %xmm3, %xmm9
-; SSE41-NEXT: andpd %xmm7, %xmm9
-; SSE41-NEXT: orpd %xmm0, %xmm9
+; SSE41-NEXT: movapd %xmm3, %xmm4
+; SSE41-NEXT: andpd %xmm6, %xmm4
+; SSE41-NEXT: orpd %xmm0, %xmm4
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: cmpunordpd %xmm3, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm9
+; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm4
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: minpd %xmm5, %xmm0
; SSE41-NEXT: movapd %xmm1, %xmm3
-; SSE41-NEXT: andpd %xmm7, %xmm3
+; SSE41-NEXT: andpd %xmm6, %xmm3
; SSE41-NEXT: orpd %xmm0, %xmm3
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordpd %xmm1, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3
; SSE41-NEXT: movapd %xmm3, %xmm0
-; SSE41-NEXT: minpd %xmm9, %xmm0
+; SSE41-NEXT: minpd %xmm4, %xmm0
; SSE41-NEXT: movapd %xmm3, %xmm1
-; SSE41-NEXT: andpd %xmm7, %xmm1
+; SSE41-NEXT: andpd %xmm6, %xmm1
; SSE41-NEXT: orpd %xmm0, %xmm1
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: cmpunordpd %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1
; SSE41-NEXT: movapd %xmm2, %xmm0
-; SSE41-NEXT: minpd %xmm6, %xmm0
-; SSE41-NEXT: movapd %xmm2, %xmm3
-; SSE41-NEXT: andpd %xmm7, %xmm3
-; SSE41-NEXT: orpd %xmm0, %xmm3
-; SSE41-NEXT: movapd %xmm2, %xmm0
-; SSE41-NEXT: cmpunordpd %xmm2, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm3
-; SSE41-NEXT: movapd %xmm8, %xmm0
-; SSE41-NEXT: minpd %xmm4, %xmm0
-; SSE41-NEXT: movapd %xmm8, %xmm2
-; SSE41-NEXT: andpd %xmm7, %xmm2
-; SSE41-NEXT: orpd %xmm0, %xmm2
-; SSE41-NEXT: movapd %xmm8, %xmm0
-; SSE41-NEXT: cmpunordpd %xmm8, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm8, %xmm2
-; SSE41-NEXT: movapd %xmm2, %xmm0
-; SSE41-NEXT: minpd %xmm3, %xmm0
+; SSE41-NEXT: minpd %xmm9, %xmm0
; SSE41-NEXT: movapd %xmm2, %xmm3
-; SSE41-NEXT: andpd %xmm7, %xmm3
+; SSE41-NEXT: andpd %xmm6, %xmm3
; SSE41-NEXT: orpd %xmm0, %xmm3
; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: cmpunordpd %xmm2, %xmm0
@@ -1130,7 +1220,7 @@ define double @test_v16f64(<16 x double> %a0) {
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: minpd %xmm1, %xmm0
; SSE41-NEXT: movapd %xmm3, %xmm1
-; SSE41-NEXT: andpd %xmm7, %xmm1
+; SSE41-NEXT: andpd %xmm6, %xmm1
; SSE41-NEXT: orpd %xmm0, %xmm1
; SSE41-NEXT: movapd %xmm3, %xmm0
; SSE41-NEXT: cmpunordpd %xmm3, %xmm0
@@ -1139,46 +1229,81 @@ define double @test_v16f64(<16 x double> %a0) {
; SSE41-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE41-NEXT: movapd %xmm1, %xmm2
; SSE41-NEXT: minsd %xmm0, %xmm2
-; SSE41-NEXT: andpd %xmm1, %xmm7
-; SSE41-NEXT: orpd %xmm2, %xmm7
+; SSE41-NEXT: andpd %xmm1, %xmm6
+; SSE41-NEXT: orpd %xmm2, %xmm6
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: cmpunordsd %xmm1, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm7
-; SSE41-NEXT: movapd %xmm7, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm6
+; SSE41-NEXT: movapd %xmm6, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: test_v16f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vminpd %ymm3, %ymm1, %ymm3
-; AVX-NEXT: vbroadcastsd {{.*#+}} ymm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX-NEXT: vandpd %ymm4, %ymm1, %ymm5
-; AVX-NEXT: vorpd %ymm3, %ymm5, %ymm3
-; AVX-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm5
-; AVX-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
-; AVX-NEXT: vminpd %ymm2, %ymm0, %ymm2
-; AVX-NEXT: vandpd %ymm4, %ymm0, %ymm3
-; AVX-NEXT: vorpd %ymm2, %ymm3, %ymm2
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
-; AVX-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
-; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm1
-; AVX-NEXT: vandpd %ymm4, %ymm0, %ymm2
-; AVX-NEXT: vorpd %ymm1, %ymm2, %ymm1
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
-; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandpd %xmm4, %xmm0, %xmm2
-; AVX-NEXT: vorpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
-; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vandpd %xmm4, %xmm0, %xmm2
-; AVX-NEXT: vorpd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
-; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vzeroupper
-; AVX-NEXT: retq
+; AVX1-LABEL: test_v16f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminpd %ymm3, %ymm1, %ymm3
+; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX1-NEXT: vandpd %ymm4, %ymm1, %ymm5
+; AVX1-NEXT: vorpd %ymm3, %ymm5, %ymm3
+; AVX1-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm5
+; AVX1-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vminpd %ymm2, %ymm0, %ymm2
+; AVX1-NEXT: vandpd %ymm4, %ymm0, %ymm3
+; AVX1-NEXT: vorpd %ymm2, %ymm3, %ymm2
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX1-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
+; AVX1-NEXT: vminpd %ymm1, %ymm0, %ymm1
+; AVX1-NEXT: vandpd %ymm4, %ymm0, %ymm2
+; AVX1-NEXT: vorpd %ymm1, %ymm2, %ymm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vminpd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX1-NEXT: vandpd %xmm4, %xmm0, %xmm3
+; AVX1-NEXT: vorpd %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX1-NEXT: vminsd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0]
+; AVX1-NEXT: # xmm2 = mem[0,0]
+; AVX1-NEXT: vandpd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT: vorpd %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v16f64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vminpd %ymm3, %ymm1, %ymm3
+; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX2-NEXT: vandpd %ymm4, %ymm1, %ymm5
+; AVX2-NEXT: vorpd %ymm3, %ymm5, %ymm3
+; AVX2-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm5
+; AVX2-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
+; AVX2-NEXT: vminpd %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vandpd %ymm4, %ymm0, %ymm3
+; AVX2-NEXT: vorpd %ymm2, %ymm3, %ymm2
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
+; AVX2-NEXT: vminpd %ymm1, %ymm0, %ymm1
+; AVX2-NEXT: vandpd %ymm4, %ymm0, %ymm2
+; AVX2-NEXT: vorpd %ymm1, %ymm2, %ymm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX2-NEXT: vminpd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vandpd %xmm4, %xmm0, %xmm3
+; AVX2-NEXT: vorpd %xmm1, %xmm3, %xmm1
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vminsd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vandpd %xmm4, %xmm0, %xmm2
+; AVX2-NEXT: vorpd %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm2
+; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
;
; AVX512BW-LABEL: test_v16f64:
; AVX512BW: # %bb.0:
@@ -1188,17 +1313,15 @@ define double @test_v16f64(<16 x double> %a0) {
; AVX512BW-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
; AVX512BW-NEXT: vmovapd %zmm0, %zmm1 {%k1}
; AVX512BW-NEXT: vextractf64x4 $1, %zmm1, %ymm0
-; AVX512BW-NEXT: vminpd %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vandpd %ymm2, %ymm1, %ymm3
-; AVX512BW-NEXT: vorpd %ymm0, %ymm3, %ymm0
-; AVX512BW-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm3
-; AVX512BW-NEXT: vblendvpd %ymm3, %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vminpd %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm0 = zmm0 | (zmm1 & zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm1, %zmm1, %k1
+; AVX512BW-NEXT: vmovapd %zmm1, %zmm0 {%k1}
; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512BW-NEXT: vminpd %xmm1, %xmm0, %xmm1
-; AVX512BW-NEXT: vandpd %xmm2, %xmm0, %xmm3
-; AVX512BW-NEXT: vorpd %xmm1, %xmm3, %xmm1
-; AVX512BW-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm3
-; AVX512BW-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 | (zmm0 & zmm2)
+; AVX512BW-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512BW-NEXT: vmovapd %zmm0, %zmm1 {%k1}
; AVX512BW-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
; AVX512BW-NEXT: vminsd %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vandpd %xmm2, %xmm1, %xmm2
@@ -1210,27 +1333,27 @@ define double @test_v16f64(<16 x double> %a0) {
;
; AVX512VL-LABEL: test_v16f64:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vminpd %zmm1, %zmm0, %zmm1
-; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
-; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 | (zmm0 & zmm2)
+; AVX512VL-NEXT: vminpd %zmm1, %zmm0, %zmm2
+; AVX512VL-NEXT: vpbroadcastq {{.*#+}} zmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm2 = zmm2 | (zmm0 & zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
+; AVX512VL-NEXT: vmovapd %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vextractf64x4 $1, %zmm2, %ymm0
+; AVX512VL-NEXT: vminpd %zmm0, %zmm2, %zmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm0 = zmm0 | (zmm2 & zmm1)
+; AVX512VL-NEXT: vcmpunordpd %zmm2, %zmm2, %k1
+; AVX512VL-NEXT: vmovapd %zmm2, %zmm0 {%k1}
+; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX512VL-NEXT: vminpd %xmm2, %xmm0, %xmm2
+; AVX512VL-NEXT: vpternlogq {{.*#+}} zmm2 = zmm2 | (zmm0 & zmm1)
; AVX512VL-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
-; AVX512VL-NEXT: vmovapd %zmm0, %zmm1 {%k1}
-; AVX512VL-NEXT: vextractf64x4 $1, %zmm1, %ymm0
-; AVX512VL-NEXT: vminpd %ymm0, %ymm1, %ymm0
-; AVX512VL-NEXT: vmovdqa %ymm2, %ymm3
-; AVX512VL-NEXT: vpternlogq {{.*#+}} ymm3 = (ymm3 & ymm1) | ymm0
-; AVX512VL-NEXT: vcmpunordpd %ymm1, %ymm1, %k1
-; AVX512VL-NEXT: vmovapd %ymm1, %ymm3 {%k1}
-; AVX512VL-NEXT: vextractf128 $1, %ymm3, %xmm0
-; AVX512VL-NEXT: vminpd %xmm0, %xmm3, %xmm1
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = xmm1 | (xmm3 & xmm2)
-; AVX512VL-NEXT: vcmpunordpd %xmm3, %xmm3, %k1
-; AVX512VL-NEXT: vmovapd %xmm3, %xmm1 {%k1}
-; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
-; AVX512VL-NEXT: vminsd %xmm0, %xmm1, %xmm0
-; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm0 | (xmm1 & xmm2)
-; AVX512VL-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512VL-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
+; AVX512VL-NEXT: vmovapd %zmm0, %zmm2 {%k1}
+; AVX512VL-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
+; AVX512VL-NEXT: vminsd %xmm0, %xmm2, %xmm0
+; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm1 = (xmm1 & xmm2) | xmm0
+; AVX512VL-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512VL-NEXT: vmovsd %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovapd %xmm1, %xmm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
%1 = call double @llvm.vector.reduce.fminimum.v16f64(<16 x double> %a0)
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