[llvm] 2972615 - [X86] fmaddsub-combine.ll - remove 128/256-bit buildvector tests (#207436)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 3 11:21:58 PDT 2026
Author: Simon Pilgrim
Date: 2026-07-03T18:21:53Z
New Revision: 297261502dcf30ad06f45edd4a250f4f3af27014
URL: https://github.com/llvm/llvm-project/commit/297261502dcf30ad06f45edd4a250f4f3af27014
DIFF: https://github.com/llvm/llvm-project/commit/297261502dcf30ad06f45edd4a250f4f3af27014.diff
LOG: [X86] fmaddsub-combine.ll - remove 128/256-bit buildvector tests (#207436)
These are covered by PhaseOrdering/X86/fmaddsub.ll which outputs the
vectorized shuffle patterns already tested for in fmaddsub-combine.ll
and fmsubadd-combine.ll
Minor cleanup for #144489
Added:
Modified:
llvm/test/CodeGen/X86/fmaddsub-combine.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/fmaddsub-combine.ll b/llvm/test/CodeGen/X86/fmaddsub-combine.ll
index 2af219b3cdabb..7c0aec1db213a 100644
--- a/llvm/test/CodeGen/X86/fmaddsub-combine.ll
+++ b/llvm/test/CodeGen/X86/fmaddsub-combine.ll
@@ -168,162 +168,6 @@ entry:
ret <16 x float> %Addsub
}
-define <4 x float> @buildvector_mul_addsub_ps128(<4 x float> %C, <4 x float> %D, <4 x float> %B) {
-; NOFMA-LABEL: buildvector_mul_addsub_ps128:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulps %xmm1, %xmm0, %xmm0
-; NOFMA-NEXT: vaddsubps %xmm2, %xmm0, %xmm0
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_addsub_ps128:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmaddsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) +/- xmm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_addsub_ps128:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmaddsubps {{.*#+}} xmm0 = (xmm0 * xmm1) +/- xmm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <4 x float> %C, %D
- %A0 = extractelement <4 x float> %A, i32 0
- %B0 = extractelement <4 x float> %B, i32 0
- %sub0 = fsub contract float %A0, %B0
- %A2 = extractelement <4 x float> %A, i32 2
- %B2 = extractelement <4 x float> %B, i32 2
- %sub2 = fsub contract float %A2, %B2
- %A1 = extractelement <4 x float> %A, i32 1
- %B1 = extractelement <4 x float> %B, i32 1
- %add1 = fadd contract float %A1, %B1
- %A3 = extractelement <4 x float> %A, i32 3
- %B3 = extractelement <4 x float> %B, i32 3
- %add3 = fadd contract float %A3, %B3
- %vecinsert1 = insertelement <4 x float> undef, float %sub0, i32 0
- %vecinsert2 = insertelement <4 x float> %vecinsert1, float %add1, i32 1
- %vecinsert3 = insertelement <4 x float> %vecinsert2, float %sub2, i32 2
- %vecinsert4 = insertelement <4 x float> %vecinsert3, float %add3, i32 3
- ret <4 x float> %vecinsert4
-}
-
-define <2 x double> @buildvector_mul_addsub_pd128(<2 x double> %C, <2 x double> %D, <2 x double> %B) {
-; NOFMA-LABEL: buildvector_mul_addsub_pd128:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulpd %xmm1, %xmm0, %xmm0
-; NOFMA-NEXT: vaddsubpd %xmm2, %xmm0, %xmm0
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_addsub_pd128:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmaddsub213pd {{.*#+}} xmm0 = (xmm1 * xmm0) +/- xmm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_addsub_pd128:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmaddsubpd {{.*#+}} xmm0 = (xmm0 * xmm1) +/- xmm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <2 x double> %C, %D
- %A0 = extractelement <2 x double> %A, i32 0
- %B0 = extractelement <2 x double> %B, i32 0
- %sub0 = fsub contract double %A0, %B0
- %A1 = extractelement <2 x double> %A, i32 1
- %B1 = extractelement <2 x double> %B, i32 1
- %add1 = fadd contract double %A1, %B1
- %vecinsert1 = insertelement <2 x double> undef, double %sub0, i32 0
- %vecinsert2 = insertelement <2 x double> %vecinsert1, double %add1, i32 1
- ret <2 x double> %vecinsert2
-}
-
-define <8 x float> @buildvector_mul_addsub_ps256(<8 x float> %C, <8 x float> %D, <8 x float> %B) {
-; NOFMA-LABEL: buildvector_mul_addsub_ps256:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulps %ymm1, %ymm0, %ymm0
-; NOFMA-NEXT: vaddsubps %ymm2, %ymm0, %ymm0
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_addsub_ps256:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmaddsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_addsub_ps256:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmaddsubps {{.*#+}} ymm0 = (ymm0 * ymm1) +/- ymm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <8 x float> %C, %D
- %A0 = extractelement <8 x float> %A, i32 0
- %B0 = extractelement <8 x float> %B, i32 0
- %sub0 = fsub contract float %A0, %B0
- %A2 = extractelement <8 x float> %A, i32 2
- %B2 = extractelement <8 x float> %B, i32 2
- %sub2 = fsub contract float %A2, %B2
- %A4 = extractelement <8 x float> %A, i32 4
- %B4 = extractelement <8 x float> %B, i32 4
- %sub4 = fsub contract float %A4, %B4
- %A6 = extractelement <8 x float> %A, i32 6
- %B6 = extractelement <8 x float> %B, i32 6
- %sub6 = fsub contract float %A6, %B6
- %A1 = extractelement <8 x float> %A, i32 1
- %B1 = extractelement <8 x float> %B, i32 1
- %add1 = fadd contract float %A1, %B1
- %A3 = extractelement <8 x float> %A, i32 3
- %B3 = extractelement <8 x float> %B, i32 3
- %add3 = fadd contract float %A3, %B3
- %A5 = extractelement <8 x float> %A, i32 5
- %B5 = extractelement <8 x float> %B, i32 5
- %add5 = fadd contract float %A5, %B5
- %A7 = extractelement <8 x float> %A, i32 7
- %B7 = extractelement <8 x float> %B, i32 7
- %add7 = fadd contract float %A7, %B7
- %vecinsert1 = insertelement <8 x float> undef, float %sub0, i32 0
- %vecinsert2 = insertelement <8 x float> %vecinsert1, float %add1, i32 1
- %vecinsert3 = insertelement <8 x float> %vecinsert2, float %sub2, i32 2
- %vecinsert4 = insertelement <8 x float> %vecinsert3, float %add3, i32 3
- %vecinsert5 = insertelement <8 x float> %vecinsert4, float %sub4, i32 4
- %vecinsert6 = insertelement <8 x float> %vecinsert5, float %add5, i32 5
- %vecinsert7 = insertelement <8 x float> %vecinsert6, float %sub6, i32 6
- %vecinsert8 = insertelement <8 x float> %vecinsert7, float %add7, i32 7
- ret <8 x float> %vecinsert8
-}
-
-define <4 x double> @buildvector_mul_addsub_pd256(<4 x double> %C, <4 x double> %D, <4 x double> %B) {
-; NOFMA-LABEL: buildvector_mul_addsub_pd256:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulpd %ymm1, %ymm0, %ymm0
-; NOFMA-NEXT: vaddsubpd %ymm2, %ymm0, %ymm0
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_addsub_pd256:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmaddsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_addsub_pd256:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmaddsubpd {{.*#+}} ymm0 = (ymm0 * ymm1) +/- ymm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <4 x double> %C, %D
- %A0 = extractelement <4 x double> %A, i32 0
- %B0 = extractelement <4 x double> %B, i32 0
- %sub0 = fsub contract double %A0, %B0
- %A2 = extractelement <4 x double> %A, i32 2
- %B2 = extractelement <4 x double> %B, i32 2
- %sub2 = fsub contract double %A2, %B2
- %A1 = extractelement <4 x double> %A, i32 1
- %B1 = extractelement <4 x double> %B, i32 1
- %add1 = fadd contract double %A1, %B1
- %A3 = extractelement <4 x double> %A, i32 3
- %B3 = extractelement <4 x double> %B, i32 3
- %add3 = fadd contract double %A3, %B3
- %vecinsert1 = insertelement <4 x double> undef, double %sub0, i32 0
- %vecinsert2 = insertelement <4 x double> %vecinsert1, double %add1, i32 1
- %vecinsert3 = insertelement <4 x double> %vecinsert2, double %sub2, i32 2
- %vecinsert4 = insertelement <4 x double> %vecinsert3, double %add3, i32 3
- ret <4 x double> %vecinsert4
-}
-
define <16 x float> @buildvector_mul_addsub_ps512(<16 x float> %C, <16 x float> %D, <16 x float> %B) {
; NOFMA-LABEL: buildvector_mul_addsub_ps512:
; NOFMA: # %bb.0: # %bb
@@ -477,218 +321,6 @@ bb:
ret <8 x double> %vecinsert8
}
-define <4 x float> @buildvector_mul_subadd_ps128(<4 x float> %C, <4 x float> %D, <4 x float> %B) {
-; NOFMA-LABEL: buildvector_mul_subadd_ps128:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulps %xmm1, %xmm0, %xmm0
-; NOFMA-NEXT: vaddss %xmm2, %xmm0, %xmm1
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm4 = xmm2[1,0]
-; NOFMA-NEXT: vaddss %xmm4, %xmm3, %xmm3
-; NOFMA-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; NOFMA-NEXT: vmovshdup {{.*#+}} xmm5 = xmm2[1,1,3,3]
-; NOFMA-NEXT: vsubss %xmm5, %xmm4, %xmm4
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[2,3]
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
-; NOFMA-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; NOFMA-NEXT: vshufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
-; NOFMA-NEXT: vsubss %xmm2, %xmm0, %xmm0
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_subadd_ps128:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmsubadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_subadd_ps128:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmsubaddps {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <4 x float> %C, %D
- %A0 = extractelement <4 x float> %A, i32 0
- %B0 = extractelement <4 x float> %B, i32 0
- %sub0 = fadd contract float %A0, %B0
- %A2 = extractelement <4 x float> %A, i32 2
- %B2 = extractelement <4 x float> %B, i32 2
- %sub2 = fadd contract float %A2, %B2
- %A1 = extractelement <4 x float> %A, i32 1
- %B1 = extractelement <4 x float> %B, i32 1
- %add1 = fsub contract float %A1, %B1
- %A3 = extractelement <4 x float> %A, i32 3
- %B3 = extractelement <4 x float> %B, i32 3
- %add3 = fsub contract float %A3, %B3
- %vecinsert1 = insertelement <4 x float> undef, float %sub0, i32 0
- %vecinsert2 = insertelement <4 x float> %vecinsert1, float %add1, i32 1
- %vecinsert3 = insertelement <4 x float> %vecinsert2, float %sub2, i32 2
- %vecinsert4 = insertelement <4 x float> %vecinsert3, float %add3, i32 3
- ret <4 x float> %vecinsert4
-}
-
-define <2 x double> @buildvector_mul_subadd_pd128(<2 x double> %C, <2 x double> %D, <2 x double> %B) {
-; NOFMA-LABEL: buildvector_mul_subadd_pd128:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulpd %xmm1, %xmm0, %xmm0
-; NOFMA-NEXT: vaddsd %xmm2, %xmm0, %xmm1
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
-; NOFMA-NEXT: vsubsd %xmm2, %xmm0, %xmm0
-; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_subadd_pd128:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmsubadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_subadd_pd128:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmsubaddpd {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <2 x double> %C, %D
- %A0 = extractelement <2 x double> %A, i32 0
- %B0 = extractelement <2 x double> %B, i32 0
- %sub0 = fadd contract double %A0, %B0
- %A1 = extractelement <2 x double> %A, i32 1
- %B1 = extractelement <2 x double> %B, i32 1
- %add1 = fsub contract double %A1, %B1
- %vecinsert1 = insertelement <2 x double> undef, double %sub0, i32 0
- %vecinsert2 = insertelement <2 x double> %vecinsert1, double %add1, i32 1
- ret <2 x double> %vecinsert2
-}
-
-define <8 x float> @buildvector_mul_subadd_ps256(<8 x float> %C, <8 x float> %D, <8 x float> %B) {
-; NOFMA-LABEL: buildvector_mul_subadd_ps256:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulps %ymm1, %ymm0, %ymm0
-; NOFMA-NEXT: vaddss %xmm2, %xmm0, %xmm1
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm4 = xmm2[1,0]
-; NOFMA-NEXT: vaddss %xmm4, %xmm3, %xmm3
-; NOFMA-NEXT: vextractf128 $1, %ymm0, %xmm4
-; NOFMA-NEXT: vextractf128 $1, %ymm2, %xmm5
-; NOFMA-NEXT: vaddss %xmm5, %xmm4, %xmm6
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm7 = xmm4[1,0]
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm8 = xmm5[1,0]
-; NOFMA-NEXT: vaddss %xmm7, %xmm8, %xmm7
-; NOFMA-NEXT: vmovshdup {{.*#+}} xmm8 = xmm0[1,1,3,3]
-; NOFMA-NEXT: vmovshdup {{.*#+}} xmm9 = xmm2[1,1,3,3]
-; NOFMA-NEXT: vsubss %xmm9, %xmm8, %xmm8
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm8[0],xmm1[2,3]
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
-; NOFMA-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; NOFMA-NEXT: vshufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
-; NOFMA-NEXT: vsubss %xmm2, %xmm0, %xmm0
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
-; NOFMA-NEXT: vmovshdup {{.*#+}} xmm1 = xmm4[1,1,3,3]
-; NOFMA-NEXT: vmovshdup {{.*#+}} xmm2 = xmm5[1,1,3,3]
-; NOFMA-NEXT: vsubss %xmm2, %xmm1, %xmm1
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm6[0],xmm1[0],xmm6[2,3]
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm7[0],xmm1[3]
-; NOFMA-NEXT: vshufps {{.*#+}} xmm2 = xmm4[3,3,3,3]
-; NOFMA-NEXT: vshufps {{.*#+}} xmm3 = xmm5[3,3,3,3]
-; NOFMA-NEXT: vsubss %xmm3, %xmm2, %xmm2
-; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
-; NOFMA-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_subadd_ps256:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmsubadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_subadd_ps256:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <8 x float> %C, %D
- %A0 = extractelement <8 x float> %A, i32 0
- %B0 = extractelement <8 x float> %B, i32 0
- %sub0 = fadd contract float %A0, %B0
- %A2 = extractelement <8 x float> %A, i32 2
- %B2 = extractelement <8 x float> %B, i32 2
- %sub2 = fadd contract float %A2, %B2
- %A4 = extractelement <8 x float> %A, i32 4
- %B4 = extractelement <8 x float> %B, i32 4
- %sub4 = fadd contract float %A4, %B4
- %A6 = extractelement <8 x float> %A, i32 6
- %B6 = extractelement <8 x float> %B, i32 6
- %sub6 = fadd contract float %A6, %B6
- %A1 = extractelement <8 x float> %A, i32 1
- %B1 = extractelement <8 x float> %B, i32 1
- %add1 = fsub contract float %A1, %B1
- %A3 = extractelement <8 x float> %A, i32 3
- %B3 = extractelement <8 x float> %B, i32 3
- %add3 = fsub contract float %A3, %B3
- %A5 = extractelement <8 x float> %A, i32 5
- %B5 = extractelement <8 x float> %B, i32 5
- %add5 = fsub contract float %A5, %B5
- %A7 = extractelement <8 x float> %A, i32 7
- %B7 = extractelement <8 x float> %B, i32 7
- %add7 = fsub contract float %A7, %B7
- %vecinsert1 = insertelement <8 x float> undef, float %sub0, i32 0
- %vecinsert2 = insertelement <8 x float> %vecinsert1, float %add1, i32 1
- %vecinsert3 = insertelement <8 x float> %vecinsert2, float %sub2, i32 2
- %vecinsert4 = insertelement <8 x float> %vecinsert3, float %add3, i32 3
- %vecinsert5 = insertelement <8 x float> %vecinsert4, float %sub4, i32 4
- %vecinsert6 = insertelement <8 x float> %vecinsert5, float %add5, i32 5
- %vecinsert7 = insertelement <8 x float> %vecinsert6, float %sub6, i32 6
- %vecinsert8 = insertelement <8 x float> %vecinsert7, float %add7, i32 7
- ret <8 x float> %vecinsert8
-}
-
-define <4 x double> @buildvector_mul_subadd_pd256(<4 x double> %C, <4 x double> %D, <4 x double> %B) {
-; NOFMA-LABEL: buildvector_mul_subadd_pd256:
-; NOFMA: # %bb.0: # %bb
-; NOFMA-NEXT: vmulpd %ymm1, %ymm0, %ymm0
-; NOFMA-NEXT: vaddsd %xmm2, %xmm0, %xmm1
-; NOFMA-NEXT: vextractf128 $1, %ymm0, %xmm3
-; NOFMA-NEXT: vextractf128 $1, %ymm2, %xmm4
-; NOFMA-NEXT: vaddsd %xmm4, %xmm3, %xmm5
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
-; NOFMA-NEXT: vsubsd %xmm2, %xmm0, %xmm0
-; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm1 = xmm3[1,0]
-; NOFMA-NEXT: vshufpd {{.*#+}} xmm2 = xmm4[1,0]
-; NOFMA-NEXT: vsubsd %xmm2, %xmm1, %xmm1
-; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm5[0],xmm1[0]
-; NOFMA-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; NOFMA-NEXT: retq
-;
-; FMA3-LABEL: buildvector_mul_subadd_pd256:
-; FMA3: # %bb.0: # %bb
-; FMA3-NEXT: vfmsubadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2
-; FMA3-NEXT: retq
-;
-; FMA4-LABEL: buildvector_mul_subadd_pd256:
-; FMA4: # %bb.0: # %bb
-; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm2
-; FMA4-NEXT: retq
-bb:
- %A = fmul contract <4 x double> %C, %D
- %A0 = extractelement <4 x double> %A, i32 0
- %B0 = extractelement <4 x double> %B, i32 0
- %sub0 = fadd contract double %A0, %B0
- %A2 = extractelement <4 x double> %A, i32 2
- %B2 = extractelement <4 x double> %B, i32 2
- %sub2 = fadd contract double %A2, %B2
- %A1 = extractelement <4 x double> %A, i32 1
- %B1 = extractelement <4 x double> %B, i32 1
- %add1 = fsub contract double %A1, %B1
- %A3 = extractelement <4 x double> %A, i32 3
- %B3 = extractelement <4 x double> %B, i32 3
- %add3 = fsub contract double %A3, %B3
- %vecinsert1 = insertelement <4 x double> undef, double %sub0, i32 0
- %vecinsert2 = insertelement <4 x double> %vecinsert1, double %add1, i32 1
- %vecinsert3 = insertelement <4 x double> %vecinsert2, double %sub2, i32 2
- %vecinsert4 = insertelement <4 x double> %vecinsert3, double %add3, i32 3
- ret <4 x double> %vecinsert4
-}
-
define <16 x float> @buildvector_mul_subadd_ps512(<16 x float> %C, <16 x float> %D, <16 x float> %B) {
; NOFMA-LABEL: buildvector_mul_subadd_ps512:
; NOFMA: # %bb.0: # %bb
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