[llvm] [RISCV] Add SelectAddrRegImm26 isel complex pattern for Xqcilo 26-bit load/store (PR #207363)

[Craig Topper via llvm-commits]

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@@ -3589,6 +3589,55 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
   return true;
 }
 
+/// Similar to SelectAddrRegImm, except that the offset is a 26-bit signed
+/// immediate. This is used by the Qualcomm Xqcilo large offset load/store
+/// instructions (qc.e.lw/qc.e.sw), whose offset field is 26 bits wide.
+/// Only matches offsets that do not fit a 12-bit signed immediate, so that
+/// offsets in the simm12 range keep using the shorter (and possibly
+/// compressible) standard load/store instructions.
+bool RISCVDAGToDAGISel::SelectAddrRegImm26(SDValue Addr, SDValue &Base,
+                                           SDValue &Offset) {
+  SDLoc DL(Addr);
+  MVT VT = Addr.getSimpleValueType();
+
+  if (CurDAG->isBaseWithConstantOffset(Addr)) {
+    int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+    // Fold a 26-bit (but not 12-bit) signed offset directly into the
+    // load/store.
+    if (isInt<26>(CVal) && !isInt<12>(CVal)) {
+      Base = Addr.getOperand(0);
+      if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
+        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
+      Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
+      return true;
+    }
+  }
+
+  // The offset is just outside the 26-bit range. Split off a small (simm12)
+  // adjustment with a plain ADDI and fold the remaining 26-bit offset into the
+  // load/store. A plain ADDI is used (rather than the wide qc.e.addi/qc.e.addai)
+  // because the adjustment fits simm12: this keeps it a short, compressible
+  // (c.addi) instruction and is available without Xqcilia.
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topperc wrote:

This creates an addi with -2048 or 2047, which isn't compressible to c.addi.

https://github.com/llvm/llvm-project/pull/207363