[llvm] [GlobalISel][AArch64] Legalize PHIs with vectors smaller than 64-bits (PR #207356)

[David Green via llvm-commits]

https://github.com/davemgreen commented:

I think this should be something like `.widenScalarOrEltToNextPow2OrMinSize(0, 8)`, (perhaps with some optimizations later to make sure we optimize the result). i1 vectors might need a fair amount of optimizations as whatever you do will be wrong for one of the obvious cases.

Our widening vs promoting is inconsistent at the moment, but we were aiming to switch to more widening. I was hoping to remove widenVectorEltsToVectorMinSize. 

https://github.com/llvm/llvm-project/pull/207356