[llvm] AMDGPU/GlobalISel: Switch to extended LLTs (PR #207419)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 3 08:46:34 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
IRtranslator now translates bfloat. Switch tablegen to use extendedLLTs.
Around 300 regression tests fail to inst-select because GIM_SwitchType
does not accept LLT::scalar. Around 100 mir inst select tests had input
updated to i32/f32 and selects successfully. Then there are 24 various
crashes, mostly combiner or machine-verifier, those tests are disabled.
Most problems come from mixing s32 with i32/f32 and the way
operator== works with extendedLLTs compared to GIM_SwitchType.
In general, for inst-select fixes, think it would be best to try and avoid
explicit use of LLT::scalar in lowering to avoid mixing it with i32/f32
See inst-select-extendedLLTs.mir and inst-select-extendedLLTs-err.mir.
---
Patch is 29.98 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/207419.diff
691 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+1)
- (modified) llvm/lib/Target/AMDGPU/CMakeLists.txt (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll (+28-53)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll (+160-257)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll (+179-188)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll (+61-60)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll (+45-59)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll (+151-278)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll (+510-556)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll (+49-17)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll (+19-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll (+9-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll (+25-37)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll (+121-100)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll (+28-60)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll (+121-201)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll (+46-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll (+179-213)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll (+66-66)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll (+96-122)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll (+89-137)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll (+75-98)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll (+38-33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll (+29-29)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll (+66-74)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll (+960-491)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll (+17-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll (+8-19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll (+1305-3424)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll (+436-460)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll (+190-196)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll (+24-169)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll (+35-53)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll (+935-185)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll (+10-19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll (+3-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll (+8-19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll (+149-175)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll (+17-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll (+405-1317)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll (+420-264)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+3264-3798)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll (+3056-5528)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll (+3095-5582)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll (+8-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll (+589-589)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll (+4462-2736)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll (+5250-2205)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll (+589-926)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir (+26-22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir (+48-48)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir (+26-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir (+26-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir (+31-31)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir (+40-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir (+31-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir (+21-27)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir (+72-72)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir (+215-215)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir (+33-33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir (+28-28)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir (+125-125)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir (+52-52)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir (+8-8)
- (added) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs-err.mir (+671)
- (added) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir (+917)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir (+187-249)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir (+63-63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir (+86-86)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir (+77-77)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir (+38-38)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir (+85-64)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir (+267-234)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir (+84-56)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir (+84-84)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir (+168-128)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir (+85-64)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir (+63-63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir (+18-19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir (+383-454)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir (+36-36)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir (+33-33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir (+33-33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir (+2-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir (+45-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir (+75-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir (+27-27)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir (+45-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir (+54-54)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir (+34-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir (+102-72)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir (+36-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir (+36-32)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir (+18-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir (+72-72)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir (+215-215)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir (+33-33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (+31-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir (+21-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir (+21-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir (+57-57)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir (+64-64)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir (+57-57)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir (+64-64)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir (+27-27)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir (+48-48)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir (+59-59)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir (+72-72)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir (+146-146)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir (+10-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir (+72-72)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir (+215-215)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir (+33-33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir (+26-28)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir (+45-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir (+36-36)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir (+62-42)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir (+34-36)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir (+31-45)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir (+10-14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir (+17-17)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll (+133-133)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll (+76-76)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll (+300-300)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll (+48-47)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll (+32-32)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll (+70-67)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll (+240-240)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll (+279-279)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll (+1148-1114)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll (+74-74)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll (+33-33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll (+1663-1661)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll (+115-115)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll (+79-79)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll (+39-39)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll (+88-88)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll (+48-48)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll (+186-186)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll (+708-708)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir (+21-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir (+53-53)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (+225-225)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (+138-137)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir (+71-70)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir (+443-443)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 06bfc7e1a5162..c9797d8ce2d87 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -878,6 +878,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
else if (getMCSubtargetInfo().checkFeatures("+wavefrontsize32"))
MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
}
+ LLT::setUseExtended(true);
}
bool AMDGPUTargetMachine::EnableFunctionCalls = false;
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index 46edc44e2cc05..b7e679a69a80d 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -20,13 +20,13 @@ tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
-tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel -gisel-extended-llt)
tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
- -combiners="AMDGPUPreLegalizerCombiner")
+ -combiners="AMDGPUPreLegalizerCombiner" -gisel-extended-llt)
tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
- -combiners="AMDGPUPostLegalizerCombiner")
+ -combiners="AMDGPUPostLegalizerCombiner" -gisel-extended-llt)
tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner
- -combiners="AMDGPURegBankCombiner")
+ -combiners="AMDGPURegBankCombiner" -gisel-extended-llt)
set(LLVM_TARGET_DEFINITIONS R600.td)
tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
index 262254c8a9cf7..f268dbb56ed0e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12 %s
define i16 @s_add_i16(i16 inreg %a, i16 inreg %b) {
; GFX7-LABEL: s_add_i16:
@@ -200,13 +200,12 @@ define <2 x i16> @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX7-LABEL: s_add_v2i16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_lshr_b32 s4, s16, 16
-; GFX7-NEXT: s_lshr_b32 s5, s17, 16
-; GFX7-NEXT: s_add_i32 s4, s4, s5
+; GFX7-NEXT: s_lshr_b32 s4, s17, 16
+; GFX7-NEXT: s_lshr_b32 s5, s16, 16
+; GFX7-NEXT: s_add_i32 s5, s5, s4
; GFX7-NEXT: s_add_i32 s16, s16, s17
-; GFX7-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX7-NEXT: s_lshl_b32 s4, s5, 16
; GFX7-NEXT: s_and_b32 s5, s16, 0xffff
-; GFX7-NEXT: s_lshl_b32 s4, s4, 16
; GFX7-NEXT: s_or_b32 s4, s5, s4
; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -214,24 +213,19 @@ define <2 x i16> @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX9-LABEL: s_add_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_lshr_b32 s4, s16, 16
-; GFX9-NEXT: s_lshr_b32 s5, s17, 16
-; GFX9-NEXT: s_add_i32 s16, s16, s17
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
+; GFX9-NEXT: v_pk_add_u16 v0, s16, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: s_add_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_lshr_b32 s4, s16, 16
-; GFX8-NEXT: s_lshr_b32 s5, s17, 16
-; GFX8-NEXT: s_add_i32 s4, s4, s5
+; GFX8-NEXT: s_lshr_b32 s4, s17, 16
+; GFX8-NEXT: s_lshr_b32 s5, s16, 16
+; GFX8-NEXT: s_add_i32 s5, s5, s4
; GFX8-NEXT: s_add_i32 s16, s16, s17
-; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX8-NEXT: s_and_b32 s5, 0xffff, s16
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
+; GFX8-NEXT: s_lshl_b32 s4, s5, 16
+; GFX8-NEXT: s_and_b32 s5, s16, 0xffff
; GFX8-NEXT: s_or_b32 s4, s5, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -239,23 +233,13 @@ define <2 x i16> @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX10-LABEL: s_add_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_lshr_b32 s4, s16, 16
-; GFX10-NEXT: s_lshr_b32 s5, s17, 16
-; GFX10-NEXT: s_add_i32 s16, s16, s17
-; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s16, s4
-; GFX10-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-NEXT: v_pk_add_u16 v0, s16, s17
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_add_v2i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: s_lshr_b32 s3, s1, 16
-; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: s_add_i32 s2, s2, s3
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_pk_add_u16 v0, s0, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: s_add_v2i16:
@@ -265,15 +249,7 @@ define <2 x i16> @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-NEXT: s_lshr_b32 s3, s1, 16
-; GFX12-NEXT: s_add_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s2, s2, s3
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: v_pk_add_u16 v0, s0, s1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = add <2 x i16> %a, %b
ret <2 x i16> %c
@@ -283,14 +259,13 @@ define <2 x i16> @v_add_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX7-LABEL: v_add_v2i16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX7-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16:
@@ -302,9 +277,9 @@ define <2 x i16> @v_add_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX8-LABEL: v_add_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_add_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
index 1878465b477a5..a22c0b5932d7f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
@@ -1,22 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
define <2 x i16> @v_add_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX7-LABEL: v_add_v2i16:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX7-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16:
@@ -28,9 +27,9 @@ define <2 x i16> @v_add_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX8-LABEL: v_add_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_add_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16:
@@ -47,14 +46,13 @@ define <2 x i16> @v_add_v2i16_fneg_lhs(<2 x half> %a, <2 x i16> %b) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX7-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_fneg_lhs:
@@ -67,9 +65,9 @@ define <2 x i16> @v_add_v2i16_fneg_lhs(<2 x half> %a, <2 x i16> %b) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX8-NEXT: v_add_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16_fneg_lhs:
@@ -90,12 +88,11 @@ define <2 x i16> @v_add_v2i16_fneg_rhs(<2 x i16> %a, <2 x half> %b) {
; GFX7-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_fneg_rhs:
@@ -108,9 +105,9 @@ define <2 x i16> @v_add_v2i16_fneg_rhs(<2 x i16> %a, <2 x half> %b) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
-; GFX8-NEXT: v_add_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16_fneg_rhs:
@@ -134,7 +131,6 @@ define <2 x i16> @v_add_v2i16_fneg_lhs_fneg_rhs(<2 x half> %a, <2 x half> %b) {
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v3
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
@@ -173,13 +169,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
; GFX7-LABEL: v_add_v2i16_neg_inline_imm_splat:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc0, v1
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc0, v0
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_subrev_i32_e32 v1, vcc, 64, v0
+; GFX7-NEXT: s_mov_b32 s4, 0xffff0000
+; GFX7-NEXT: v_bfi_b32 v0, s4, v0, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffc00000, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_neg_inline_imm_splat:
@@ -191,10 +184,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
; GFX8-LABEL: v_add_v2i16_neg_inline_imm_splat:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_add_u16_e32 v2, 0xffc0, v0
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 64
+; GFX8-NEXT: v_sub_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_subrev_u16_e32 v0, 64, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16_neg_inline_imm_splat:
@@ -210,13 +203,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_lo(<2 x i16> %a) {
; GFX7-LABEL: v_add_v2i16_neg_inline_imm_lo:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, 4, v1
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc0, v0
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_subrev_i32_e32 v1, vcc, 64, v0
+; GFX7-NEXT: s_mov_b32 s4, 0xffff0000
+; GFX7-NEXT: v_bfi_b32 v0, s4, v0, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0x40000, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_neg_inline_imm_lo:
@@ -229,10 +219,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_lo(<2 x i16> %a) {
; GFX8-LABEL: v_add_v2i16_neg_inline_imm_lo:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, 4
-; GFX8-NEXT: v_add_u16_e32 v1, 0xffc0, v0
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 4
+; GFX8-NEXT: v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_subrev_u16_e32 v0, 64, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16_neg_inline_imm_lo:
@@ -248,13 +238,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_hi(<2 x i16> %a) {
; GFX7-LABEL: v_add_v2i16_neg_inline_imm_hi:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc0, v1
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, 4, v0
-; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_add_i32_e32 v1, vcc, 4, v0
+; GFX7-NEXT: s_mov_b32 s4, 0xffff0000
+; GFX7-NEXT: v_bfi_b32 v0, s4, v0, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffc00000, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_neg_inline_imm_hi:
@@ -267,10 +254,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_hi(<2 x i16> %a) {
; GFX8-LABEL: v_add_v2i16_neg_inline_imm_hi:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_not_b32_e32 v1, 63
-; GFX8-NEXT: v_add_u16_e32 v2, 4, v0
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 64
+; GFX8-NEXT: v_add_u16_e32 v1, 4, v0
+; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16_neg_inline_imm_hi:
@@ -285,40 +272,32 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_hi(<2 x i16> %a) {
define amdgpu_ps i32 @s_add_v2i16_neg_inline_imm_splat(<2 x i16> inreg %a) {
; GFX7-LABEL: s_add_v2i16_neg_inline_imm_splat:
; ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/207419
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