[llvm] [AMDGPU] Improve codegen for copysign(x, fneg(y)) (PR #207178)

[Madhur Kumar via llvm-commits]

MadhurKumar004 wrote:

> So maybe it would make sense to add patterns for the (fcopysign (f32 fpimm_zero), (fneg f32:$src1)) case too?

That make sense - I am new to AMDGPU backend so a little help would be appreciated. I will revise the patch to use tablegen pattern instead of dag combine. I can fix the fpimm_pos_zero -> fpimm_zero in the existing pattern as a separate NFC patch if you'd like.

> Alternatively maybe all fcopysign should get lowered to bit twiddling before we get to instruction selection, so that generic DAG combines can do this optimization for us.

I think a tablegen pattern would be cleaner and more localized than lowering all fcopysign to bit operations - but i am happy to do either if you have a preference.

https://github.com/llvm/llvm-project/pull/207178