[llvm] [RISCV] Add AddrRegImm26 addressing mode for Xqcilo large-offset load/store (PR #207363)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index c8518d264..be507ce10 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3619,8 +3619,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm26(SDValue Addr, SDValue &Base,
   // destructive qc.e.addai, the ADDI writes a fresh register, keeping the
   // base live for other uses (avoiding an extra copy).
   // Handle ADD with large immediates.
-  if (Addr.getOpcode() == ISD::ADD &&
-      isa<ConstantSDNode>(Addr.getOperand(1))) {
+  if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Addr.getOperand(1))) {
     int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
     // Only offsets that don't fit simm26 need splitting; simm26 (but not
     // simm12) offsets are folded directly above, and simm12 offsets are left
@@ -3629,9 +3628,9 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm26(SDValue Addr, SDValue &Base,
       int64_t Adj = CVal < 0 ? -2048 : 2047;
       if (isInt<26>(CVal - Adj)) {
         Base = SDValue(CurDAG->getMachineNode(
-                            RISCV::ADDI, DL, VT, Addr.getOperand(0),
-                            CurDAG->getSignedTargetConstant(Adj, DL, VT)),
-                        0);
+                           RISCV::ADDI, DL, VT, Addr.getOperand(0),
+                           CurDAG->getSignedTargetConstant(Adj, DL, VT)),
+                       0);
         Offset = CurDAG->getSignedTargetConstant(CVal - Adj, DL, VT);
         return true;
       }

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https://github.com/llvm/llvm-project/pull/207363