[llvm] [RegisterPressure] Remove dead defs correctly (PR #156576)
Hongyu Chen via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 3 02:50:53 PDT 2026
https://github.com/XChy updated https://github.com/llvm/llvm-project/pull/156576
>From 11ad2985aeebb6865cf7503af2de9dc69a19ff77 Mon Sep 17 00:00:00 2001
From: XChy <xxs_chy at outlook.com>
Date: Fri, 3 Jul 2026 17:48:15 +0800
Subject: [PATCH] [RegisterPressure] Remove dead defs correctly
---
llvm/lib/CodeGen/RegisterPressure.cpp | 43 +-
llvm/test/CodeGen/X86/clmul.ll | 859 ------------------
.../CodeGen/X86/dead-register-pr76416.mir | 32 +
llvm/test/CodeGen/X86/inline-asm-pr155807.ll | 21 +
llvm/test/CodeGen/X86/inline-asm-pr76416.ll | 75 ++
llvm/test/CodeGen/X86/pr205272.ll | 23 +
llvm/test/CodeGen/X86/ssub_sat_plus.ll | 4 +-
llvm/test/CodeGen/X86/usub_sat_plus.ll | 4 +-
llvm/test/CodeGen/X86/xmulo.ll | 12 +-
9 files changed, 193 insertions(+), 880 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/dead-register-pr76416.mir
create mode 100644 llvm/test/CodeGen/X86/inline-asm-pr155807.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-pr76416.ll
create mode 100644 llvm/test/CodeGen/X86/pr205272.ll
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index dd7468a1309de..0fe766782a52e 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -476,25 +476,45 @@ class RegisterOperandsCollector {
: RegOpers(RegOpers), TRI(TRI), MRI(MRI), IgnoreDead(IgnoreDead) {}
void collectInstr(const MachineInstr &MI) const {
- for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
- collectOperand(*OperI);
+ RegisterOperands ImplicitDefs;
+ for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI) {
+ if (OperI->isReg() && OperI->isImplicit() && OperI->isDef())
+ collectOperand(*OperI, ImplicitDefs);
+ else
+ collectOperand(*OperI, RegOpers);
+ }
- // Remove redundant physreg dead defs.
- for (const VRegMaskOrUnit &P : RegOpers.Defs)
- removeRegLanes(RegOpers.DeadDefs, P);
+ // Remove redundant physreg dead defs according to definition order.
+ mergeDeadDefs(ImplicitDefs);
}
void collectInstrLanes(const MachineInstr &MI) const {
- for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
- collectOperandLanes(*OperI);
+ RegisterOperands ImplicitDefs;
+ for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI) {
+ if (OperI->isReg() && OperI->isImplicit() && OperI->isDef())
+ collectOperandLanes(*OperI, ImplicitDefs);
+ else
+ collectOperandLanes(*OperI, RegOpers);
+ }
+
+ // Remove redundant physreg dead defs according to definition order.
+ mergeDeadDefs(ImplicitDefs);
+ }
- // Remove redundant physreg dead defs.
- for (const VRegMaskOrUnit &P : RegOpers.Defs)
+ void mergeDeadDefs(RegisterOperands &ImplicitDefs) const{
+ for (const VRegMaskOrUnit &P : RegOpers.DeadDefs)
+ removeRegLanes(RegOpers.Defs, P);
+ for (const VRegMaskOrUnit &P : ImplicitDefs.Defs)
removeRegLanes(RegOpers.DeadDefs, P);
+ for (const VRegMaskOrUnit &P : ImplicitDefs.DeadDefs)
+ removeRegLanes(ImplicitDefs.Defs, P);
+ RegOpers.Defs.append(ImplicitDefs.Defs);
+ RegOpers.DeadDefs.append(ImplicitDefs.DeadDefs);
}
/// Push this operand's register onto the correct vectors.
- void collectOperand(const MachineOperand &MO) const {
+ void collectOperand(const MachineOperand &MO,
+ RegisterOperands &RegOpers) const {
if (!MO.isReg() || !MO.getReg())
return;
Register Reg = MO.getReg();
@@ -526,7 +546,8 @@ class RegisterOperandsCollector {
}
}
- void collectOperandLanes(const MachineOperand &MO) const {
+ void collectOperandLanes(const MachineOperand &MO,
+ RegisterOperands &RegOpers) const {
if (!MO.isReg() || !MO.getReg())
return;
Register Reg = MO.getReg();
diff --git a/llvm/test/CodeGen/X86/clmul.ll b/llvm/test/CodeGen/X86/clmul.ll
index 3394d7081a677..5f82602b3382c 100644
--- a/llvm/test/CodeGen/X86/clmul.ll
+++ b/llvm/test/CodeGen/X86/clmul.ll
@@ -1902,862 +1902,3 @@ define void @mul_use_commutative_clmul_i8(i8 %x, i8 %y, ptr %p0, ptr %p1) nounwi
store i8 %yx, ptr %p1
ret void
}
-
-
-define i8 @clmul_i8_allones(i8 %x) nounwind {
-; SCALAR-LABEL: clmul_i8_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: # kill: def $edi killed $edi def $rdi
-; SCALAR-NEXT: leal (%rdi,%rdi), %eax
-; SCALAR-NEXT: xorb %dil, %al
-; SCALAR-NEXT: leal (,%rax,4), %ecx
-; SCALAR-NEXT: xorb %al, %cl
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shlb $4, %al
-; SCALAR-NEXT: xorb %cl, %al
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i8_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $255, %eax
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: # kill: def $al killed $al killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i8_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $255, %eax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: # kill: def $al killed $al killed $rax
-; AVX-NEXT: retq
- %r = call i8 @llvm.clmul.i8(i8 %x, i8 -1)
- ret i8 %r
-}
-
-define i16 @clmul_i16_allones(i16 %x) nounwind {
-; SCALAR-LABEL: clmul_i16_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: # kill: def $edi killed $edi def $rdi
-; SCALAR-NEXT: leal (%rdi,%rdi), %eax
-; SCALAR-NEXT: xorl %edi, %eax
-; SCALAR-NEXT: leal (,%rax,4), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %edx
-; SCALAR-NEXT: shll $4, %edx
-; SCALAR-NEXT: xorl %ecx, %edx
-; SCALAR-NEXT: movl %edx, %eax
-; SCALAR-NEXT: shll $8, %eax
-; SCALAR-NEXT: xorl %edx, %eax
-; SCALAR-NEXT: # kill: def $ax killed $ax killed $eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i16_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $65535, %eax # imm = 0xFFFF
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: # kill: def $ax killed $ax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i16_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $65535, %eax # imm = 0xFFFF
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: # kill: def $ax killed $ax killed $rax
-; AVX-NEXT: retq
- %r = call i16 @llvm.clmul.i16(i16 %x, i16 -1)
- ret i16 %r
-}
-
-define i32 @clmul_i32_allones(i32 %x) nounwind {
-; SCALAR-LABEL: clmul_i32_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: # kill: def $edi killed $edi def $rdi
-; SCALAR-NEXT: leal (%rdi,%rdi), %eax
-; SCALAR-NEXT: xorl %edi, %eax
-; SCALAR-NEXT: leal (,%rax,4), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shll $4, %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: movl %eax, %ecx
-; SCALAR-NEXT: shll $8, %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shll $16, %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i32_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: # kill: def $eax killed $eax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i32_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: # kill: def $eax killed $eax killed $rax
-; AVX-NEXT: retq
- %r = call i32 @llvm.clmul.i32(i32 %x, i32 -1)
- ret i32 %r
-}
-
-define i64 @clmul_i64_allones(i64 %x) nounwind {
-; SCALAR-LABEL: clmul_i64_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: leaq (%rdi,%rdi), %rax
-; SCALAR-NEXT: xorq %rdi, %rax
-; SCALAR-NEXT: leaq (,%rax,4), %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rax
-; SCALAR-NEXT: shlq $4, %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: movq %rax, %rcx
-; SCALAR-NEXT: shlq $8, %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rdx
-; SCALAR-NEXT: shlq $16, %rdx
-; SCALAR-NEXT: xorq %rcx, %rdx
-; SCALAR-NEXT: movq %rdx, %rax
-; SCALAR-NEXT: shlq $32, %rax
-; SCALAR-NEXT: xorq %rdx, %rax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i64_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movq $-1, %rax
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movq %rdi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i64_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movq $-1, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovq %rdi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: retq
- %r = call i64 @llvm.clmul.i64(i64 %x, i64 -1)
- ret i64 %r
-}
-
-define i7 @clmul_i7_allones(i7 %x) nounwind {
-; SCALAR-LABEL: clmul_i7_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: # kill: def $edi killed $edi def $rdi
-; SCALAR-NEXT: leal (%rdi,%rdi), %eax
-; SCALAR-NEXT: xorb %dil, %al
-; SCALAR-NEXT: leal (,%rax,4), %ecx
-; SCALAR-NEXT: xorb %al, %cl
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shlb $4, %al
-; SCALAR-NEXT: xorb %cl, %al
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i7_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $127, %eax
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: # kill: def $al killed $al killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i7_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $127, %eax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: # kill: def $al killed $al killed $rax
-; AVX-NEXT: retq
- %r = call i7 @llvm.clmul.i7(i7 %x, i7 -1)
- ret i7 %r
-}
-
-define i10 @clmul_i10_allones(i10 %x) nounwind {
-; SCALAR-LABEL: clmul_i10_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: # kill: def $edi killed $edi def $rdi
-; SCALAR-NEXT: leal (%rdi,%rdi), %eax
-; SCALAR-NEXT: xorl %edi, %eax
-; SCALAR-NEXT: leal (,%rax,4), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %edx
-; SCALAR-NEXT: shll $4, %edx
-; SCALAR-NEXT: xorl %ecx, %edx
-; SCALAR-NEXT: movl %edx, %eax
-; SCALAR-NEXT: shll $8, %eax
-; SCALAR-NEXT: xorl %edx, %eax
-; SCALAR-NEXT: # kill: def $ax killed $ax killed $eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i10_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $1023, %eax # imm = 0x3FF
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: # kill: def $ax killed $ax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i10_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $1023, %eax # imm = 0x3FF
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: # kill: def $ax killed $ax killed $rax
-; AVX-NEXT: retq
- %r = call i10 @llvm.clmul.i10(i10 %x, i10 -1)
- ret i10 %r
-}
-
-define i25 @clmul_i25_allones(i25 %x) nounwind {
-; SCALAR-LABEL: clmul_i25_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: # kill: def $edi killed $edi def $rdi
-; SCALAR-NEXT: leal (%rdi,%rdi), %eax
-; SCALAR-NEXT: xorl %edi, %eax
-; SCALAR-NEXT: leal (,%rax,4), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shll $4, %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: movl %eax, %ecx
-; SCALAR-NEXT: shll $8, %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shll $16, %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i25_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $33554431, %eax # imm = 0x1FFFFFF
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: # kill: def $eax killed $eax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i25_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $33554431, %eax # imm = 0x1FFFFFF
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: # kill: def $eax killed $eax killed $rax
-; AVX-NEXT: retq
- %r = call i25 @llvm.clmul.i25(i25 %x, i25 -1)
- ret i25 %r
-}
-
-define i44 @clmul_i44_allones(i44 %x) nounwind {
-; SCALAR-LABEL: clmul_i44_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: leaq (%rdi,%rdi), %rax
-; SCALAR-NEXT: xorq %rdi, %rax
-; SCALAR-NEXT: leaq (,%rax,4), %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rax
-; SCALAR-NEXT: shlq $4, %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: movq %rax, %rcx
-; SCALAR-NEXT: shlq $8, %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rdx
-; SCALAR-NEXT: shlq $16, %rdx
-; SCALAR-NEXT: xorq %rcx, %rdx
-; SCALAR-NEXT: movq %rdx, %rax
-; SCALAR-NEXT: shlq $32, %rax
-; SCALAR-NEXT: xorq %rdx, %rax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmul_i44_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movabsq $17592186044415, %rax # imm = 0xFFFFFFFFFFF
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movq %rdi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmul_i44_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movabsq $17592186044415, %rax # imm = 0xFFFFFFFFFFF
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovq %rdi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: retq
- %r = call i44 @llvm.clmul.i44(i44 %x, i44 -1)
- ret i44 %r
-}
-
-define i8 @clmulr_i8_allones(i8 %x) nounwind {
-; SCALAR-LABEL: clmulr_i8_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: movzbl %dil, %eax
-; SCALAR-NEXT: leal (%rax,%rax), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: leal (,%rcx,4), %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: movl %eax, %ecx
-; SCALAR-NEXT: shll $4, %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shll $8, %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: shrl $7, %eax
-; SCALAR-NEXT: # kill: def $al killed $al killed $eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmulr_i8_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $65535, %eax # imm = 0xFFFF
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movzbl %dil, %eax
-; SSE-PCLMUL-NEXT: movd %eax, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: shrl $7, %eax
-; SSE-PCLMUL-NEXT: # kill: def $al killed $al killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulr_i8_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $65535, %eax # imm = 0xFFFF
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: movzbl %dil, %eax
-; AVX-NEXT: vmovd %eax, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: shrl $7, %eax
-; AVX-NEXT: # kill: def $al killed $al killed $rax
-; AVX-NEXT: retq
- %x.ext = zext i8 %x to i16
- %clmul = call i16 @llvm.clmul.i16(i16 %x.ext, i16 -1)
- %res.ext = lshr i16 %clmul, 7
- %res = trunc i16 %res.ext to i8
- ret i8 %res
-}
-
-define i16 @clmulr_i16_allones(i16 %x) nounwind {
-; SCALAR-LABEL: clmulr_i16_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: movzwl %di, %eax
-; SCALAR-NEXT: leal (%rax,%rax), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: leal (,%rcx,4), %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: movl %eax, %ecx
-; SCALAR-NEXT: shll $4, %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %edx
-; SCALAR-NEXT: shll $8, %edx
-; SCALAR-NEXT: xorl %ecx, %edx
-; SCALAR-NEXT: movl %edx, %eax
-; SCALAR-NEXT: shll $16, %eax
-; SCALAR-NEXT: xorl %edx, %eax
-; SCALAR-NEXT: shrl $15, %eax
-; SCALAR-NEXT: # kill: def $ax killed $ax killed $eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmulr_i16_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movzwl %di, %eax
-; SSE-PCLMUL-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
-; SSE-PCLMUL-NEXT: movq %rcx, %xmm0
-; SSE-PCLMUL-NEXT: movd %eax, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: shrl $15, %eax
-; SSE-PCLMUL-NEXT: # kill: def $ax killed $ax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulr_i16_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movzwl %di, %eax
-; AVX-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
-; AVX-NEXT: vmovq %rcx, %xmm0
-; AVX-NEXT: vmovd %eax, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: shrl $15, %eax
-; AVX-NEXT: # kill: def $ax killed $ax killed $rax
-; AVX-NEXT: retq
- %x.ext = zext i16 %x to i32
- %clmul = call i32 @llvm.clmul.i32(i32 %x.ext, i32 -1)
- %res.ext = lshr i32 %clmul, 15
- %res = trunc i32 %res.ext to i16
- ret i16 %res
-}
-
-define i32 @clmulr_i32_allones(i32 %x) nounwind {
-; SCALAR-LABEL: clmulr_i32_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: movl %edi, %eax
-; SCALAR-NEXT: leaq (%rax,%rax), %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: leaq (,%rcx,4), %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: movq %rax, %rcx
-; SCALAR-NEXT: shlq $4, %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rax
-; SCALAR-NEXT: shlq $8, %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: movq %rax, %rcx
-; SCALAR-NEXT: shlq $16, %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rax
-; SCALAR-NEXT: shlq $32, %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: shrq $31, %rax
-; SCALAR-NEXT: # kill: def $eax killed $eax killed $rax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmulr_i32_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movq $-1, %rax
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: shrq $31, %rax
-; SSE-PCLMUL-NEXT: # kill: def $eax killed $eax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulr_i32_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movq $-1, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: shrq $31, %rax
-; AVX-NEXT: # kill: def $eax killed $eax killed $rax
-; AVX-NEXT: retq
- %x.ext = zext i32 %x to i64
- %clmul = call i64 @llvm.clmul.i64(i64 %x.ext, i64 -1)
- %res.ext = lshr i64 %clmul, 31
- %res = trunc i64 %res.ext to i32
- ret i32 %res
-}
-
-define i64 @clmulr_i64_allones(i64 %x) nounwind {
-; SCALAR-LABEL: clmulr_i64_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: leaq (%rdi,%rdi), %rcx
-; SCALAR-NEXT: xorq %rdi, %rcx
-; SCALAR-NEXT: bswapq %rdi
-; SCALAR-NEXT: movq %rdi, %rax
-; SCALAR-NEXT: shrq $4, %rax
-; SCALAR-NEXT: movabsq $1085102592571150095, %rsi # imm = 0xF0F0F0F0F0F0F0F
-; SCALAR-NEXT: andq %rsi, %rax
-; SCALAR-NEXT: andq %rsi, %rdi
-; SCALAR-NEXT: shlq $4, %rdi
-; SCALAR-NEXT: orq %rax, %rdi
-; SCALAR-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
-; SCALAR-NEXT: movq %rdi, %rdx
-; SCALAR-NEXT: andq %rax, %rdx
-; SCALAR-NEXT: shrq $2, %rdi
-; SCALAR-NEXT: andq %rax, %rdi
-; SCALAR-NEXT: leaq (%rdi,%rdx,4), %rdi
-; SCALAR-NEXT: movabsq $6148914691236517205, %rdx # imm = 0x5555555555555555
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: andq %rdx, %r8
-; SCALAR-NEXT: shrq %rdi
-; SCALAR-NEXT: andq %rdx, %rdi
-; SCALAR-NEXT: leaq (%rdi,%r8,2), %rdi
-; SCALAR-NEXT: leaq (%rdi,%rdi), %r8
-; SCALAR-NEXT: xorq %rdi, %r8
-; SCALAR-NEXT: leaq (,%r8,4), %rdi
-; SCALAR-NEXT: xorq %r8, %rdi
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: shlq $4, %r8
-; SCALAR-NEXT: xorq %rdi, %r8
-; SCALAR-NEXT: movq %r8, %rdi
-; SCALAR-NEXT: shlq $8, %rdi
-; SCALAR-NEXT: xorq %r8, %rdi
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: shlq $16, %r8
-; SCALAR-NEXT: xorq %rdi, %r8
-; SCALAR-NEXT: movq %r8, %rdi
-; SCALAR-NEXT: shlq $32, %rdi
-; SCALAR-NEXT: xorq %r8, %rdi
-; SCALAR-NEXT: bswapq %rdi
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: shrq $4, %r8
-; SCALAR-NEXT: andq %rsi, %r8
-; SCALAR-NEXT: andq %rsi, %rdi
-; SCALAR-NEXT: shlq $4, %rdi
-; SCALAR-NEXT: orq %r8, %rdi
-; SCALAR-NEXT: movq %rdi, %rsi
-; SCALAR-NEXT: andq %rax, %rsi
-; SCALAR-NEXT: shrq $2, %rdi
-; SCALAR-NEXT: andq %rax, %rdi
-; SCALAR-NEXT: leaq (%rdi,%rsi,4), %rax
-; SCALAR-NEXT: andq %rax, %rdx
-; SCALAR-NEXT: shrq %rax
-; SCALAR-NEXT: movabsq $6148914691236517204, %rsi # imm = 0x5555555555555554
-; SCALAR-NEXT: andq %rax, %rsi
-; SCALAR-NEXT: leaq (%rsi,%rdx,2), %rax
-; SCALAR-NEXT: shrq %rax
-; SCALAR-NEXT: leaq (,%rcx,4), %rdx
-; SCALAR-NEXT: xorq %rcx, %rdx
-; SCALAR-NEXT: movq %rdx, %rcx
-; SCALAR-NEXT: shlq $4, %rcx
-; SCALAR-NEXT: xorq %rdx, %rcx
-; SCALAR-NEXT: movq %rcx, %rdx
-; SCALAR-NEXT: shlq $8, %rdx
-; SCALAR-NEXT: xorq %rcx, %rdx
-; SCALAR-NEXT: movq %rdx, %rcx
-; SCALAR-NEXT: shlq $16, %rcx
-; SCALAR-NEXT: xorq %rdx, %rcx
-; SCALAR-NEXT: movq %rcx, %rdx
-; SCALAR-NEXT: shlq $32, %rdx
-; SCALAR-NEXT: xorq %rcx, %rdx
-; SCALAR-NEXT: xorq %rdx, %rax
-; SCALAR-NEXT: shldq $1, %rdx, %rax
-; SCALAR-NEXT: retq
-;
-; SSE2-PCLMUL-LABEL: clmulr_i64_allones:
-; SSE2-PCLMUL: # %bb.0:
-; SSE2-PCLMUL-NEXT: movq $-1, %rax
-; SSE2-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE2-PCLMUL-NEXT: movq %rdi, %xmm1
-; SSE2-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE2-PCLMUL-NEXT: movq %xmm1, %rcx
-; SSE2-PCLMUL-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
-; SSE2-PCLMUL-NEXT: movq %xmm0, %rax
-; SSE2-PCLMUL-NEXT: xorq %rcx, %rax
-; SSE2-PCLMUL-NEXT: shldq $1, %rcx, %rax
-; SSE2-PCLMUL-NEXT: retq
-;
-; SSE42-PCLMUL-LABEL: clmulr_i64_allones:
-; SSE42-PCLMUL: # %bb.0:
-; SSE42-PCLMUL-NEXT: movq $-1, %rax
-; SSE42-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE42-PCLMUL-NEXT: movq %rdi, %xmm1
-; SSE42-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE42-PCLMUL-NEXT: movq %xmm1, %rcx
-; SSE42-PCLMUL-NEXT: pextrq $1, %xmm1, %rax
-; SSE42-PCLMUL-NEXT: xorq %rcx, %rax
-; SSE42-PCLMUL-NEXT: shldq $1, %rcx, %rax
-; SSE42-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulr_i64_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movq $-1, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovq %rdi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: vpextrq $1, %xmm0, %rax
-; AVX-NEXT: xorq %rcx, %rax
-; AVX-NEXT: shldq $1, %rcx, %rax
-; AVX-NEXT: retq
- %x.ext = zext i64 %x to i128
- %clmul = call i128 @llvm.clmul.i128(i128 %x.ext, i128 -1)
- %res.ext = lshr i128 %clmul, 63
- %res = trunc i128 %res.ext to i64
- ret i64 %res
-}
-
-define i8 @clmulh_i8_allones(i8 %x) nounwind {
-; SCALAR-LABEL: clmulh_i8_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: movzbl %dil, %eax
-; SCALAR-NEXT: leal (%rax,%rax), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: leal (,%rcx,4), %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: movl %eax, %ecx
-; SCALAR-NEXT: shll $4, %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %eax
-; SCALAR-NEXT: shll $8, %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: shrl $8, %eax
-; SCALAR-NEXT: # kill: def $al killed $al killed $eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmulh_i8_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movl $65535, %eax # imm = 0xFFFF
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movzbl %dil, %eax
-; SSE-PCLMUL-NEXT: movd %eax, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: shrl $8, %eax
-; SSE-PCLMUL-NEXT: # kill: def $al killed $al killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulh_i8_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $65535, %eax # imm = 0xFFFF
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: movzbl %dil, %eax
-; AVX-NEXT: vmovd %eax, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: shrl $8, %eax
-; AVX-NEXT: # kill: def $al killed $al killed $rax
-; AVX-NEXT: retq
- %x.ext = zext i8 %x to i16
- %clmul = call i16 @llvm.clmul.i16(i16 %x.ext, i16 -1)
- %res.ext = lshr i16 %clmul, 8
- %res = trunc i16 %res.ext to i8
- ret i8 %res
-}
-
-define i16 @clmulh_i16_allones(i16 %x) nounwind {
-; SCALAR-LABEL: clmulh_i16_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: movzwl %di, %eax
-; SCALAR-NEXT: leal (%rax,%rax), %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: leal (,%rcx,4), %eax
-; SCALAR-NEXT: xorl %ecx, %eax
-; SCALAR-NEXT: movl %eax, %ecx
-; SCALAR-NEXT: shll $4, %ecx
-; SCALAR-NEXT: xorl %eax, %ecx
-; SCALAR-NEXT: movl %ecx, %edx
-; SCALAR-NEXT: shll $8, %edx
-; SCALAR-NEXT: xorl %ecx, %edx
-; SCALAR-NEXT: movl %edx, %eax
-; SCALAR-NEXT: shll $16, %eax
-; SCALAR-NEXT: xorl %edx, %eax
-; SCALAR-NEXT: shrl $16, %eax
-; SCALAR-NEXT: # kill: def $ax killed $ax killed $eax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmulh_i16_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movzwl %di, %eax
-; SSE-PCLMUL-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
-; SSE-PCLMUL-NEXT: movq %rcx, %xmm0
-; SSE-PCLMUL-NEXT: movd %eax, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: shrl $16, %eax
-; SSE-PCLMUL-NEXT: # kill: def $ax killed $ax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulh_i16_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movzwl %di, %eax
-; AVX-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
-; AVX-NEXT: vmovq %rcx, %xmm0
-; AVX-NEXT: vmovd %eax, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: shrl $16, %eax
-; AVX-NEXT: # kill: def $ax killed $ax killed $rax
-; AVX-NEXT: retq
- %x.ext = zext i16 %x to i32
- %clmul = call i32 @llvm.clmul.i32(i32 %x.ext, i32 -1)
- %res.ext = lshr i32 %clmul, 16
- %res = trunc i32 %res.ext to i16
- ret i16 %res
-}
-
-define i32 @clmulh_i32_allones(i32 %x) nounwind {
-; SCALAR-LABEL: clmulh_i32_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: movl %edi, %eax
-; SCALAR-NEXT: leaq (%rax,%rax), %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: leaq (,%rcx,4), %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: movq %rax, %rcx
-; SCALAR-NEXT: shlq $4, %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rax
-; SCALAR-NEXT: shlq $8, %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: movq %rax, %rcx
-; SCALAR-NEXT: shlq $16, %rcx
-; SCALAR-NEXT: xorq %rax, %rcx
-; SCALAR-NEXT: movq %rcx, %rax
-; SCALAR-NEXT: shlq $32, %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: shrq $32, %rax
-; SCALAR-NEXT: # kill: def $eax killed $eax killed $rax
-; SCALAR-NEXT: retq
-;
-; SSE-PCLMUL-LABEL: clmulh_i32_allones:
-; SSE-PCLMUL: # %bb.0:
-; SSE-PCLMUL-NEXT: movq $-1, %rax
-; SSE-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE-PCLMUL-NEXT: movd %edi, %xmm1
-; SSE-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE-PCLMUL-NEXT: movq %xmm1, %rax
-; SSE-PCLMUL-NEXT: shrq $32, %rax
-; SSE-PCLMUL-NEXT: # kill: def $eax killed $eax killed $rax
-; SSE-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulh_i32_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movq $-1, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovd %edi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: shrq $32, %rax
-; AVX-NEXT: # kill: def $eax killed $eax killed $rax
-; AVX-NEXT: retq
- %x.ext = zext i32 %x to i64
- %clmul = call i64 @llvm.clmul.i64(i64 %x.ext, i64 -1)
- %res.ext = lshr i64 %clmul, 32
- %res = trunc i64 %res.ext to i32
- ret i32 %res
-}
-
-define i64 @clmulh_i64_allones(i64 %x) nounwind {
-; SCALAR-LABEL: clmulh_i64_allones:
-; SCALAR: # %bb.0:
-; SCALAR-NEXT: leaq (%rdi,%rdi), %rax
-; SCALAR-NEXT: xorq %rdi, %rax
-; SCALAR-NEXT: bswapq %rdi
-; SCALAR-NEXT: movq %rdi, %rcx
-; SCALAR-NEXT: shrq $4, %rcx
-; SCALAR-NEXT: movabsq $1085102592571150095, %rsi # imm = 0xF0F0F0F0F0F0F0F
-; SCALAR-NEXT: andq %rsi, %rcx
-; SCALAR-NEXT: andq %rsi, %rdi
-; SCALAR-NEXT: shlq $4, %rdi
-; SCALAR-NEXT: orq %rcx, %rdi
-; SCALAR-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
-; SCALAR-NEXT: movq %rdi, %rdx
-; SCALAR-NEXT: andq %rcx, %rdx
-; SCALAR-NEXT: shrq $2, %rdi
-; SCALAR-NEXT: andq %rcx, %rdi
-; SCALAR-NEXT: leaq (%rdi,%rdx,4), %rdi
-; SCALAR-NEXT: movabsq $6148914691236517205, %rdx # imm = 0x5555555555555555
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: andq %rdx, %r8
-; SCALAR-NEXT: shrq %rdi
-; SCALAR-NEXT: andq %rdx, %rdi
-; SCALAR-NEXT: leaq (%rdi,%r8,2), %rdi
-; SCALAR-NEXT: leaq (%rdi,%rdi), %r8
-; SCALAR-NEXT: xorq %rdi, %r8
-; SCALAR-NEXT: leaq (,%r8,4), %rdi
-; SCALAR-NEXT: xorq %r8, %rdi
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: shlq $4, %r8
-; SCALAR-NEXT: xorq %rdi, %r8
-; SCALAR-NEXT: movq %r8, %rdi
-; SCALAR-NEXT: shlq $8, %rdi
-; SCALAR-NEXT: xorq %r8, %rdi
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: shlq $16, %r8
-; SCALAR-NEXT: xorq %rdi, %r8
-; SCALAR-NEXT: movq %r8, %rdi
-; SCALAR-NEXT: shlq $32, %rdi
-; SCALAR-NEXT: xorq %r8, %rdi
-; SCALAR-NEXT: bswapq %rdi
-; SCALAR-NEXT: movq %rdi, %r8
-; SCALAR-NEXT: shrq $4, %r8
-; SCALAR-NEXT: andq %rsi, %r8
-; SCALAR-NEXT: andq %rsi, %rdi
-; SCALAR-NEXT: shlq $4, %rdi
-; SCALAR-NEXT: orq %r8, %rdi
-; SCALAR-NEXT: movq %rdi, %rsi
-; SCALAR-NEXT: andq %rcx, %rsi
-; SCALAR-NEXT: shrq $2, %rdi
-; SCALAR-NEXT: andq %rcx, %rdi
-; SCALAR-NEXT: leaq (%rdi,%rsi,4), %rcx
-; SCALAR-NEXT: andq %rcx, %rdx
-; SCALAR-NEXT: shrq %rcx
-; SCALAR-NEXT: movabsq $6148914691236517204, %rsi # imm = 0x5555555555555554
-; SCALAR-NEXT: andq %rcx, %rsi
-; SCALAR-NEXT: leaq (%rsi,%rdx,2), %rcx
-; SCALAR-NEXT: shrq %rcx
-; SCALAR-NEXT: leaq (,%rax,4), %rdx
-; SCALAR-NEXT: xorq %rax, %rdx
-; SCALAR-NEXT: movq %rdx, %rax
-; SCALAR-NEXT: shlq $4, %rax
-; SCALAR-NEXT: xorq %rdx, %rax
-; SCALAR-NEXT: movq %rax, %rdx
-; SCALAR-NEXT: shlq $8, %rdx
-; SCALAR-NEXT: xorq %rax, %rdx
-; SCALAR-NEXT: movq %rdx, %rsi
-; SCALAR-NEXT: shlq $16, %rsi
-; SCALAR-NEXT: xorq %rdx, %rsi
-; SCALAR-NEXT: movq %rsi, %rax
-; SCALAR-NEXT: shlq $32, %rax
-; SCALAR-NEXT: xorq %rsi, %rax
-; SCALAR-NEXT: xorq %rcx, %rax
-; SCALAR-NEXT: retq
-;
-; SSE2-PCLMUL-LABEL: clmulh_i64_allones:
-; SSE2-PCLMUL: # %bb.0:
-; SSE2-PCLMUL-NEXT: movq $-1, %rax
-; SSE2-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE2-PCLMUL-NEXT: movq %rdi, %xmm1
-; SSE2-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE2-PCLMUL-NEXT: movq %xmm1, %rcx
-; SSE2-PCLMUL-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
-; SSE2-PCLMUL-NEXT: movq %xmm0, %rax
-; SSE2-PCLMUL-NEXT: xorq %rcx, %rax
-; SSE2-PCLMUL-NEXT: retq
-;
-; SSE42-PCLMUL-LABEL: clmulh_i64_allones:
-; SSE42-PCLMUL: # %bb.0:
-; SSE42-PCLMUL-NEXT: movq $-1, %rax
-; SSE42-PCLMUL-NEXT: movq %rax, %xmm0
-; SSE42-PCLMUL-NEXT: movq %rdi, %xmm1
-; SSE42-PCLMUL-NEXT: pclmulqdq $0, %xmm0, %xmm1
-; SSE42-PCLMUL-NEXT: movq %xmm1, %rcx
-; SSE42-PCLMUL-NEXT: pextrq $1, %xmm1, %rax
-; SSE42-PCLMUL-NEXT: xorq %rcx, %rax
-; SSE42-PCLMUL-NEXT: retq
-;
-; AVX-LABEL: clmulh_i64_allones:
-; AVX: # %bb.0:
-; AVX-NEXT: movq $-1, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovq %rdi, %xmm1
-; AVX-NEXT: vpclmulqdq $0, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: vpextrq $1, %xmm0, %rax
-; AVX-NEXT: xorq %rcx, %rax
-; AVX-NEXT: retq
- %x.ext = zext i64 %x to i128
- %clmul = call i128 @llvm.clmul.i128(i128 %x.ext, i128 -1)
- %res.ext = lshr i128 %clmul, 64
- %res = trunc i128 %res.ext to i64
- ret i64 %res
-}
diff --git a/llvm/test/CodeGen/X86/dead-register-pr76416.mir b/llvm/test/CodeGen/X86/dead-register-pr76416.mir
new file mode 100644
index 0000000000000..f20080fcfb87d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dead-register-pr76416.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=x86_64-unknown-unknown -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+---
+name: vga_load_state
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $rdi
+
+ ; CHECK-LABEL: name: vga_load_state
+ ; CHECK: liveins: $rdi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: dead undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+ %0:gr64 = COPY $rdi
+ undef %1.sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+ dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+ INLINEASM &"", 1 /* sideeffect attdialect */
+ dead $eax = MOV32r0 implicit-def dead $eflags
+ INLINEASM &"", 1 /* sideeffect attdialect */
+ dead $eax = MOV32r0 implicit-def dead $eflags
+ dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax
+
+...
+
diff --git a/llvm/test/CodeGen/X86/inline-asm-pr155807.ll b/llvm/test/CodeGen/X86/inline-asm-pr155807.ll
new file mode 100644
index 0000000000000..3c10773dbb66c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-pr155807.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=x86_64 < %s | FileCheck %s
+
+; LiveVariable Analysis transforms (inlineasm rax, eax) to (inlineasm dead rax, eax)
+; instead of (inlineasm dead rax, dead eax). RegisterPressure fails at considering
+; eax as dead register.
+define i64 @pr155807(i64 %vecext) {
+; CHECK-LABEL: pr155807:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movabsq $705425148255374, %rax # imm = 0x2819497609C8E
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: idivq %rdi
+; CHECK-NEXT: movq %rdx, %rax
+; CHECK-NEXT: retq
+entry:
+ tail call void asm sideeffect "", "~{rax},~{eax},~{dirflag},~{fpsr},~{flags}"()
+ %rem = srem i64 705425148255374, %vecext
+ ret i64 %rem
+}
diff --git a/llvm/test/CodeGen/X86/inline-asm-pr76416.ll b/llvm/test/CodeGen/X86/inline-asm-pr76416.ll
new file mode 100644
index 0000000000000..b14a6eda7a6a6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-pr76416.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -O2 -mtriple=x86_64 < %s | FileCheck %s
+%struct.anon.5.28.78.99.149.119 = type { [4 x i8] }
+
+ at vga_load_state_p = external dso_local global ptr, align 8
+ at vga_load_state_data = external dso_local global i8, align 1
+
+define dso_local void @vga_load_state() #0 {
+; CHECK-LABEL: vga_load_state:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jg .LBB0_3
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB0_2: # %for.body
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jle .LBB0_2
+; CHECK-NEXT: .LBB0_3: # %for.end
+; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB0_4: # %for.cond1
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: # implicit-def: $edx
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movq vga_load_state_p(%rip), %rax
+; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
+; CHECK-NEXT: movzbl (%rax,%rcx), %eax
+; CHECK-NEXT: movb %al, vga_load_state_data(%rip)
+; CHECK-NEXT: leal 1(%rcx), %eax
+; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT: jmp .LBB0_4
+entry:
+ %i = alloca i32, align 4
+ store i32 0, ptr %i, align 4
+ br label %for.cond
+
+for.cond: ; preds = %for.body, %entry
+ %0 = load i32, ptr %i, align 4
+ %cmp = icmp slt i32 %0, 4
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body: ; preds = %for.cond
+ call void asm sideeffect "", "{ax},~{dirflag},~{fpsr},~{flags}"(i8 0) #2
+ %1 = load i32, ptr %i, align 4
+ %inc = add nsw i32 %1, 1
+ store i32 %inc, ptr %i, align 4
+ br label %for.cond
+
+for.end: ; preds = %for.cond
+ store i32 0, ptr %i, align 4
+ br label %for.cond1
+
+for.cond1: ; preds = %for.cond1, %for.end
+ call void asm sideeffect "", "N{dx},~{dirflag},~{fpsr},~{flags}"(i32 poison) #2
+ %2 = load ptr, ptr @vga_load_state_p, align 8
+ %regs = getelementptr inbounds %struct.anon.5.28.78.99.149.119, ptr %2, i32 0, i32 0
+ %3 = load i32, ptr %i, align 4
+ %idxprom = sext i32 %3 to i64
+ %arrayidx = getelementptr inbounds [4 x i8], ptr %regs, i64 0, i64 %idxprom
+ %4 = load i8, ptr %arrayidx, align 1
+ store i8 %4, ptr @vga_load_state_data, align 1
+ %5 = load i32, ptr %i, align 4
+ %inc5 = add nsw i32 %5, 1
+ store i32 %inc5, ptr %i, align 4
+ br label %for.cond1, !llvm.loop !1
+}
+
+!1 = distinct !{!1, !2}
+!2 = !{!"llvm.loop.mustprogress"}
diff --git a/llvm/test/CodeGen/X86/pr205272.ll b/llvm/test/CodeGen/X86/pr205272.ll
new file mode 100644
index 0000000000000..1cfdae2dcc110
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr205272.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+declare i64 @llvm.x86.rdpmc(i32) #0
+declare i64 @llvm.x86.rdpru(i32) #0
+
+define i64 @f(i32 %0) #1 {
+; CHECK-LABEL: f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: rdpmc
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: rdpru
+; CHECK-NEXT: shlq $32, %rdx
+; CHECK-NEXT: orq %rdx, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.x86.rdpmc(i32 0)
+ %3 = tail call i64 @llvm.x86.rdpru(i32 %0)
+ ret i64 %3
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { "target-features"="+avx512f" }
diff --git a/llvm/test/CodeGen/X86/ssub_sat_plus.ll b/llvm/test/CodeGen/X86/ssub_sat_plus.ll
index 5baf7a1dac74c..8b96a8050e65e 100644
--- a/llvm/test/CodeGen/X86/ssub_sat_plus.ll
+++ b/llvm/test/CodeGen/X86/ssub_sat_plus.ll
@@ -105,9 +105,9 @@ define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounw
define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
; X86-LABEL: func8:
; X86: # %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: cmpb %al, %dl
; X86-NEXT: setns %cl
@@ -140,9 +140,9 @@ define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
; X86-LABEL: func4:
; X86: # %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: shlb $4, %al
; X86-NEXT: sarb $4, %al
; X86-NEXT: subb %al, %cl
diff --git a/llvm/test/CodeGen/X86/usub_sat_plus.ll b/llvm/test/CodeGen/X86/usub_sat_plus.ll
index 0fb14ad5cf7b0..725de4401cb87 100644
--- a/llvm/test/CodeGen/X86/usub_sat_plus.ll
+++ b/llvm/test/CodeGen/X86/usub_sat_plus.ll
@@ -82,9 +82,9 @@ define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounw
define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
; X86-LABEL: func8:
; X86: # %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: subb %al, %cl
; X86-NEXT: movzbl %cl, %eax
@@ -111,9 +111,9 @@ define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
; X86-LABEL: func4:
; X86: # %bb.0:
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mulb {{[0-9]+}}(%esp)
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andb $15, %al
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: subb %al, %cl
diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll
index a076d0d762aa3..657547800075c 100644
--- a/llvm/test/CodeGen/X86/xmulo.ll
+++ b/llvm/test/CodeGen/X86/xmulo.ll
@@ -90,9 +90,9 @@ define zeroext i1 @smuloi8(i8 %v1, i8 %v2, ptr %res) {
;
; WIN32-LABEL: smuloi8:
; WIN32: # %bb.0:
-; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; WIN32-NEXT: imulb {{[0-9]+}}(%esp)
+; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: seto %cl
; WIN32-NEXT: movb %al, (%edx)
; WIN32-NEXT: movl %ecx, %eax
@@ -303,9 +303,9 @@ define zeroext i1 @umuloi8(i8 %v1, i8 %v2, ptr %res) {
;
; WIN32-LABEL: umuloi8:
; WIN32: # %bb.0:
-; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; WIN32-NEXT: mulb {{[0-9]+}}(%esp)
+; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: seto %cl
; WIN32-NEXT: movb %al, (%edx)
; WIN32-NEXT: movl %ecx, %eax
@@ -1386,10 +1386,10 @@ define zeroext i1 @smuloi8_load(ptr %ptr1, i8 %v2, ptr %res) {
;
; WIN32-LABEL: smuloi8_load:
; WIN32: # %bb.0:
-; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: movl {{[0-9]+}}(%esp), %eax
; WIN32-NEXT: movzbl (%eax), %eax
; WIN32-NEXT: imulb {{[0-9]+}}(%esp)
+; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: seto %cl
; WIN32-NEXT: movb %al, (%edx)
; WIN32-NEXT: movl %ecx, %eax
@@ -1435,10 +1435,10 @@ define zeroext i1 @smuloi8_load2(i8 %v1, ptr %ptr2, ptr %res) {
;
; WIN32-LABEL: smuloi8_load2:
; WIN32: # %bb.0:
-; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; WIN32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; WIN32-NEXT: imulb (%ecx)
+; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: seto %cl
; WIN32-NEXT: movb %al, (%edx)
; WIN32-NEXT: movl %ecx, %eax
@@ -1829,10 +1829,10 @@ define zeroext i1 @umuloi8_load(ptr %ptr1, i8 %v2, ptr %res) {
;
; WIN32-LABEL: umuloi8_load:
; WIN32: # %bb.0:
-; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: movl {{[0-9]+}}(%esp), %eax
; WIN32-NEXT: movzbl (%eax), %eax
; WIN32-NEXT: mulb {{[0-9]+}}(%esp)
+; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: seto %cl
; WIN32-NEXT: movb %al, (%edx)
; WIN32-NEXT: movl %ecx, %eax
@@ -1878,10 +1878,10 @@ define zeroext i1 @umuloi8_load2(i8 %v1, ptr %ptr2, ptr %res) {
;
; WIN32-LABEL: umuloi8_load2:
; WIN32: # %bb.0:
-; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; WIN32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; WIN32-NEXT: mulb (%ecx)
+; WIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; WIN32-NEXT: seto %cl
; WIN32-NEXT: movb %al, (%edx)
; WIN32-NEXT: movl %ecx, %eax
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