[llvm] [SelectionDAG] Merge consecutive loads feeding as shuffle operands (PR #207303)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 3 02:48:28 PDT 2026
================
@@ -27001,6 +27007,125 @@ static SDValue combineConcatVectorOfShuffleAndItsOperands(
return DAG.getVectorShuffle(VT, dl, ShufOps[0], ShufOps[1], Mask);
}
+// concat(shuffle(mask0, loadA, loadB), shuffle(mask1, loadA, loadB))
+// -> shuffle(concat(mask0, mask1), loadAB, poison)
+// only if loadA and loadB can be proven consecutive.
+static SDValue combineConcatVectorOfShuffles(SDNode *N, SelectionDAG &DAG,
+ const TargetLowering &TLI,
+ bool LegalTypes) {
+ // Check if concat has only two operands
+ if (N->getNumOperands() != 2)
+ return SDValue();
+
+ // Check if both operands are shuffle
+ if (N->getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE ||
+ N->getOperand(1).getOpcode() != ISD::VECTOR_SHUFFLE)
+ return SDValue();
+
+ // Check if both shuffles have both of its operands as loads and they are same
+ // respectively.
+ auto *L00 = dyn_cast<LoadSDNode>(N->getOperand(0).getOperand(0));
+ auto *L01 = dyn_cast<LoadSDNode>(N->getOperand(0).getOperand(1));
+ auto *L10 = dyn_cast<LoadSDNode>(N->getOperand(1).getOperand(0));
+ auto *L11 = dyn_cast<LoadSDNode>(N->getOperand(1).getOperand(1));
+ if (!L00 || !L01 || !L10 || !L11)
+ return SDValue();
+ if (L00 != L10 || L01 != L11)
----------------
RKSimon wrote:
Just use sd_match for all of this
https://github.com/llvm/llvm-project/pull/207303
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